More bits in progress, adapted from NetBSD.

12 files changed, 1823 insertions, 24 deletions

diff --git a/sys/arch/landisk/conf/GENERIC b/sys/arch/landisk/conf/GENERIC
index dd87ef1f6d8..a55e214eb73 100644
--- a/sys/arch/landisk/conf/GENERIC
+++ b/sys/arch/landisk/conf/GENERIC
@@ -1,4 +1,4 @@
-# $OpenBSD: GENERIC,v 1.2 2006/10/06 21:48:50 mickey Exp $
+# $OpenBSD: GENERIC,v 1.3 2006/10/07 20:52:38 miod Exp $
 #
 # For further information on compiling OpenBSD kernels, see the config(8)
 # man page.
@@ -41,17 +41,17 @@ pci0	at shpcic?
 shb*	at mainbus?
 
 # ob-board I/O bus
-#obio0	at mainbus?
+obio0	at mainbus?
 
 # Serial Devices
 option	SCIFCONSOLE
 option	SCIFCN_SPEED=9600
 scif0	at shb?
 
-#clock0 at shb?
+rsclock0 at shb?
 
-#wdc0	at obio? port 0x14000000 irq 10		# CF
-#wd*	at wdc? flags 0x0000
+wdc0	at obio? port 0x14000000 irq 10		# CF
+wd*	at wdc? flags 0x0000
 
 # Network Interfaces
 
diff --git a/sys/arch/landisk/conf/files.landisk b/sys/arch/landisk/conf/files.landisk
index b5164cdf8bc..74ff0187559 100644
--- a/sys/arch/landisk/conf/files.landisk
+++ b/sys/arch/landisk/conf/files.landisk
@@ -1,4 +1,4 @@
-#	$OpenBSD: files.landisk,v 1.1 2006/10/06 21:16:15 miod Exp $
+#	$OpenBSD: files.landisk,v 1.2 2006/10/07 20:52:38 miod Exp $
 #	$NetBSD: files.landisk,v 1.2 2006/09/07 01:55:02 uwe Exp $
 
 # maxpartitions must be first item in files.${MACHINE}
@@ -72,9 +72,9 @@ include "dev/usb/files.usb"
 include	"arch/sh/conf/files.shb"
 
 # Ricoh RS5C313 Real Time Clock
-device	clock
-attach	clock at shb
-file	arch/landisk/dev/rs5c313.c		clock
+device	rsclock
+attach	rsclock at shb
+file	arch/landisk/dev/rs5c313.c		rsclock
 
 #
 # on-board I/O bus
diff --git a/sys/arch/landisk/dev/obio.c b/sys/arch/landisk/dev/obio.c
new file mode 100644
index 00000000000..13aa0156a71
--- /dev/null
+++ b/sys/arch/landisk/dev/obio.c
@@ -0,0 +1,955 @@
+/*	$OpenBSD: obio.c,v 1.1 2006/10/07 20:52:40 miod Exp $	*/
+/*	$NetBSD: obio.c,v 1.1 2006/09/01 21:26:18 uwe Exp $	*/
+
+/*-
+ * Copyright (c) 1998 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Charles M. Hannum.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *        This product includes software developed by the NetBSD
+ *        Foundation, Inc. and its contributors.
+ * 4. Neither the name of The NetBSD Foundation nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/device.h>
+
+#include <uvm/uvm_extern.h>
+
+#include <sh/devreg.h>
+#include <sh/mmu.h>
+#include <sh/pmap.h>
+#include <sh/pte.h>
+
+#include <machine/bus.h>
+#include <machine/cpu.h>
+#include <machine/intr.h>
+
+#include <landisk/dev/obiovar.h>
+
+int	obio_match(struct device *, void *, void *);
+void	obio_attach(struct device *, struct device *, void *);
+int	obio_print(void *, const char *);
+int	obio_search(struct device *, void *, void *);
+
+struct cfattach obio_ca = {
+	sizeof(struct device), obio_match, obio_attach
+};
+
+struct cfdriver obio_cd = {
+	0, "obio", DV_DULL
+};
+
+int
+obio_match(struct device *parent, void *vcf, void *aux)
+{
+	struct obiobus_attach_args *oba = aux;
+
+	if (strcmp(oba->oba_busname, obio_cd.cd_name) != 0)
+		return (0);
+
+	return (1);
+}
+
+void
+obio_attach(struct device *parent, struct device *self, void *aux)
+{
+	struct obio_softc *sc = (struct obio_softc *)self;
+	struct obiobus_attach_args *oba = aux;
+
+	printf("\n");
+
+	sc->sc_iot = oba->oba_iot;
+	sc->sc_memt = oba->oba_memt;
+
+	config_search(obio_search, self, NULL);
+}
+
+int
+obio_search(struct device *parent, void *vcf, void *aux)
+{
+	struct obio_softc *sc = (struct obio_softc *)parent;
+	struct cfdata *cf = vcf;
+	struct obio_attach_args oa;
+	struct obio_io res_io[1];
+	struct obio_iomem res_mem[1];
+	struct obio_irq res_irq[1];
+
+	oa.oa_iot = sc->sc_iot;
+	oa.oa_memt = sc->sc_memt;
+
+	res_io[0].or_addr = cf->cf_iobase;
+	res_io[0].or_size = cf->cf_iosize;
+
+	res_mem[0].or_addr = cf->cf_maddr;
+	res_mem[0].or_size = cf->cf_msize;
+
+	res_irq[0].or_irq = cf->cf_irq;
+
+	oa.oa_io = res_io;
+	oa.oa_nio = 1;
+
+	oa.oa_iomem = res_mem;
+	oa.oa_niomem = 1;
+
+	oa.oa_irq = res_irq;
+	oa.oa_nirq = 1;
+
+	if ((*cf->cf_attach->ca_match)(parent, cf, &oa) == 0)
+		return (0);
+
+	config_attach(parent, cf, &oa, obio_print);
+	return (1);
+}
+
+int
+obio_print(void *args, const char *name)
+{
+	struct obio_attach_args *oa = args;
+	const char *sep;
+	int i;
+
+	if (oa->oa_nio) {
+		sep = "";
+		printf(" port ");
+		for (i = 0; i < oa->oa_nio; i++) {
+			if (oa->oa_io[i].or_size == 0)
+				continue;
+			printf("%s0x%x", sep, oa->oa_io[i].or_addr);
+			if (oa->oa_io[i].or_size > 1)
+				printf("-0x%x", oa->oa_io[i].or_addr +
+				    oa->oa_io[i].or_size - 1);
+			sep = ",";
+		}
+	}
+
+	if (oa->oa_niomem) {
+		sep = "";
+		printf(" iomem ");
+		for (i = 0; i < oa->oa_niomem; i++) {
+			if (oa->oa_iomem[i].or_size == 0)
+				continue;
+			printf("%s0x%x", sep, oa->oa_iomem[i].or_addr);
+			if (oa->oa_iomem[i].or_size > 1)
+				printf("-0x%x", oa->oa_iomem[i].or_addr +
+				    oa->oa_iomem[i].or_size - 1);
+			sep = ",";
+		}
+	}
+
+	if (oa->oa_nirq) {
+		sep = "";
+		printf(" irq ");
+		for (i = 0; i < oa->oa_nirq; i++) {
+			if (oa->oa_irq[i].or_irq == IRQUNK)
+				continue;
+			printf("%s%d", sep, oa->oa_irq[i].or_irq);
+			sep = ",";
+		}
+	}
+
+	return (UNCONF);
+}
+
+/*
+ * Set up an interrupt handler to start being called.
+ */
+void *
+obio_intr_establish(int irq, int level, int (*ih_fun)(void *), void *ih_arg,
+    const char *ih_name)
+{
+	return extintr_establish(irq, level, ih_fun, ih_arg, ih_name);
+}
+
+/*
+ * Deregister an interrupt handler.
+ */
+void
+obio_intr_disestablish(void *arg)
+{
+	extintr_disestablish(arg);
+}
+
+/*
+ * on-board I/O bus space
+ */
+#define	OBIO_IOMEM_IO		0	/* space is i/o space */
+#define	OBIO_IOMEM_MEM		1	/* space is mem space */
+#define	OBIO_IOMEM_PCMCIA_IO	2	/* PCMCIA IO space */
+#define	OBIO_IOMEM_PCMCIA_MEM	3	/* PCMCIA Mem space */
+#define	OBIO_IOMEM_PCMCIA_ATT	4	/* PCMCIA Attr space */
+#define	OBIO_IOMEM_PCMCIA_8BIT	0x8000	/* PCMCIA BUS 8 BIT WIDTH */
+#define	OBIO_IOMEM_PCMCIA_IO8 \
+	    (OBIO_IOMEM_PCMCIA_IO|OBIO_IOMEM_PCMCIA_8BIT)
+#define	OBIO_IOMEM_PCMCIA_MEM8 \
+	    (OBIO_IOMEM_PCMCIA_MEM|OBIO_IOMEM_PCMCIA_8BIT)
+#define	OBIO_IOMEM_PCMCIA_ATT8 \
+	    (OBIO_IOMEM_PCMCIA_ATT|OBIO_IOMEM_PCMCIA_8BIT)
+
+int obio_iomem_map(void *v, bus_addr_t bpa, bus_size_t size, int flags,
+    bus_space_handle_t *bshp);
+void obio_iomem_unmap(void *v, bus_space_handle_t bsh, bus_size_t size);
+int obio_iomem_subregion(void *v, bus_space_handle_t bsh,
+    bus_size_t offset, bus_size_t size, bus_space_handle_t *nbshp);
+int obio_iomem_alloc(void *v, bus_addr_t rstart, bus_addr_t rend,
+    bus_size_t size, bus_size_t alignment, bus_size_t boundary, int flags,
+    bus_addr_t *bpap, bus_space_handle_t *bshp);
+void obio_iomem_free(void *v, bus_space_handle_t bsh, bus_size_t size);
+
+int obio_iomem_add_mapping(bus_addr_t, bus_size_t, int,
+    bus_space_handle_t *);
+
+int
+obio_iomem_add_mapping(bus_addr_t bpa, bus_size_t size, int type,
+    bus_space_handle_t *bshp)
+{
+	u_long pa, endpa;
+	vaddr_t va;
+	pt_entry_t *pte;
+	unsigned int m = 0;
+	int io_type = type & ~OBIO_IOMEM_PCMCIA_8BIT;
+
+	pa = trunc_page(bpa);
+	endpa = round_page(bpa + size);
+
+#ifdef DIAGNOSTIC
+	if (endpa <= pa)
+		panic("obio_iomem_add_mapping: overflow");
+#endif
+
+	va = uvm_km_alloc(kernel_map, endpa - pa);
+	if (va == 0){
+		printf("obio_iomem_add_mapping: nomem\n");
+		return (ENOMEM);
+	}
+
+	*bshp = (bus_space_handle_t)(va + (bpa & PGOFSET));
+
+#define MODE(t, s)							\
+	((t) & OBIO_IOMEM_PCMCIA_8BIT) ?				\
+		_PG_PCMCIA_ ## s ## 8 :					\
+		_PG_PCMCIA_ ## s ## 16
+	switch (io_type) {
+	default:
+		panic("unknown pcmcia space.");
+		/* NOTREACHED */
+	case OBIO_IOMEM_PCMCIA_IO:
+		m = MODE(type, IO);
+		break;
+	case OBIO_IOMEM_PCMCIA_MEM:
+		m = MODE(type, MEM);
+		break;
+	case OBIO_IOMEM_PCMCIA_ATT:
+		m = MODE(type, ATTR);
+		break;
+	}
+#undef MODE
+
+	for (; pa < endpa; pa += PAGE_SIZE, va += PAGE_SIZE) {
+		pmap_kenter_pa(va, pa, VM_PROT_READ | VM_PROT_WRITE);
+		pte = __pmap_kpte_lookup(va);
+		KDASSERT(pte);
+		*pte |= m;  /* PTEA PCMCIA assistant bit */
+		sh_tlb_update(0, va, *pte);
+	}
+
+	return (0);
+}
+
+int
+obio_iomem_map(void *v, bus_addr_t bpa, bus_size_t size,
+    int flags, bus_space_handle_t *bshp)
+{
+	bus_addr_t addr = SH3_PHYS_TO_P2SEG(bpa);
+	int error;
+
+	KASSERT((bpa & SH3_PHYS_MASK) == bpa);
+
+	if (bpa < 0x14000000 || bpa >= 0x1c000000) {
+		/* CS0,1,2,3,4,7 */
+		*bshp = (bus_space_handle_t)addr;
+		return (0);
+	}
+
+	/* CS5,6 */
+	error = obio_iomem_add_mapping(addr, size, (int)(u_long)v, bshp);
+
+	return (error);
+}
+
+void
+obio_iomem_unmap(void *v, bus_space_handle_t bsh, bus_size_t size)
+{
+	u_long va, endva;
+	bus_addr_t bpa;
+
+	if (bsh >= SH3_P2SEG_BASE && bsh <= SH3_P2SEG_END) {
+		/* maybe CS0,1,2,3,4,7 */
+		return;
+	}
+
+	/* CS5,6 */
+	va = trunc_page(bsh);
+	endva = round_page(bsh + size);
+
+#ifdef DIAGNOSTIC
+	if (endva <= va)
+		panic("obio_io_unmap: overflow");
+#endif
+
+	pmap_extract(pmap_kernel(), va, &bpa);
+	bpa += bsh & PGOFSET;
+
+	pmap_kremove(va, endva - va);
+
+	/*
+	 * Free the kernel virtual mapping.
+	 */
+	uvm_km_free(kernel_map, va, endva - va);
+}
+
+int
+obio_iomem_subregion(void *v, bus_space_handle_t bsh,
+    bus_size_t offset, bus_size_t size, bus_space_handle_t *nbshp)
+{
+	*nbshp = bsh + offset;
+
+	return (0);
+}
+
+int
+obio_iomem_alloc(void *v, bus_addr_t rstart, bus_addr_t rend,
+    bus_size_t size, bus_size_t alignment, bus_size_t boundary, int flags,
+    bus_addr_t *bpap, bus_space_handle_t *bshp)
+{
+	*bshp = *bpap = rstart;
+
+	return (0);
+}
+
+void
+obio_iomem_free(void *v, bus_space_handle_t bsh, bus_size_t size)
+{
+	obio_iomem_unmap(v, bsh, size);
+}
+
+/*
+ * on-board I/O bus space read/write
+ */
+uint8_t obio_iomem_read_1(void *v, bus_space_handle_t bsh, bus_size_t offset);
+uint16_t obio_iomem_read_2(void *v, bus_space_handle_t bsh, bus_size_t offset);
+uint32_t obio_iomem_read_4(void *v, bus_space_handle_t bsh, bus_size_t offset);
+void obio_iomem_read_multi_1(void *v, bus_space_handle_t bsh,
+    bus_size_t offset, uint8_t *addr, bus_size_t count);
+void obio_iomem_read_multi_2(void *v, bus_space_handle_t bsh,
+    bus_size_t offset, uint16_t *addr, bus_size_t count);
+void obio_iomem_read_multi_4(void *v, bus_space_handle_t bsh,
+    bus_size_t offset, uint32_t *addr, bus_size_t count);
+void obio_iomem_read_raw_multi_2(void *v, bus_space_handle_t bsh,
+    bus_size_t offset, uint8_t *addr, bus_size_t count);
+void obio_iomem_read_raw_multi_4(void *v, bus_space_handle_t bsh,
+    bus_size_t offset, uint8_t *addr, bus_size_t count);
+void obio_iomem_read_region_1(void *v, bus_space_handle_t bsh,
+    bus_size_t offset, uint8_t *addr, bus_size_t count);
+void obio_iomem_read_region_2(void *v, bus_space_handle_t bsh,
+    bus_size_t offset, uint16_t *addr, bus_size_t count);
+void obio_iomem_read_region_4(void *v, bus_space_handle_t bsh,
+    bus_size_t offset, uint32_t *addr, bus_size_t count);
+void obio_iomem_read_raw_region_2(void *v, bus_space_handle_t bsh,
+    bus_size_t offset, uint8_t *addr, bus_size_t count);
+void obio_iomem_read_raw_region_4(void *v, bus_space_handle_t bsh,
+    bus_size_t offset, uint8_t *addr, bus_size_t count);
+void obio_iomem_write_1(void *v, bus_space_handle_t bsh, bus_size_t offset,
+    uint8_t value);
+void obio_iomem_write_2(void *v, bus_space_handle_t bsh, bus_size_t offset,
+    uint16_t value);
+void obio_iomem_write_4(void *v, bus_space_handle_t bsh, bus_size_t offset,
+    uint32_t value);
+void obio_iomem_write_multi_1(void *v, bus_space_handle_t bsh,
+    bus_size_t offset, const uint8_t *addr, bus_size_t count);
+void obio_iomem_write_multi_2(void *v, bus_space_handle_t bsh,
+    bus_size_t offset, const uint16_t *addr, bus_size_t count);
+void obio_iomem_write_multi_4(void *v, bus_space_handle_t bsh,
+    bus_size_t offset, const uint32_t *addr, bus_size_t count);
+void obio_iomem_write_raw_multi_2(void *v, bus_space_handle_t bsh,
+    bus_size_t offset, const uint8_t *addr, bus_size_t count);
+void obio_iomem_write_raw_multi_4(void *v, bus_space_handle_t bsh,
+    bus_size_t offset, const uint8_t *addr, bus_size_t count);
+void obio_iomem_write_region_1(void *v, bus_space_handle_t bsh,
+    bus_size_t offset, const uint8_t *addr, bus_size_t count);
+void obio_iomem_write_region_2(void *v, bus_space_handle_t bsh,
+    bus_size_t offset, const uint16_t *addr, bus_size_t count);
+void obio_iomem_write_region_4(void *v, bus_space_handle_t bsh,
+    bus_size_t offset, const uint32_t *addr, bus_size_t count);
+void obio_iomem_write_raw_region_2(void *v, bus_space_handle_t bsh,
+    bus_size_t offset, const uint8_t *addr, bus_size_t count);
+void obio_iomem_write_raw_region_4(void *v, bus_space_handle_t bsh,
+    bus_size_t offset, const uint8_t *addr, bus_size_t count);
+void obio_iomem_set_multi_1(void *v, bus_space_handle_t bsh, bus_size_t offset,
+    uint8_t val, bus_size_t count);
+void obio_iomem_set_multi_2(void *v, bus_space_handle_t bsh, bus_size_t offset,
+    uint16_t val, bus_size_t count);
+void obio_iomem_set_multi_4(void *v, bus_space_handle_t bsh, bus_size_t offset,
+    uint32_t val, bus_size_t count);
+void obio_iomem_set_region_1(void *v, bus_space_handle_t bsh,
+    bus_size_t offset, uint8_t val, bus_size_t count);
+void obio_iomem_set_region_2(void *v, bus_space_handle_t bsh,
+    bus_size_t offset, uint16_t val, bus_size_t count);
+void obio_iomem_set_region_4(void *v, bus_space_handle_t bsh,
+    bus_size_t offset, uint32_t val, bus_size_t count);
+void obio_iomem_copy_region_1(void *v, bus_space_handle_t h1, bus_size_t o1,
+    bus_space_handle_t h2, bus_size_t o2, bus_size_t count);
+void obio_iomem_copy_region_2(void *v, bus_space_handle_t h1, bus_size_t o1,
+    bus_space_handle_t h2, bus_size_t o2, bus_size_t count);
+void obio_iomem_copy_region_4(void *v, bus_space_handle_t h1, bus_size_t o1,
+    bus_space_handle_t h2, bus_size_t o2, bus_size_t count);
+
+struct _bus_space obio_bus_io =
+{
+	.bs_cookie = (void *)OBIO_IOMEM_PCMCIA_IO,
+
+	.bs_map = obio_iomem_map,
+	.bs_unmap = obio_iomem_unmap,
+	.bs_subregion = obio_iomem_subregion,
+
+	.bs_alloc = obio_iomem_alloc,
+	.bs_free = obio_iomem_free,
+
+	.bs_r_1 = obio_iomem_read_1,
+	.bs_r_2 = obio_iomem_read_2,
+	.bs_r_4 = obio_iomem_read_4,
+
+	.bs_rm_1 = obio_iomem_read_multi_1,
+	.bs_rm_2 = obio_iomem_read_multi_2,
+	.bs_rm_4 = obio_iomem_read_multi_4,
+
+	.bs_rrm_2 = obio_iomem_read_raw_multi_2,
+	.bs_rrm_4 = obio_iomem_read_raw_multi_4,
+
+	.bs_rr_1 = obio_iomem_read_region_1,
+	.bs_rr_2 = obio_iomem_read_region_2,
+	.bs_rr_4 = obio_iomem_read_region_4,
+
+	.bs_rrr_2 = obio_iomem_read_raw_region_2,
+	.bs_rrr_4 = obio_iomem_read_raw_region_4,
+
+	.bs_w_1 = obio_iomem_write_1,
+	.bs_w_2 = obio_iomem_write_2,
+	.bs_w_4 = obio_iomem_write_4,
+
+	.bs_wm_1 = obio_iomem_write_multi_1,
+	.bs_wm_2 = obio_iomem_write_multi_2,
+	.bs_wm_4 = obio_iomem_write_multi_4,
+
+	.bs_wrm_2 = obio_iomem_write_raw_multi_2,
+	.bs_wrm_4 = obio_iomem_write_raw_multi_4,
+
+	.bs_wr_1 = obio_iomem_write_region_1,
+	.bs_wr_2 = obio_iomem_write_region_2,
+	.bs_wr_4 = obio_iomem_write_region_4,
+
+	.bs_wrr_2 = obio_iomem_write_raw_region_2,
+	.bs_wrr_4 = obio_iomem_write_raw_region_4,
+
+	.bs_sm_1 = obio_iomem_set_multi_1,
+	.bs_sm_2 = obio_iomem_set_multi_2,
+	.bs_sm_4 = obio_iomem_set_multi_4,
+
+	.bs_sr_1 = obio_iomem_set_region_1,
+	.bs_sr_2 = obio_iomem_set_region_2,
+	.bs_sr_4 = obio_iomem_set_region_4,
+
+	.bs_c_1 = obio_iomem_copy_region_1,
+	.bs_c_2 = obio_iomem_copy_region_2,
+	.bs_c_4 = obio_iomem_copy_region_4,
+};
+
+struct _bus_space obio_bus_mem =
+{
+	.bs_cookie = (void *)OBIO_IOMEM_PCMCIA_MEM,
+
+	.bs_map = obio_iomem_map,
+	.bs_unmap = obio_iomem_unmap,
+	.bs_subregion = obio_iomem_subregion,
+
+	.bs_alloc = obio_iomem_alloc,
+	.bs_free = obio_iomem_free,
+
+	.bs_r_1 = obio_iomem_read_1,
+	.bs_r_2 = obio_iomem_read_2,
+	.bs_r_4 = obio_iomem_read_4,
+
+	.bs_rm_1 = obio_iomem_read_multi_1,
+	.bs_rm_2 = obio_iomem_read_multi_2,
+	.bs_rm_4 = obio_iomem_read_multi_4,
+
+	.bs_rrm_2 = obio_iomem_read_raw_multi_2,
+	.bs_rrm_4 = obio_iomem_read_raw_multi_4,
+
+	.bs_rr_1 = obio_iomem_read_region_1,
+	.bs_rr_2 = obio_iomem_read_region_2,
+	.bs_rr_4 = obio_iomem_read_region_4,
+
+	.bs_rrr_2 = obio_iomem_read_raw_region_2,
+	.bs_rrr_4 = obio_iomem_read_raw_region_4,
+
+	.bs_w_1 = obio_iomem_write_1,
+	.bs_w_2 = obio_iomem_write_2,
+	.bs_w_4 = obio_iomem_write_4,
+
+	.bs_wm_1 = obio_iomem_write_multi_1,
+	.bs_wm_2 = obio_iomem_write_multi_2,
+	.bs_wm_4 = obio_iomem_write_multi_4,
+
+	.bs_wrm_2 = obio_iomem_write_raw_multi_2,
+	.bs_wrm_4 = obio_iomem_write_raw_multi_4,
+
+	.bs_wr_1 = obio_iomem_write_region_1,
+	.bs_wr_2 = obio_iomem_write_region_2,
+	.bs_wr_4 = obio_iomem_write_region_4,
+
+	.bs_wrr_2 = obio_iomem_write_raw_region_2,
+	.bs_wrr_4 = obio_iomem_write_raw_region_4,
+
+	.bs_sm_1 = obio_iomem_set_multi_1,
+	.bs_sm_2 = obio_iomem_set_multi_2,
+	.bs_sm_4 = obio_iomem_set_multi_4,
+
+	.bs_sr_1 = obio_iomem_set_region_1,
+	.bs_sr_2 = obio_iomem_set_region_2,
+	.bs_sr_4 = obio_iomem_set_region_4,
+
+	.bs_c_1 = obio_iomem_copy_region_1,
+	.bs_c_2 = obio_iomem_copy_region_2,
+	.bs_c_4 = obio_iomem_copy_region_4,
+};
+
+/* read */
+uint8_t
+obio_iomem_read_1(void *v, bus_space_handle_t bsh, bus_size_t offset)
+{
+	return *(volatile uint8_t *)(bsh + offset);
+}
+
+uint16_t
+obio_iomem_read_2(void *v, bus_space_handle_t bsh, bus_size_t offset)
+{
+	return *(volatile uint16_t *)(bsh + offset);
+}
+
+uint32_t
+obio_iomem_read_4(void *v, bus_space_handle_t bsh, bus_size_t offset)
+{
+	return *(volatile uint32_t *)(bsh + offset);
+}
+
+void
+obio_iomem_read_multi_1(void *v, bus_space_handle_t bsh,
+    bus_size_t offset, uint8_t *addr, bus_size_t count)
+{
+	volatile uint8_t *p = (void *)(bsh + offset);
+
+	while (count--) {
+		*addr++ = *p;
+	}
+}
+
+void
+obio_iomem_read_multi_2(void *v, bus_space_handle_t bsh,
+    bus_size_t offset, uint16_t *addr, bus_size_t count)
+{
+	volatile uint16_t *p = (void *)(bsh + offset);
+
+	while (count--) {
+		*addr++ = *p;
+	}
+}
+
+void
+obio_iomem_read_multi_4(void *v, bus_space_handle_t bsh,
+    bus_size_t offset, uint32_t *addr, bus_size_t count)
+{
+	volatile uint32_t *p = (void *)(bsh + offset);
+
+	while (count--) {
+		*addr++ = *p;
+	}
+}
+
+void
+obio_iomem_read_raw_multi_2(void *v, bus_space_handle_t bsh,
+    bus_size_t offset, uint8_t *addr, bus_size_t count)
+{
+	volatile uint16_t *p = (void *)(bsh + offset);
+
+	count >>= 1;
+	while (count--) {
+		*(uint16_t *)addr = *p;
+		addr += 2;
+	}
+}
+
+void
+obio_iomem_read_raw_multi_4(void *v, bus_space_handle_t bsh,
+    bus_size_t offset, uint8_t *addr, bus_size_t count)
+{
+	volatile uint32_t *p = (void *)(bsh + offset);
+
+	count >>= 2;
+	while (count--) {
+		*(uint32_t *)addr = *p;
+		addr += 4;
+	}
+}
+
+void
+obio_iomem_read_region_1(void *v, bus_space_handle_t bsh,
+    bus_size_t offset, uint8_t *addr, bus_size_t count)
+{
+	volatile uint8_t *p = (void *)(bsh + offset);
+
+	while (count--) {
+		*addr++ = *p++;
+	}
+}
+
+void
+obio_iomem_read_region_2(void *v, bus_space_handle_t bsh,
+    bus_size_t offset, uint16_t *addr, bus_size_t count)
+{
+	volatile uint16_t *p = (void *)(bsh + offset);
+
+	while (count--) {
+		*addr++ = *p++;
+	}
+}
+
+void
+obio_iomem_read_region_4(void *v, bus_space_handle_t bsh,
+    bus_size_t offset, uint32_t *addr, bus_size_t count)
+{
+	volatile uint32_t *p = (void *)(bsh + offset);
+
+	while (count--) {
+		*addr++ = *p++;
+	}
+}
+
+void
+obio_iomem_read_raw_region_2(void *v, bus_space_handle_t bsh,
+    bus_size_t offset, uint8_t *addr, bus_size_t count)
+{
+	volatile uint16_t *p = (void *)(bsh + offset);
+
+	count >>= 1;
+	while (count--) {
+		*(uint16_t *)addr = *p++;
+		addr += 2;
+	}
+}
+
+void
+obio_iomem_read_raw_region_4(void *v, bus_space_handle_t bsh,
+    bus_size_t offset, uint8_t *addr, bus_size_t count)
+{
+	volatile uint32_t *p = (void *)(bsh + offset);
+
+	count >>= 2;
+	while (count--) {
+		*(uint32_t *)addr = *p++;
+		addr += 4;
+	}
+}
+
+/* write */
+void
+obio_iomem_write_1(void *v, bus_space_handle_t bsh, bus_size_t offset,
+    uint8_t value)
+{
+	*(volatile uint8_t *)(bsh + offset) = value;
+}
+
+void
+obio_iomem_write_2(void *v, bus_space_handle_t bsh, bus_size_t offset,
+    uint16_t value)
+{
+	*(volatile uint16_t *)(bsh + offset) = value;
+}
+
+void
+obio_iomem_write_4(void *v, bus_space_handle_t bsh, bus_size_t offset,
+    uint32_t value)
+{
+	*(volatile uint32_t *)(bsh + offset) = value;
+}
+
+void
+obio_iomem_write_multi_1(void *v, bus_space_handle_t bsh,
+    bus_size_t offset, const uint8_t *addr, bus_size_t count)
+{
+	volatile uint8_t *p = (void *)(bsh + offset);
+
+	while (count--) {
+		*p = *addr++;
+	}
+}
+
+void
+obio_iomem_write_multi_2(void *v, bus_space_handle_t bsh,
+    bus_size_t offset, const uint16_t *addr, bus_size_t count)
+{
+	volatile uint16_t *p = (void *)(bsh + offset);
+
+	while (count--) {
+		*p = *addr++;
+	}
+}
+
+void
+obio_iomem_write_multi_4(void *v, bus_space_handle_t bsh,
+    bus_size_t offset, const uint32_t *addr, bus_size_t count)
+{
+	volatile uint32_t *p = (void *)(bsh + offset);
+
+	while (count--) {
+		*p = *addr++;
+	}
+}
+
+void
+obio_iomem_write_raw_multi_2(void *v, bus_space_handle_t bsh,
+    bus_size_t offset, const uint8_t *addr, bus_size_t count)
+{
+	volatile uint16_t *p = (void *)(bsh + offset);
+
+	count >>= 1;
+	while (count--) {
+		*p = *(uint16_t *)addr;
+		addr += 2;
+	}
+}
+
+void
+obio_iomem_write_raw_multi_4(void *v, bus_space_handle_t bsh,
+    bus_size_t offset, const uint8_t *addr, bus_size_t count)
+{
+	volatile uint32_t *p = (void *)(bsh + offset);
+
+	count >>= 2;
+	while (count--) {
+		*p = *(uint32_t *)addr;
+		addr += 4;
+	}
+}
+
+void
+obio_iomem_write_region_1(void *v, bus_space_handle_t bsh,
+    bus_size_t offset, const uint8_t *addr, bus_size_t count)
+{
+	volatile uint8_t *p = (void *)(bsh + offset);
+
+	while (count--) {
+		*p++ = *addr++;
+	}
+}
+
+void
+obio_iomem_write_region_2(void *v, bus_space_handle_t bsh,
+    bus_size_t offset, const uint16_t *addr, bus_size_t count)
+{
+	volatile uint16_t *p = (void *)(bsh + offset);
+
+	while (count--) {
+		*p++ = *addr++;
+	}
+}
+
+void
+obio_iomem_write_region_4(void *v, bus_space_handle_t bsh,
+    bus_size_t offset, const uint32_t *addr, bus_size_t count)
+{
+	volatile uint32_t *p = (void *)(bsh + offset);
+
+	while (count--) {
+		*p++ = *addr++;
+	}
+}
+
+void
+obio_iomem_write_raw_region_2(void *v, bus_space_handle_t bsh,
+    bus_size_t offset, const uint8_t *addr, bus_size_t count)
+{
+	volatile uint16_t *p = (void *)(bsh + offset);
+
+	count >>= 1;
+	while (count--) {
+		*p++ = *(uint16_t *)addr;
+		addr += 2;
+	}
+}
+
+void
+obio_iomem_write_raw_region_4(void *v, bus_space_handle_t bsh,
+    bus_size_t offset, const uint8_t *addr, bus_size_t count)
+{
+	volatile uint32_t *p = (void *)(bsh + offset);
+
+	count >>= 2;
+	while (count--) {
+		*p++ = *(uint32_t *)addr;
+		addr += 4;
+	}
+}
+
+void
+obio_iomem_set_multi_1(void *v, bus_space_handle_t bsh,
+    bus_size_t offset, uint8_t val, bus_size_t count)
+{
+	volatile uint8_t *p = (void *)(bsh + offset);
+
+	while (count--) {
+		*p = val;
+	}
+}
+
+void
+obio_iomem_set_multi_2(void *v, bus_space_handle_t bsh,
+    bus_size_t offset, uint16_t val, bus_size_t count)
+{
+	volatile uint16_t *p = (void *)(bsh + offset);
+
+	while (count--) {
+		*p = val;
+	}
+}
+
+void
+obio_iomem_set_multi_4(void *v, bus_space_handle_t bsh,
+    bus_size_t offset, uint32_t val, bus_size_t count)
+{
+	volatile uint32_t *p = (void *)(bsh + offset);
+
+	while (count--) {
+		*p = val;
+	}
+}
+
+void
+obio_iomem_set_region_1(void *v, bus_space_handle_t bsh,
+    bus_size_t offset, uint8_t val, bus_size_t count)
+{
+	volatile uint8_t *addr = (void *)(bsh + offset);
+
+	while (count--) {
+		*addr++ = val;
+	}
+}
+
+void
+obio_iomem_set_region_2(void *v, bus_space_handle_t bsh,
+    bus_size_t offset, uint16_t val, bus_size_t count)
+{
+	volatile uint16_t *addr = (void *)(bsh + offset);
+
+	while (count--) {
+		*addr++ = val;
+	}
+}
+
+void
+obio_iomem_set_region_4(void *v, bus_space_handle_t bsh,
+    bus_size_t offset, uint32_t val, bus_size_t count)
+{
+	volatile uint32_t *addr = (void *)(bsh + offset);
+
+	while (count--) {
+		*addr++ = val;
+	}
+}
+
+void
+obio_iomem_copy_region_1(void *v, bus_space_handle_t h1, bus_size_t o1,
+    bus_space_handle_t h2, bus_size_t o2, bus_size_t count)
+{
+	volatile uint8_t *addr1 = (void *)(h1 + o1);
+	volatile uint8_t *addr2 = (void *)(h2 + o2);
+
+	if (addr1 >= addr2) {	/* src after dest: copy forward */
+		while (count--) {
+			*addr2++ = *addr1++;
+		}
+	} else {		/* dest after src: copy backwards */
+		addr1 += count - 1;
+		addr2 += count - 1;
+		while (count--) {
+			*addr2-- = *addr1--;
+		}
+	}
+}
+
+void
+obio_iomem_copy_region_2(void *v, bus_space_handle_t h1, bus_size_t o1,
+    bus_space_handle_t h2, bus_size_t o2, bus_size_t count)
+{
+	volatile uint16_t *addr1 = (void *)(h1 + o1);
+	volatile uint16_t *addr2 = (void *)(h2 + o2);
+
+	if (addr1 >= addr2) {	/* src after dest: copy forward */
+		while (count--) {
+			*addr2++ = *addr1++;
+		}
+	} else {		/* dest after src: copy backwards */
+		addr1 += count - 1;
+		addr2 += count - 1;
+		while (count--) {
+			*addr2-- = *addr1--;
+		}
+	}
+}
+
+void
+obio_iomem_copy_region_4(void *v, bus_space_handle_t h1, bus_size_t o1,
+    bus_space_handle_t h2, bus_size_t o2, bus_size_t count)
+{
+	volatile uint32_t *addr1 = (void *)(h1 + o1);
+	volatile uint32_t *addr2 = (void *)(h2 + o2);
+
+	if (addr1 >= addr2) {	/* src after dest: copy forward */
+		while (count--) {
+			*addr2++ = *addr1++;
+		}
+	} else {		/* dest after src: copy backwards */
+		addr1 += count - 1;
+		addr2 += count - 1;
+		while (count--) {
+			*addr2-- = *addr1--;
+		}
+	}
+}
diff --git a/sys/arch/landisk/dev/obiovar.h b/sys/arch/landisk/dev/obiovar.h
index 8b263f49a8e..72c44a01865 100644
--- a/sys/arch/landisk/dev/obiovar.h
+++ b/sys/arch/landisk/dev/obiovar.h
@@ -1,3 +1,4 @@
+/*	$OpenBSD: obiovar.h,v 1.2 2006/10/07 20:52:40 miod Exp $	*/
 /*	$NetBSD: obiovar.h,v 1.1 2006/09/01 21:26:18 uwe Exp $	*/
 
 /*-
@@ -150,7 +151,7 @@ struct obio_softc {
 #define		cf_msize		cf_loc[3]
 #define		cf_irq			cf_loc[4]
 
-void *obio_intr_establish(int irq, int level, int (*func)(void *), void *arg);
-void obio_intr_disestablish(void *ih);
+void *obio_intr_establish(int, int, int (*)(void *), void *, const char *);
+void obio_intr_disestablish(void *);
 
 #endif /* _LANDISK_OBIOVAR_H_ */
diff --git a/sys/arch/landisk/dev/rs5c313.c b/sys/arch/landisk/dev/rs5c313.c
new file mode 100644
index 00000000000..e606c21872c
--- /dev/null
+++ b/sys/arch/landisk/dev/rs5c313.c
@@ -0,0 +1,437 @@
+/*	$OpenBSD: rs5c313.c,v 1.1 2006/10/07 20:52:40 miod Exp $	*/
+/*	$NetBSD: rs5c313.c,v 1.1 2006/09/07 01:12:00 uwe Exp $	*/
+/*	$NetBSD: rs5c313_landisk.c,v 1.1 2006/09/07 01:55:03 uwe Exp $	*/
+
+/*-
+ * Copyright (c) 2002 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *        This product includes software developed by the NetBSD
+ *        Foundation, Inc. and its contributors.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * RICOH RS5C313 Real Time Clock
+ */
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/device.h>
+#include <sys/kernel.h>
+
+#include <dev/clock_subr.h>
+#include <sh/clock.h>
+
+#include <sh/devreg.h>
+#include <sh/dev/scireg.h>
+
+#include <landisk/dev/rs5c313reg.h>
+#include <landisk/landisk/landiskreg.h>
+
+struct rs5c313_softc {
+	struct device sc_dev;
+
+	int sc_valid;		/* oscillation halt sensing on init */
+};
+
+/* chip access methods */
+void rtc_begin(struct rs5c313_softc *);
+void rtc_ce(struct rs5c313_softc *, int);
+void rtc_dir(struct rs5c313_softc *, int);
+void rtc_clk(struct rs5c313_softc *, int);
+int  rtc_read(struct rs5c313_softc *);
+void rtc_write(struct rs5c313_softc *, int);
+
+int rs5c313_init(struct rs5c313_softc *);
+int rs5c313_read_reg(struct rs5c313_softc *, int);
+void rs5c313_write_reg(struct rs5c313_softc *, int, int);
+void rs5c313_gettime(void *, time_t, struct clock_ymdhms *);
+void rs5c313_settime(void *, struct clock_ymdhms *);
+
+int
+rs5c313_init(struct rs5c313_softc *sc)
+{
+	int status = 0;
+	int retry;
+
+	rtc_ce(sc, 0);
+
+	rtc_begin(sc);
+	rtc_ce(sc, 1);
+
+	if ((rs5c313_read_reg(sc, RS5C313_CTRL) & CTRL_XSTP) == 0) {
+		sc->sc_valid = 1;
+		goto done;
+	}
+
+	sc->sc_valid = 0;
+	printf("%s: time not valid\n", sc->sc_dev.dv_xname);
+
+	rs5c313_write_reg(sc, RS5C313_TINT, 0);
+	rs5c313_write_reg(sc, RS5C313_CTRL, (CTRL_BASE | CTRL_ADJ));
+
+	for (retry = 1000; retry > 0; --retry) {
+		if (rs5c313_read_reg(sc, RS5C313_CTRL) & CTRL_BSY)
+			delay(1);
+		else
+			break;
+	}
+
+	if (retry == 0) {
+		status = EIO;
+		goto done;
+	}
+
+	rs5c313_write_reg(sc, RS5C313_CTRL, CTRL_BASE);
+
+done:
+	rtc_ce(sc, 0);
+	return status;
+}
+
+int
+rs5c313_read_reg(struct rs5c313_softc *sc, int addr)
+{
+	int data;
+
+	/* output */
+	rtc_dir(sc, 1);
+
+	/* control */
+	rtc_write(sc, 1);		/* ignored */
+	rtc_write(sc, 1);		/* R/#W = 1(READ) */
+	rtc_write(sc, 1);		/* AD = 1 */
+	rtc_write(sc, 0);		/* DT = 0 */
+
+	/* address */
+	rtc_write(sc, addr & 0x8);	/* A3 */
+	rtc_write(sc, addr & 0x4);	/* A2 */
+	rtc_write(sc, addr & 0x2);	/* A1 */
+	rtc_write(sc, addr & 0x1);	/* A0 */
+
+	/* input */
+	rtc_dir(sc, 0);
+
+	/* ignore */
+	(void)rtc_read(sc);
+	(void)rtc_read(sc);
+	(void)rtc_read(sc);
+	(void)rtc_read(sc);
+
+	/* data */
+	data = rtc_read(sc);	/* D3 */
+	data <<= 1;
+	data |= rtc_read(sc);	/* D2 */
+	data <<= 1;
+	data |= rtc_read(sc);	/* D1 */
+	data <<= 1;
+	data |= rtc_read(sc);	/* D0 */
+
+	return data;
+}
+
+void
+rs5c313_write_reg(struct rs5c313_softc *sc, int addr, int data)
+{
+	/* output */
+	rtc_dir(sc, 1);
+
+	/* control */
+	rtc_write(sc, 1);		/* ignored */
+	rtc_write(sc, 0);		/* R/#W = 0 (WRITE) */
+	rtc_write(sc, 1);		/* AD = 1 */
+	rtc_write(sc, 0);		/* DT = 0 */
+
+	/* address */
+	rtc_write(sc, addr & 0x8);	/* A3 */
+	rtc_write(sc, addr & 0x4);	/* A2 */
+	rtc_write(sc, addr & 0x2);	/* A1 */
+	rtc_write(sc, addr & 0x1);	/* A0 */
+
+	/* control */
+	rtc_write(sc, 1);		/* ignored */
+	rtc_write(sc, 0);		/* R/#W = 0(WRITE) */
+	rtc_write(sc, 0);		/* AD = 0 */
+	rtc_write(sc, 1);		/* DT = 1 */
+
+	/* data */
+	rtc_write(sc, data & 0x8);	/* D3 */
+	rtc_write(sc, data & 0x4);	/* D2 */
+	rtc_write(sc, data & 0x2);	/* D1 */
+	rtc_write(sc, data & 0x1);	/* D0 */
+}
+
+void
+rs5c313_gettime(void *cookie, time_t base, struct clock_ymdhms *dt)
+{
+	struct rs5c313_softc *sc = cookie;
+	int retry;
+	int s;
+
+	/*
+	 * If chip had invalid data on init, don't bother reading
+	 * bogus values.
+	 */
+	if (sc->sc_valid == 0)
+		return;
+
+	s = splhigh();
+
+	rtc_begin(sc);
+	for (retry = 10; retry > 0; --retry) {
+		rtc_ce(sc, 1);
+
+		rs5c313_write_reg(sc, RS5C313_CTRL, CTRL_BASE);
+		if ((rs5c313_read_reg(sc, RS5C313_CTRL) & CTRL_BSY) == 0)
+			break;
+
+		rtc_ce(sc, 0);
+		delay(1);
+	}
+
+	if (retry == 0) {
+		splx(s);
+		return;
+	}
+
+#define RTCGET(x, y)							\
+	do {								\
+		int ones = rs5c313_read_reg(sc, RS5C313_ ## y ## 1);	\
+		int tens = rs5c313_read_reg(sc, RS5C313_ ## y ## 10);	\
+		dt->dt_ ## x = tens * 10 + ones;			\
+	} while (/* CONSTCOND */0)
+
+	RTCGET(sec, SEC);
+	RTCGET(min, MIN);
+	RTCGET(hour, HOUR);
+	RTCGET(day, DAY);
+	RTCGET(mon, MON);
+	RTCGET(year, YEAR);
+#undef	RTCGET
+	dt->dt_wday = rs5c313_read_reg(sc, RS5C313_WDAY);
+
+	rtc_ce(sc, 0);
+	splx(s);
+
+	dt->dt_year = (dt->dt_year % 100) + 1900;
+	if (dt->dt_year < 1970) {
+		dt->dt_year += 100;
+	}
+}
+
+void
+rs5c313_settime(void *cookie, struct clock_ymdhms *dt)
+{
+	struct rs5c313_softc *sc = cookie;
+	int retry;
+	int t;
+	int s;
+
+	s = splhigh();
+
+	rtc_begin(sc);
+	for (retry = 10; retry > 0; --retry) {
+		rtc_ce(sc, 1);
+
+		rs5c313_write_reg(sc, RS5C313_CTRL, CTRL_BASE);
+		if ((rs5c313_read_reg(sc, RS5C313_CTRL) & CTRL_BSY) == 0)
+			break;
+
+		rtc_ce(sc, 0);
+		delay(1);
+	}
+
+	if (retry == 0) {
+		splx(s);
+		return;
+	}
+
+#define	RTCSET(x, y)							     \
+	do {								     \
+		t = TOBCD(dt->dt_ ## y) & 0xff;				     \
+		rs5c313_write_reg(sc, RS5C313_ ## x ## 1, t & 0x0f);	     \
+		rs5c313_write_reg(sc, RS5C313_ ## x ## 10, (t >> 4) & 0x0f); \
+	} while (/* CONSTCOND */0)
+
+	RTCSET(SEC, sec);
+	RTCSET(MIN, min);
+	RTCSET(HOUR, hour);
+	RTCSET(DAY, day);
+	RTCSET(MON, mon);
+
+#undef	RTCSET
+
+	t = dt->dt_year % 100;
+	t = TOBCD(t);
+	rs5c313_write_reg(sc, RS5C313_YEAR1, t & 0x0f);
+	rs5c313_write_reg(sc, RS5C313_YEAR10, (t >> 4) & 0x0f);
+
+	rs5c313_write_reg(sc, RS5C313_WDAY, dt->dt_wday);
+
+	rtc_ce(sc, 0);
+	splx(s);
+
+	sc->sc_valid = 1;
+}
+
+struct rtc_ops rs5c313_ops = {
+	NULL,
+	NULL,			/* not used */
+	rs5c313_gettime,
+	rs5c313_settime
+};
+
+void
+rtc_begin(struct rs5c313_softc *sc)
+{
+	SHREG_SCSPTR = SCSPTR_SPB1IO | SCSPTR_SPB1DT
+		     | SCSPTR_SPB0IO | SCSPTR_SPB0DT;
+	delay(100);
+}
+
+/*
+ * CE pin
+ */
+void
+rtc_ce(struct rs5c313_softc *sc, int onoff)
+{
+	if (onoff)
+		_reg_write_1(LANDISK_PWRMNG, PWRMNG_RTC_CE);
+	else
+		_reg_write_1(LANDISK_PWRMNG, 0);
+	delay(600);
+}
+
+/*
+ * SCLK pin is connnected to SPB0DT.
+ * SPB0DT is always in output mode, we set SPB0IO in rtc_begin.
+ */
+void
+rtc_clk(struct rs5c313_softc *sc, int onoff)
+{
+	uint8_t r = SHREG_SCSPTR;
+
+	if (onoff)
+		r |= SCSPTR_SPB0DT;
+	else
+		r &= ~SCSPTR_SPB0DT;
+	SHREG_SCSPTR = r;
+}
+
+/*
+ * SIO pin is connected to SPB1DT.
+ * SPB1DT is output when SPB1IO is set.
+ */
+void
+rtc_dir(struct rs5c313_softc *sc, int output)
+{
+	uint8_t r = SHREG_SCSPTR;
+
+	if (output)
+		r |= SCSPTR_SPB1IO;
+	else
+		r &= ~SCSPTR_SPB1IO;
+	SHREG_SCSPTR = r;
+}
+
+/* 
+ * Read bit from SPB1DT pin.
+ */
+int
+rtc_read(struct rs5c313_softc *sc)
+{
+	int bit;
+
+	delay(300);
+
+	bit = (SHREG_SCSPTR & SCSPTR_SPB1DT) ? 1 : 0;
+
+	rtc_clk(sc, 0);
+	delay(300);
+	rtc_clk(sc, 1);
+
+	return bit;
+}
+
+/* 
+ * Write bit via SPB1DT pin.
+ */
+void
+rtc_write(struct rs5c313_softc *sc, int bit)
+{
+	uint8_t r = SHREG_SCSPTR;
+
+	if (bit)
+		r |= SCSPTR_SPB1DT;
+	else
+		r &= ~SCSPTR_SPB1DT;
+	SHREG_SCSPTR = r;
+
+	delay(300);
+
+	rtc_clk(sc, 0);
+	delay(300);
+	rtc_clk(sc, 1);
+}
+
+/* autoconf glue */
+int rs5c313_landisk_match(struct device *, void *, void *);
+void rs5c313_landisk_attach(struct device *, struct device *, void *);
+
+const struct cfattach rsclock_ca = {
+	sizeof (struct rs5c313_softc),
+	rs5c313_landisk_match, rs5c313_landisk_attach
+};
+
+struct cfdriver rsclock_cd = {
+	0, "rsclock", DV_DULL
+};
+
+int
+rs5c313_landisk_match(struct device *parent, void *vcf, void *aux)
+{
+	static int matched = 0;
+
+	if (matched)
+		return (0);
+
+	return (matched = 1);
+}
+
+void
+rs5c313_landisk_attach(struct device *parent, struct device *self, void *aux)
+{
+	struct rs5c313_softc *sc = (void *)self;
+
+	printf(": RS5C313 real time clock\n");
+
+	if (rs5c313_init(sc) != 0) {
+		printf("%s: init failed\n", self->dv_xname);
+		return;
+	}
+
+	rs5c313_ops._cookie = sc;
+	sh_clock_init(0, &rs5c313_ops);
+}
diff --git a/sys/arch/landisk/dev/wdc_obio.c b/sys/arch/landisk/dev/wdc_obio.c
new file mode 100644
index 00000000000..b2d7f40d8ce
--- /dev/null
+++ b/sys/arch/landisk/dev/wdc_obio.c
@@ -0,0 +1,142 @@
+/*	$OpenBSD: wdc_obio.c,v 1.1 2006/10/07 20:52:40 miod Exp $	*/
+/*	$NetBSD: wdc_obio.c,v 1.1 2006/09/01 21:26:18 uwe Exp $	*/
+
+/*-
+ * Copyright (c) 1998, 2003 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Charles M. Hannum and by Onno van der Linden.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *        This product includes software developed by the NetBSD
+ *        Foundation, Inc. and its contributors.
+ * 4. Neither the name of The NetBSD Foundation nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/device.h>
+#include <sys/malloc.h>
+
+#include <machine/bus.h>
+#include <machine/intr.h>
+
+#include <dev/ata/atavar.h>
+#include <dev/ic/wdcvar.h>
+
+#include <landisk/dev/obiovar.h>
+
+struct wdc_obio_softc {
+	struct	wdc_softc sc_wdcdev;
+	struct	channel_softc *sc_chanptr;
+	struct	channel_softc sc_channel;
+
+	void	*sc_ih;
+};
+
+int	wdc_obio_match(struct device *, void *, void *);
+void	wdc_obio_attach(struct device *, struct device *, void *);
+
+struct cfattach wdc_obio_ca = {
+	sizeof(struct wdc_obio_softc), wdc_obio_match, wdc_obio_attach
+};
+
+#define	WDC_OBIO_REG_NPORTS	WDC_NREG
+#define	WDC_OBIO_REG_SIZE	(WDC_OBIO_REG_NPORTS * 2)
+#define	WDC_OBIO_AUXREG_NPORTS	1
+#define	WDC_OBIO_AUXREG_SIZE	(WDC_OBIO_AUXREG_NPORTS * 2)
+#define	WDC_OBIO_AUXREG_OFFSET	0x2c
+
+int
+wdc_obio_match(struct device *parent, void *vcf, void *aux)
+{
+	struct obio_attach_args *oa = aux;
+
+	if (oa->oa_nio != 1)
+		return (0);
+	if (oa->oa_nirq != 1)
+		return (0);
+	if (oa->oa_niomem != 0)
+		return (0);
+
+	if (oa->oa_io[0].or_addr == IOBASEUNK)
+		return (0);
+	if (oa->oa_irq[0].or_irq == IRQUNK)
+		return (0);
+
+	/* XXX should probe for hardware */
+
+	oa->oa_io[0].or_size = WDC_OBIO_REG_SIZE;
+
+	return (1);
+}
+
+void
+wdc_obio_attach(struct device *parent, struct device *self, void *aux)
+{
+	struct wdc_obio_softc *sc = (void *)self;
+	struct obio_attach_args *oa = aux;
+	struct channel_softc *chp = &sc->sc_channel;
+
+	printf("\n");
+
+	chp->cmd_iot = chp->ctl_iot = oa->oa_iot;
+
+	if (bus_space_map(chp->cmd_iot, oa->oa_io[0].or_addr,
+	    WDC_OBIO_REG_SIZE, 0, &chp->cmd_ioh)
+	 || bus_space_map(chp->ctl_iot,
+	    oa->oa_io[0].or_addr + WDC_OBIO_AUXREG_OFFSET,
+	    WDC_OBIO_AUXREG_SIZE, 0, &chp->ctl_ioh)) {
+		printf(": couldn't map registers\n");
+		return;
+	}
+	chp->data32iot = chp->cmd_iot;
+	chp->data32ioh = chp->cmd_ioh;
+
+	sc->sc_ih = obio_intr_establish(oa->oa_irq[0].or_irq, IPL_BIO, wdcintr,
+	    chp, self->dv_xname);
+
+	sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_PREATA;
+	sc->sc_wdcdev.PIO_cap = 0;
+	sc->sc_chanptr = chp;
+	sc->sc_wdcdev.channels = &sc->sc_chanptr;
+	sc->sc_wdcdev.nchannels = 1;
+	chp->channel = 0;
+	chp->wdc = &sc->sc_wdcdev;
+
+	chp->ch_queue = malloc(sizeof(struct channel_queue), M_DEVBUF,
+	    M_NOWAIT);
+	if (chp->ch_queue == NULL) {
+		printf("%s: can't allocate memory for command queue\n",
+		    self->dv_xname);
+		obio_intr_disestablish(sc->sc_ih);
+		return;
+	}
+
+	wdcattach(chp);
+	wdc_print_current_modes(chp);
+}
diff --git a/sys/arch/landisk/include/bus.h b/sys/arch/landisk/include/bus.h
index b91feb43364..1794cc96183 100644
--- a/sys/arch/landisk/include/bus.h
+++ b/sys/arch/landisk/include/bus.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: bus.h,v 1.1 2006/10/06 21:16:15 miod Exp $	*/
+/*	$OpenBSD: bus.h,v 1.2 2006/10/07 20:52:40 miod Exp $	*/
 /*	$NetBSD: bus.h,v 1.1 2006/09/01 21:26:18 uwe Exp $	*/
 
 /*-
@@ -136,7 +136,7 @@ struct _bus_space {
 	void *		(*bs_vaddr)(void *, bus_space_handle_t);
 
 	/* read (single) */
-	uint8_t	(*bs_r_1)(void *, bus_space_handle_t,
+	uint8_t		(*bs_r_1)(void *, bus_space_handle_t,
 			    bus_size_t);
 	uint16_t	(*bs_r_2)(void *, bus_space_handle_t,
 			    bus_size_t);
@@ -156,11 +156,11 @@ struct _bus_space {
 			    bus_size_t, uint64_t *, bus_size_t);
 
 	void		(*bs_rrm_2)(void *, bus_space_handle_t,
-			    bus_size_t, uint16_t *, bus_size_t);
+			    bus_size_t, uint8_t *, bus_size_t);
 	void		(*bs_rrm_4)(void *, bus_space_handle_t,
-			    bus_size_t, uint32_t *, bus_size_t);
+			    bus_size_t, uint8_t *, bus_size_t);
 	void		(*bs_rrm_8)(void *, bus_space_handle_t,
-			    bus_size_t, uint64_t *, bus_size_t);
+			    bus_size_t, uint8_t *, bus_size_t);
 
 	/* read region */
 	void		(*bs_rr_1)(void *, bus_space_handle_t,
diff --git a/sys/arch/landisk/landisk/shpcic_machdep.c b/sys/arch/landisk/landisk/shpcic_machdep.c
index 214aedc5e13..9cb723f06c5 100644
--- a/sys/arch/landisk/landisk/shpcic_machdep.c
+++ b/sys/arch/landisk/landisk/shpcic_machdep.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: shpcic_machdep.c,v 1.1 2006/10/06 21:16:15 miod Exp $	*/
+/*	$OpenBSD: shpcic_machdep.c,v 1.2 2006/10/07 20:52:40 miod Exp $	*/
 /*	$NetBSD: shpcic_machdep.c,v 1.1 2006/09/01 21:26:18 uwe Exp $	*/
 
 /*
@@ -187,10 +187,16 @@ struct _bus_space landisk_pci_bus_io =
 	.bs_rm_2 = shpcic_io_read_multi_2,
 	.bs_rm_4 = shpcic_io_read_multi_4,
 
+	.bs_rrm_2 = shpcic_io_read_raw_multi_2,
+	.bs_rrm_4 = shpcic_io_read_raw_multi_4,
+
 	.bs_rr_1 = shpcic_io_read_region_1,
 	.bs_rr_2 = shpcic_io_read_region_2,
 	.bs_rr_4 = shpcic_io_read_region_4,
 
+	.bs_rrr_2 = shpcic_io_read_raw_region_2,
+	.bs_rrr_4 = shpcic_io_read_raw_region_4,
+
 	.bs_w_1 = shpcic_io_write_1,
 	.bs_w_2 = shpcic_io_write_2,
 	.bs_w_4 = shpcic_io_write_4,
@@ -199,10 +205,16 @@ struct _bus_space landisk_pci_bus_io =
 	.bs_wm_2 = shpcic_io_write_multi_2,
 	.bs_wm_4 = shpcic_io_write_multi_4,
 
+	.bs_wrm_2 = shpcic_io_write_raw_multi_2,
+	.bs_wrm_4 = shpcic_io_write_raw_multi_4,
+
 	.bs_wr_1 = shpcic_io_write_region_1,
 	.bs_wr_2 = shpcic_io_write_region_2,
 	.bs_wr_4 = shpcic_io_write_region_4,
 
+	.bs_wrr_2 = shpcic_io_write_raw_region_2,
+	.bs_wrr_4 = shpcic_io_write_raw_region_4,
+
 	.bs_sm_1 = shpcic_io_set_multi_1,
 	.bs_sm_2 = shpcic_io_set_multi_2,
 	.bs_sm_4 = shpcic_io_set_multi_4,
@@ -235,10 +247,16 @@ struct _bus_space landisk_pci_bus_mem =
 	.bs_rm_2 = shpcic_mem_read_multi_2,
 	.bs_rm_4 = shpcic_mem_read_multi_4,
 
+	.bs_rrm_2 = shpcic_mem_read_raw_multi_2,
+	.bs_rrm_4 = shpcic_mem_read_raw_multi_4,
+
 	.bs_rr_1 = shpcic_mem_read_region_1,
 	.bs_rr_2 = shpcic_mem_read_region_2,
 	.bs_rr_4 = shpcic_mem_read_region_4,
 
+	.bs_rrr_2 = shpcic_mem_read_raw_region_2,
+	.bs_rrr_4 = shpcic_mem_read_raw_region_4,
+
 	.bs_w_1 = shpcic_mem_write_1,
 	.bs_w_2 = shpcic_mem_write_2,
 	.bs_w_4 = shpcic_mem_write_4,
@@ -247,10 +265,16 @@ struct _bus_space landisk_pci_bus_mem =
 	.bs_wm_2 = shpcic_mem_write_multi_2,
 	.bs_wm_4 = shpcic_mem_write_multi_4,
 
+	.bs_wrm_2 = shpcic_mem_write_raw_multi_2,
+	.bs_wrm_4 = shpcic_mem_write_raw_multi_4,
+
 	.bs_wr_1 = shpcic_mem_write_region_1,
 	.bs_wr_2 = shpcic_mem_write_region_2,
 	.bs_wr_4 = shpcic_mem_write_region_4,
 
+	.bs_wrr_2 = shpcic_mem_write_raw_region_2,
+	.bs_wrr_4 = shpcic_mem_write_raw_region_4,
+
 	.bs_sm_1 = shpcic_mem_set_multi_1,
 	.bs_sm_2 = shpcic_mem_set_multi_2,
 	.bs_sm_4 = shpcic_mem_set_multi_4,
diff --git a/sys/arch/sh/dev/shpcic.c b/sys/arch/sh/dev/shpcic.c
index c1357e2d708..fe94c98fb50 100644
--- a/sys/arch/sh/dev/shpcic.c
+++ b/sys/arch/sh/dev/shpcic.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: shpcic.c,v 1.1 2006/10/06 21:02:55 miod Exp $	*/
+/*	$OpenBSD: shpcic.c,v 1.2 2006/10/07 20:52:40 miod Exp $	*/
 /*	$NetBSD: shpcic.c,v 1.10 2005/12/24 20:07:32 perry Exp $	*/
 
 /*
@@ -600,7 +600,54 @@ shpcic_mem_read_multi_4(void *v, bus_space_handle_t bsh,
 }
 
 /*
- *
+ * read raw multi
+ */
+
+void
+shpcic_io_read_raw_multi_2(void *v, bus_space_handle_t bsh,
+    bus_size_t offset, uint8_t *addr, bus_size_t count)
+{
+	count >>= 1;
+	while (count--) {
+		*(uint16_t *)addr = __shpcic_io_read_2(bsh, offset);
+		addr += 2;
+	}
+}
+
+void
+shpcic_io_read_raw_multi_4(void *v, bus_space_handle_t bsh,
+    bus_size_t offset, uint8_t *addr, bus_size_t count)
+{
+	count >>= 2;
+	while (count--) {
+		*(uint32_t *)addr = __shpcic_io_read_4(bsh, offset);
+		addr += 4;
+	}
+}
+
+void
+shpcic_mem_read_raw_multi_2(void *v, bus_space_handle_t bsh,
+    bus_size_t offset, uint8_t *addr, bus_size_t count)
+{
+	count >>= 1;
+	while (count--) {
+		*(uint16_t *)addr = __shpcic_mem_read_2(bsh, offset);
+		addr += 2;
+	}
+}
+
+void
+shpcic_mem_read_raw_multi_4(void *v, bus_space_handle_t bsh,
+    bus_size_t offset, uint8_t *addr, bus_size_t count)
+{
+	count >>= 2;
+	while (count--) {
+		*(uint32_t *)addr = __shpcic_mem_read_4(bsh, offset);
+		addr += 4;
+	}
+}
+
+/*
  * read region
  */
 void
@@ -663,6 +710,58 @@ shpcic_mem_read_region_4(void *v, bus_space_handle_t bsh,
 	}
 }
 
+/*
+ * read raw region
+ */
+
+void
+shpcic_io_read_raw_region_2(void *v, bus_space_handle_t bsh,
+    bus_size_t offset, uint8_t *addr, bus_size_t count)
+{
+	count >>= 1;
+	while (count--) {
+		*(uint16_t *)addr = __shpcic_io_read_2(bsh, offset);
+		addr += 2;
+		offset += 2;
+	}
+}
+
+void
+shpcic_io_read_raw_region_4(void *v, bus_space_handle_t bsh,
+    bus_size_t offset, uint8_t *addr, bus_size_t count)
+{
+	count >>= 2;
+	while (count--) {
+		*(uint32_t *)addr = __shpcic_io_read_4(bsh, offset);
+		addr += 4;
+		offset += 4;
+	}
+}
+
+void
+shpcic_mem_read_raw_region_2(void *v, bus_space_handle_t bsh,
+    bus_size_t offset, uint8_t *addr, bus_size_t count)
+{
+	count >>= 1;
+	while (count--) {
+		*(uint16_t *)addr = __shpcic_mem_read_2(bsh, offset);
+		addr += 2;
+		offset += 2;
+	}
+}
+
+void
+shpcic_mem_read_raw_region_4(void *v, bus_space_handle_t bsh,
+    bus_size_t offset, uint8_t *addr, bus_size_t count)
+{
+	count >>= 2;
+	while (count--) {
+		*(uint32_t *)addr = __shpcic_mem_read_4(bsh, offset);
+		addr += 4;
+		offset += 4;
+	}
+}
+
 /* write */
 static inline void __shpcic_io_write_1(bus_space_handle_t bsh,
     bus_size_t offset, uint8_t value);
@@ -834,6 +933,54 @@ shpcic_mem_write_multi_4(void *v, bus_space_handle_t bsh,
 }
 
 /*
+ * write raw multi
+ */
+
+void
+shpcic_io_write_raw_multi_2(void *v, bus_space_handle_t bsh,
+    bus_size_t offset, const uint8_t *addr, bus_size_t count)
+{
+	count >>= 1;
+	while (count--) {
+		__shpcic_io_write_2(bsh, offset, *(uint16_t *)addr);
+		addr += 2;
+	}
+}
+
+void
+shpcic_io_write_raw_multi_4(void *v, bus_space_handle_t bsh,
+    bus_size_t offset, const uint8_t *addr, bus_size_t count)
+{
+	count >>= 2;
+	while (count--) {
+		__shpcic_io_write_4(bsh, offset, *(uint32_t *)addr);
+		addr += 4;
+	}
+}
+
+void
+shpcic_mem_write_raw_multi_2(void *v, bus_space_handle_t bsh,
+    bus_size_t offset, const uint8_t *addr, bus_size_t count)
+{
+	count >>= 1;
+	while (count--) {
+		__shpcic_mem_write_2(bsh, offset, *(uint16_t *)addr);
+		addr += 2;
+	}
+}
+
+void
+shpcic_mem_write_raw_multi_4(void *v, bus_space_handle_t bsh,
+    bus_size_t offset, const uint8_t *addr, bus_size_t count)
+{
+	count >>= 2;
+	while (count--) {
+		__shpcic_mem_write_4(bsh, offset, *(uint32_t *)addr);
+		addr += 4;
+	}
+}
+
+/*
  * write region
  */
 void
@@ -897,6 +1044,58 @@ shpcic_mem_write_region_4(void *v, bus_space_handle_t bsh,
 }
 
 /*
+ * write raw region
+ */
+
+void
+shpcic_io_write_raw_region_2(void *v, bus_space_handle_t bsh,
+    bus_size_t offset, const uint8_t *addr, bus_size_t count)
+{
+	count >>= 1;
+	while (count--) {
+		__shpcic_io_write_2(bsh, offset, *(uint16_t *)addr);
+		addr += 2;
+		offset += 2;
+	}
+}
+
+void
+shpcic_io_write_raw_region_4(void *v, bus_space_handle_t bsh,
+    bus_size_t offset, const uint8_t *addr, bus_size_t count)
+{
+	count >>= 1;
+	while (count--) {
+		__shpcic_io_write_4(bsh, offset, *(uint32_t *)addr);
+		addr += 4;
+		offset += 4;
+	}
+}
+
+void
+shpcic_mem_write_raw_region_2(void *v, bus_space_handle_t bsh,
+    bus_size_t offset, const uint8_t *addr, bus_size_t count)
+{
+	count >>= 1;
+	while (count--) {
+		__shpcic_mem_write_2(bsh, offset, *(uint16_t *)addr);
+		addr += 2;
+		offset += 2;
+	}
+}
+
+void
+shpcic_mem_write_raw_region_4(void *v, bus_space_handle_t bsh,
+    bus_size_t offset, const uint8_t *addr, bus_size_t count)
+{
+	count >>= 2;
+	while (count--) {
+		__shpcic_mem_write_4(bsh, offset, *(uint32_t *)addr);
+		addr += 4;
+		offset += 4;
+	}
+}
+
+/*
  * set multi
  */
 void
diff --git a/sys/arch/sh/dev/shpcicvar.h b/sys/arch/sh/dev/shpcicvar.h
index f000fec3084..2e2a2fa8d04 100644
--- a/sys/arch/sh/dev/shpcicvar.h
+++ b/sys/arch/sh/dev/shpcicvar.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: shpcicvar.h,v 1.1 2006/10/06 21:02:55 miod Exp $	*/
+/*	$OpenBSD: shpcicvar.h,v 1.2 2006/10/07 20:52:40 miod Exp $	*/
 /*	$NetBSD: shpcicvar.h,v 1.6 2005/12/11 12:18:58 christos Exp $	*/
 
 /*-
@@ -79,6 +79,16 @@ void shpcic_mem_read_multi_2(void *v, bus_space_handle_t bsh,
 void shpcic_mem_read_multi_4(void *v, bus_space_handle_t bsh,
     bus_size_t offset, uint32_t *addr, bus_size_t count);
 
+/* read raw multi */
+void shpcic_io_read_raw_multi_2(void *v, bus_space_handle_t bsh,
+    bus_size_t offset, uint8_t *addr, bus_size_t count);
+void shpcic_io_read_raw_multi_4(void *v, bus_space_handle_t bsh,
+    bus_size_t offset, uint8_t *addr, bus_size_t count);
+void shpcic_mem_read_raw_multi_2(void *v, bus_space_handle_t bsh,
+    bus_size_t offset, uint8_t *addr, bus_size_t count);
+void shpcic_mem_read_raw_multi_4(void *v, bus_space_handle_t bsh,
+    bus_size_t offset, uint8_t *addr, bus_size_t count);
+
 /* read region */
 void shpcic_io_read_region_1(void *v, bus_space_handle_t bsh,
     bus_size_t offset, uint8_t *addr, bus_size_t count);
@@ -93,6 +103,16 @@ void shpcic_mem_read_region_2(void *v, bus_space_handle_t bsh,
 void shpcic_mem_read_region_4(void *v, bus_space_handle_t bsh,
     bus_size_t offset, uint32_t *addr, bus_size_t count);
 
+/* read raw region */
+void shpcic_io_read_raw_region_2(void *v, bus_space_handle_t bsh,
+    bus_size_t offset, uint8_t *addr, bus_size_t count);
+void shpcic_io_read_raw_region_4(void *v, bus_space_handle_t bsh,
+    bus_size_t offset, uint8_t *addr, bus_size_t count);
+void shpcic_mem_read_raw_region_2(void *v, bus_space_handle_t bsh,
+    bus_size_t offset, uint8_t *addr, bus_size_t count);
+void shpcic_mem_read_raw_region_4(void *v, bus_space_handle_t bsh,
+    bus_size_t offset, uint8_t *addr, bus_size_t count);
+
 /* write single */
 void shpcic_io_write_1(void *v, bus_space_handle_t bsh,
     bus_size_t offset, uint8_t data);
@@ -121,6 +141,16 @@ void shpcic_mem_write_multi_2(void *v, bus_space_handle_t bsh,
 void shpcic_mem_write_multi_4(void *v, bus_space_handle_t bsh,
     bus_size_t offset, const uint32_t *addr, bus_size_t count);
 
+/* write raw multi */
+void shpcic_io_write_raw_multi_2(void *v, bus_space_handle_t bsh,
+    bus_size_t offset, const uint8_t *addr, bus_size_t count);
+void shpcic_io_write_raw_multi_4(void *v, bus_space_handle_t bsh,
+    bus_size_t offset, const uint8_t *addr, bus_size_t count);
+void shpcic_mem_write_raw_multi_2(void *v, bus_space_handle_t bsh,
+    bus_size_t offset, const uint8_t *addr, bus_size_t count);
+void shpcic_mem_write_raw_multi_4(void *v, bus_space_handle_t bsh,
+    bus_size_t offset, const uint8_t *addr, bus_size_t count);
+
 /* write region */
 void shpcic_io_write_region_1(void *v, bus_space_handle_t bsh,
     bus_size_t offset, const uint8_t *addr, bus_size_t count);
@@ -135,6 +165,16 @@ void shpcic_mem_write_region_2(void *v, bus_space_handle_t bsh,
 void shpcic_mem_write_region_4(void *v, bus_space_handle_t bsh,
     bus_size_t offset, const uint32_t *addr, bus_size_t count);
 
+/* write raw region */
+void shpcic_io_write_raw_region_2(void *v, bus_space_handle_t bsh,
+    bus_size_t offset, const uint8_t *addr, bus_size_t count);
+void shpcic_io_write_raw_region_4(void *v, bus_space_handle_t bsh,
+    bus_size_t offset, const uint8_t *addr, bus_size_t count);
+void shpcic_mem_write_raw_region_2(void *v, bus_space_handle_t bsh,
+    bus_size_t offset, const uint8_t *addr, bus_size_t count);
+void shpcic_mem_write_raw_region_4(void *v, bus_space_handle_t bsh,
+    bus_size_t offset, const uint8_t *addr, bus_size_t count);
+
 /* set multi */
 void shpcic_io_set_multi_1(void *v, bus_space_handle_t bsh,
     bus_size_t offset, uint8_t val, bus_size_t count);
diff --git a/sys/arch/sh/sh/clock.c b/sys/arch/sh/sh/clock.c
index 5db3106de69..cfe6788f6e1 100644
--- a/sys/arch/sh/sh/clock.c
+++ b/sys/arch/sh/sh/clock.c
@@ -1,3 +1,4 @@
+/*	$OpenBSD: clock.c,v 1.2 2006/10/07 20:52:40 miod Exp $	*/
 /*	$NetBSD: clock.c,v 1.32 2006/09/05 11:09:36 uwe Exp $	*/
 
 /*-
@@ -109,6 +110,7 @@ do {									\
 } while (/*CONSTCOND*/0)
 #define	TMU_ELAPSED(x)							\
 	(0xffffffff - _reg_read_4(SH_(TCNT ## x)))
+
 void
 sh_clock_init(int flags, struct rtc_ops *rtc)
 {
@@ -283,7 +285,8 @@ cpu_initclocks()
 	_reg_write_4(SH_(TCOR2), 0xffffffff);
 
 	/* Make sure to start RTC */
-	sh_clock.rtc.init(sh_clock.rtc._cookie);
+	if (sh_clock.rtc.init != NULL)
+		sh_clock.rtc.init(sh_clock.rtc._cookie);
 }
 
 void
diff --git a/sys/arch/sh/sh/sh_machdep.c b/sys/arch/sh/sh/sh_machdep.c
index 04594cdd493..bc40ee71b52 100644
--- a/sys/arch/sh/sh/sh_machdep.c
+++ b/sys/arch/sh/sh/sh_machdep.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: sh_machdep.c,v 1.3 2006/10/06 23:15:12 mickey Exp $	*/
+/*	$OpenBSD: sh_machdep.c,v 1.4 2006/10/07 20:52:40 miod Exp $	*/
 /*	$NetBSD: sh3_machdep.c,v 1.59 2006/03/04 01:13:36 uwe Exp $	*/
 
 /*-
@@ -152,8 +152,6 @@ long dumplo;	 		/* blocks */
 void
 sh_cpu_init(int arch, int product)
 {
-	int i;
-
 	/* CPU type */
 	cpu_arch = arch;
 	cpu_product = product;