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authorMichael Shalayeff <mickey@cvs.openbsd.org>2003-07-25 21:42:03 +0000
committerMichael Shalayeff <mickey@cvs.openbsd.org>2003-07-25 21:42:03 +0000
commit54a3a21a4606d783c77efd46eaa2e25a4b4229eb (patch)
treec5c39c793378a0362f5ce138119b1082ec9af9c5 /sys
parent1da5a507eebff4c5e5ceaeb3e2c5bb02247b2abd (diff)
s/CPUID_SYS2/CPUID_SEP/ to avoid confusion
Diffstat (limited to 'sys')
-rw-r--r--sys/arch/i386/i386/machdep.c8
-rw-r--r--sys/arch/i386/include/specialreg.h4
2 files changed, 6 insertions, 6 deletions
diff --git a/sys/arch/i386/i386/machdep.c b/sys/arch/i386/i386/machdep.c
index fd6d0a6dccd..9a2132f73bd 100644
--- a/sys/arch/i386/i386/machdep.c
+++ b/sys/arch/i386/i386/machdep.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: machdep.c,v 1.238 2003/07/25 17:41:19 tedu Exp $ */
+/* $OpenBSD: machdep.c,v 1.239 2003/07/25 21:42:02 mickey Exp $ */
/* $NetBSD: machdep.c,v 1.214 1996/11/10 03:16:17 thorpej Exp $ */
/*-
@@ -984,7 +984,7 @@ const struct cpu_cpuid_feature i386_cpuid_features[] = {
{ CPUID_CX8, "CX8" },
{ CPUID_APIC, "APIC" },
{ CPUID_SYS1, "SYS" },
- { CPUID_SYS2, "SYS" },
+ { CPUID_SEP, "SEP" },
{ CPUID_MTRR, "MTRR" },
{ CPUID_PGE, "PGE" },
{ CPUID_MCA, "MCA" },
@@ -1258,12 +1258,12 @@ intel686_cpu_setup(cpu_device, model, step)
* From Intel Application Note #485.
*/
if ((model == 1) && (step < 3))
- cpu_feature &= ~CPUID_SYS2;
+ cpu_feature &= ~CPUID_SEP;
/*
* Make sure SYSENTER is disabled.
*/
- if (cpu_feature & CPUID_SYS2)
+ if (cpu_feature & CPUID_SEP)
wrmsr(MSR_SYSENTER_CS, 0);
/*
diff --git a/sys/arch/i386/include/specialreg.h b/sys/arch/i386/include/specialreg.h
index 4876dec9eae..3c5dd045a57 100644
--- a/sys/arch/i386/include/specialreg.h
+++ b/sys/arch/i386/include/specialreg.h
@@ -1,4 +1,4 @@
-/* $OpenBSD: specialreg.h,v 1.15 2003/07/25 17:41:18 tedu Exp $ */
+/* $OpenBSD: specialreg.h,v 1.16 2003/07/25 21:42:02 mickey Exp $ */
/* $NetBSD: specialreg.h,v 1.7 1994/10/27 04:16:26 cgd Exp $ */
/*-
@@ -99,7 +99,7 @@
#define CPUID_CX8 0x00000100 /* has CMPXCHG8B instruction */
#define CPUID_APIC 0x00000200 /* has enabled APIC */
#define CPUID_SYS1 0x00000400 /* has SYSCALL/SYSRET inst. (Cyrix) */
-#define CPUID_SYS2 0x00000800 /* has SYSCALL/SYSRET inst. (AMD/Intel) */
+#define CPUID_SEP 0x00000800 /* has SYSCALL/SYSRET inst. (AMD/Intel) */
#define CPUID_MTRR 0x00001000 /* has memory type range register */
#define CPUID_PGE 0x00002000 /* has page global extension */
#define CPUID_MCA 0x00004000 /* has machine check architecture */