diff options
| author | Owain Ainsworth <oga@cvs.openbsd.org> | 2009-05-24 01:40:59 +0000 |
|---|---|---|
| committer | Owain Ainsworth <oga@cvs.openbsd.org> | 2009-05-24 01:40:59 +0000 |
| commit | 666eaba82d7e6355f951dadbe98fbf44cb6e03c0 (patch) | |
| tree | 3d30d26256c22c8161fa08130de33cb132c82fc4 /sys | |
| parent | b1b471866bd1bcf489ec3badc2924fb42b49e2e3 (diff) | |
Instead of using magic numbers, define the bits that we set in gtt ptes
and use those defines.
Diffstat (limited to 'sys')
| -rw-r--r-- | sys/dev/pci/agp_i810.c | 19 |
1 files changed, 15 insertions, 4 deletions
diff --git a/sys/dev/pci/agp_i810.c b/sys/dev/pci/agp_i810.c index 3b1a18346ee..5bf42fe13af 100644 --- a/sys/dev/pci/agp_i810.c +++ b/sys/dev/pci/agp_i810.c @@ -1,4 +1,4 @@ -/* $OpenBSD: agp_i810.c,v 1.52 2009/05/10 16:57:44 oga Exp $ */ +/* $OpenBSD: agp_i810.c,v 1.53 2009/05/24 01:40:58 oga Exp $ */ /*- * Copyright (c) 2000 Doug Rabson @@ -51,6 +51,16 @@ #define READ4(off) bus_space_read_4(isc->map->bst, isc->map->bsh, off) #define WRITE4(off,v) bus_space_write_4(isc->map->bst, isc->map->bsh, off, v) +/* + * Intel IGP gtt bits. + */ +/* PTE is enabled */ +#define INTEL_ENABLED 0x1 +/* I810/I815 only, memory is in dcache */ +#define INTEL_LOCAL 0x2 +/* Memory is snooped, must not be accessed through gtt from the cpu. */ +#define INTEL_COHERENT 0x6 + enum { CHIP_NONE = 0, /* not integrated graphics */ CHIP_I810 = 1, /* i810/i815 */ @@ -653,7 +663,8 @@ agp_i810_bind_memory(void *sc, struct agp_memory *mem, bus_size_t offset) if (regval != (isc->gatt->ag_physical | 1)) { printf("agp_i810_bind_memory: PGTBL_CTL is 0x%x - fixing\n", regval); - WRITE4(AGP_I810_PGTBL_CTL, isc->gatt->ag_physical | 1); + WRITE4(AGP_I810_PGTBL_CTL, isc->gatt->ag_physical | + INTEL_ENABLED); } if (mem->am_type == 2) { @@ -671,7 +682,7 @@ agp_i810_bind_memory(void *sc, struct agp_memory *mem, bus_size_t offset) return (EINVAL); for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) - intagp_write_gtt(isc, i, i | 3); + intagp_write_gtt(isc, i, i | INTEL_ENABLED | INTEL_LOCAL); mem->am_is_bound = 1; return (0); } @@ -712,7 +723,7 @@ intagp_write_gtt(struct agp_i810_softc *isc, bus_size_t off, paddr_t v) bus_size_t baseoff, wroff; if (v != 0) { - pte = v | 1; + pte = v | INTEL_ENABLED; /* 965+ can do 36-bit addressing, add in the extra bits */ if (isc->chiptype == CHIP_I965 || isc->chiptype == CHIP_G4X) pte |= (v & 0x0000000f00000000ULL) >> 28; |