diff options
| author | Miod Vallat <miod@cvs.openbsd.org> | 2004-04-24 19:51:50 +0000 |
|---|---|---|
| committer | Miod Vallat <miod@cvs.openbsd.org> | 2004-04-24 19:51:50 +0000 |
| commit | 915c9097dfba70544f63ef9ade9d5057a9309f73 (patch) | |
| tree | 6ca709504e608d4dcf774401f54ec8d6d23610c1 /sys | |
| parent | ec053ecdd6fe18ab575f9b48eeebce50e5d161cf (diff) | |
Preliminary switch to an mvme88k bus_space world. Not all drivers have been
converted yet, and they rely upon some linear mappings provided by bus_space.
In order to not impact performance, almost all the bus_space accesses go
through macros and inline functions. This currently restricts us to D16 and
D32 access modes, which are selected at compilation time. Since there are no
plans to support D8 vme devices in the future, this is acceptable for now.
This makes the "len" locator for vme devices go away, and allows to simplify
some code which was using the pcctwo device, and will now directly access
hardware which is known to exist, rather than wait until the device is
attached.
While there, try to enforce more interrupt vector number checks, since these
changes pointed out that dart(4) had been working correctly so far by sheer
luck only.
Diffstat (limited to 'sys')
40 files changed, 3075 insertions, 2386 deletions
diff --git a/sys/arch/mvme88k/conf/GENERIC b/sys/arch/mvme88k/conf/GENERIC index c2277030c50..ae2d606f820 100644 --- a/sys/arch/mvme88k/conf/GENERIC +++ b/sys/arch/mvme88k/conf/GENERIC @@ -1,4 +1,4 @@ -# $OpenBSD: GENERIC,v 1.39 2004/01/05 20:07:59 miod Exp $ +# $OpenBSD: GENERIC,v 1.40 2004/04/24 19:51:44 miod Exp $ machine mvme88k @@ -30,7 +30,7 @@ bugtty0 at mainbus0 pcctwo0 at mainbus0 addr 0xfff00000 # MVME187 bussw0 at mainbus0 addr 0xfff00000 # MVME197 sram0 at mainbus0 addr 0xffe00000 # MVME187 -pcctwo0 at bussw0 offset 0x42000 # MVME197 +pcctwo0 at bussw0 offset 0x00000 # MVME197 clock0 at pcctwo0 ipl 5 nvram0 at pcctwo0 offset 0xc0000 vme0 at pcctwo0 offset 0x40000 @@ -52,19 +52,19 @@ vme0 at syscon0 offset 0x85000 vmes0 at vme0 vmel0 at vme0 -vx0 at vmes0 addr 0xff780000 ipl 3 len 0x10000 -vx1 at vmes0 addr 0xff790000 ipl 3 len 0x10000 -vx2 at vmes0 addr 0xff7a0000 ipl 3 len 0x10000 -vx3 at vmes0 addr 0xff7b0000 ipl 3 len 0x10000 -le0 at vmes0 addr 0xffff1200 ipl 1 len 0x100 -le1 at vmes0 addr 0xffff1400 ipl 1 len 0x100 -le2 at vmes0 addr 0xffff1600 ipl 1 len 0x100 -vs0 at vmes0 addr 0xffff9000 ipl 2 len 0x800 -vs1 at vmes0 addr 0xffff9800 ipl 2 len 0x800 -vs2 at vmes0 addr 0xffff4800 ipl 2 len 0x800 -vs3 at vmes0 addr 0xffff5800 ipl 2 len 0x800 -vs4 at vmes0 addr 0xffff7000 ipl 2 len 0x800 -vs5 at vmes0 addr 0xffff7800 ipl 2 len 0x800 +vx0 at vmes0 addr 0xff780000 ipl 3 +vx1 at vmes0 addr 0xff790000 ipl 3 +vx2 at vmes0 addr 0xff7a0000 ipl 3 +vx3 at vmes0 addr 0xff7b0000 ipl 3 +le0 at vmes0 addr 0xffff1200 ipl 1 +le1 at vmes0 addr 0xffff1400 ipl 1 +le2 at vmes0 addr 0xffff1600 ipl 1 +vs0 at vmes0 addr 0xffff9000 ipl 2 +vs1 at vmes0 addr 0xffff9800 ipl 2 +vs2 at vmes0 addr 0xffff4800 ipl 2 +vs3 at vmes0 addr 0xffff5800 ipl 2 +vs4 at vmes0 addr 0xffff7000 ipl 2 +vs5 at vmes0 addr 0xffff7800 ipl 2 scsibus* at vs? scsibus* at ssh? diff --git a/sys/arch/mvme88k/conf/M187 b/sys/arch/mvme88k/conf/M187 index 50db5ddbd80..d35ff8fe42d 100644 --- a/sys/arch/mvme88k/conf/M187 +++ b/sys/arch/mvme88k/conf/M187 @@ -1,4 +1,4 @@ -# $OpenBSD: M187,v 1.27 2004/01/05 20:07:59 miod Exp $ +# $OpenBSD: M187,v 1.28 2004/04/24 19:51:44 miod Exp $ machine mvme88k @@ -41,19 +41,19 @@ vmes0 at vme0 vmel0 at vme0 # ------------------------------ vmes0 devices ------------------------- -vx0 at vmes0 addr 0xff780000 ipl 3 len 0x10000 -vx1 at vmes0 addr 0xff790000 ipl 3 len 0x10000 -vx2 at vmes0 addr 0xff7a0000 ipl 3 len 0x10000 -vx3 at vmes0 addr 0xff7b0000 ipl 3 len 0x10000 -le0 at vmes0 addr 0xffff1200 ipl 1 len 0x100 -le1 at vmes0 addr 0xffff1400 ipl 1 len 0x100 -le2 at vmes0 addr 0xffff1600 ipl 1 len 0x100 -vs0 at vmes0 addr 0xffff9000 ipl 2 len 0x800 -vs1 at vmes0 addr 0xffff9800 ipl 2 len 0x800 -vs2 at vmes0 addr 0xffff4800 ipl 2 len 0x800 -vs3 at vmes0 addr 0xffff5800 ipl 2 len 0x800 -vs4 at vmes0 addr 0xffff7000 ipl 2 len 0x800 -vs5 at vmes0 addr 0xffff7800 ipl 2 len 0x800 +vx0 at vmes0 addr 0xff780000 ipl 3 +vx1 at vmes0 addr 0xff790000 ipl 3 +vx2 at vmes0 addr 0xff7a0000 ipl 3 +vx3 at vmes0 addr 0xff7b0000 ipl 3 +le0 at vmes0 addr 0xffff1200 ipl 1 +le1 at vmes0 addr 0xffff1400 ipl 1 +le2 at vmes0 addr 0xffff1600 ipl 1 +vs0 at vmes0 addr 0xffff9000 ipl 2 +vs1 at vmes0 addr 0xffff9800 ipl 2 +vs2 at vmes0 addr 0xffff4800 ipl 2 +vs3 at vmes0 addr 0xffff5800 ipl 2 +vs4 at vmes0 addr 0xffff7000 ipl 2 +vs5 at vmes0 addr 0xffff7800 ipl 2 # ------------------------------- vs0 devices -------------------------- scsibus* at vs? diff --git a/sys/arch/mvme88k/conf/M188 b/sys/arch/mvme88k/conf/M188 index dbaf7986884..70de9ff7096 100644 --- a/sys/arch/mvme88k/conf/M188 +++ b/sys/arch/mvme88k/conf/M188 @@ -1,4 +1,4 @@ -# $OpenBSD: M188,v 1.20 2003/12/27 23:58:08 miod Exp $ +# $OpenBSD: M188,v 1.21 2004/04/24 19:51:44 miod Exp $ machine mvme88k @@ -35,19 +35,19 @@ vmes0 at vme0 vmel0 at vme0 # ------------------------------ vmes0 devices ------------------------- -vx0 at vmes0 addr 0xff780000 ipl 3 len 0x10000 -vx1 at vmes0 addr 0xff790000 ipl 3 len 0x10000 -vx2 at vmes0 addr 0xff7a0000 ipl 3 len 0x10000 -vx3 at vmes0 addr 0xff7b0000 ipl 3 len 0x10000 -le0 at vmes0 addr 0xffff1200 ipl 1 len 0x100 -le1 at vmes0 addr 0xffff1400 ipl 1 len 0x100 -le2 at vmes0 addr 0xffff1600 ipl 1 len 0x100 -vs0 at vmes0 addr 0xffff9000 ipl 2 len 0x800 -vs1 at vmes0 addr 0xffff9800 ipl 2 len 0x800 -vs2 at vmes0 addr 0xffff4800 ipl 2 len 0x800 -vs3 at vmes0 addr 0xffff5800 ipl 2 len 0x800 -vs4 at vmes0 addr 0xffff7000 ipl 2 len 0x800 -vs5 at vmes0 addr 0xffff7800 ipl 2 len 0x800 +vx0 at vmes0 addr 0xff780000 ipl 3 +vx1 at vmes0 addr 0xff790000 ipl 3 +vx2 at vmes0 addr 0xff7a0000 ipl 3 +vx3 at vmes0 addr 0xff7b0000 ipl 3 +le0 at vmes0 addr 0xffff1200 ipl 1 +le1 at vmes0 addr 0xffff1400 ipl 1 +le2 at vmes0 addr 0xffff1600 ipl 1 +vs0 at vmes0 addr 0xffff9000 ipl 2 +vs1 at vmes0 addr 0xffff9800 ipl 2 +vs2 at vmes0 addr 0xffff4800 ipl 2 +vs3 at vmes0 addr 0xffff5800 ipl 2 +vs4 at vmes0 addr 0xffff7000 ipl 2 +vs5 at vmes0 addr 0xffff7800 ipl 2 # ------------------------------- vs0 devices -------------------------- scsibus* at vs? diff --git a/sys/arch/mvme88k/conf/M197 b/sys/arch/mvme88k/conf/M197 index 33b8b675af4..5e84ca75a65 100644 --- a/sys/arch/mvme88k/conf/M197 +++ b/sys/arch/mvme88k/conf/M197 @@ -1,4 +1,4 @@ -# $OpenBSD: M197,v 1.21 2003/12/27 23:58:08 miod Exp $ +# $OpenBSD: M197,v 1.22 2004/04/24 19:51:44 miod Exp $ machine mvme88k @@ -25,7 +25,7 @@ bugtty0 at mainbus0 bussw0 at mainbus0 addr 0xfff00000 # ----------------------------- busswitch devices ----------------------- -pcctwo0 at bussw0 offset 0x42000 +pcctwo0 at bussw0 offset 0x00000 # ------------------------------ pcctwo devices ------------------------- clock0 at pcctwo0 ipl 5 @@ -43,19 +43,19 @@ vmes0 at vme0 vmel0 at vme0 # ------------------------------ vmes0 devices ------------------------- -vx0 at vmes0 addr 0xff780000 ipl 3 len 0x10000 -vx1 at vmes0 addr 0xff790000 ipl 3 len 0x10000 -vx2 at vmes0 addr 0xff7a0000 ipl 3 len 0x10000 -vx3 at vmes0 addr 0xff7b0000 ipl 3 len 0x10000 -le0 at vmes0 addr 0xffff1200 ipl 1 len 0x100 -le1 at vmes0 addr 0xffff1400 ipl 1 len 0x100 -le2 at vmes0 addr 0xffff1600 ipl 1 len 0x100 -vs0 at vmes0 addr 0xffff9000 ipl 2 len 0x800 -vs1 at vmes0 addr 0xffff9800 ipl 2 len 0x800 -vs2 at vmes0 addr 0xffff4800 ipl 2 len 0x800 -vs3 at vmes0 addr 0xffff5800 ipl 2 len 0x800 -vs4 at vmes0 addr 0xffff7000 ipl 2 len 0x800 -vs5 at vmes0 addr 0xffff7800 ipl 2 len 0x800 +vx0 at vmes0 addr 0xff780000 ipl 3 +vx1 at vmes0 addr 0xff790000 ipl 3 +vx2 at vmes0 addr 0xff7a0000 ipl 3 +vx3 at vmes0 addr 0xff7b0000 ipl 3 +le0 at vmes0 addr 0xffff1200 ipl 1 +le1 at vmes0 addr 0xffff1400 ipl 1 +le2 at vmes0 addr 0xffff1600 ipl 1 +vs0 at vmes0 addr 0xffff9000 ipl 2 +vs1 at vmes0 addr 0xffff9800 ipl 2 +vs2 at vmes0 addr 0xffff4800 ipl 2 +vs3 at vmes0 addr 0xffff5800 ipl 2 +vs4 at vmes0 addr 0xffff7000 ipl 2 +vs5 at vmes0 addr 0xffff7800 ipl 2 # ------------------------------- vs0 devices -------------------------- scsibus* at vs? diff --git a/sys/arch/mvme88k/conf/RAMDISK b/sys/arch/mvme88k/conf/RAMDISK index c8ed4f42482..a7310e9dacb 100644 --- a/sys/arch/mvme88k/conf/RAMDISK +++ b/sys/arch/mvme88k/conf/RAMDISK @@ -1,4 +1,4 @@ -# $OpenBSD: RAMDISK,v 1.20 2004/01/12 13:15:34 miod Exp $ +# $OpenBSD: RAMDISK,v 1.21 2004/04/24 19:51:44 miod Exp $ machine mvme88k @@ -40,7 +40,7 @@ bussw0 at mainbus0 addr 0xfff00000 pcctwo0 at mainbus0 addr 0xfff00000 syscon0 at mainbus0 addr 0xfff00000 -pcctwo0 at bussw0 offset 0x42000 +pcctwo0 at bussw0 offset 0x00000 clock0 at pcctwo0 ipl 5 vme0 at pcctwo0 offset 0x40000 @@ -58,19 +58,19 @@ vme0 at syscon0 offset 0x85000 vmes0 at vme0 #vmel0 at vme0 -#vx0 at vmes0 addr 0xff780000 ipl 3 len 0x10000 -#vx1 at vmes0 addr 0xff790000 ipl 3 len 0x10000 -#vx2 at vmes0 addr 0xff7a0000 ipl 3 len 0x10000 -#vx3 at vmes0 addr 0xff7b0000 ipl 3 len 0x10000 -le0 at vmes0 addr 0xffff1200 ipl 1 len 0x100 -le1 at vmes0 addr 0xffff1400 ipl 1 len 0x100 -le2 at vmes0 addr 0xffff1600 ipl 1 len 0x100 -vs0 at vmes0 addr 0xffff9000 ipl 2 len 0x800 -vs1 at vmes0 addr 0xffff9800 ipl 2 len 0x800 -vs2 at vmes0 addr 0xffff4800 ipl 2 len 0x800 -vs3 at vmes0 addr 0xffff5800 ipl 2 len 0x800 -vs4 at vmes0 addr 0xffff7000 ipl 2 len 0x800 -vs5 at vmes0 addr 0xffff7800 ipl 2 len 0x800 +#vx0 at vmes0 addr 0xff780000 ipl 3 +#vx1 at vmes0 addr 0xff790000 ipl 3 +#vx2 at vmes0 addr 0xff7a0000 ipl 3 +#vx3 at vmes0 addr 0xff7b0000 ipl 3 +le0 at vmes0 addr 0xffff1200 ipl 1 +le1 at vmes0 addr 0xffff1400 ipl 1 +le2 at vmes0 addr 0xffff1600 ipl 1 +vs0 at vmes0 addr 0xffff9000 ipl 2 +vs1 at vmes0 addr 0xffff9800 ipl 2 +vs2 at vmes0 addr 0xffff4800 ipl 2 +vs3 at vmes0 addr 0xffff5800 ipl 2 +vs4 at vmes0 addr 0xffff7000 ipl 2 +vs5 at vmes0 addr 0xffff7800 ipl 2 scsibus* at vs? scsibus* at ssh? diff --git a/sys/arch/mvme88k/conf/files.mvme88k b/sys/arch/mvme88k/conf/files.mvme88k index 169090baece..723cb448f29 100644 --- a/sys/arch/mvme88k/conf/files.mvme88k +++ b/sys/arch/mvme88k/conf/files.mvme88k @@ -1,4 +1,4 @@ -# $OpenBSD: files.mvme88k,v 1.25 2004/01/13 21:29:21 miod Exp $ +# $OpenBSD: files.mvme88k,v 1.26 2004/04/24 19:51:44 miod Exp $ # maxpartitions 16 @@ -27,12 +27,11 @@ file arch/mvme88k/dev/memc.c memc device sram attach sram at mainbus +file arch/mvme88k/dev/sram.c sram needs-count device nvram attach nvram at pcctwo, syscon -file arch/mvme88k/dev/sram.c sram needs-count file arch/mvme88k/dev/nvram.c nvram needs-count -file arch/mvme88k/dev/memdevs.c nvram | sram device cl: tty attach cl at pcctwo @@ -61,9 +60,9 @@ file arch/mvme88k/dev/ssh.c ssh device vme { } attach vme at pcctwo, syscon -device vmes { [addr = -1], [len = -1], [vec = -1], [ipl = 0] } +device vmes { [addr = -1], [vec = -1], [ipl = 0] } attach vmes at vme -device vmel { [addr = -1], [len = -1], [vec = -1], [ipl = 0] } +device vmel { [addr = -1], [vec = -1], [ipl = 0] } attach vmel at vme file arch/mvme88k/dev/vme.c vme | vmes | vmel file arch/mvme88k/dev/vmes.c vmes needs-count @@ -103,8 +102,9 @@ file arch/mvme88k/ddb/db_disasm.c ddb file arch/mvme88k/ddb/db_interface.c ddb file arch/mvme88k/ddb/db_sstep.c ddb file arch/mvme88k/ddb/db_trace.c ddb -file arch/mvme88k/dev/mainbus.c file arch/mvme88k/dev/bugio.c +file arch/mvme88k/dev/mainbus.c +file arch/mvme88k/dev/memdevs.c nvram | sram attach ie at pcctwo: ifnet, ether file arch/mvme88k/dev/if_ie.c ie diff --git a/sys/arch/mvme88k/dev/bussw.c b/sys/arch/mvme88k/dev/bussw.c index 5cb31f6f72a..1368cfd9a0d 100644 --- a/sys/arch/mvme88k/dev/bussw.c +++ b/sys/arch/mvme88k/dev/bussw.c @@ -1,5 +1,4 @@ -/* $OpenBSD: bussw.c,v 1.12 2004/04/14 13:43:13 miod Exp $ */ - +/* $OpenBSD: bussw.c,v 1.13 2004/04/24 19:51:47 miod Exp $ */ /* * Copyright (c) 1999 Steve Murphree, Jr. * @@ -39,14 +38,13 @@ #include <machine/vmparam.h> #include <mvme88k/dev/busswreg.h> -#include <mvme88k/dev/busswfunc.h> struct bussw_softc { struct device sc_dev; - void * sc_paddr; - void * sc_vaddr; + paddr_t sc_base; struct intrhand sc_abih; /* `abort' switch */ - struct bussw_reg *sc_bussw; + bus_space_tag_t sc_iot; + bus_space_handle_t sc_ioh; }; void bussw_attach(struct device *, struct device *, void *); @@ -60,9 +58,10 @@ struct cfdriver bussw_cd = { NULL, "bussw", DV_DULL }; -int bussw_print(void *args, const char *bus); -int bussw_scan(struct device *parent, void *child, void *args); -int busswabort(void *); +int bussw_print(void *, const char *); +int bussw_scan(struct device *, void *, void *); +int busswabort(void *); +int busswintr_establish(int, struct intrhand *); int bussw_match(parent, vcf, args) @@ -70,17 +69,29 @@ bussw_match(parent, vcf, args) void *vcf, *args; { struct confargs *ca = args; - struct bussw_reg *bussw; + bus_space_handle_t ioh; + int rc; + u_int8_t chipid; /* Don't match if wrong cpu */ if (brdtyp != BRD_197) - return (0); - - bussw = (struct bussw_reg *)(IIOV(ca->ca_paddr)); - if (badvaddr((vaddr_t)bussw, 4)) - return (0); + return 0; + + if (bus_space_map(ca->ca_iot, ca->ca_paddr, BS_SIZE, 0, &ioh) != 0) + return 0; + rc = badvaddr((vaddr_t)bus_space_vaddr(ca->ca_iot, ioh), 4); + if (rc == 0) { + chipid = bus_space_read_1(ca->ca_iot, ioh, BS_CHIPID); + if (chipid != BUSSWITCH_ID) { +#ifdef DEBUG + printf("==> busswitch: wrong chip id %x\n", chipid); +#endif + rc = -1; + } + } + bus_space_unmap(ca->ca_iot, ioh, BS_SIZE); - return (1); + return rc == 0; } void @@ -90,23 +101,37 @@ bussw_attach(parent, self, args) { struct confargs *ca = args; struct bussw_softc *sc = (struct bussw_softc *)self; - struct bussw_reg *bs; + bus_space_handle_t ioh; + + if (bus_space_map(ca->ca_iot, ca->ca_paddr, BS_SIZE, 0, &ioh) != 0) { + printf(": can't map registers!\n"); + return; + } + + sc->sc_iot = ca->ca_iot; + sc->sc_ioh = ioh; + sc->sc_base = ca->ca_paddr; + + bus_space_write_1(sc->sc_iot, ioh, BS_VBASE, + bus_space_read_1(sc->sc_iot, ioh, BS_VBASE) | BS_VECBASE); + bus_space_write_2(sc->sc_iot, ioh, BS_GCSR, + bus_space_read_2(sc->sc_iot, ioh, BS_GCSR) | BS_GCSR_XIPL); - sc->sc_vaddr = sc->sc_paddr = ca->ca_paddr; - bs = sc->sc_bussw = (struct bussw_reg *)sc->sc_vaddr; - bs->bs_intr2 |= BS_VECBASE; - bs->bs_gcsr |= BS_GCSR_XIPL; /* * pseudo driver, abort interrupt handler - */ + */ sc->sc_abih.ih_fn = busswabort; sc->sc_abih.ih_arg = 0; sc->sc_abih.ih_wantframe = 1; - sc->sc_abih.ih_ipl = IPL_NMI; /* level 8!! */ + sc->sc_abih.ih_ipl = IPL_NMI; + busswintr_establish(BS_ABORTIRQ, &sc->sc_abih); - bs->bs_intr1 |= BS_INTR1_ABORT_IEN; + bus_space_write_1(sc->sc_iot, ioh, BS_ABORT, + bus_space_read_4(sc->sc_iot, ioh, BS_ABORT) | BS_ABORT_IEN); + + printf(": rev %x\n", + bus_space_read_1(sc->sc_iot, ioh, BS_CHIPREV)); - printf(": rev %ld\n", BS_CHIPREV(bs)); config_search(bussw_scan, self, args); } @@ -134,17 +159,15 @@ bussw_scan(parent, child, args) struct confargs oca; bzero(&oca, sizeof oca); + oca.ca_iot = sc->sc_iot; oca.ca_offset = cf->cf_loc[0]; oca.ca_ipl = cf->cf_loc[1]; - if (((int)oca.ca_offset != -1) && ISIIOVA(sc->sc_vaddr + oca.ca_offset)) { - oca.ca_vaddr = sc->sc_vaddr + oca.ca_offset; - oca.ca_paddr = sc->sc_paddr + oca.ca_offset; + if (oca.ca_offset != -1) { + oca.ca_paddr = sc->sc_base + oca.ca_offset; } else { - oca.ca_vaddr = (void *)-1; - oca.ca_paddr = (void *)-1; + oca.ca_paddr = -1; } oca.ca_bustype = BUS_BUSSWITCH; - oca.ca_master = (void *)sc->sc_bussw; oca.ca_name = cf->cf_driver->cd_name; if ((*cf->cf_attach->ca_match)(parent, cf, &oca) == 0) return (0); @@ -157,11 +180,12 @@ busswintr_establish(vec, ih) int vec; struct intrhand *ih; { - if (vec >= BS_NVEC) { - printf("bussw: illegal vector: 0x%x\n", vec); - panic("busswintr_establish"); - } - return (intr_establish(BS_VECBASE+vec, ih)); +#ifdef DIAGNOSTIC + if (vec < 0 || vec >= BS_NVEC) + panic("busswintr_establish: illegal vector 0x%x\n", vec); +#endif + + return (intr_establish(BS_VECBASE + vec, ih)); } int @@ -171,13 +195,14 @@ busswabort(eframe) struct frame *frame = eframe; struct bussw_softc *sc = (struct bussw_softc *)bussw_cd.cd_devs[0]; - struct bussw_reg *bs = sc->sc_bussw; + u_int8_t abort; - if (bs->bs_intr1 & BS_INTR1_ABORT_INT) { - bs->bs_intr1 |= BS_INTR1_ABORT_ICLR; + abort = bus_space_read_1(sc->sc_iot, sc->sc_ioh, BS_ABORT); + if (abort & BS_ABORT_INT) { + bus_space_write_1(sc->sc_iot, sc->sc_ioh, BS_ABORT, + abort | BS_ABORT_ICLR); nmihand(frame); return 1; } return 0; } - diff --git a/sys/arch/mvme88k/dev/busswfunc.h b/sys/arch/mvme88k/dev/busswfunc.h deleted file mode 100644 index 9be2d17309b..00000000000 --- a/sys/arch/mvme88k/dev/busswfunc.h +++ /dev/null @@ -1,9 +0,0 @@ -/* $OpenBSD: busswfunc.h,v 1.4 2002/03/14 01:26:39 millert Exp $ */ - -#ifndef _MVME88K_BUSSWF_H_ -#define _MVME88K_BUSSWF_H_ - -int busswintr_establish(int vec, struct intrhand *ih); - -#endif /* _MVME88K_PCCTWO_H_ */ - diff --git a/sys/arch/mvme88k/dev/busswreg.h b/sys/arch/mvme88k/dev/busswreg.h index 06eea179daf..e7935f16d96 100644 --- a/sys/arch/mvme88k/dev/busswreg.h +++ b/sys/arch/mvme88k/dev/busswreg.h @@ -1,81 +1,87 @@ -/* $OpenBSD: busswreg.h,v 1.5 2004/04/14 20:17:21 miod Exp $ */ +/* $OpenBSD: busswreg.h,v 1.6 2004/04/24 19:51:47 miod Exp $ */ /* * Memory map for BusSwitch chip found in mvme197 boards. */ -#ifndef BUSSWREG_H -#define BUSSWREG_H -#define BS_BASE 0xFFF00000 - -struct bussw_reg { - volatile u_long bs_gcsr; - volatile u_short bs_iodata; - volatile u_short bs_iodir; - volatile u_short bs_psar1; - volatile u_short bs_pear1; - volatile u_short bs_psar2; - volatile u_short bs_pear2; - volatile u_short bs_psar3; - volatile u_short bs_pear3; - volatile u_short bs_psar4; - volatile u_short bs_pear4; - volatile u_short bs_ptr1; - volatile u_short bs_ptsr1; - volatile u_short bs_ptr2; - volatile u_short bs_ptsr2; - volatile u_short bs_ptr3; - volatile u_short bs_ptsr3; - volatile u_short bs_ptr4; - volatile u_short bs_ptsr4; - volatile u_short bs_ssar1; - volatile u_short bs_sear1; - volatile u_short bs_ssar2; - volatile u_short bs_sear2; - volatile u_short bs_ssar3; - volatile u_short bs_sear3; - volatile u_short bs_ssar4; - volatile u_short bs_sear4; - volatile u_short bs_str1; - volatile u_short bs_stsr1; - volatile u_short bs_str2; - volatile u_short bs_stsr2; - volatile u_short bs_str3; - volatile u_short bs_stsr3; - volatile u_short bs_str4; - volatile u_short bs_stsr4; - volatile u_long bs_par; - volatile u_long bs_sar; - volatile u_long bs_btimer; - volatile u_long bs_pal; - volatile u_long bs_wppa; - volatile u_long bs_wp; - volatile u_long bs_romcr; - volatile u_long bs_lmi; - volatile u_long bs_intr1; - volatile u_long bs_intr2; - volatile u_long bs_tcomp1; - volatile u_long bs_tcount1; - volatile u_long bs_tcomp2; - volatile u_long bs_tcount2; - volatile u_long bs_gpr1; - volatile u_long bs_gpr2; - volatile u_long bs_gpr3; - volatile u_long bs_gpr4; - volatile u_long bs_xctags; - volatile u_int8_t bs_res[(0x100 - 0x94)]; - volatile u_long bs_xccr; - volatile u_long bs_vec1; - volatile u_long bs_vec2; - volatile u_long bs_vec3; - volatile u_long bs_vec4; - volatile u_long bs_vec5; - volatile u_long bs_vec6; - volatile u_long bs_vec7; -}; +#ifndef BUSSWREG_H +#define BUSSWREG_H + +#define BS_BASE 0xfff00000 +#define BS_SIZE 0x00000120 + +#define BS_CHIPID 0x0000 +#define BS_CHIPREV 0x0001 +#define BS_GCSR 0x0002 +#define BS_IODATA 0x0004 +#define BS_IODIR 0x0006 +#define BS_PSAR1 0x0008 +#define BS_PEAR1 0x000a +#define BS_PSAR2 0x000c +#define BS_PEAR2 0x000e +#define BS_PSAR3 0x0010 +#define BS_PEAR3 0x0012 +#define BS_PSAR4 0x0014 +#define BS_PEAR4 0x0016 +#define BS_PTR1 0x0018 +#define BS_PTSR1 0x001a +#define BS_PTR2 0x001c +#define BS_PTSR2 0x001e +#define BS_PTR3 0x0020 +#define BS_PTSR3 0x0022 +#define BS_PTR4 0x0024 +#define BS_PTSR4 0x0026 +#define BS_SSAR1 0x0028 +#define BS_SEAR1 0x002a +#define BS_SSAR2 0x002c +#define BS_SEAR2 0x002e +#define BS_SSAR3 0x0030 +#define BS_SEAR3 0x0032 +#define BS_SSAR4 0x0034 +#define BS_SEAR4 0x0036 +#define BS_STR1 0x0038 +#define BS_STSR1 0x003a +#define BS_STR2 0x003c +#define BS_STSR2 0x003e +#define BS_STR3 0x0040 +#define BS_STSR3 0x0042 +#define BS_STR4 0x0044 +#define BS_STSR4 0x0046 +#define BS_PAR 0x0048 +#define BS_SAR 0x004c +#define BS_BTIMER 0x0051 +#define BS_PADJUST 0x0052 +#define BS_PCOUNT 0x0053 +#define BS_PAL 0x0054 +#define BS_WPPA 0x0058 +#define BS_WPTPA 0x005c +#define BS_WPPAT 0x005e +#define BS_ROMCR 0x0060 +#define BS_TCTRL1 0x0062 +#define BS_TCTRL2 0x0063 +#define BS_LEVEL 0x0064 +#define BS_MASK 0x0065 +#define BS_ISEL0 0x0066 +#define BS_ISEL1 0x0067 +#define BS_ABORT 0x0068 +#define BS_CPINT 0x0069 +#define BS_TINT1 0x006a +#define BS_TINT2 0x006b +#define BS_WPINT 0x006c +#define BS_PALINT 0x006d +#define BS_XINT 0x006e +#define BS_VBASE 0x006f +#define BS_TCOMP1 0x0070 +#define BS_TCOUNT1 0x0074 +#define BS_TCOMP2 0x0078 +#define BS_TCOUNT2 0x007c +#define BS_GPR 0x0080 +#define BS_XCTAGS 0x0090 +#define BS_XCCR 0x0100 +#define BS_VEC 0x0104 + +#define BUSSWITCH_ID 0x21 /* value at CHIPID */ /* GCSR bit definitions */ -#define BS_CHIPID(x) (((x)->bs_gcsr & 0xFF000000) >> 16) -#define BS_CHIPREV(x) (((x)->bs_gcsr & 0x00FF0000) >> 16) #define BS_GCSR_APRI0 0x00000001 /* Bus Request 0 Priority indicator (CPU0)*/ #define BS_GCSR_APRI1 0x00000002 /* Bus Request 1 Priority indicator (CPU1)*/ #define BS_GCSR_APRI2 0x00000003 /* Bus Request 2 Priority indicator (mc88410)*/ @@ -109,10 +115,10 @@ struct bussw_reg { #define BS_BTIMER_SBTD (0x03 << 2) /* System Bus Timout, disable */ /* Prescaler Adjust values */ -#define BS_PADJUST_50 0xCE /* 50 MHz clock */ -#define BS_PADJUST_40 0xD8 /* 40 MHz clock */ -#define BS_PADJUST_33 0xDF /* 33 MHz clock */ -#define BS_PADJUST_25 0xE7 /* 25 MHz clock */ +#define BS_PADJUST_50 0xce /* 50 MHz clock */ +#define BS_PADJUST_40 0xd8 /* 40 MHz clock */ +#define BS_PADJUST_33 0xdf /* 33 MHz clock */ +#define BS_PADJUST_25 0xe7 /* 25 MHz clock */ /* ROM Control Register bit definitions */ #define BS_ROMCR_WEN0 0x01000000 @@ -126,34 +132,56 @@ struct bussw_reg { #define BS_XCC_FBSY 0x00000004 #define BS_XCC_DIAG 0x00000008 -/* - * INTR1 - Abort Control Register - * Cross Processor Interrupt Register - * Timer Interrupt 1 Register - * Timer Interrupt 2 Register - */ -#define BS_INTR1_ABORT_ICLR 0x08000000 /* abort interrupt clear */ -#define BS_INTR1_ABORT_IEN 0x10000000 /* abort interrupt enable */ -#define BS_INTR1_ABORT_INT 0x20000000 /* abort interrupt received */ -#define BS_INTR1_ABORT_ABT 0x40000000 /* abort interrupt asserted */ - -#define BS_INTR1_CPI_ICLR 0x00080000 /* cpi interrupt clear */ -#define BS_INTR1_CPI_IEN 0x00100000 /* cpi interrupt enable */ -#define BS_INTR1_CPI_INT 0x00200000 /* cpi interrupt received */ -#define BS_INTR1_CPI_STAT 0x00400000 /* cpi interrupt status */ -#define BS_INTR1_CPI_SCPI 0x00800000 /* send cross proc interrupt */ - -#define BS_INTR1_TINT1_ICLR 0x00000800 /* timer 1 interrupt clear */ -#define BS_INTR1_TINT1_IEN 0x00001000 /* timer 1 interrupt enable */ -#define BS_INTR1_TINT1_INT 0x00002000 /* timer 1 interrupt received */ -#define BS_INTR1_TINT1_LM 0x00000700 /* timer 1 level mask */ -#define BS_INTR1_TINT1_LEVEL(x) ((x << 8) & BS_INTR1_TINT1_LM) - -#define BS_INTR1_TINT2_ICLR 0x00000008 /* timer 1 interrupt clear */ -#define BS_INTR1_TINT2_IEN 0x00000010 /* timer 1 interrupt enable */ -#define BS_INTR1_TINT2_INT 0x00000020 /* timer 1 interrupt received */ -#define BS_INTR1_TINT2_LM 0x00000007 /* timer 1 level mask */ -#define BS_INTR1_TINT2_LEVEL(x) (x & BS_INTR1_TINT2_LM) +/* Abort Control Register */ +#define BS_ABORT_ICLR 0x08 /* abort interrupt clear */ +#define BS_ABORT_IEN 0x10 /* abort interrupt enable */ +#define BS_ABORT_INT 0x20 /* abort interrupt received */ +#define BS_ABORT_ABT 0x40 /* abort interrupt asserted */ + +/* Cross Processor Interrupt Register */ +#define BS_CPI_ICLR 0x08 /* cpi interrupt clear */ +#define BS_CPI_IEN 0x10 /* cpi interrupt enable */ +#define BS_CPI_INT 0x20 /* cpi interrupt received */ +#define BS_CPI_STAT 0x40 /* cpi interrupt status */ +#define BS_CPI_SCPI 0x80 /* send cross proc interrupt */ + +/* Timer Interrupt 1 Register */ +#define BS_TINT1_ICLR 0x08 /* timer 1 interrupt clear */ +#define BS_TINT1_IEN 0x10 /* timer 1 interrupt enable */ +#define BS_TINT1_INT 0x20 /* timer 1 interrupt received */ +#define BS_TINT1_LM 0x07 /* timer 1 level mask */ +#define BS_TINT1_LEVEL(x) (x & BS_TINT1_LM) + +/* Timer Interrupt 2 Register */ +#define BS_TINT2_ICLR 0x08 /* timer 1 interrupt clear */ +#define BS_TINT2_IEN 0x10 /* timer 1 interrupt enable */ +#define BS_TINT2_INT 0x20 /* timer 1 interrupt received */ +#define BS_TINT2_LM 0x07 /* timer 1 level mask */ +#define BS_TINT2_LEVEL(x) (x & BS_TINT2_LM) + +/* Write Post Control Register */ +#define BS_WPINT_ICLR 0x08 /* WPINT interrupt clear */ +#define BS_WPINT_IEN 0x10 /* WPINT interrupt enable */ +#define BS_WPINT_INT 0x20 /* WPINT interrupt received */ +#define BS_WPINT_LM 0x07 /* WPINT level mask */ +#define BS_WPINT_LEVEL(x) (x & BS_WPINT_LM) + +/* Processor Address Log Interrupt Register */ +#define BS_PALINT_ICLR 0x00 /* PALINT interrupt clear */ +#define BS_PALINT_IEN 0x10 /* PALINT interrupt enable */ +#define BS_PALINT_INT 0x20 /* PALINT interrupt received */ +#define BS_PALINT_PLTY 0x80 /* PALINT polarity */ +#define BS_PALINT_LM 0x07 /* PALINT level mask */ +#define BS_PALINT_LEVEL(x) (x & BS_PALINT_LM) + +/* External Interrupt Register */ +#define BS_XINT_ICLR 0x00 /* XINT interrupt clear */ +#define BS_XINT_IEN 0x10 /* XINT interrupt enable */ +#define BS_XINT_INT 0x20 /* XINT interrupt received */ +#define BS_XINT_EL 0x40 /* XINT edge/level */ +#define BS_XINT_PLTY 0x80 /* XINT polarity */ +#define BS_XINT_LM 0x07 /* XINT level mask */ +#define BS_XINT_LEVEL(x) (x & BS_XINT_LM) /* Vector Base Register (A read upon an interrupt reveals the source) */ #define BS_VBASE_SRC_TMR1 0x0 @@ -163,36 +191,9 @@ struct bussw_reg { #define BS_VBASE_SRC_EXT 0x4 /* external interrupt */ #define BS_VBASE_SRC_SPUR 0x7 /* spurious interrupt */ -/* - * INTR2 - Write Post Control Register - * Processor Address Log Interrupt Register - * External Interrupt Register - * Vector Base - */ -#define BS_INTR2_WPINT_ICLR 0x08000000 /* WPINT interrupt clear */ -#define BS_INTR2_WPINT_IEN 0x10000000 /* WPINT interrupt enable */ -#define BS_INTR2_WPINT_INT 0x20000000 /* WPINT interrupt received */ -#define BS_INTR2_WPINT_LM 0x07000000 /* WPINT level mask */ -#define BS_INTR2_WPINT_LEVEL(x) ((x << 24) & BS_INTR2_WPINT_LM) - -#define BS_INTR2_PALINT_ICLR 0x00080000 /* PALINT interrupt clear */ -#define BS_INTR2_PALINT_IEN 0x00100000 /* PALINT interrupt enable */ -#define BS_INTR2_PALINT_INT 0x00200000 /* PALINT interrupt received */ -#define BS_INTR2_PALINT_PLTY 0x00800000 /* PALINT polarity */ -#define BS_INTR2_PALINT_LM 0x00070000 /* PALINT level mask */ -#define BS_INTR2_PALINT_LEVEL(x) ((x << 16) & BS_INTR2_PALINT_LM) - -#define BS_INTR2_XINT_ICLR 0x00000800 /* XINT interrupt clear */ -#define BS_INTR2_XINT_IEN 0x00001000 /* XINT interrupt enable */ -#define BS_INTR2_XINT_INT 0x00002000 /* XINT interrupt received */ -#define BS_INTR2_XINT_EL 0x00004000 /* XINT edge/level */ -#define BS_INTR2_XINT_PLTY 0x00008000 /* XINT polarity */ -#define BS_INTR2_XINT_LM 0x00000700 /* XINT level mask */ -#define BS_INTR2_XINT_LEVEL(x) ((x << 24) & BS_INTR2_XINT_LM) - /* We lock off BusSwitch vectors at 0x40 */ #define BS_VECBASE 0x40 -#define BS_NVEC 16 +#define BS_NVEC 0x10 /* Bottom 4 bits of the vector returned during IACK cycle */ #define BS_TMR1IRQ 0x01 /* lowest */ @@ -202,4 +203,4 @@ struct bussw_reg { /* Define the Abort vector */ #define BS_ABORTVEC (BS_VECBASE | BS_ABORTIRQ) -#endif /* BUSSWREG_H */ +#endif /* BUSSWREG_H */ diff --git a/sys/arch/mvme88k/dev/cl.c b/sys/arch/mvme88k/dev/cl.c index f55b48dbfee..889d6c77053 100644 --- a/sys/arch/mvme88k/dev/cl.c +++ b/sys/arch/mvme88k/dev/cl.c @@ -1,4 +1,4 @@ -/* $OpenBSD: cl.c,v 1.43 2004/04/16 23:32:44 miod Exp $ */ +/* $OpenBSD: cl.c,v 1.44 2004/04/24 19:51:47 miod Exp $ */ /* * Copyright (c) 1995 Dale Rahn. All rights reserved. @@ -46,6 +46,7 @@ #include <mvme88k/dev/clreg.h> #include <mvme88k/dev/pcctworeg.h> +#include <mvme88k/dev/pcctwovar.h> #ifdef DDB #include <ddb/db_var.h> @@ -67,10 +68,10 @@ #define CL_RXINTR 0x02 struct cl_cons { - void *cl_paddr; - struct clreg *volatile cl_vaddr; - struct pcctworeg *volatile pcctwoaddr; - u_char channel; + bus_space_tag_t cl_iot; + bus_space_handle_t cl_ioh; + volatile u_int8_t *cl_rxiack; + u_int8_t channel; } cl_cons; struct cl_info { @@ -84,7 +85,9 @@ struct cl_info { u_char cl_txmode; u_char cl_clen; u_char cl_parity; +#if 0 u_char transmitting; +#endif u_long txcnt; u_long rxcnt; @@ -103,21 +106,19 @@ char cl_dmabuf1[CLCD_PORTS_PER_CHIP * CL_BUFSIZE * 4]; #endif struct clsoftc { - struct device sc_dev; - struct evcnt sc_txintrcnt; - struct evcnt sc_rxintrcnt; - struct evcnt sc_mxintrcnt; - time_t sc_rotime; /* time of last ring overrun */ - time_t sc_fotime; /* time of last fifo overrun */ - u_char *pbase; - struct clreg *cl_reg; + struct device sc_dev; + bus_space_tag_t sc_iot; + bus_space_handle_t sc_ioh; + struct evcnt sc_txintrcnt; + struct evcnt sc_rxintrcnt; + struct evcnt sc_mxintrcnt; + time_t sc_fotime; /* time of last fifo overrun */ struct cl_info sc_cl[CLCD_PORTS_PER_CHIP]; struct intrhand sc_ih_e; struct intrhand sc_ih_m; struct intrhand sc_ih_t; struct intrhand sc_ih_r; - struct pcctworeg *sc_pcctwo; - int sc_flags; + struct pcctwosoftc *sc_pcctwo; }; const struct { @@ -144,12 +145,14 @@ const struct { { 0, 0x00, 0, 0}, }; +#define CL_SAFE_CLOCK 4 /* 9600 entry */ + /* prototypes */ cons_decl(cl); int cl_instat(struct clsoftc *sc); -u_char cl_clkdiv(int speed); -u_char cl_clknum(int speed); -u_char cl_clkrxtimeout(int speed); +u_int8_t cl_clkdiv(int speed); +u_int8_t cl_clknum(int speed); +u_int8_t cl_clkrxtimeout(int speed); void clstart(struct tty *tp); void cl_unblock(struct tty *tp); int clccparam(struct clsoftc *sc, struct termios *par, int channel); @@ -164,15 +167,14 @@ void cl_frame(struct clsoftc *sc, int channel); void cl_break( struct clsoftc *sc, int channel); int clmctl(dev_t dev, int bits, int how); #ifdef DEBUG -void cl_dumpport(int channel); +void cl_dumpport(struct clsoftc *, int); #endif int clprobe(struct device *parent, void *self, void *aux); void clattach(struct device *parent, struct device *self, void *aux); -void cl_initchannel(struct clsoftc *sc, int channel); -void clputc(struct clsoftc *sc, int unit, u_char c); -u_char clgetc(struct clsoftc *sc, int *channel); +void cl_initchannel(struct clsoftc *sc, int channel); +void clputc(struct clsoftc *sc, int unit, u_char c); struct cfattach cl_ca = { sizeof(struct clsoftc), clprobe, clattach @@ -200,7 +202,7 @@ cltty(dev) unit = CL_UNIT(dev); if (unit >= cl_cd.cd_ndevs || (sc = (struct clsoftc *)cl_cd.cd_devs[unit]) == NULL) { - return (NULL); + return NULL; } channel = CL_CHANNEL(dev); return sc->sc_cl[channel].tty; @@ -212,25 +214,27 @@ clprobe(parent, self, aux) void *self; void *aux; { - struct clreg *cl_reg; struct confargs *ca = aux; + bus_space_handle_t ioh; + int rc; if (brdtyp == BRD_188) - return (0); + return 0; /* * We do not accept empty locators here... */ - if ((vaddr_t)ca->ca_paddr == CD2400_BASE_ADDR || - ((vaddr_t)ca->ca_paddr == CD2400_SECONDARY_ADDR && - brdtyp == BRD_8120)) { - ca->ca_ipl = IPL_TTY; - ca->ca_vaddr = ca->ca_paddr; + if (ca->ca_paddr == CD2400_BASE_ADDR || + (ca->ca_paddr == CD2400_SECONDARY_ADDR && brdtyp == BRD_8120)) { + if (bus_space_map(ca->ca_iot, ca->ca_paddr, CD2400_SIZE, + 0, &ioh) != 0) + return 0; + rc = badvaddr((vaddr_t)bus_space_vaddr(ca->ca_iot, ioh), 1); + bus_space_unmap(ca->ca_iot, ca->ca_paddr, CD2400_SIZE); + return rc == 0; + } - cl_reg = (struct clreg *)ca->ca_vaddr; - return (!badvaddr((vaddr_t)&cl_reg->cl_gfrcr, 1)); - } else - return (0); + return 0; } void @@ -241,31 +245,41 @@ clattach(parent, self, aux) { struct clsoftc *sc = (struct clsoftc *)self; struct confargs *ca = aux; + bus_space_tag_t iot; + bus_space_handle_t ioh; int i; - sc->cl_reg = (struct clreg *)ca->ca_vaddr; - sc->sc_pcctwo = ca->ca_master; + if (ca->ca_ipl < 0) + ca->ca_ipl = IPL_TTY; + + iot = sc->sc_iot = ca->ca_iot; + if (bus_space_map(iot, ca->ca_paddr, CD2400_SIZE, 0, &ioh) != 0) { + printf(": can't map registers!\n"); + return; + } + sc->sc_ioh = ioh; + sc->sc_pcctwo = (struct pcctwosoftc *)parent; - if ((paddr_t)ca->ca_paddr == CD2400_BASE_ADDR) { + if (ca->ca_paddr == CD2400_BASE_ADDR) { /* * Although we are still running using the BUG routines, * this device will be elected as the console after * autoconf. Mark it as such. */ sc->sc_cl[0].cl_consio = 1; - printf(": console "); + printf(": console"); } else { /* reset chip only if we are not console device */ /* wait for GFRCR */ } - /* allow chip to settle before continuing */ - delay(800); + /* allow chip to settle before continuing */ + delay(800); /* set up global registers */ - sc->cl_reg->cl_tpr = CL_TIMEOUT; - sc->cl_reg->cl_rpilr = 0x03; - sc->cl_reg->cl_tpilr = 0x02; - sc->cl_reg->cl_mpilr = 0x01; + bus_space_write_1(iot, ioh, CL_TPR, CL_TIMEOUT); + bus_space_write_1(iot, ioh, CL_RPILR, 0x03); + bus_space_write_1(iot, ioh, CL_TPILR, 0x02); + bus_space_write_1(iot, ioh, CL_MPILR, 0x01); #ifdef DO_MALLOC sc->sc_cl[0].rx[0] = (void *)(dvma_malloc(16 * CL_BUFSIZE)); @@ -317,6 +331,11 @@ clattach(parent, self, aux) #endif cl_initchannel(sc, i); } + + /* clear errors */ + bus_space_write_1(sc->sc_pcctwo->sc_iot, sc->sc_pcctwo->sc_ioh, + PCCTWO_SCCERR, 0x01); + /* enable interrupts */ sc->sc_ih_e.ih_fn = cl_rxintr; sc->sc_ih_e.ih_arg = sc; @@ -338,21 +357,22 @@ clattach(parent, self, aux) sc->sc_ih_e.ih_wantframe = 0; sc->sc_ih_r.ih_ipl = ca->ca_ipl; - intr_establish(PCC2_VECT + SRXEIRQ, &sc->sc_ih_e); - intr_establish(PCC2_VECT + SMOIRQ, &sc->sc_ih_m); - intr_establish(PCC2_VECT + STxIRQ, &sc->sc_ih_t); - intr_establish(PCC2_VECT + SRxIRQ, &sc->sc_ih_r); - sc->sc_pcctwo = ca->ca_master; - sc->sc_pcctwo->pcc2_sccerr = 0x01; /* clear errors */ + pcctwointr_establish(PCC2V_SCC_RXE, &sc->sc_ih_e); + pcctwointr_establish(PCC2V_SCC_M, &sc->sc_ih_m); + pcctwointr_establish(PCC2V_SCC_TX, &sc->sc_ih_t); + pcctwointr_establish(PCC2V_SCC_RX, &sc->sc_ih_r); - /* enable all interrupts at ca_ipl */ - sc->sc_pcctwo->pcc2_sccirq = 0x10 | (ca->ca_ipl & 0x7); - sc->sc_pcctwo->pcc2_scctx = 0x10 | (ca->ca_ipl & 0x7); - sc->sc_pcctwo->pcc2_sccrx = 0x10 | (ca->ca_ipl & 0x7); + bus_space_write_1(sc->sc_pcctwo->sc_iot, sc->sc_pcctwo->sc_ioh, + PCCTWO_SCCICR, PCC2_IRQ_IEN | (ca->ca_ipl & PCC2_IRQ_IPL)); + bus_space_write_1(sc->sc_pcctwo->sc_iot, sc->sc_pcctwo->sc_ioh, + PCCTWO_SCCTX, PCC2_IRQ_IEN | (ca->ca_ipl & PCC2_IRQ_IPL)); + bus_space_write_1(sc->sc_pcctwo->sc_iot, sc->sc_pcctwo->sc_ioh, + PCCTWO_SCCRX, PCC2_IRQ_IEN | (ca->ca_ipl & PCC2_IRQ_IPL)); evcnt_attach(&sc->sc_dev, "intr", &sc->sc_txintrcnt); evcnt_attach(&sc->sc_dev, "intr", &sc->sc_rxintrcnt); evcnt_attach(&sc->sc_dev, "intr", &sc->sc_mxintrcnt); + printf("\n"); } @@ -362,43 +382,49 @@ cl_initchannel(sc, channel) int channel; { int s; - struct clreg *cl_reg = sc->cl_reg; + bus_space_tag_t iot; + bus_space_handle_t ioh; + + iot = sc->sc_iot; + ioh = sc->sc_ioh; + /* set up option registers */ sc->sc_cl[channel].tty = NULL; s = splhigh(); - cl_reg->cl_car = (u_char) channel; - cl_reg->cl_livr = PCC2_VECT + 0xc;/* set vector base at 5C */ - cl_reg->cl_ier = 0x00; - /* if the port is not the console, should be init for all ports??*/ - if (sc->sc_cl[channel].cl_consio != 1) { - cl_reg->cl_cmr = 0x02; - cl_reg->cl_cor1 = 0x17; - cl_reg->cl_cor2 = 0x00; - cl_reg->cl_cor3 = 0x02; - cl_reg->cl_cor4 = 0xec; - cl_reg->cl_cor5 = 0xec; - cl_reg->cl_cor6 = 0x00; - cl_reg->cl_cor7 = 0x00; - cl_reg->cl_schr1 = 0x00; - cl_reg->cl_schr2 = 0x00; - cl_reg->cl_schr3 = 0x00; - cl_reg->cl_schr4 = 0x00; - cl_reg->cl_scrl = 0x00; - cl_reg->cl_scrh = 0x00; - cl_reg->cl_lnxt = 0x00; - cl_reg->cl_rbpr = 0x40; /* 9600 */ - cl_reg->cl_rcor = 0x01; - cl_reg->cl_tbpr = 0x40; /* 9600 */ - cl_reg->cl_tcor = 0x01 << 5; + + bus_space_write_1(iot, ioh, CL_CAR, channel); + bus_space_write_1(iot, ioh, CL_LIVR, PCC2_VECT + PCC2V_SCC_RXE); + bus_space_write_1(iot, ioh, CL_IER, 0); + + if (sc->sc_cl[channel].cl_consio == 0) { + bus_space_write_1(iot, ioh, CL_CMR, 0x02); + bus_space_write_1(iot, ioh, CL_COR1, 0x17); + bus_space_write_1(iot, ioh, CL_COR2, 0x00); + bus_space_write_1(iot, ioh, CL_COR3, 0x02); + bus_space_write_1(iot, ioh, CL_COR4, 0xec); + bus_space_write_1(iot, ioh, CL_COR5, 0xec); + bus_space_write_1(iot, ioh, CL_COR6, 0x00); + bus_space_write_1(iot, ioh, CL_COR7, 0x00); + bus_space_write_1(iot, ioh, CL_SCHR1, 0x00); + bus_space_write_1(iot, ioh, CL_SCHR2, 0x00); + bus_space_write_1(iot, ioh, CL_SCHR3, 0x00); + bus_space_write_1(iot, ioh, CL_SCHR4, 0x00); + bus_space_write_1(iot, ioh, CL_SCRL, 0x00); + bus_space_write_1(iot, ioh, CL_SCRH, 0x00); + bus_space_write_1(iot, ioh, CL_LNXT, 0x00); + bus_space_write_1(iot, ioh, CL_RBPR, 0x40); /* 9600 */ + bus_space_write_1(iot, ioh, CL_RCOR, 0x01); + bus_space_write_1(iot, ioh, CL_TBPR, 0x40); /* 9600 */ + bus_space_write_1(iot, ioh, CL_TCOR, 0x01 << 5); /* console port should be 0x88 already */ - cl_reg->cl_msvr_rts = 0x00; - cl_reg->cl_msvr_dtr = 0x00; - cl_reg->cl_rtprl = CL_RX_TIMEOUT; - cl_reg->cl_rtprh = 0x00; - } - sc->cl_reg->cl_ccr = 0x20; - while (sc->cl_reg->cl_ccr != 0) { + bus_space_write_1(iot, ioh, CL_MSVR_RTS, 0x00); + bus_space_write_1(iot, ioh, CL_MSVR_DTR, 0x00); + bus_space_write_1(iot, ioh, CL_RTPRL, CL_RX_TIMEOUT); + bus_space_write_1(iot, ioh, CL_RTPRH, 0x00); } + bus_space_write_1(iot, ioh, CL_CCR, 0x20); + while (bus_space_read_1(iot, ioh, CL_CCR) != 0) + ; splx(s); } @@ -412,71 +438,63 @@ clmctl(dev, bits, how) int bits; int how; { - int s; struct clsoftc *sc; + bus_space_tag_t iot; + bus_space_handle_t ioh; + int s; + /* should only be called with valid device */ - sc = (struct clsoftc *) cl_cd.cd_devs[CL_UNIT(dev)]; - /* - printf("mctl: dev %x, bits %x, how %x,\n",dev, bits, how); - */ + sc = (struct clsoftc *)cl_cd.cd_devs[CL_UNIT(dev)]; + iot = sc->sc_iot; + ioh = sc->sc_ioh; + /* settings are currently ignored */ s = splcl(); switch (how) { case DMSET: - if( bits & TIOCM_RTS) { - sc->cl_reg->cl_msvr_rts = 0x01; - } else { - sc->cl_reg->cl_msvr_rts = 0x00; - } - if( bits & TIOCM_DTR) { - sc->cl_reg->cl_msvr_dtr = 0x02; - } else { - sc->cl_reg->cl_msvr_dtr = 0x00; - } + if (bits & TIOCM_RTS) + bus_space_write_1(iot, ioh, CL_MSVR_RTS, 0x01); + else + bus_space_write_1(iot, ioh, CL_MSVR_RTS, 0x00); + if (bits & TIOCM_DTR) + bus_space_write_1(iot, ioh, CL_MSVR_DTR, 0x02); + else + bus_space_write_1(iot, ioh, CL_MSVR_DTR, 0x00); break; case DMBIC: - if( bits & TIOCM_RTS) { - sc->cl_reg->cl_msvr_rts = 0x00; - } - if( bits & TIOCM_DTR) { - sc->cl_reg->cl_msvr_dtr = 0x00; - } + if (bits & TIOCM_RTS) + bus_space_write_1(iot, ioh, CL_MSVR_RTS, 0x00); + if (bits & TIOCM_DTR) + bus_space_write_1(iot, ioh, CL_MSVR_DTR, 0x00); break; case DMBIS: - if( bits & TIOCM_RTS) { - sc->cl_reg->cl_msvr_rts = 0x01; - } - if( bits & TIOCM_DTR) { - sc->cl_reg->cl_msvr_dtr = 0x02; - } + if (bits & TIOCM_RTS) + bus_space_write_1(iot, ioh, CL_MSVR_RTS, 0x01); + if (bits & TIOCM_DTR) + bus_space_write_1(iot, ioh, CL_MSVR_DTR, 0x02); break; case DMGET: bits = 0; { - u_char msvr; - msvr = sc->cl_reg->cl_msvr_rts; - if( msvr & 0x80) { + u_int8_t msvr; + + msvr = bus_space_read_1(iot, ioh, CL_MSVR_RTS); + if (msvr & 0x80) bits |= TIOCM_DSR; - } - if( msvr & 0x40) { + if (msvr & 0x40) bits |= TIOCM_CD; - } - if( msvr & 0x20) { + if (msvr & 0x20) bits |= TIOCM_CTS; - } - if( msvr & 0x10) { + if (msvr & 0x10) bits |= TIOCM_DTR; - } - if( msvr & 0x02) { + if (msvr & 0x02) bits |= TIOCM_DTR; - } - if( msvr & 0x01) { + if (msvr & 0x01) bits |= TIOCM_RTS; - } } break; } @@ -492,10 +510,7 @@ clmctl(dev, bits, how) bits |= TIOCM_DSR; #endif - /* - printf("retbits %x\n", bits); - */ - return(bits); + return bits; } int @@ -512,11 +527,13 @@ clopen(dev, flag, mode, p) unit = CL_UNIT(dev); if (unit >= cl_cd.cd_ndevs || - (sc = (struct clsoftc *) cl_cd.cd_devs[unit]) == NULL) { - return (ENODEV); + (sc = (struct clsoftc *)cl_cd.cd_devs[unit]) == NULL) { + return ENODEV; } + channel = CL_CHANNEL(dev); cl = &sc->sc_cl[channel]; + s = splcl(); if (cl->tty) { tp = cl->tty; @@ -539,7 +556,7 @@ clopen(dev, flag, mode, p) tp->t_lflag = TTYDEF_LFLAG; tp->t_ispeed = tp->t_ospeed = cldefaultrate; - if(sc->sc_cl[channel].cl_consio == 1) { + if (sc->sc_cl[channel].cl_consio != 0) { /* console is 8N1 */ tp->t_cflag = (CREAD | CS8 | HUPCL); } else { @@ -569,76 +586,30 @@ clopen(dev, flag, mode, p) #endif tp->t_state |= TS_CARR_ON; { - u_char save = sc->cl_reg->cl_car; - sc->cl_reg->cl_car = channel; - sc->cl_reg->cl_ier = 0x88; -#ifdef CL_DMA_WORKS - { - sc->cl_reg->cl_cmr = - /* CL_TXDMAINT | */ CL_RXDMAINT; - sc->cl_reg->cl_ier = 0xa8; - sc->cl_reg->cl_licr = 0x00; - } - sc->cl_reg->cl_arbadrl = - ((u_long)sc->sc_cl[channel].rxp[0]) & 0xffff; - sc->cl_reg->cl_arbadru = - ((u_long)sc->sc_cl[channel].rxp[0]) >> 16; - sc->cl_reg->cl_brbadrl = - ((u_long)sc->sc_cl[channel].rxp[1]) & 0xffff; - sc->cl_reg->cl_brbadru = - ((u_long)sc->sc_cl[channel].rxp[1]) >> 16; - sc->cl_reg->cl_atbadrl = - ((u_long)sc->sc_cl[channel].txp[0]) & 0xffff; - sc->cl_reg->cl_atbadru = - ((u_long)sc->sc_cl[channel].txp[0]) >> 16; - sc->cl_reg->cl_btbadrl = - ((u_long)sc->sc_cl[channel].txp[1]) & 0xffff; - sc->cl_reg->cl_btbadru = - ((u_long)sc->sc_cl[channel].txp[1]) >> 16; - sc->cl_reg->cl_arbcnt = CL_BUFSIZE; - sc->cl_reg->cl_brbcnt = CL_BUFSIZE; - sc->cl_reg->cl_arbsts = 0x01; - sc->cl_reg->cl_brbsts = 0x01; -if (channel == 2) { /* test one channel now */ - /* shift for tx DMA */ - /* no shift for rx DMA */ -#if 0 - /* tx only */ - sc->cl_reg->cl_licr = (CL_DMAMODE << 4); - sc->cl_reg->cl_cmr = 0x42; -#endif - /* rx only */ - sc->cl_reg->cl_licr = 0x00; - sc->cl_reg->cl_cmr = 0x82; -} - sc->cl_reg->cl_ccr = 0x20; - while (sc->cl_reg->cl_ccr != 0) { - } -#endif /* CL_DMA_WORKS */ - sc->cl_reg->cl_car = save; + u_int8_t save; + + save = bus_space_read_1(sc->sc_iot, sc->sc_ioh, CL_CAR); + bus_space_write_1(sc->sc_iot, sc->sc_ioh, CL_CAR, + channel); + bus_space_write_1(sc->sc_iot, sc->sc_ioh, CL_IER, 0x88); + bus_space_write_1(sc->sc_iot, sc->sc_ioh, CL_CAR, + save); } } else if (tp->t_state & TS_XCLUDE && p->p_ucred->cr_uid != 0) { splx(s); - return(EBUSY); + return EBUSY; } -#ifdef XXX - /* - * if NONBLOCK requested, ignore carrier - */ - if (flag & O_NONBLOCK) - goto done; -#endif - splx(s); + /* * Reset the tty pointer, as there could have been a dialout * use of the tty with a dialin open waiting. */ tp->t_dev = dev; #ifdef DEBUG - cl_dumpport(channel); + cl_dumpport(sc, channel); #endif - return((*linesw[tp->t_line].l_open)(dev, tp)); + return (*linesw[tp->t_line].l_open)(dev, tp); } int @@ -654,8 +625,8 @@ clparam(tp, t) dev = tp->t_dev; unit = CL_UNIT(dev); if (unit >= cl_cd.cd_ndevs || - (sc = (struct clsoftc *) cl_cd.cd_devs[unit]) == NULL) { - return (ENODEV); + (sc = (struct clsoftc *)cl_cd.cd_devs[unit]) == NULL) { + return ENODEV; } channel = CL_CHANNEL(dev); tp->t_ispeed = t->c_ispeed; @@ -683,7 +654,7 @@ cloutput(tp) dev = tp->t_dev; unit = CL_UNIT(dev); if (unit >= cl_cd.cd_ndevs || - (sc = (struct clsoftc *) cl_cd.cd_devs[unit]) == NULL) { + (sc = (struct clsoftc *)cl_cd.cd_devs[unit]) == NULL) { return; } channel = CL_CHANNEL(dev); @@ -720,26 +691,31 @@ clclose(dev, flag, mode, p) struct tty *tp; struct cl_info *cl; struct clsoftc *sc; + bus_space_tag_t iot; + bus_space_handle_t ioh; int s; + unit = CL_UNIT(dev); if (unit >= cl_cd.cd_ndevs || - (sc = (struct clsoftc *) cl_cd.cd_devs[unit]) == NULL) { - return (ENODEV); + (sc = (struct clsoftc *)cl_cd.cd_devs[unit]) == NULL) { + return ENODEV; } channel = CL_CHANNEL(dev); cl = &sc->sc_cl[channel]; + iot = sc->sc_iot; + ioh = sc->sc_ioh; tp = cl->tty; (*linesw[tp->t_line].l_close)(tp, flag); s = splcl(); - - sc->cl_reg->cl_car = channel; - if(cl->cl_consio == 0 && (tp->t_cflag & HUPCL) != 0) { - sc->cl_reg->cl_msvr_rts = 0x00; - sc->cl_reg->cl_msvr_dtr = 0x00; - sc->cl_reg->cl_ccr = 0x05; + bus_space_write_1(iot, ioh, CL_CAR, channel); + if (cl->cl_consio == 0 && (tp->t_cflag & HUPCL) != 0) { + bus_space_write_1(iot, ioh, CL_MSVR_RTS, 0x00); + bus_space_write_1(iot, ioh, CL_MSVR_DTR, 0x00); + bus_space_write_1(iot, ioh, CL_CCR, 0x05); } + splx(s); ttyclose(tp); @@ -747,7 +723,7 @@ clclose(dev, flag, mode, p) cl->tty = NULL; #endif #ifdef DEBUG - cl_dumpport(channel); + cl_dumpport(sc, channel); #endif return 0; @@ -765,15 +741,15 @@ clread(dev, uio, flag) struct clsoftc *sc; unit = CL_UNIT(dev); if (unit >= cl_cd.cd_ndevs || - (sc = (struct clsoftc *) cl_cd.cd_devs[unit]) == NULL) { - return (ENODEV); + (sc = (struct clsoftc *)cl_cd.cd_devs[unit]) == NULL) { + return ENODEV; } channel = CL_CHANNEL(dev); cl = &sc->sc_cl[channel]; tp = cl->tty; - if (!tp) + if (tp == NULL) return ENXIO; - return((*linesw[tp->t_line].l_read)(tp, uio, flag)); + return (*linesw[tp->t_line].l_read)(tp, uio, flag); } int @@ -788,15 +764,15 @@ clwrite(dev, uio, flag) struct clsoftc *sc; unit = CL_UNIT(dev); if (unit >= cl_cd.cd_ndevs || - (sc = (struct clsoftc *) cl_cd.cd_devs[unit]) == NULL) { - return (ENODEV); + (sc = (struct clsoftc *)cl_cd.cd_devs[unit]) == NULL) { + return ENODEV; } channel = CL_CHANNEL(dev); cl = &sc->sc_cl[channel]; tp = cl->tty; - if (!tp) + if (tp == NULL) return ENXIO; - return((*linesw[tp->t_line].l_write)(tp, uio, flag)); + return (*linesw[tp->t_line].l_write)(tp, uio, flag); } int @@ -814,22 +790,22 @@ clioctl(dev, cmd, data, flag, p) struct clsoftc *sc; unit = CL_UNIT(dev); if (unit >= cl_cd.cd_ndevs || - (sc = (struct clsoftc *) cl_cd.cd_devs[unit]) == NULL) { - return (ENODEV); + (sc = (struct clsoftc *)cl_cd.cd_devs[unit]) == NULL) { + return ENODEV; } channel = CL_CHANNEL(dev); cl = &sc->sc_cl[channel]; tp = cl->tty; - if (!tp) + if (tp == NULL) return ENXIO; error = (*linesw[tp->t_line].l_ioctl)(tp, cmd, data, flag, p); if (error >= 0) - return(error); + return error; error = ttioctl(tp, cmd, data, flag, p); if (error >= 0) - return(error); + return error; switch (cmd) { case TIOCSBRK: @@ -869,14 +845,14 @@ clioctl(dev, cmd, data, flag, p) case TIOCSFLAGS: error = suser(p, 0); if (error != 0) - return(EPERM); + return EPERM; cl->cl_swflags = *(int *)data; cl->cl_swflags &= /* only allow valid flags */ (TIOCFLAG_SOFTCAR | TIOCFLAG_CLOCAL | TIOCFLAG_CRTSCTS); break; default: - return(ENOTTY); + return ENOTTY; } return 0; @@ -898,13 +874,6 @@ clstop(tp, flag) return 0; } -/* - * clcn* stuff happens before configure() runs kicking off - * autoconfig. Use a virtual mapping set up in locore till - * the device is actually configured. Need mappings for - * pcc2 space and Cirrus chip area. - */ - void clcnprobe(cp) struct consdev *cp; @@ -917,6 +886,10 @@ clcnprobe(cp) if (brdtyp == BRD_188 || badaddr(CD2400_BASE_ADDR, 1) != 0) return; + /* do not attach as console if cl has been disabled */ + if (cl_cd.cd_ndevs == 0 || cl_cd.cd_devs[0] == NULL) + return; + /* locate the major number */ for (maj = 0; maj < nchrdev; maj++) if (cdevsw[maj].d_open == clopen) @@ -932,113 +905,70 @@ void clcninit(cp) struct consdev *cp; { - struct clreg *volatile cl_reg; - - cl_cons.cl_paddr = (void *)CD2400_BASE_ADDR; - cl_cons.cl_vaddr = (struct clreg *)IIOV(cl_cons.cl_paddr); - cl_cons.pcctwoaddr = (void *)IIOV(0xfff42000); - cl_reg = cl_cons.cl_vaddr; - /* reset the chip? */ -#ifdef CLCD_DO_RESET -#endif - /* set up globals */ -#ifdef NOT_ALREADY_SETUP - cl_reg->cl_tftc = 0x10; - cl_reg->cl_tpr = CL_TIMEOUT; /* is this correct?? */ - cl_reg->cl_rpilr = 0x03; - cl_reg->cl_tpilr = 0x02; - cl_reg->cl_mpilr = 0x01; - - /* set up the tty00 to be 9600 8N1 */ - cl_reg->cl_car = 0x00; - cl_reg->cl_cor1 = 0x17; /* No parity, ignore parity, 8 bit char */ - cl_reg->cl_cor2 = 0x00; - cl_reg->cl_cor3 = 0x02; /* 1 stop bit */ - cl_reg->cl_cor4 = 0x00; - cl_reg->cl_cor5 = 0x00; - cl_reg->cl_cor6 = 0x00; - cl_reg->cl_cor7 = 0x00; - cl_reg->cl_schr1 = 0x00; - cl_reg->cl_schr2 = 0x00; - cl_reg->cl_schr3 = 0x00; - cl_reg->cl_schr4 = 0x00; - cl_reg->cl_scrl = 0x00; - cl_reg->cl_scrh = 0x00; - cl_reg->cl_lnxt = 0x00; - cl_reg->cl_cpsr = 0x00; -#endif + struct clsoftc *sc; + + sc = (struct clsoftc *)cl_cd.cd_devs[0]; + cl_cons.cl_iot = sc->sc_iot; + cl_cons.cl_ioh = sc->sc_ioh; + cl_cons.cl_rxiack = (void *)(sc->sc_pcctwo->sc_base + PCCTWO_SCCRXIACK); } int cl_instat(sc) struct clsoftc *sc; { - struct clreg *volatile cl_reg; - if ( NULL == sc) { - cl_reg = cl_cons.cl_vaddr; - } else { - cl_reg = sc->cl_reg; - } - return (cl_reg->cl_rir & 0x40); + u_int8_t rir; + + if (sc == NULL) + rir = bus_space_read_1(cl_cons.cl_iot, cl_cons.cl_ioh, CL_RIR); + else + rir = bus_space_read_1(sc->sc_iot, sc->sc_ioh, CL_RIR); + + return (rir & 0x40); } int clcngetc(dev) dev_t dev; { - u_char val, reoir, licr, isrl, data = 0, fifo_cnt; -#if 0 - u_char status; -#endif + u_int8_t val, reoir, licr, data; int got_char = 0; - u_char ier_old = 0xff; - struct clreg *volatile cl_reg = cl_cons.cl_vaddr; - struct pcctworeg *volatile pcc2_base = cl_cons.pcctwoaddr; - cl_reg->cl_car = 0; - if (!(cl_reg->cl_ier & 0x08)) { - ier_old = cl_reg->cl_ier; - cl_reg->cl_ier = 0x08; - } + u_int8_t ier_old; + bus_space_tag_t iot; + bus_space_handle_t ioh; + + iot = cl_cons.cl_iot; + ioh = cl_cons.cl_ioh; + + bus_space_write_1(iot, ioh, CL_CAR, 0); + ier_old = bus_space_read_1(iot, ioh, CL_IER); + if ((ier_old & 0x08) == 0) { + bus_space_write_1(iot, ioh, CL_IER, 0x08); + } else + ier_old = 0xff; while (got_char == 0) { - val = cl_reg->cl_rir; + val = bus_space_read_1(iot, ioh, CL_RIR); /* if no receive interrupt pending wait */ - if (!(val & 0x80)) { + if ((val & 0x80) == 0) continue; - } + /* XXX do we need to suck the entire FIFO contents? */ - reoir = pcc2_base->pcc2_sccrxiack; /* receive PIACK */ - licr = cl_reg->cl_licr; + reoir = *cl_cons.cl_rxiack; /* receive PIACK */ + licr = bus_space_read_1(iot, ioh, CL_LICR); + /* is the interrupt for us? (port 0) */ if (((licr >> 2) & 0x3) == 0) { - /* is the interrupt for us (port 0) */ - /* the character is for us yea. */ - isrl = cl_reg->cl_risrl; -#if 0 - if (isrl & 0x01) { - status = BREAK; - } - if (isrl & 0x02) { - status = FRAME; - } - if (isrl & 0x04) { - status = PARITY; - } - if (isrl & 0x08) { - status = OVERFLOW; - } - /* we do not have special characters ;-) */ -#endif - fifo_cnt = cl_reg->cl_rfoc; - data = cl_reg->cl_rdr; - if (ier_old != 0xff) { - cl_reg->cl_ier = ier_old; - } + (void)bus_space_read_1(iot, ioh, CL_RISRL); + (void)bus_space_read_1(iot, ioh, CL_RFOC); + data = bus_space_read_1(iot, ioh, CL_RDR); + if (ier_old != 0xff) + bus_space_write_1(iot, ioh, CL_IER, ier_old); got_char = 1; - cl_reg->cl_teoir = 0x00; } else { - data = cl_reg->cl_rdr; - cl_reg->cl_teoir = 0x00; + /* read and discard the character */ + data = bus_space_read_1(iot, ioh, CL_RDR); } + bus_space_write_1(iot, ioh, CL_TEOIR, 0x00); } return data; @@ -1057,12 +987,11 @@ clcnpollc(dev, on) dev_t dev; int on; { - if (1 == on) { + if (on != 0) { /* enable polling */ } else { /* disable polling */ } - return; } void @@ -1071,112 +1000,43 @@ clputc(sc, unit, c) int unit; u_char c; { + u_int8_t schar; + u_int8_t oldchannel; + bus_space_tag_t iot; + bus_space_handle_t ioh; int s; - u_char schar; - u_char oldchannel; - struct clreg *volatile cl_reg; - if (0 == sc) { + + if (sc == NULL) { /* output on console */ - cl_reg = cl_cons.cl_vaddr; + iot = cl_cons.cl_iot; + ioh = cl_cons.cl_ioh; } else { - cl_reg = sc->cl_reg; + iot = sc->sc_iot; + ioh = sc->sc_ioh; } -#ifdef NEW_CLCD_STRUCT - /* should we disable, flush and all that goo? */ - cl->car = unit; - schar = cl->schr3; - cl->schr3 = c; - cl->stcr = 0x08 | 0x03; /* send special char, char 3 */ - while (0 != cl->stcr) { - /* wait until cl notices the command - * otherwise it may not notice the character - * if we send characters too fast. - */ - } - cl->schr3 = schar; -#else + + s = splhigh(); + oldchannel = bus_space_read_1(iot, ioh, CL_CAR); + bus_space_write_1(iot, ioh, CL_CAR, unit); if (unit == 0) { - s = splhigh(); - oldchannel = cl_reg->cl_car; - cl_reg->cl_car = unit; - schar = cl_reg->cl_schr3; - cl_reg->cl_schr3 = c; - cl_reg->cl_stcr = 0x08 | 0x03; /* send special char, char 3 */ - while (0 != cl_reg->cl_stcr) { + schar = bus_space_read_1(iot, ioh, CL_SCHR3); + /* send special char, number 3 */ + bus_space_write_1(iot, ioh, CL_SCHR3, c); + bus_space_write_1(iot, ioh, CL_STCR, 0x08 | 3); + while (bus_space_read_1(iot, ioh, CL_STCR) != 0) { /* wait until cl notices the command * otherwise it may not notice the character * if we send characters too fast. */ } DELAY(5); - cl_reg->cl_schr3 = schar; - cl_reg->cl_car = oldchannel; - splx(s); - } else { - s = splhigh(); - oldchannel = cl_reg->cl_car; - cl_reg->cl_car = unit; - if (cl_reg->cl_tftc > 0) { - cl_reg->cl_tdr = c; - } - cl_reg->cl_car = oldchannel; - splx(s); - } -#endif - return; -} - -u_char -clgetc(sc, channel) - struct clsoftc *sc; - int *channel; -{ - struct clreg *volatile cl_reg; - struct pcctworeg *volatile pcc2_base; - u_char val, reoir, licr, isrl, fifo_cnt, data; - if (0 == sc) { - cl_reg = cl_cons.cl_vaddr; - pcc2_base = cl_cons.pcctwoaddr; - } else { - cl_reg = sc->cl_reg; - pcc2_base = sc->sc_pcctwo; - } - val = cl_reg->cl_rir; - /* if no receive interrupt pending wait */ - if (!(val & 0x80)) { - return 0; - } - /* XXX do we need to suck the entire FIFO contents? */ - reoir = pcc2_base->pcc2_sccrxiack; /* receive PIACK */ - licr = cl_reg->cl_licr; - *channel = (licr >> 2) & 0x3; - /* is the interrupt for us (port 0) */ - /* the character is for us yea. */ - isrl = cl_reg->cl_risrl; -#if 0 - if (isrl & 0x01) { - status = BREAK; - } - if (isrl & 0x02) { - status = FRAME; - } - if (isrl & 0x04) { - status = PARITY; - } - if (isrl & 0x08) { - status = OVERFLOW; - } - /* we do not have special characters ;-) */ -#endif - fifo_cnt = cl_reg->cl_rfoc; - if (fifo_cnt > 0) { - data = cl_reg->cl_rdr; - cl_reg->cl_teoir = 0x00; + bus_space_write_1(iot, ioh, CL_SCHR3, schar); } else { - data = 0; - cl_reg->cl_teoir = 0x08; + if (bus_space_read_1(iot, ioh, CL_TFTC) != 0) + bus_space_write_1(iot, ioh, CL_TDR, c); } - return data; + bus_space_write_1(iot, ioh, CL_CAR, oldchannel); + splx(s); } int @@ -1185,36 +1045,41 @@ clccparam(sc, par, channel) struct termios *par; int channel; { + bus_space_tag_t iot; + bus_space_handle_t ioh; u_int divisor, clk, clen; int s, imask, ints; + iot = sc->sc_iot; + ioh = sc->sc_ioh; + s = splcl(); - sc->cl_reg->cl_car = channel; + bus_space_write_1(iot, ioh, CL_CAR, channel); if (par->c_ospeed == 0) { /* dont kill the console */ - if(sc->sc_cl[channel].cl_consio == 0) { + if (sc->sc_cl[channel].cl_consio == 0) { /* disconnect, drop RTS DTR stop receiver */ - sc->cl_reg->cl_msvr_rts = 0x00; - sc->cl_reg->cl_msvr_dtr = 0x00; - sc->cl_reg->cl_ccr = 0x05; + bus_space_write_1(iot, ioh, CL_MSVR_RTS, 0x00); + bus_space_write_1(iot, ioh, CL_MSVR_DTR, 0x00); + bus_space_write_1(iot, ioh, CL_CCR, 0x05); } splx(s); - return (0xff); + return 0xff; } - sc->cl_reg->cl_msvr_rts = 0x03; - sc->cl_reg->cl_msvr_dtr = 0x03; + bus_space_write_1(iot, ioh, CL_MSVR_RTS, 0x03); + bus_space_write_1(iot, ioh, CL_MSVR_DTR, 0x03); divisor = cl_clkdiv(par->c_ospeed); clk = cl_clknum(par->c_ospeed); - sc->cl_reg->cl_tbpr = divisor; - sc->cl_reg->cl_tcor = clk << 5; + bus_space_write_1(iot, ioh, CL_TBPR, divisor); + bus_space_write_1(iot, ioh, CL_TCOR, clk << 5); divisor = cl_clkdiv(par->c_ispeed); clk = cl_clknum(par->c_ispeed); - sc->cl_reg->cl_rbpr = divisor; - sc->cl_reg->cl_rcor = clk; - sc->cl_reg->cl_rtprl = cl_clkrxtimeout(par->c_ispeed); - sc->cl_reg->cl_rtprh = 0x00; + bus_space_write_1(iot, ioh, CL_RBPR, divisor); + bus_space_write_1(iot, ioh, CL_RCOR, clk); + bus_space_write_1(iot, ioh, CL_RTPRL, cl_clkrxtimeout(par->c_ispeed)); + bus_space_write_1(iot, ioh, CL_RTPRH, 0x00); switch (par->c_cflag & CSIZE) { case CS5: @@ -1233,10 +1098,11 @@ clccparam(sc, par, channel) clen = 7; imask = 0xFF; } - sc->cl_reg->cl_cor3 = par->c_cflag & PARENB ? 4 : 2; + + bus_space_write_1(iot, ioh, CL_COR3, par->c_cflag & PARENB ? 4 : 2); { - u_char cor1; + u_int8_t cor1; if (par->c_cflag & PARENB) { if (par->c_cflag & PARODD) { cor1 = 0xE0 | clen ; /* odd */ @@ -1246,23 +1112,23 @@ clccparam(sc, par, channel) } else { cor1 = 0x10 | clen; /* ignore parity */ } - if (sc->cl_reg->cl_cor1 != cor1) { - sc->cl_reg->cl_cor1 = cor1; - sc->cl_reg->cl_ccr = 0x20; - while (sc->cl_reg->cl_ccr != 0) { - } + + if (bus_space_read_1(iot, ioh, CL_COR1) != cor1) { + bus_space_write_1(iot, ioh, CL_COR1, cor1); + bus_space_write_1(iot, ioh, CL_CCR, 0x20); + while (bus_space_read_1(iot, ioh, CL_CCR) != 0) + ; } } - if (sc->sc_cl[channel].cl_consio == 0 - && (par->c_cflag & CREAD) == 0 ) - { - sc->cl_reg->cl_ccr = 0x08; - } else { - sc->cl_reg->cl_ccr = 0x0a; - } - while (sc->cl_reg->cl_ccr != 0) { - } + if (sc->sc_cl[channel].cl_consio == 0 && (par->c_cflag & CREAD) == 0) + bus_space_write_1(iot, ioh, CL_CCR, 0x08); + else + bus_space_write_1(iot, ioh, CL_CCR, 0x0a); + + while (bus_space_read_1(iot, ioh, CL_CCR) != 0) + ; + ints = 0; #define SCC_DSR 0x80 #define SCC_DCD 0x40 @@ -1281,68 +1147,74 @@ clccparam(sc, par, channel) ints |= SCC_DSR; } #endif - sc->cl_reg->cl_cor4 = ints | CL_FIFO_CNT; - sc->cl_reg->cl_cor5 = ints | CL_FIFO_CNT; + bus_space_write_1(iot, ioh, CL_COR4, ints | CL_FIFO_CNT); + bus_space_write_1(iot, ioh, CL_COR5, ints | CL_FIFO_CNT); splx(s); + return imask; } static int clknum = 0; -u_char +u_int8_t cl_clkdiv(speed) int speed; { - int i = 0; - if (cl_clocks[clknum].speed == speed) { + int i; + + if (cl_clocks[clknum].speed == speed) return cl_clocks[clknum].divisor; - } + for (i = 0; cl_clocks[i].speed != 0; i++) { if (cl_clocks[i].speed == speed) { clknum = i; return cl_clocks[clknum].divisor; } } + /* return some sane value if unknown speed */ - return cl_clocks[4].divisor; + return cl_clocks[CL_SAFE_CLOCK].divisor; } -u_char +u_int8_t cl_clknum(speed) int speed; { - int found = 0; - int i = 0; - if (cl_clocks[clknum].speed == speed) { + int i; + + if (cl_clocks[clknum].speed == speed) return cl_clocks[clknum].clock; - } - for (i = 0; found != 0 && cl_clocks[i].speed != 0; i++) { + + for (i = 0; cl_clocks[i].speed != 0; i++) { if (cl_clocks[clknum].speed == speed) { clknum = i; return cl_clocks[clknum].clock; } } + /* return some sane value if unknown speed */ - return cl_clocks[4].clock; + return cl_clocks[CL_SAFE_CLOCK].clock; } -u_char +u_int8_t cl_clkrxtimeout(speed) int speed; { - int i = 0; - if (cl_clocks[clknum].speed == speed) { + int i; + + if (cl_clocks[clknum].speed == speed) return cl_clocks[clknum].rx_timeout; - } + for (i = 0; cl_clocks[i].speed != 0; i++) { if (cl_clocks[i].speed == speed) { clknum = i; return cl_clocks[clknum].rx_timeout; } } + /* return some sane value if unknown speed */ - return cl_clocks[4].rx_timeout; + return cl_clocks[CL_SAFE_CLOCK].rx_timeout; } void @@ -1363,7 +1235,7 @@ clstart(tp) int channel, unit, s; #if 0 int cnt; - u_char cbuf; + u_int8_t cbuf; #endif dev = tp->t_dev; @@ -1377,7 +1249,7 @@ clstart(tp) #endif unit = CL_UNIT(dev); if (unit >= cl_cd.cd_ndevs || - (sc = (struct clsoftc *) cl_cd.cd_devs[unit]) == NULL) { + (sc = (struct clsoftc *)cl_cd.cd_devs[unit]) == NULL) { return; } @@ -1394,8 +1266,8 @@ clstart(tp) cnt = q_to_b(&tp->t_outq, &cbuf, 1); if ( cnt != 0 ) { sc->sc_cl[channel].transmitting = 1; - sc->cl_reg->cl_car = channel; - sc->cl_reg->cl_tdr = cbuf; + bus_space_write_1(sc->sc_iot, sc->sc_ioh, CL_CAR, channel); + bus_space_write_1(sc->sc_iot, sc->sc_ioh, CL_TDR, cbuf); } else { sc->sc_cl[channel].transmitting = 0; } @@ -1403,12 +1275,12 @@ clstart(tp) if ((tp->t_state & (TS_TIMEOUT | TS_BUSY | TS_TTSTOP | TS_FLUSH)) == 0) { tp->t_state |= TS_BUSY; - sc->cl_reg->cl_car = channel; - sc->cl_reg->cl_ier = sc->cl_reg->cl_ier | 0x3; + bus_space_write_1(sc->sc_iot, sc->sc_ioh, CL_CAR, channel); + bus_space_write_1(sc->sc_iot, sc->sc_ioh, CL_IER, + bus_space_read_1(sc->sc_iot, sc->sc_ioh, CL_IER) | 0x03); } #endif splx(s); - return; } int @@ -1416,11 +1288,16 @@ cl_mintr(arg) void *arg; { struct clsoftc *sc = arg; - - u_char mir, misr, msvr; + bus_space_tag_t iot; + bus_space_handle_t ioh; + u_int8_t mir, misr, msvr; int channel; - if(((mir = sc->cl_reg->cl_mir) & 0x40) == 0x0) { + iot = sc->sc_iot; + ioh = sc->sc_ioh; + + mir = bus_space_read_1(iot, ioh, CL_MIR); + if ((mir & 0x40) == 0) { /* only if intr is not shared? */ log(LOG_WARNING, "cl_mintr extra intr\n"); return 0; @@ -1428,8 +1305,8 @@ cl_mintr(arg) sc->sc_mxintrcnt.ev_count++; channel = mir & 0x03; - misr = sc->cl_reg->cl_misr; - msvr = sc->cl_reg->cl_msvr_rts; + misr = bus_space_read_1(iot, ioh, CL_MISR); + msvr = bus_space_read_1(iot, ioh, CL_MSVR_RTS); if (misr & 0x01) { /* timers are not currently used?? */ log(LOG_WARNING, "cl_mintr: channel %x timer 1 unexpected\n",channel); @@ -1440,13 +1317,13 @@ cl_mintr(arg) } if (misr & 0x20) { log(LOG_WARNING, "cl_mintr: channel %x cts %x\n",channel, - ((msvr & 0x20) != 0x0) + ((msvr & 0x20) != 0x0) ); } if (misr & 0x40) { struct tty *tp = sc->sc_cl[channel].tty; log(LOG_WARNING, "cl_mintr: channel %x cd %x\n",channel, - ((msvr & 0x40) != 0x0) + ((msvr & 0x40) != 0x0) ); ttymodem(tp, ((msvr & 0x40) != 0x0) ); } @@ -1455,7 +1332,7 @@ cl_mintr(arg) ((msvr & 0x80) != 0x0) ); } - sc->cl_reg->cl_meoir = 0x00; + bus_space_write_1(iot, ioh, CL_MEOIR, 0); return 1; } @@ -1463,17 +1340,21 @@ int cl_txintr(arg) void *arg; { + static int empty; struct clsoftc *sc = arg; - - static int empty = 0; - u_char tir, cmr, teoir; - u_char max; + bus_space_tag_t iot; + bus_space_handle_t ioh; + u_int8_t tir, cmr, teoir; + u_int8_t max; int channel; struct tty *tp; int cnt; u_char buffer[CL_FIFO_MAX +1]; - u_char *tptr; - if (((tir = sc->cl_reg->cl_tir) & 0x40) == 0x0) { + + iot = sc->sc_iot; + ioh = sc->sc_ioh; + tir = bus_space_read_1(iot, ioh, CL_TIR); + if ((tir & 0x40) == 0) { /* only if intr is not shared ??? */ log(LOG_WARNING, "cl_txintr extra intr\n"); return 0; @@ -1481,80 +1362,83 @@ cl_txintr(arg) sc->sc_txintrcnt.ev_count++; channel = tir & 0x03; - cmr = sc->cl_reg->cl_cmr; - sc->sc_cl[channel].txcnt ++; + cmr = bus_space_read_1(iot, ioh, CL_CMR); + tp = sc->sc_cl[channel].tty; if (tp == NULL || (tp->t_state & TS_ISOPEN) == 0) { - sc->cl_reg->cl_ier = sc->cl_reg->cl_ier & ~0x3; - sc->cl_reg->cl_teoir = 0x08; + bus_space_write_1(iot, ioh, CL_IER, + bus_space_read_1(iot, ioh, CL_IER) & ~0x03); + bus_space_write_1(iot, ioh, CL_TEOIR, 0x08); return 1; } + switch (cmr & CL_TXMASK) { case CL_TXDMAINT: - { - u_char dmabsts; - int nbuf, busy, resid; - void *pbuffer; - dmabsts = sc->cl_reg->cl_dmabsts; - log(LOG_WARNING, "cl_txintr: DMAMODE channel %x dmabsts %x\n", - channel, dmabsts); - nbuf = ((dmabsts & 0x8) >> 3) & 0x1; - busy = ((dmabsts & 0x4) >> 2) & 0x1; - - do { - pbuffer = sc->sc_cl[channel].tx[nbuf]; - resid = tp->t_outq.c_cc; - cnt = min (CL_BUFSIZE,resid); - log(LOG_WARNING, "cl_txintr: resid %x cnt %x pbuf %p\n", - resid, cnt, pbuffer); - if (cnt != 0) { - cnt = q_to_b(&tp->t_outq, pbuffer, cnt); - resid -= cnt; - if (nbuf == 0) { - sc->cl_reg->cl_atbadru = - ((u_long) sc->sc_cl[channel].txp[nbuf]) >> 16; - sc->cl_reg->cl_atbadrl = - ((u_long) sc->sc_cl[channel].txp[nbuf]) & 0xffff; - sc->cl_reg->cl_atbcnt = cnt; - sc->cl_reg->cl_atbsts = 0x43; - } else { - sc->cl_reg->cl_btbadru = - ((u_long) sc->sc_cl[channel].txp[nbuf]) >> 16; - sc->cl_reg->cl_btbadrl = - ((u_long) sc->sc_cl[channel].txp[nbuf]) & 0xffff; - sc->cl_reg->cl_btbcnt = cnt; - sc->cl_reg->cl_btbsts = 0x43; - } - teoir = 0x08; + { + u_int8_t dmabsts; + int nbuf, busy, resid; + void *pbuffer; + + dmabsts = bus_space_read_1(iot, ioh, CL_DMABSTS); + nbuf = ((dmabsts & 0x8) >> 3) & 0x1; + busy = ((dmabsts & 0x4) >> 2) & 0x1; + + do { + pbuffer = sc->sc_cl[channel].tx[nbuf]; + resid = tp->t_outq.c_cc; + cnt = min (CL_BUFSIZE,resid); + log(LOG_WARNING, "cl_txintr: resid %x cnt %x pbuf %p\n", + resid, cnt, pbuffer); + if (cnt != 0) { + cnt = q_to_b(&tp->t_outq, pbuffer, cnt); + resid -= cnt; + if (nbuf == 0) { + bus_space_write_2(iot, ioh, CL_ATBADRU, + ((u_long)sc->sc_cl[channel].txp[nbuf]) >> 16); + bus_space_write_2(iot, ioh, CL_ATBADRL, + ((u_long) sc->sc_cl[channel].txp[nbuf]) & 0xffff); + bus_space_write_2(iot, ioh, CL_ATBCNT, + cnt); + bus_space_write_1(iot, ioh, CL_ATBSTS, + 0x43); } else { - teoir = 0x08; - if (tp->t_state & TS_BUSY) { - tp->t_state &= ~(TS_BUSY | TS_FLUSH); - if (tp->t_state & TS_ASLEEP) { - tp->t_state &= ~TS_ASLEEP; - wakeup((caddr_t) &tp->t_outq); - } - selwakeup(&tp->t_wsel); + bus_space_write_2(iot, ioh, CL_BTBADRU, + ((u_long)sc->sc_cl[channel].txp[nbuf]) >> 16); + bus_space_write_2(iot, ioh, CL_BTBADRL, + ((u_long) sc->sc_cl[channel].txp[nbuf]) & 0xffff); + bus_space_write_2(iot, ioh, CL_BTBCNT, + cnt); + bus_space_write_1(iot, ioh, CL_BTBSTS, + 0x43); + } + teoir = 0x08; + } else { + teoir = 0x08; + if (tp->t_state & TS_BUSY) { + tp->t_state &= ~(TS_BUSY | TS_FLUSH); + if (tp->t_state & TS_ASLEEP) { + tp->t_state &= ~TS_ASLEEP; + wakeup((caddr_t) &tp->t_outq); } - sc->cl_reg->cl_ier = sc->cl_reg->cl_ier & ~0x3; + selwakeup(&tp->t_wsel); } - nbuf = ~nbuf & 0x1; - busy--; - } while (resid != 0 && busy != -1);/* if not busy do other buffer */ - log(LOG_WARNING, "cl_txintr: done\n"); - } + bus_space_write_1(iot, ioh, CL_IER, + bus_space_read_1(iot, ioh, CL_IER) & ~0x03); + } + nbuf = ~nbuf & 0x1; + busy--; + } while (resid != 0 && busy != -1);/* if not busy do other buffer */ + } break; case CL_TXINTR: - max = sc->cl_reg->cl_tftc; - cnt = min ((int)max,tp->t_outq.c_cc); + max = bus_space_read_1(iot, ioh, CL_TFTC); + cnt = min((int)max,tp->t_outq.c_cc); if (cnt != 0) { cnt = q_to_b(&tp->t_outq, buffer, cnt); empty = 0; - for (tptr = buffer; tptr < &buffer[cnt]; tptr++) { - sc->cl_reg->cl_tdr = *tptr; - } + bus_space_write_multi_1(iot, ioh, CL_TDR, buffer, cnt); teoir = 0x00; } else { if (empty > 5 && ((empty % 20000 )== 0)) { @@ -1571,7 +1455,8 @@ cl_txintr(arg) } selwakeup(&tp->t_wsel); } - sc->cl_reg->cl_ier = sc->cl_reg->cl_ier & ~0x3; + bus_space_write_1(iot, ioh, CL_IER, + bus_space_read_1(iot, ioh, CL_IER) & ~0x03); } break; default: @@ -1579,7 +1464,7 @@ cl_txintr(arg) /* we probably will go to hell quickly now */ teoir = 0x08; } - sc->cl_reg->cl_teoir = teoir; + bus_space_write_1(iot, ioh, CL_TEOIR, teoir); return 1; } @@ -1588,34 +1473,38 @@ cl_rxintr(arg) void *arg; { struct clsoftc *sc = arg; - - u_char rir, channel, cmr, risrl; - u_char fifocnt; + bus_space_tag_t iot; + bus_space_handle_t ioh; + u_int8_t rir, channel, cmr, risrl; + u_int8_t fifocnt; struct tty *tp; int i; - u_char reoir; + u_int8_t reoir; u_char buffer[CL_FIFO_MAX +1]; - rir = sc->cl_reg->cl_rir; - if((rir & 0x40) == 0x0) { + iot = sc->sc_iot; + ioh = sc->sc_ioh; + + rir = bus_space_read_1(iot, ioh, CL_RIR); + if ((rir & 0x40) == 0x0) { /* only if intr is not shared ??? */ log(LOG_WARNING, "cl_rxintr extra intr\n"); return 0; } sc->sc_rxintrcnt.ev_count++; channel = rir & 0x3; - cmr = sc->cl_reg->cl_cmr; + cmr = bus_space_read_1(iot, ioh, CL_CMR); reoir = 0x08; sc->sc_cl[channel].rxcnt ++; - risrl = sc->cl_reg->cl_risrl; + risrl = bus_space_read_1(iot, ioh, CL_RISRL); if (risrl & 0x80) { /* timeout, no characters */ reoir = 0x08; } else /* We don't need no sinkin special characters */ if (risrl & 0x08) { - cl_overflow (sc, channel, (long *)&sc->sc_fotime, "fifo"); + cl_overflow(sc, channel, (long *)&sc->sc_fotime, "fifo"); reoir = 0x08; } else if (risrl & 0x04) { @@ -1633,94 +1522,79 @@ cl_rxintr(arg) switch (cmr & CL_RXMASK) { case CL_RXDMAINT: - { - int nbuf; - u_short cnt; - int bufcomplete; - u_char status, dmabsts; - u_char risrh = sc->cl_reg->cl_risrh; - dmabsts = sc->cl_reg->cl_dmabsts; -#ifdef DMA_DEBUG -log(LOG_WARNING, "cl_txintr: DMAMODE channel %x dmabsts %x risrl %x risrh %x\n", - channel, dmabsts, risrl, risrh); -#endif - nbuf = (risrh & 0x08) ? 1 : 0; - bufcomplete = (risrh & 0x20) ? 1 : 0; - if (nbuf == 0) { - cnt = sc->cl_reg->cl_arbcnt; - status = sc->cl_reg->cl_arbsts; - } else { - cnt = sc->cl_reg->cl_brbcnt; - status = sc->cl_reg->cl_brbsts; - } -#ifdef DMA_DEBUG - log(LOG_WARNING, "cl_rxintr: 1channel %x buf %x cnt %x status %x\n", - channel, nbuf, cnt, status); -#endif + { + int nbuf; + u_int16_t cnt; + int bufcomplete; + u_int8_t status, dmabsts; + u_int8_t risrh; + + risrh = bus_space_read_1(iot, ioh, CL_RISRH); + dmabsts = bus_space_read_1(iot, ioh, CL_DMABSTS); + nbuf = (risrh & 0x08) ? 1 : 0; + bufcomplete = (risrh & 0x20) ? 1 : 0; + if (nbuf == 0) { + cnt = bus_space_read_2(iot, ioh, CL_ARBCNT); + status = bus_space_read_1(iot, ioh, CL_ARBSTS); + } else { + cnt = bus_space_read_2(iot, ioh, CL_BRBCNT); + status = bus_space_read_1(iot, ioh, CL_BRBSTS); + } #if USE_BUFFER - cl_appendbufn(sc, channel, sc->rx[nbuf], cnt); + cl_appendbufn(sc, channel, sc->rx[nbuf], cnt); #else + { + int i; + u_char *pbuf; + + tp = sc->sc_cl[channel].tty; + pbuf = sc->sc_cl[channel].rx[nbuf]; + /* this should be done at off level */ { - int i; - u_char *pbuf; - tp = sc->sc_cl[channel].tty; - pbuf = sc->sc_cl[channel].rx[nbuf]; - /* this should be done at off level */ - { - u_short rcbadru, rcbadrl; - u_char arbsts, brbsts; - u_char *pbufs, *pbufe; - rcbadru = sc->cl_reg->cl_rcbadru; - rcbadrl = sc->cl_reg->cl_rcbadrl; - arbsts = sc->cl_reg->cl_arbsts; - brbsts = sc->cl_reg->cl_brbsts; - pbufs = sc->sc_cl[channel].rxp[nbuf]; - pbufe = (u_char *)(((u_long)rcbadru << 16) | (u_long)rcbadrl); - cnt = pbufe - pbufs; -#ifdef DMA_DEBUG - log(LOG_WARNING, "cl_rxintr: rcbadru %x rcbadrl %x arbsts %x brbsts %x cnt %x\n", - rcbadru, rcbadrl, arbsts, brbsts, cnt); -#endif -#ifdef DMA_DEBUG1 - log(LOG_WARNING, "cl_rxintr: buf %x cnt %x\n", - nbuf, cnt); -#endif - } - reoir = 0x0 | (bufcomplete) ? 0 : 0xd0; - sc->cl_reg->cl_reoir = reoir; -#ifdef DMA_DEBUG - log(LOG_WARNING, "cl_rxintr: reoir %x\n", reoir); -#endif - delay(10); /* give the chip a moment */ -#ifdef DMA_DEBUG - log(LOG_WARNING, "cl_rxintr: 2channel %x buf %x cnt %x status %x\n", - channel, nbuf, cnt, status); -#endif - for (i = 0; i < cnt; i++) { - u_char c; - c = pbuf[i]; - (*linesw[tp->t_line].l_rint)(c,tp); - } + u_int16_t rcbadru, rcbadrl; + u_int8_t arbsts, brbsts; + u_char *pbufs, *pbufe; + + rcbadru = bus_space_read_2(iot, ioh, + CL_RCBADRU); + rcbadrl = bus_space_read_2(iot, ioh, + CL_RCBADRL); + arbsts = bus_space_read_1(iot, ioh, CL_ARBSTS); + brbsts = bus_space_read_1(iot, ioh, CL_BRBSTS); + pbufs = sc->sc_cl[channel].rxp[nbuf]; + pbufe = (u_char *)(((u_long)rcbadru << 16) | (u_long)rcbadrl); + cnt = pbufe - pbufs; + } + reoir = 0x0 | (bufcomplete) ? 0 : 0xd0; + bus_space_write_1(iot, ioh, CL_REOIR, reoir); + + DELAY(10); /* give the chip a moment */ + + for (i = 0; i < cnt; i++) { + u_char c; + c = pbuf[i]; + (*linesw[tp->t_line].l_rint)(c,tp); + } /* this should be done at off level */ - if (nbuf == 0) { - sc->cl_reg->cl_arbcnt = CL_BUFSIZE; - sc->cl_reg->cl_arbsts = 0x01; - } else { - sc->cl_reg->cl_brbcnt = CL_BUFSIZE; - sc->cl_reg->cl_brbsts = 0x01; - } + if (nbuf == 0) { + bus_space_write_2(iot, ioh, CL_ARBCNT, + CL_BUFSIZE); + bus_space_write_2(iot, ioh, CL_ARBSTS, 0x01); + } else { + bus_space_write_2(iot, ioh, CL_BRBCNT, + CL_BUFSIZE); + bus_space_write_2(iot, ioh, CL_BRBSTS, 0x01); } -#endif } - sc->cl_reg->cl_reoir = reoir; +#endif + } + bus_space_write_1(iot, ioh, CL_REOIR, reoir); break; case CL_RXINTR: - fifocnt = sc->cl_reg->cl_rfoc; + fifocnt = bus_space_read_1(iot, ioh, CL_RFOC); tp = sc->sc_cl[channel].tty; - for (i = 0; i < fifocnt; i++) { - buffer[i] = sc->cl_reg->cl_rdr; - } - if (NULL == tp) { + bus_space_read_multi_1(iot, ioh, CL_RDR, buffer, fifocnt); + if (tp == NULL) { /* if the channel is not configured, * dont send characters upstream. * also fix problem with NULL dereference @@ -1729,7 +1603,7 @@ log(LOG_WARNING, "cl_txintr: DMAMODE channel %x dmabsts %x risrl %x risrh %x\n", break; } - sc->cl_reg->cl_reoir = reoir; + bus_space_write_1(iot, ioh, CL_REOIR, reoir); for (i = 0; i < fifocnt; i++) { u_char c; c = buffer[i]; @@ -1746,7 +1620,7 @@ log(LOG_WARNING, "cl_txintr: DMAMODE channel %x dmabsts %x risrl %x risrh %x\n", default: log(LOG_WARNING, "cl_rxintr unknown mode %x\n", cmr); /* we probably will go to hell quickly now */ - sc->cl_reg->cl_reoir = 0x08; + bus_space_write_1(iot, ioh, CL_REOIR, 0x08); } return 1; } @@ -1796,92 +1670,77 @@ cl_break(sc, channel) #ifdef DEBUG void -cl_dumpport(channel) - int channel; +cl_dumpport(struct clsoftc *sc, int channel) { - u_char livr, cmr, cor1, cor2, cor3, cor4, cor5, cor6, cor7, - schr1, schr2, schr3, schr4, scrl, scrh, lnxt, - rbpr, rcor, tbpr, tcor, rpilr, rir, tpr, ier, ccr, - dmabsts, arbsts, brbsts, atbsts, btbsts, - csr, rts, dtr, rtprl, rtprh; - void *volatile parbadru, *volatile parbadrl, - *volatile parbsts, *volatile parbcnt; - u_short rcbadru, rcbadrl, arbadru, arbadrl, arbcnt, - brbadru, brbadrl, brbcnt; - u_short tcbadru, tcbadrl, atbadru, atbadrl, atbcnt, - btbadru, btbadrl, btbcnt; - struct clsoftc *sc; - - struct clreg *volatile cl_reg; + bus_space_tag_t iot; + bus_space_handle_t ioh; + u_int8_t livr, cmr, cor1, cor2, cor3, cor4, cor5, cor6, cor7, + schr1, schr2, schr3, schr4, scrl, scrh, lnxt, + rbpr, rcor, tbpr, tcor, rpilr, rir, tpr, ier, ccr, + dmabsts, arbsts, brbsts, atbsts, btbsts, + csr, rts, dtr, rtprl, rtprh; + u_int16_t rcbadru, rcbadrl, arbadru, arbadrl, arbcnt, + brbadru, brbadrl, brbcnt; + u_int16_t tcbadru, tcbadrl, atbadru, atbadrl, atbcnt, + btbadru, btbadrl, btbcnt; int s; - cl_reg = cl_cons.cl_vaddr; - - sc = (struct clsoftc *) cl_cd.cd_devs[0]; + iot = sc->sc_iot; + ioh = sc->sc_ioh; s = splcl(); - cl_reg->cl_car = (u_char) channel; - livr = cl_reg->cl_livr; - cmr = cl_reg->cl_cmr; - cor1 = cl_reg->cl_cor1; - cor2 = cl_reg->cl_cor2; - cor3 = cl_reg->cl_cor3; - cor4 = cl_reg->cl_cor4; - cor5 = cl_reg->cl_cor5; - cor6 = cl_reg->cl_cor6; - cor7 = cl_reg->cl_cor7; - schr1 = cl_reg->cl_schr1; - schr2 = cl_reg->cl_schr2; - schr3 = cl_reg->cl_schr3; - schr4 = cl_reg->cl_schr4; - scrl = cl_reg->cl_scrl; - scrh = cl_reg->cl_scrh; - lnxt = cl_reg->cl_lnxt; - rbpr = cl_reg->cl_rbpr; - rcor = cl_reg->cl_rcor; - tbpr = cl_reg->cl_tbpr; - rpilr = cl_reg->cl_rpilr; - rir = cl_reg->cl_rir; - ier = cl_reg->cl_ier; - ccr = cl_reg->cl_ccr; - tcor = cl_reg->cl_tcor; - csr = cl_reg->cl_csr; - tpr = cl_reg->cl_tpr; - rts = cl_reg->cl_msvr_rts; - dtr = cl_reg->cl_msvr_dtr; - rtprl = cl_reg->cl_rtprl; - rtprh = cl_reg->cl_rtprh; - dmabsts = cl_reg->cl_dmabsts; - tcbadru = cl_reg->cl_tcbadru; - tcbadrl = cl_reg->cl_tcbadrl; - rcbadru = cl_reg->cl_rcbadru; - rcbadrl = cl_reg->cl_rcbadrl; - - parbadru = &(cl_reg->cl_arbadru); - parbadrl = &(cl_reg->cl_arbadrl); - parbcnt = &(cl_reg->cl_arbcnt); - parbsts = &(cl_reg->cl_arbsts); - - arbadru = cl_reg->cl_arbadru; - arbadrl = cl_reg->cl_arbadrl; - arbcnt = cl_reg->cl_arbcnt; - arbsts = cl_reg->cl_arbsts; - - brbadru = cl_reg->cl_brbadru; - brbadrl = cl_reg->cl_brbadrl; - brbcnt = cl_reg->cl_brbcnt; - brbsts = cl_reg->cl_brbsts; - - atbadru = cl_reg->cl_atbadru; - atbadrl = cl_reg->cl_atbadrl; - atbcnt = cl_reg->cl_atbcnt; - atbsts = cl_reg->cl_atbsts; - - btbadru = cl_reg->cl_btbadru; - btbadrl = cl_reg->cl_btbadrl; - btbcnt = cl_reg->cl_btbcnt; - btbsts = cl_reg->cl_btbsts; - + bus_space_write_1(iot, ioh, CL_CAR, channel); + livr = bus_space_read_1(iot, ioh, CL_LIVR); + cmr = bus_space_read_1(iot, ioh, CL_CMR); + cor1 = bus_space_read_1(iot, ioh, CL_COR1); + cor2 = bus_space_read_1(iot, ioh, CL_COR2); + cor3 = bus_space_read_1(iot, ioh, CL_COR3); + cor4 = bus_space_read_1(iot, ioh, CL_COR4); + cor5 = bus_space_read_1(iot, ioh, CL_COR5); + cor6 = bus_space_read_1(iot, ioh, CL_COR6); + cor7 = bus_space_read_1(iot, ioh, CL_COR7); + schr1 = bus_space_read_1(iot, ioh, CL_SCHR1); + schr2 = bus_space_read_1(iot, ioh, CL_SCHR2); + schr3 = bus_space_read_1(iot, ioh, CL_SCHR3); + schr4 = bus_space_read_1(iot, ioh, CL_SCHR4); + scrl = bus_space_read_1(iot, ioh, CL_SCRL); + scrh = bus_space_read_1(iot, ioh, CL_SCRH); + lnxt = bus_space_read_1(iot, ioh, CL_LNXT); + rbpr = bus_space_read_1(iot, ioh, CL_RBPR); + rcor = bus_space_read_1(iot, ioh, CL_RCOR); + tbpr = bus_space_read_1(iot, ioh, CL_TBPR); + rpilr = bus_space_read_1(iot, ioh, CL_RPILR); + rir = bus_space_read_1(iot, ioh, CL_RIR); + ier = bus_space_read_1(iot, ioh, CL_IER); + ccr = bus_space_read_1(iot, ioh, CL_CCR); + tcor = bus_space_read_1(iot, ioh, CL_TCOR); + csr = bus_space_read_1(iot, ioh, CL_CSR); + tpr = bus_space_read_1(iot, ioh, CL_TPR); + rts = bus_space_read_1(iot, ioh, CL_MSVR_RTS); + dtr = bus_space_read_1(iot, ioh, CL_MSVR_DTR); + rtprl = bus_space_read_1(iot, ioh, CL_RTPRL); + rtprh = bus_space_read_1(iot, ioh, CL_RTPRH); + dmabsts = bus_space_read_1(iot, ioh, CL_DMABSTS); + tcbadru = bus_space_read_2(iot, ioh, CL_TCBADRU); + tcbadrl = bus_space_read_2(iot, ioh, CL_TCBADRL); + rcbadru = bus_space_read_2(iot, ioh, CL_RCBADRU); + rcbadrl = bus_space_read_2(iot, ioh, CL_RCBADRL); + arbadru = bus_space_read_2(iot, ioh, CL_ARBADRU); + arbadrl = bus_space_read_2(iot, ioh, CL_ARBADRL); + arbcnt = bus_space_read_2(iot, ioh, CL_ARBCNT); + arbsts = bus_space_read_1(iot, ioh, CL_ARBSTS); + brbadru = bus_space_read_2(iot, ioh, CL_BRBADRU); + brbadrl = bus_space_read_2(iot, ioh, CL_BRBADRL); + brbcnt = bus_space_read_2(iot, ioh, CL_BRBCNT); + brbsts = bus_space_read_1(iot, ioh, CL_BRBSTS); + atbadru = bus_space_read_2(iot, ioh, CL_ATBADRU); + atbadrl = bus_space_read_2(iot, ioh, CL_ATBADRL); + atbcnt = bus_space_read_2(iot, ioh, CL_ATBCNT); + atbsts = bus_space_read_1(iot, ioh, CL_ATBSTS); + btbadru = bus_space_read_2(iot, ioh, CL_BTBADRU); + btbadrl = bus_space_read_2(iot, ioh, CL_BTBADRL); + btbcnt = bus_space_read_2(iot, ioh, CL_BTBCNT); + btbsts = bus_space_read_1(iot, ioh, CL_BTBSTS); splx(s); printf("{ port %x livr %x cmr %x\n", @@ -1904,8 +1763,6 @@ cl_dumpport(channel) sc->sc_cl[channel].rxcnt, sc->sc_cl[channel].txcnt); printf("dmabsts %x, tcbadru %x, tcbadrl %x, rcbadru %x, rcbadrl %x,\n", dmabsts, tcbadru, tcbadrl, rcbadru, rcbadrl ); - printf("parbadru %x, parbadrl %x, parbcnt %x, parbsts %x\n", - parbadru, parbadrl, parbcnt, parbsts); printf("arbadru %x, arbadrl %x, arbcnt %x, arbsts %x\n", arbadru, arbadrl, arbcnt, arbsts); printf("brbadru %x, brbadrl %x, brbcnt %x, brbsts %x\n", diff --git a/sys/arch/mvme88k/dev/clock.c b/sys/arch/mvme88k/dev/clock.c index 4eac54c85ac..0cb3f3fdf07 100644 --- a/sys/arch/mvme88k/dev/clock.c +++ b/sys/arch/mvme88k/dev/clock.c @@ -1,4 +1,4 @@ -/* $OpenBSD: clock.c,v 1.29 2004/01/14 20:50:48 miod Exp $ */ +/* $OpenBSD: clock.c,v 1.30 2004/04/24 19:51:47 miod Exp $ */ /* * Copyright (c) 1999 Steve Murphree, Jr. * Copyright (c) 1995 Theo de Raadt @@ -86,16 +86,15 @@ #include "pcctwo.h" #if NPCCTWO > 0 -#include <mvme88k/dev/pcctwofunc.h> +#include <mvme88k/dev/pcctwovar.h> #include <mvme88k/dev/pcctworeg.h> -extern struct vme2reg *sys_vme2; #endif #include "syscon.h" #if NSYSCON > 0 -#include <mvme88k/dev/sysconfunc.h> #include <mvme88k/dev/sysconreg.h> #endif + #include <mvme88k/dev/vme.h> #include "bugtty.h" @@ -134,8 +133,10 @@ int sbc_statintr(void *); int m188_clockintr(void *); int m188_statintr(void *); +#if NPCCTWO > 0 u_int8_t prof_reset; u_int8_t stat_reset; +#endif struct simplelock cio_lock; @@ -236,11 +237,14 @@ sbc_initclock(void) } /* profclock */ - sys_pcc2->pcc2_t1ctl = 0; - sys_pcc2->pcc2_t1cmp = pcc2_timer_us2lim(tick); - sys_pcc2->pcc2_t1count = 0; - sys_pcc2->pcc2_t1ctl = PCC2_TCTL_CEN | PCC2_TCTL_COC | PCC2_TCTL_COVF; - sys_pcc2->pcc2_t1irq = prof_reset; + *(volatile u_int8_t *)(OBIO_START + PCC2_BASE + PCCTWO_T1CTL) = 0; + *(volatile u_int32_t *)(OBIO_START + PCC2_BASE + PCCTWO_T1CMP) = + pcc2_timer_us2lim(tick); + *(volatile u_int32_t *)(OBIO_START + PCC2_BASE + PCCTWO_T1COUNT) = 0; + *(volatile u_int8_t *)(OBIO_START + PCC2_BASE + PCCTWO_T1CTL) = + PCC2_TCTL_CEN | PCC2_TCTL_COC | PCC2_TCTL_COVF; + *(volatile u_int8_t *)(OBIO_START + PCC2_BASE + PCCTWO_T1ICR) = + prof_reset; } @@ -250,7 +254,8 @@ sbc_initclock(void) int sbc_clockintr(void *eframe) { - sys_pcc2->pcc2_t1irq = prof_reset; + *(volatile u_int8_t *)(OBIO_START + PCC2_BASE + PCCTWO_T1ICR) = + prof_reset; intrcnt[M88K_CLK_IRQ]++; hardclock(eframe); @@ -283,11 +288,14 @@ sbc_initstatclock(void) statvar >>= 1; /* statclock */ - sys_pcc2->pcc2_t2ctl = 0; - sys_pcc2->pcc2_t2cmp = pcc2_timer_us2lim(statint); - sys_pcc2->pcc2_t2count = 0; - sys_pcc2->pcc2_t2ctl = PCC2_TCTL_CEN | PCC2_TCTL_COC | PCC2_TCTL_COVF; - sys_pcc2->pcc2_t2irq = stat_reset; + *(volatile u_int8_t *)(OBIO_START + PCC2_BASE + PCCTWO_T2CTL) = 0; + *(volatile u_int32_t *)(OBIO_START + PCC2_BASE + PCCTWO_T2CMP) = + pcc2_timer_us2lim(tick); + *(volatile u_int32_t *)(OBIO_START + PCC2_BASE + PCCTWO_T2COUNT) = 0; + *(volatile u_int8_t *)(OBIO_START + PCC2_BASE + PCCTWO_T2CTL) = + PCC2_TCTL_CEN | PCC2_TCTL_COC | PCC2_TCTL_COVF; + *(volatile u_int8_t *)(OBIO_START + PCC2_BASE + PCCTWO_T2ICR) = + stat_reset; statmin = statint - (statvar >> 1); } @@ -297,7 +305,8 @@ sbc_statintr(void *eframe) { u_long newint, r, var; - sys_pcc2->pcc2_t2irq = stat_reset; + *(volatile u_int8_t *)(OBIO_START + PCC2_BASE + PCCTWO_T2ICR) = + stat_reset; /* increment intr counter */ intrcnt[M88K_SCLK_IRQ]++; @@ -315,11 +324,14 @@ sbc_statintr(void *eframe) } while (r == 0); newint = statmin + r; - sys_pcc2->pcc2_t2ctl = 0; - sys_pcc2->pcc2_t2cmp = pcc2_timer_us2lim(newint); - sys_pcc2->pcc2_t2count = 0; /* should I? */ - sys_pcc2->pcc2_t2irq = stat_reset; - sys_pcc2->pcc2_t2ctl = PCC2_TCTL_CEN | PCC2_TCTL_COC; + *(volatile u_int8_t *)(OBIO_START + PCC2_BASE + PCCTWO_T2CTL) = 0; + *(volatile u_int32_t *)(OBIO_START + PCC2_BASE + PCCTWO_T2CMP) = + pcc2_timer_us2lim(tick); + *(volatile u_int32_t *)(OBIO_START + PCC2_BASE + PCCTWO_T2COUNT) = 0; + *(volatile u_int8_t *)(OBIO_START + PCC2_BASE + PCCTWO_T2ICR) = + stat_reset; + *(volatile u_int8_t *)(OBIO_START + PCC2_BASE + PCCTWO_T2CTL) = + PCC2_TCTL_CEN | PCC2_TCTL_COC; return (1); } @@ -375,9 +387,9 @@ m188_timer_init(unsigned period) int counter; /* make sure the counter range is proper. */ - if ( period < 9 ) + if (period < 9) counter = 2; - else if ( period > 284421 ) + else if (period > 284421) counter = 65535; else counter = period / 4.34; @@ -396,7 +408,8 @@ m188_timer_init(unsigned period) *((int *volatile)DART_CTUR) = counter / 256; /* set counter MSB */ *((int *volatile)DART_CTLR) = counter % 256; /* set counter LSB */ - *((int *volatile)DART_IVR) = SYSCV_TIMER1; /* set interrupt vec */ + /* set interrupt vec */ + *((int *volatile)DART_IVR) = SYSCON_VECT + SYSCV_TIMER1; /* give the start counter/timer command */ /* (yes, this is supposed to be a read) */ @@ -417,7 +430,7 @@ m188_statintr(void *eframe) intrcnt[M88K_SCLK_IRQ]++; statclock((struct clockframe *)eframe); - write_cio(CIO_CSR1, CIO_GCB|CIO_CIP); /* Ack the interrupt */ + write_cio(CIO_CSR1, CIO_GCB | CIO_CIP); /* Ack the interrupt */ /* * Compute new randomized interval. The intervals are uniformly @@ -435,7 +448,7 @@ m188_statintr(void *eframe) write_cio(CIO_CT1LSB, newint & 0xff); /* Start CTC #1 running */ - write_cio(CIO_CSR1, CIO_GCB|CIO_CIP); + write_cio(CIO_CSR1, CIO_GCB | CIO_CIP); CIO_UNLOCK; return (1); @@ -566,31 +579,27 @@ m188_cio_init(unsigned p) void delay(int us) { - -#if NPCCTWO > 0 - /* - * On MVME187 and MVME197, we use the vme system controller for - * the delay clock. - * Do not go to the real timer until the vme device is attached. - * We could directly access the chip, but oh well, who cares. - */ - if (sys_vme2 != NULL) { - sys_vme2->vme2_t1cmp = 0xffffffff; - sys_vme2->vme2_t1count = 0; - sys_vme2->vme2_tctl |= VME2_TCTL1_CEN; - - while (sys_vme2->vme2_t1count < us) - ; - sys_vme2->vme2_tctl &= ~VME2_TCTL1_CEN; - } else -#endif - - /* - * If we can't use a real timer, use a tight loop. - */ - { + if (brdtyp == BRD_188) { + /* + * Unable to use a real timer, use a tight loop. + */ volatile int c = (25 * us) / 3; /* XXX not accurate! */ while (--c > 0) ; + } else { + /* + * On MVME187 and MVME197, use the VMEchip for the + * delay clock. + */ + *(volatile u_int32_t *)(VME2_BASE + VME2_T1CMP) = 0xffffffff; + *(volatile u_int32_t *)(VME2_BASE + VME2_T1COUNT) = 0; + *(volatile u_int32_t *)(VME2_BASE + VME2_TCTL) |= + VME2_TCTL1_CEN; + + while ((*(volatile u_int32_t *)(VME2_BASE + VME2_T1COUNT)) < + (u_int32_t)us) + ; + *(volatile u_int32_t *)(VME2_BASE + VME2_TCTL) &= + ~VME2_TCTL1_CEN; } } diff --git a/sys/arch/mvme88k/dev/clreg.h b/sys/arch/mvme88k/dev/clreg.h index 91f69b2be4b..a3c66c92b18 100644 --- a/sys/arch/mvme88k/dev/clreg.h +++ b/sys/arch/mvme88k/dev/clreg.h @@ -1,4 +1,4 @@ -/* $OpenBSD: clreg.h,v 1.5 2004/01/05 20:08:01 miod Exp $ */ +/* $OpenBSD: clreg.h,v 1.6 2004/04/24 19:51:47 miod Exp $ */ /* Copyright (c) 1998 Steve Murphree, Jr. * Copyright (c) 1995 Dale Rahn. All rights reserved. @@ -27,139 +27,94 @@ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -struct clreg { - volatile u_char anon1[0x7]; - volatile u_char cl_cor7; /* 0x07 */ - volatile u_char anon2[0x1]; - volatile u_char cl_livr; /* 0x09 */ - volatile u_char anon3[0x6]; - volatile u_char cl_cor1; /* 0x10 */ - volatile u_char cl_ier; /* 0x11 */ - volatile u_char cl_stcr; /* 0x12 */ - volatile u_char cl_ccr; /* 0x13 */ - volatile u_char cl_cor5; /* 0x14 */ - volatile u_char cl_cor4; /* 0x15 */ - volatile u_char cl_cor3; /* 0x16 */ - volatile u_char cl_cor2; /* 0x17 */ - volatile u_char cl_cor6; /* 0x18 */ - volatile u_char cl_dmabsts; /* 0x19 */ - volatile u_char cl_csr; /* 0x1a */ - volatile u_char cl_cmr; /* 0x1b */ - volatile u_char cl_schr4; /* 0x1c */ - volatile u_char cl_schr3; /* 0x1d */ - volatile u_char cl_schr2; /* 0x1e */ - volatile u_char cl_schr1; /* 0x1f */ - volatile u_char anon5[0x2]; - volatile u_char cl_scrh; /* 0x22 */ - volatile u_char cl_scrl; /* 0x23 */ -#define cl_rtpr rtpr.rtpr_rtpr -#define cl_rtprh rtpr.hl.rtpr_rtprh -#define cl_rtprl rtpr.hl.rtpr_rtprl - union { - volatile u_short rtpr_rtpr; /* 0x24 */ - struct { - volatile u_char rtpr_rtprh; /* 0x24 */ - volatile u_char rtpr_rtprl; /* 0x25 */ - }hl; - }rtpr; - volatile u_char cl_licr; /* 0x26 */ - volatile u_char anon6[0x7]; - volatile u_char cl_lnxt; /* 0x2e */ - volatile u_char anon7[0x1]; - volatile u_char cl_rfoc; /* 0x30 */ - volatile u_char anon8[0x7]; - volatile u_short cl_tcbadru; /* 0x38 */ - volatile u_short cl_tcbadrl; /* 0x3a */ - volatile u_short cl_rcbadru; /* 0x3c */ - volatile u_short cl_rcbadrl; /* 0x3e */ - volatile u_short cl_arbadru; /* 0x40 */ - volatile u_short cl_arbadrl; /* 0x42 */ - volatile u_short cl_brbadru; /* 0x44 */ - volatile u_short cl_brbadrl; /* 0x46 */ - volatile u_short cl_brbcnt; /* 0x48 */ - volatile u_short cl_arbcnt; /* 0x4a */ - volatile u_char anoni[0x2]; - volatile u_char cl_brbsts; /* 0x4e */ - volatile u_char cl_arbsts; /* 0x4f */ -#define cl_atbadr atbadr.atbadr -#define cl_atbadru atbadr.hl.atbadru -#define cl_atbadrl atbadr.hl.atbadrl - union { - struct { - volatile u_short atbadru; /* 0x50 */ - volatile u_short atbadrl; /* 0x52 */ - }hl; - volatile u_long atbadr; /* 0x50 */ - }atbadr; -#define cl_btbadr btbadr.btbadr -#define cl_btbadru btbadr.hl.btbadru -#define cl_btbadrl btbadr.hl.btbadrl - union { - struct { - volatile u_short btbadru; /* 0x54 */ - volatile u_short btbadrl; /* 0x56 */ - }hl; - volatile u_long btbadr; /* 0x54 */ - }btbadr; - volatile u_short cl_btbcnt; /* 0x58 */ - volatile u_short cl_atbcnt; /* 0x5a */ - volatile u_char anono[0x2]; - volatile u_char cl_btbsts; /* 0x5e */ - volatile u_char cl_atbsts; /* 0x5f */ - volatile u_char anonp[0x20]; - volatile u_char cl_tftc; /* 0x80 */ - volatile u_char cl_gfrcr; /* 0x81 */ - volatile u_char anonq[0x2]; - volatile u_char cl_reoir; /* 0x84 */ - volatile u_char cl_teoir; /* 0x85 */ - volatile u_char cl_meoir; /* 0x86 */ - volatile u_char anonr[0x1]; -#define cl_risr risr.risr_risr -#define cl_risrl risr.hl.risr_risrl -#define cl_risrh risr.hl.risr_risrh - union { - volatile u_short risr_risr; /* 0x88 */ - struct { - volatile u_char risr_risrh; /* 0x88 */ - volatile u_char risr_risrl; /* 0x89 */ - }hl; - }risr; - volatile u_char cl_tisr; /* 0x8a */ - volatile u_char cl_misr; /* 0x8b */ - volatile u_char anons[0x2]; - volatile u_char cl_bercnt; /* 0x8e */ - volatile u_char anont[0x31]; - volatile u_char cl_tcor; /* 0xc0 */ - volatile u_char anonu[0x2]; - volatile u_char cl_tbpr; /* 0xc3 */ - volatile u_char anonv[0x4]; - volatile u_char cl_rcor; /* 0xc8 */ - volatile u_char anonw[0x2]; - volatile u_char cl_rbpr; /* 0xcb */ - volatile u_char anonx[0xa]; - volatile u_char cl_cpsr; /* 0xd6 */ - volatile u_char anony[0x3]; - volatile u_char cl_tpr; /* 0xda */ - volatile u_char anonz[0x3]; - volatile u_char cl_msvr_rts; /* 0xde */ - volatile u_char cl_msvr_dtr; /* 0xdf */ - volatile u_char cl_tpilr; /* 0xe0 */ - volatile u_char cl_rpilr; /* 0xe1 */ - volatile u_char cl_stk; /* 0xe2 */ - volatile u_char cl_mpilr; /* 0xe3 */ - volatile u_char anonA[0x8]; - volatile u_char cl_tir; /* 0xec */ - volatile u_char cl_rir; /* 0xed */ - volatile u_char cl_car; /* 0xee */ - volatile u_char cl_mir; /* 0xef */ - volatile u_char anonB[0x6]; - volatile u_char cl_dmr; /* 0xf6 */ - volatile u_char anonC[0x1]; -#define cl_rdr cl_tdr - volatile u_char cl_tdr; /* 0xf8 */ - volatile u_char anonD[7]; -}; +#define CL_COR7 0x0007 +#define CL_LIVR 0x0009 +#define CL_COR1 0x0010 +#define CL_IER 0x0011 +#define CL_STCR 0x0012 +#define CL_CCR 0x0013 +#define CL_COR5 0x0014 +#define CL_COR4 0x0015 +#define CL_COR3 0x0016 +#define CL_COR2 0x0017 +#define CL_COR6 0x0018 +#define CL_DMABSTS 0x0019 +#define CL_CSR 0x001a +#define CL_CMR 0x001b +#define CL_SCHR4 0x001c +#define CL_SCHR3 0x001d +#define CL_SCHR2 0x001e +#define CL_SCHR1 0x001f +#define CL_SCRH 0x0022 +#define CL_SCRL 0x0023 +#define CL_RTPR 0x0024 +#define CL_RTPRH 0x0024 +#define CL_RTPRL 0x0025 + +#define CL_LICR 0x0026 +#define CL_LNXT 0x002e +#define CL_RFOC 0x0030 + +#define CL_TCBADRU 0x0038 +#define CL_TCBADRL 0x003a +#define CL_RCBADRU 0x003c +#define CL_RCBADRL 0x003e +#define CL_ARBADRU 0x0040 +#define CL_ARBARDL 0x0042 +#define CL_BRBADRU 0x0044 +#define CL_BRBADRL 0x0046 +#define CL_BRBCNT 0x0048 +#define CL_ARBCNT 0x004a + +#define CL_BRBSTS 0x004e +#define CL_ARBSTS 0x004f + +#define CL_ATBADR 0x0050 +#define CL_ATBADRU 0x0050 +#define CL_ATBADRL 0x0052 +#define CL_BTBADR 0x0054 +#define CL_BTBADRU 0x0054 +#define CL_BTBADRL 0x0056 + +#define CL_BTBCNT 0x0058 +#define CL_ATBCNT 0x005a + +#define CL_BTBSTS 0x005e +#define CL_ATBSTS 0x005f + +#define CL_TFTC 0x0080 +#define CL_GFRCR 0x0081 +#define CL_REOIR 0x0084 +#define CL_TEOIR 0x0085 +#define CL_MEOIR 0x0086 + +#define CL_RISR 0x0088 +#define CL_RISRH 0x0088 +#define CL_RISRL 0x0089 + +#define CL_TISR 0x008a +#define CL_MISR 0x008b +#define CL_BERCNT 0x008e +#define CL_TCOR 0x00c0 +#define CL_TBPR 0x00c3 +#define CL_RCOR 0x00c8 +#define CL_RBPR 0x00cb +#define CL_CPSR 0x00d6 +#define CL_TPR 0x00da +#define CL_MSVR_RTS 0x00de +#define CL_MSVR_DTR 0x00df +#define CL_TPILR 0x00e0 +#define CL_RPILR 0x00e1 +#define CL_STK 0x00e2 +#define CL_MPILR 0x00e3 +#define CL_TIR 0x00ec +#define CL_RIR 0x00ed +#define CL_CAR 0x00ee +#define CL_MIR 0x00ef +#define CL_DMR 0x00f6 +#define CL_RDR 0x00f8 +#define CL_TDR 0x00f8 #define CD2400_SIZE 0x200 diff --git a/sys/arch/mvme88k/dev/dart.c b/sys/arch/mvme88k/dev/dart.c index 99d88bb0440..a613a5a10b6 100644 --- a/sys/arch/mvme88k/dev/dart.c +++ b/sys/arch/mvme88k/dev/dart.c @@ -1,4 +1,4 @@ -/* $OpenBSD: dart.c,v 1.32 2004/04/16 23:32:44 miod Exp $ */ +/* $OpenBSD: dart.c,v 1.33 2004/04/24 19:51:47 miod Exp $ */ /* * Mach Operating System @@ -143,19 +143,19 @@ const struct dart_s { {B4800, BD4800 }, /* 4800 baud */ {B9600, BD9600 }, /* 9600 baud */ {B19200, BD19200 }, /* 19200 baud */ - {0xFFFF, NOBAUD }, /* anything more is uncivilized */ + {-1, NOBAUD }, /* anything more is uncivilized */ }; int dart_speed(speed) int speed; { - const struct dart_s *ds = dart_speeds; - while (ds->kspeed != 0xFFFF) { + const struct dart_s *ds; + + for (ds = dart_speeds; ds->kspeed != -1; ds++) if (ds->kspeed == speed) return ds->dspeed; - ds++; - } + return NOBAUD; } @@ -183,14 +183,18 @@ dartmatch(parent, vcf, args) union dartreg *addr; /* Don't match if wrong cpu */ - if (brdtyp != BRD_188) return (0); - ca->ca_vaddr = ca->ca_paddr; /* 1:1 */ - addr = (union dartreg *)ca->ca_vaddr; + if (brdtyp != BRD_188) + return (0); + + addr = (union dartreg *)ca->ca_paddr; if (badvaddr((vaddr_t)addr, 2)) { +#ifdef DEBUG printf("==> dart: failed address check.\n"); +#endif return (0); } + return (1); } @@ -206,10 +210,6 @@ dartattach(parent, self, aux) union dart_pt_io *ptaddr; /* pointer to port regs */ int port; /* port index */ - if (ca->ca_vec < 0) { - printf(": no more interrupts!\n"); - return; - } if (ca->ca_ipl < 0) ca->ca_ipl = IPL_TTY; @@ -298,7 +298,7 @@ dartattach(parent, self, aux) addr->write.wr_acr = dart_sv_reg.sv_acr; addr->write.wr_imr = dart_sv_reg.sv_imr; addr->write.wr_opcr = OPSET; - addr->write.wr_ivr = SYSCV_SCC; /* hard coded vector */ + addr->write.wr_ivr = SYSCON_VECT + SYSCV_SCC; /* hard coded vector */ /* enable interrupts */ sc->sc_ih.ih_fn = dartintr; @@ -306,7 +306,7 @@ dartattach(parent, self, aux) sc->sc_ih.ih_wantframe = 0; sc->sc_ih.ih_ipl = ca->ca_ipl; - intr_establish(ca->ca_vec, &sc->sc_ih); + sysconintr_establish(SYSCV_SCC, &sc->sc_ih); evcnt_attach(&sc->sc_dev, "intr", &sc->sc_intrcnt); printf("\n"); } diff --git a/sys/arch/mvme88k/dev/if_ie.c b/sys/arch/mvme88k/dev/if_ie.c index c357e4cd575..a9c3791b2ef 100644 --- a/sys/arch/mvme88k/dev/if_ie.c +++ b/sys/arch/mvme88k/dev/if_ie.c @@ -1,4 +1,4 @@ -/* $OpenBSD: if_ie.c,v 1.27 2004/01/14 20:50:48 miod Exp $ */ +/* $OpenBSD: if_ie.c,v 1.28 2004/04/24 19:51:48 miod Exp $ */ /*- * Copyright (c) 1998 Steve Murphree, Jr. @@ -127,15 +127,16 @@ Mode of operation: #include <uvm/uvm_extern.h> +#include <machine/bus.h> #include <machine/autoconf.h> +#include <machine/board.h> #include <machine/cpu.h> #include <machine/pmap.h> -#include "pcctwo.h" -#include <mvme88k/dev/pcctworeg.h> -#include <mvme88k/dev/pcctwofunc.h> + #include <mvme88k/dev/if_ie.h> #include <mvme88k/dev/i82596.h> -#include <machine/board.h> +#include <mvme88k/dev/pcctworeg.h> +#include <mvme88k/dev/pcctwovar.h> static struct mbuf *last_not_for_us; struct vm_map *ie_map; /* for obio */ @@ -226,12 +227,7 @@ struct ie_softc { #ifdef IEDEBUG int sc_debug; #endif -#if NMC > 0 - struct mcreg *sc_mc; -#endif -#if NPCCTWO > 0 - struct pcctworeg *sc_pcc2; -#endif + struct pcctwosoftc *sc_pcctwo; }; void ie_obreset(struct ie_softc *); @@ -350,9 +346,10 @@ iematch(parent, vcf, args) { struct confargs *ca = args; - if (badvaddr((unsigned)IIOV(ca->ca_vaddr), 1)){ + if (badvaddr(ca->ca_paddr, 1)) { return(0); } + return(1); } @@ -396,9 +393,6 @@ ie_obrun(sc) { } -/* - * Taken almost exactly from Bill's if_is.c, then modified beyond recognition. - */ void ieattach(parent, self, aux) struct device *parent, *self; @@ -408,17 +402,17 @@ ieattach(parent, self, aux) struct confargs *ca = aux; struct ifnet *ifp = &sc->sc_arpcom.ac_if; extern void myetheraddr(u_char *); /* should be elsewhere */ - int pri = ca->ca_ipl; struct ieob *volatile ieo; paddr_t pa; + sc->sc_pcctwo = (struct pcctwosoftc *)parent; sc->reset_596 = ie_obreset; sc->chan_attn = ie_obattend; sc->run_596 = ie_obrun; sc->memcopy = bcopy; sc->memzero = bzero; sc->sc_msize = etherlen; - sc->sc_reg = ca->ca_vaddr; + sc->sc_reg = (void *)ca->ca_paddr; ieo = (struct ieob *volatile) sc->sc_reg; /* Are we the boot device? */ @@ -427,12 +421,17 @@ ieattach(parent, self, aux) /* get the first available etherbuf */ sc->sc_maddr = etherbuf; /* maddr = vaddr */ - if (sc->sc_maddr == NULL) panic("ie: too many ethernet boards"); - if (pmap_extract(pmap_kernel(), (vaddr_t)sc->sc_maddr, &pa) == FALSE) - panic("ie: pmap_extract"); - sc->sc_iobase = (caddr_t)pa; /* iobase = paddr (24 bit) */ + if (sc->sc_maddr == NULL) { + printf(": too many ethernet boards\n"); + return; + } else + etherbuf = NULL; /* XXX */ - /*printf("maddrP %x iobaseV %x\n", sc->sc_maddr, sc->sc_iobase);*/ + if (pmap_extract(pmap_kernel(), (vaddr_t)sc->sc_maddr, &pa) == FALSE) { + printf(": pmap_extract() failed!\n"); + return; + } + sc->sc_iobase = (caddr_t)pa; /* iobase = paddr (24 bit) */ (sc->memzero)(sc->sc_maddr, sc->sc_msize); sc->iscp = (struct ie_int_sys_conf_ptr *volatile) @@ -441,7 +440,6 @@ ieattach(parent, self, aux) roundup((int)sc->iscp + sizeof(struct ie_int_sys_conf_ptr), 16); sc->scp = (struct ie_sys_conf_ptr *) roundup((int)sc->scb + sizeof(struct ie_sys_ctl_block), 16); - /*printf("scpV %x iscpV %x scbV %x\n", sc->scp, sc->iscp, sc->scb);*/ sc->scp->ie_bus_use = 0x44; pmap_extract(pmap_kernel(), (vaddr_t)sc->iscp, &pa); @@ -478,19 +476,23 @@ ieattach(parent, self, aux) sc->sc_ih.ih_fn = ieintr; sc->sc_ih.ih_arg = sc; sc->sc_ih.ih_wantframe = 0; - sc->sc_ih.ih_ipl = pri; + sc->sc_ih.ih_ipl = ca->ca_ipl; + sc->sc_failih.ih_fn = iefailintr; sc->sc_failih.ih_arg = sc; sc->sc_failih.ih_wantframe = 0; - sc->sc_failih.ih_ipl = pri; + sc->sc_failih.ih_ipl = ca->ca_ipl; pcctwointr_establish(PCC2V_IE, &sc->sc_ih); - sc->sc_pcc2 = (struct pcctworeg *)ca->ca_master; - sc->sc_pcc2->pcc2_ieirq = pri | PCC2_SC_SNOOP | - PCC2_IRQ_IEN | PCC2_IRQ_ICLR; pcctwointr_establish(PCC2V_IEFAIL, &sc->sc_failih); - sc->sc_pcc2->pcc2_iefailirq = pri | PCC2_IRQ_IEN | - PCC2_IRQ_ICLR; + + /* enable device interrupts */ + bus_space_write_1(sc->sc_pcctwo->sc_iot, sc->sc_pcctwo->sc_ioh, + PCCTWO_IEICR, PCC2_SC_SNOOP | PCC2_IRQ_IEN | PCC2_IRQ_ICLR | + (ca->ca_ipl & PCC2_IRQ_IPL)); + bus_space_write_1(sc->sc_pcctwo->sc_iot, sc->sc_pcctwo->sc_ioh, + PCCTWO_IEBERR, PCC2_IRQ_IEN | PCC2_IRQ_ICLR | + (ca->ca_ipl & PCC2_IRQ_IPL)); evcnt_attach(&sc->sc_dev, "intr", &sc->sc_intrcnt); } @@ -513,13 +515,23 @@ iewatchdog(ifp) int iefailintr(v) -void *v; + void *v; { struct ie_softc *sc = v; - sc->sc_pcc2->pcc2_ieirq |= PCC2_IRQ_ICLR; /* safe: clear irq */ - sc->sc_pcc2->pcc2_iefailirq |= PCC2_IRQ_ICLR; /* clear failure */ - sc->sc_pcc2->pcc2_ieerr = PCC2_IEERR_SCLR; /* reset error */ + /* safe: clear irq */ + bus_space_write_1(sc->sc_pcctwo->sc_iot, sc->sc_pcctwo->sc_ioh, + PCCTWO_IEICR, PCC2_IRQ_ICLR | + bus_space_read_1(sc->sc_pcctwo->sc_iot, sc->sc_pcctwo->sc_ioh, + PCCTWO_IEICR)); + /* clear failure */ + bus_space_write_1(sc->sc_pcctwo->sc_iot, sc->sc_pcctwo->sc_ioh, + PCCTWO_IEBERR, PCC2_IRQ_ICLR | + bus_space_read_1(sc->sc_pcctwo->sc_iot, sc->sc_pcctwo->sc_ioh, + PCCTWO_IEBERR)); + /* reset error */ + bus_space_write_1(sc->sc_pcctwo->sc_iot, sc->sc_pcctwo->sc_ioh, + PCCTWO_IEERR, PCC2_IEERR_SCLR); iereset(sc); return (1); @@ -536,12 +548,15 @@ ieintr(v) u_short status; status = sc->scb->ie_status; -/*printf("I");*/ loop: /* Ack interrupts FIRST in case we receive more during the ISR. */ ie_ack(sc, IE_ST_WHENCE & status); - sc->sc_pcc2->pcc2_ieirq |= PCC2_IRQ_ICLR; /* clear irq */ + /* clear irq */ + bus_space_write_1(sc->sc_pcctwo->sc_iot, sc->sc_pcctwo->sc_ioh, + PCCTWO_IEICR, PCC2_IRQ_ICLR | + bus_space_read_1(sc->sc_pcctwo->sc_iot, sc->sc_pcctwo->sc_ioh, + PCCTWO_IEICR)); if (status & (IE_ST_RECV | IE_ST_RNR)) { #ifdef IEDEBUG diff --git a/sys/arch/mvme88k/dev/if_le.c b/sys/arch/mvme88k/dev/if_le.c index b2da2aeeaa2..8116d1a3953 100644 --- a/sys/arch/mvme88k/dev/if_le.c +++ b/sys/arch/mvme88k/dev/if_le.c @@ -1,4 +1,4 @@ -/* $OpenBSD: if_le.c,v 1.3 2003/12/30 21:25:59 miod Exp $ */ +/* $OpenBSD: if_le.c,v 1.4 2004/04/24 19:51:48 miod Exp $ */ /*- * Copyright (c) 1982, 1992, 1993 @@ -31,7 +31,8 @@ * @(#)if_le.c 8.2 (Berkeley) 10/30/93 */ -#include "bpfilter.h" +/* This card lives in D16 space */ +#define __BUS_SPACE_RESTRICT_D16__ #include <sys/param.h> #include <sys/systm.h> @@ -246,8 +247,16 @@ lematch(parent, vcf, args) void *vcf, *args; { struct confargs *ca = args; + bus_space_tag_t iot = ca->ca_iot; + bus_space_handle_t ioh; + int rc; + + if (bus_space_map(iot, ca->ca_paddr, PAGE_SIZE, 0, &ioh) != 0) + return 0; + rc = badvaddr((vaddr_t)bus_space_vaddr(iot, ioh), 2); + bus_space_unmap(iot, ioh, PAGE_SIZE); - return (!badvaddr((vaddr_t)ca->ca_vaddr, 2)); + return rc == 0; } /* @@ -266,6 +275,20 @@ leattach(parent, self, aux) struct confargs *ca = aux; caddr_t addr; int card; + bus_space_tag_t iot = ca->ca_iot; + bus_space_handle_t ioh; + + if (ca->ca_vec < 0) { + printf(": no more interrupts!\n"); + return; + } + if (ca->ca_ipl < 0) + ca->ca_ipl = IPL_NET; + + if (bus_space_map(iot, ca->ca_paddr, PAGE_SIZE, 0, &ioh) != 0) { + printf(": can't map registers!\n"); + return; + } /* Are we the boot device? */ if (ca->ca_paddr == bootaddr) @@ -278,7 +301,7 @@ leattach(parent, self, aux) * at any other address. * XXX These physical addresses should be mapped in extio!!! */ - switch ((int)ca->ca_paddr) { + switch (ca->ca_paddr) { case 0xffff1200: card = 0; break; @@ -316,7 +339,7 @@ leattach(parent, self, aux) return; } - lesc->sc_r1 = (void *)ca->ca_vaddr; + lesc->sc_r1 = (void *)bus_space_vaddr(iot, ioh); lesc->sc_ipl = ca->ca_ipl; lesc->sc_vec = ca->ca_vec; sc->sc_memsize = VLEMEMSIZE; diff --git a/sys/arch/mvme88k/dev/mainbus.c b/sys/arch/mvme88k/dev/mainbus.c index d5f70518c87..12a17d1ce47 100644 --- a/sys/arch/mvme88k/dev/mainbus.c +++ b/sys/arch/mvme88k/dev/mainbus.c @@ -1,5 +1,30 @@ -/* $OpenBSD: mainbus.c,v 1.10 2004/01/14 20:50:48 miod Exp $ */ -/* Copyright (c) 1998 Steve Murphree, Jr. */ +/* $OpenBSD: mainbus.c,v 1.11 2004/04/24 19:51:48 miod Exp $ */ +/* + * Copyright (c) 1998 Steve Murphree, Jr. + * Copyright (c) 2004, Miodrag Vallat. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + #include <sys/param.h> #include <sys/systm.h> #include <sys/reboot.h> @@ -7,14 +32,108 @@ #include <sys/device.h> #include <sys/disklabel.h> +#include <machine/bus.h> +#include <machine/autoconf.h> +#include <machine/board.h> #include <machine/cmmu.h> #include <machine/cpu.h> -#include <machine/autoconf.h> -void mainbus_attach(struct device *, struct device *, void *); -int mainbus_match(struct device *, void *, void *); -int mainbus_print(void *, const char *); -int mainbus_scan(struct device *, void *, void *); +void mainbus_attach(struct device *, struct device *, void *); +int mainbus_match(struct device *, void *, void *); +int mainbus_print(void *, const char *); +int mainbus_scan(struct device *, void *, void *); + +/* + * bus_space routines for 1:1 obio mappings + */ + +int mainbus_map(bus_addr_t, bus_size_t, int, bus_space_handle_t *); +void mainbus_unmap(bus_space_handle_t, bus_size_t); +int mainbus_subregion(bus_space_handle_t, bus_size_t, bus_size_t, + bus_space_handle_t *); +void *mainbus_vaddr(bus_space_handle_t); + +const struct mvme88k_bus_space_tag mainbus_bustag = { + mainbus_map, + mainbus_unmap, + mainbus_subregion, + mainbus_vaddr +}; + +/* + * Obio (internal IO) space is mapped 1:1 (see pmap_bootstrap() for details). + * + * However, sram attaches as a child of mainbus, but does not reside in + * internal IO space. As a result, we have to allow both 1:1 and iomap + * translations, depending upon the address to map. + */ + +int +mainbus_map(bus_addr_t addr, bus_size_t size, int flags, + bus_space_handle_t *ret) +{ + vaddr_t map; + static bus_addr_t threshold = 0; + + if (threshold == 0) { + switch (brdtyp) { +#ifdef MVME188 + case BRD_188: + threshold = MVME188_UTILITY; + break; +#endif +#ifdef MVME187 + case BRD_187: + case BRD_8120: +#endif +#ifdef MVME197 + case BRD_197: +#endif + threshold = OBIO_START; + break; + } + } + + if (addr >= threshold) + map = (vaddr_t)addr; + else { +#if 0 + map = iomap_mapin(addr, size, 0); +#else + map = (vaddr_t)mapiodev((void *)addr, size); +#endif + } + + if (map == NULL) + return ENOMEM; + + *ret = (bus_space_handle_t)map; + return 0; +} + +void +mainbus_unmap(bus_space_handle_t handle, bus_size_t size) +{ + /* XXX what to do for non-obio mappings? */ +} + +int +mainbus_subregion(bus_space_handle_t handle, bus_addr_t offset, + bus_size_t size, bus_space_handle_t *ret) +{ + *ret = handle + offset; + return (0); +} + +void * +mainbus_vaddr(bus_space_handle_t handle) +{ + return (void *)handle; +} + +/* + * Configuration glue + */ struct cfattach mainbus_ca = { sizeof(struct device), mainbus_match, mainbus_attach @@ -40,8 +159,8 @@ mainbus_print(args, bus) { struct confargs *ca = args; - if (ca->ca_paddr != (void *)-1) - printf(" addr 0x%x", (u_int32_t)ca->ca_paddr); + if (ca->ca_paddr != -1) + printf(" addr 0x%x", ca->ca_paddr); return (UNCONF); } @@ -54,10 +173,10 @@ mainbus_scan(parent, child, args) struct confargs oca; bzero(&oca, sizeof oca); - oca.ca_paddr = (void *)cf->cf_loc[0]; - oca.ca_vaddr = (void *)-1; - oca.ca_ipl = -1; + oca.ca_iot = &mainbus_bustag; oca.ca_bustype = BUS_MAIN; + oca.ca_paddr = cf->cf_loc[0]; + oca.ca_ipl = -1; oca.ca_name = cf->cf_driver->cd_name; if ((*cf->cf_attach->ca_match)(parent, cf, &oca) == 0) return (0); diff --git a/sys/arch/mvme88k/dev/memc.c b/sys/arch/mvme88k/dev/memc.c index 866a6925457..822585dbfa6 100644 --- a/sys/arch/mvme88k/dev/memc.c +++ b/sys/arch/mvme88k/dev/memc.c @@ -1,4 +1,4 @@ -/* $OpenBSD: memc.c,v 1.9 2004/01/14 20:50:48 miod Exp $ */ +/* $OpenBSD: memc.c,v 1.10 2004/04/24 19:51:48 miod Exp $ */ /* * Copyright (c) 1995 Theo de Raadt @@ -52,7 +52,6 @@ struct memcsoftc { struct device sc_dev; - void * sc_vaddr; struct memcreg *sc_memc; struct intrhand sc_ih; }; @@ -68,7 +67,9 @@ struct cfdriver memc_cd = { NULL, "memc", DV_DULL }; -/*int memcintr(struct frame *frame);*/ +#if 0 +int memcintr(struct frame *frame); +#endif int memcmatch(parent, vcf, args) @@ -76,7 +77,7 @@ memcmatch(parent, vcf, args) void *vcf, *args; { struct confargs *ca = args; - struct memcreg *memc = (struct memcreg *)ca->ca_vaddr; + struct memcreg *memc = (struct memcreg *)ca->ca_paddr; if (badvaddr((vaddr_t)memc, 4)) return (0); @@ -93,11 +94,7 @@ memcattach(parent, self, args) struct confargs *ca = args; struct memcsoftc *sc = (struct memcsoftc *)self; - /* - * since we know ourself to land in intiobase land, - * we must adjust our address - */ - sc->sc_memc = (struct memcreg *)ca->ca_vaddr; + sc->sc_memc = (struct memcreg *)ca->ca_paddr; printf(": %s rev %d", (sc->sc_memc->memc_chipid == MEMC_CHIPID) ? "MEMC040" : "MCECC", diff --git a/sys/arch/mvme88k/dev/nvram.c b/sys/arch/mvme88k/dev/nvram.c index 58e4a299c97..b485e566a36 100644 --- a/sys/arch/mvme88k/dev/nvram.c +++ b/sys/arch/mvme88k/dev/nvram.c @@ -1,4 +1,4 @@ -/* $OpenBSD: nvram.c,v 1.24 2004/04/15 21:35:59 miod Exp $ */ +/* $OpenBSD: nvram.c,v 1.25 2004/04/24 19:51:48 miod Exp $ */ /* * Copyright (c) 1995 Theo de Raadt @@ -54,10 +54,11 @@ struct nvramsoftc { struct device sc_dev; - void * sc_paddr; - void * sc_vaddr; - int sc_len; - void * sc_regs; + paddr_t sc_base; + bus_space_tag_t sc_iot; + bus_space_handle_t sc_ioh; + bus_addr_t sc_regs; + size_t sc_len; }; void nvramattach(struct device *, struct device *, void *); @@ -79,24 +80,27 @@ nvrammatch(parent, vcf, args) void *vcf, *args; { #if 0 - int ret; -#endif struct confargs *ca = args; + bus_space_handle_t ioh; + int rc; +#endif struct mvmeprom_time rtc; - ca->ca_vaddr = ca->ca_paddr; /* map 1:1 */ -/*X*/ if (ca->ca_vaddr == (void *)-1) -/*X*/ return (1); -#if 0 bugrtcrd(&rtc); - if (badvaddr(IIOV(ca->ca_vaddr), 1)) { - printf("==> nvram: address 0x%x failed check\n", ca->ca_vaddr); +#if 0 + if (bus_space_map(ca->ca_iot, ca->ca_paddr, PAGE_SIZE, 0, &ioh) != 0) return (0); + if (badvaddr(bus_space_vaddr(ca->ca_iot, ioh), 1)) { +#ifdef DEBUG + printf("==> nvram: address 0x%x failed check\n", ca->ca_paddr); +#endif + rc = 0; } else - return (1); + rc = 1; + bus_space_unmap(ca->ca_iot, ioh, PAGE_SIZE); + return rc; #else - bugrtcrd(&rtc); - return (1); + return 1; #endif } @@ -106,31 +110,29 @@ nvramattach(parent, self, args) void *args; { struct confargs *ca = args; - struct nvramsoftc *sc = (struct nvramsoftc *)self; - - sc->sc_paddr = ca->ca_paddr; - sc->sc_vaddr = ca->ca_vaddr; + struct nvramsoftc *sc = (struct nvramsoftc *)self; + bus_space_handle_t ioh; if (brdtyp == BRD_188) { sc->sc_len = MK48T02_SIZE; + sc->sc_regs = M188_NVRAM_TOD_OFF; } else { sc->sc_len = MK48T08_SIZE; + sc->sc_regs = SBC_NVRAM_TOD_OFF; } -/*X*/ if (sc->sc_vaddr == (void *)-1) -/*X*/ sc->sc_vaddr = mapiodev((void *)sc->sc_paddr, -/*X*/ max(sc->sc_len, NBPG)); -/*X*/ if (sc->sc_vaddr == NULL) -/*X*/ panic("failed to map!"); + sc->sc_iot = ca->ca_iot; + sc->sc_base = ca->ca_paddr; - if (brdtyp != BRD_188) { - sc->sc_regs = (void *)(sc->sc_vaddr + sc->sc_len - - sizeof(struct clockreg)); - } else { - sc->sc_regs = (void *)(sc->sc_vaddr + M188_NVRAM_TOD_OFF); + if (bus_space_map(sc->sc_iot, sc->sc_base, round_page(sc->sc_len), + 0, &ioh) != 0) { + printf(": can't map memory!\n"); + return; } - printf(": MK48T0%d len %d\n", sc->sc_len / 1024, sc->sc_len); + sc->sc_ioh = ioh; + + printf(": MK48T0%d\n", sc->sc_len / 1024); } /* @@ -303,27 +305,51 @@ inittodr(base) base = 21*SECYR + 186*SECDAY + SECDAY/2; badbase = 1; } - if (brdtyp != BRD_188) { - struct clockreg *cl = (struct clockreg *)sc->sc_regs; - cl->cl_csr |= CLK_READ; /* enable read (stop time) */ - sec = cl->cl_sec; - min = cl->cl_min; - hour = cl->cl_hour; - day = cl->cl_mday; - mon = cl->cl_month; - year = cl->cl_year; - cl->cl_csr &= ~CLK_READ; /* time wears on... */ - } else { /* CPU_188 */ - struct m188_clockreg *cl = (struct m188_clockreg *)sc->sc_regs; - cl->cl_csr |= CLK_READ; /* enable read (stop time) */ - sec = cl->cl_sec & 0xff; - min = cl->cl_min & 0xff; - hour = cl->cl_hour & 0xff; - day = cl->cl_mday & 0xff; - mon = cl->cl_month & 0xff; - year = cl->cl_year & 0xff; - cl->cl_csr &= ~CLK_READ; /* time wears on... */ + + if (brdtyp == BRD_188) { + bus_space_write_4(sc->sc_iot, sc->sc_ioh, + sc->sc_regs + (CLK_CSR << 2), CLK_READ | + bus_space_read_4(sc->sc_iot, sc->sc_ioh, + sc->sc_regs + (CLK_CSR << 2))); + sec = bus_space_read_4(sc->sc_iot, sc->sc_ioh, + sc->sc_regs + (CLK_SEC << 2)) & 0xff; + min = bus_space_read_4(sc->sc_iot, sc->sc_ioh, + sc->sc_regs + (CLK_MIN << 2)) & 0xff; + hour = bus_space_read_4(sc->sc_iot, sc->sc_ioh, + sc->sc_regs + (CLK_HOUR << 2)) & 0xff; + day = bus_space_read_4(sc->sc_iot, sc->sc_ioh, + sc->sc_regs + (CLK_DAY << 2)) & 0xff; + mon = bus_space_read_4(sc->sc_iot, sc->sc_ioh, + sc->sc_regs + (CLK_MONTH << 2)) & 0xff; + year = bus_space_read_4(sc->sc_iot, sc->sc_ioh, + sc->sc_regs + (CLK_YEAR << 2)) & 0xff; + bus_space_write_4(sc->sc_iot, sc->sc_ioh, + sc->sc_regs + (CLK_CSR << 2), + bus_space_read_4(sc->sc_iot, sc->sc_ioh, + sc->sc_regs + (CLK_CSR << 2)) & ~CLK_READ); + } else { + bus_space_write_1(sc->sc_iot, sc->sc_ioh, + sc->sc_regs + CLK_CSR, CLK_READ | + bus_space_read_1(sc->sc_iot, sc->sc_ioh, + sc->sc_regs + CLK_CSR)); + sec = bus_space_read_1(sc->sc_iot, sc->sc_ioh, + sc->sc_regs + CLK_SEC); + min = bus_space_read_1(sc->sc_iot, sc->sc_ioh, + sc->sc_regs + CLK_MIN); + hour = bus_space_read_1(sc->sc_iot, sc->sc_ioh, + sc->sc_regs + CLK_HOUR); + day = bus_space_read_1(sc->sc_iot, sc->sc_ioh, + sc->sc_regs + CLK_DAY); + mon = bus_space_read_1(sc->sc_iot, sc->sc_ioh, + sc->sc_regs + CLK_MONTH); + year = bus_space_read_1(sc->sc_iot, sc->sc_ioh, + sc->sc_regs + CLK_YEAR); + bus_space_write_1(sc->sc_iot, sc->sc_ioh, + sc->sc_regs + CLK_CSR, + bus_space_read_1(sc->sc_iot, sc->sc_ioh, + sc->sc_regs + CLK_CSR) & ~CLK_READ); } + if ((time.tv_sec = chiptotime(sec, min, hour, day, mon, year)) == 0) { printf("WARNING: bad date in nvram"); #ifdef DEBUG @@ -362,36 +388,57 @@ resettodr() { struct nvramsoftc *sc = (struct nvramsoftc *) nvram_cd.cd_devs[0]; struct chiptime c; - if (brdtyp != BRD_188) { - struct clockreg *cl = (struct clockreg *)sc->sc_regs; - if (!time.tv_sec || cl == NULL) - return; - timetochip(&c); - cl->cl_csr |= CLK_WRITE; /* enable write */ - cl->cl_sec = c.sec; - cl->cl_min = c.min; - cl->cl_hour = c.hour; - cl->cl_wday = c.wday; - cl->cl_mday = c.day; - cl->cl_month = c.mon; - cl->cl_year = c.year; - cl->cl_csr &= ~CLK_WRITE; /* load them up */ - } else { /* CPU_188 */ - struct m188_clockreg *cl = (struct m188_clockreg *)sc->sc_regs; - - if (!time.tv_sec || cl == NULL) - return; - timetochip(&c); - cl->cl_csr |= CLK_WRITE; /* enable write */ - cl->cl_sec = c.sec; - cl->cl_min = c.min; - cl->cl_hour = c.hour; - cl->cl_wday = c.wday; - cl->cl_mday = c.day; - cl->cl_month = c.mon; - cl->cl_year = c.year; - cl->cl_csr &= ~CLK_WRITE; /* load them up */ + if (!time.tv_sec || sc == NULL) + return; + timetochip(&c); + + if (brdtyp == BRD_188) { + bus_space_write_4(sc->sc_iot, sc->sc_ioh, + sc->sc_regs + (CLK_CSR << 2), CLK_WRITE | + bus_space_read_4(sc->sc_iot, sc->sc_ioh, + sc->sc_regs + (CLK_CSR << 2))); + bus_space_write_4(sc->sc_iot, sc->sc_ioh, + sc->sc_regs + (CLK_SEC << 2), c.sec); + bus_space_write_4(sc->sc_iot, sc->sc_ioh, + sc->sc_regs + (CLK_MIN << 2), c.min); + bus_space_write_4(sc->sc_iot, sc->sc_ioh, + sc->sc_regs + (CLK_HOUR << 2), c.hour); + bus_space_write_4(sc->sc_iot, sc->sc_ioh, + sc->sc_regs + (CLK_WDAY << 2), c.wday); + bus_space_write_4(sc->sc_iot, sc->sc_ioh, + sc->sc_regs + (CLK_DAY << 2), c.day); + bus_space_write_4(sc->sc_iot, sc->sc_ioh, + sc->sc_regs + (CLK_MONTH << 2), c.mon); + bus_space_write_4(sc->sc_iot, sc->sc_ioh, + sc->sc_regs + (CLK_YEAR << 2), c.year); + bus_space_write_4(sc->sc_iot, sc->sc_ioh, + sc->sc_regs + (CLK_CSR << 2), + bus_space_read_4(sc->sc_iot, sc->sc_ioh, + sc->sc_regs + (CLK_CSR << 2)) & ~CLK_WRITE); + } else { + bus_space_write_1(sc->sc_iot, sc->sc_ioh, + sc->sc_regs + CLK_CSR, CLK_WRITE | + bus_space_read_1(sc->sc_iot, sc->sc_ioh, + sc->sc_regs + CLK_CSR)); + bus_space_write_1(sc->sc_iot, sc->sc_ioh, + sc->sc_regs + CLK_SEC, c.sec); + bus_space_write_1(sc->sc_iot, sc->sc_ioh, + sc->sc_regs + CLK_MIN, c.min); + bus_space_write_1(sc->sc_iot, sc->sc_ioh, + sc->sc_regs + CLK_HOUR, c.hour); + bus_space_write_1(sc->sc_iot, sc->sc_ioh, + sc->sc_regs + CLK_WDAY, c.wday); + bus_space_write_1(sc->sc_iot, sc->sc_ioh, + sc->sc_regs + CLK_DAY, c.day); + bus_space_write_1(sc->sc_iot, sc->sc_ioh, + sc->sc_regs + CLK_MONTH, c.mon); + bus_space_write_1(sc->sc_iot, sc->sc_ioh, + sc->sc_regs + CLK_YEAR, c.year); + bus_space_write_1(sc->sc_iot, sc->sc_ioh, + sc->sc_regs + CLK_CSR, + bus_space_read_1(sc->sc_iot, sc->sc_ioh, + sc->sc_regs + CLK_CSR) & ~CLK_WRITE); } } @@ -452,12 +499,13 @@ nvramrw(dev, uio, flags) int unit = minor(dev); struct nvramsoftc *sc = (struct nvramsoftc *) nvram_cd.cd_devs[unit]; - return (memdevrw(sc->sc_vaddr, sc->sc_len, uio, flags)); + return (memdevrw(bus_space_vaddr(sc->sc_iot, sc->sc_ioh), + sc->sc_len, uio, flags)); } /* * If the NVRAM is of the 2K variety, an extra 2K of who-knows-what - * will also be mmap'd, due to NBPG being 4K. On the MVME147 the NVRAM + * will also be mmap'd, due to PAGE_SIZE being 4K. Usually, the NVRAM * repeats, so userland gets two copies back-to-back. */ paddr_t @@ -475,5 +523,5 @@ nvrammmap(dev, off, prot) /* allow access only in RAM */ if (off < 0 || off > sc->sc_len) return (-1); - return (atop(sc->sc_paddr + off)); + return (atop(sc->sc_base + off)); } diff --git a/sys/arch/mvme88k/dev/nvramreg.h b/sys/arch/mvme88k/dev/nvramreg.h index 4ff1b688b8e..9e024408555 100644 --- a/sys/arch/mvme88k/dev/nvramreg.h +++ b/sys/arch/mvme88k/dev/nvramreg.h @@ -1,4 +1,4 @@ -/* $OpenBSD: nvramreg.h,v 1.6 2003/10/11 22:08:57 miod Exp $ */ +/* $OpenBSD: nvramreg.h,v 1.7 2004/04/24 19:51:48 miod Exp $ */ /* * Copyright (c) 1992, 1993 @@ -59,41 +59,31 @@ * 1ff8-1fff TOD clock */ -struct clockreg { - volatile u_char cl_csr; /* control register */ - volatile u_char cl_sec; /* seconds (0..59; BCD) */ - volatile u_char cl_min; /* minutes (0..59; BCD) */ - volatile u_char cl_hour; /* hour (0..23; BCD) */ - volatile u_char cl_wday; /* weekday (1..7) */ - volatile u_char cl_mday; /* day in month (1..31; BCD) */ - volatile u_char cl_month; /* month (1..12; BCD) */ - volatile u_char cl_year; /* year (0..99; BCD) */ -}; - -struct m188_clockreg { - volatile u_long cl_csr; /* control register */ - volatile u_long cl_sec; /* seconds (0..59; BCD) */ - volatile u_long cl_min; /* minutes (0..59; BCD) */ - volatile u_long cl_hour; /* hour (0..23; BCD) */ - volatile u_long cl_wday; /* weekday (1..7) */ - volatile u_long cl_mday; /* day in month (1..31; BCD) */ - volatile u_long cl_month; /* month (1..12; BCD) */ - volatile u_long cl_year; /* year (0..99; BCD) */ -}; +/* + * On MVME188, these offsets need shifting two bits, as they are 32 bit + * registers. + */ +#define CLK_CSR 0 /* control register */ +#define CLK_SEC 1 /* seconds (0..59; BCD) */ +#define CLK_MIN 2 /* minutes (0..59; BCD) */ +#define CLK_HOUR 3 /* hour (0..23; BCD) */ +#define CLK_WDAY 4 /* weekday (1..7) */ +#define CLK_DAY 5 /* day in month (1..31; BCD) */ +#define CLK_MONTH 6 /* month (1..12; BCD) */ +#define CLK_YEAR 7 /* year (0..99; BCD) */ +#define CLK_NREG 8 -/* bits in cl_csr */ +/* csr bits */ #define CLK_WRITE 0x80 /* want to write */ #define CLK_READ 0x40 /* want to read (freeze clock) */ /* - * Motorola chose the year `1900' as their base count. - * XXX what happens when it wraps? + * Motorola chose the year `1900' as their base count. It has already + * wrapped by now... */ #define YEAR0 00 -#define NVRAMSIZE 0x8000 -#define SBC_NVRAM_TOD_OFF 0x1FF8 /* offset of tod in NVRAM space */ -#define M188_NVRAM_TOD_OFF 0x1FE0 /* offset of tod in NVRAM space */ -#define MK48T02_SIZE 2*1024 -#define MK48T08_SIZE 8*1024 - +#define SBC_NVRAM_TOD_OFF 0x1ff8 /* offset of tod in NVRAM space */ +#define M188_NVRAM_TOD_OFF 0x1fe0 /* offset of tod in NVRAM space */ +#define MK48T02_SIZE 2 * 1024 +#define MK48T08_SIZE 8 * 1024 diff --git a/sys/arch/mvme88k/dev/pcctwo.c b/sys/arch/mvme88k/dev/pcctwo.c index 30253fe3b1e..d084664a55f 100644 --- a/sys/arch/mvme88k/dev/pcctwo.c +++ b/sys/arch/mvme88k/dev/pcctwo.c @@ -1,4 +1,4 @@ -/* $OpenBSD: pcctwo.c,v 1.23 2004/04/16 23:36:48 miod Exp $ */ +/* $OpenBSD: pcctwo.c,v 1.24 2004/04/24 19:51:48 miod Exp $ */ /* * Copyright (c) 1995 Theo de Raadt * All rights reserved. @@ -45,20 +45,13 @@ #include <dev/cons.h> -#include <mvme88k/dev/pcctwofunc.h> #include <mvme88k/dev/pcctworeg.h> +#include <mvme88k/dev/pcctwovar.h> #include "bussw.h" -struct pcctwosoftc { - struct device sc_dev; - void *sc_vaddr; /* PCC2 space */ - void *sc_paddr; - struct pcctworeg *sc_pcc2; /* the actual registers */ -}; - -void pcctwoattach(struct device *, struct device *, void *); -int pcctwomatch(struct device *, void *, void *); +void pcctwoattach(struct device *, struct device *, void *); +int pcctwomatch(struct device *, void *, void *); struct cfattach pcctwo_ca = { sizeof(struct pcctwosoftc), pcctwomatch, pcctwoattach @@ -68,12 +61,8 @@ struct cfdriver pcctwo_cd = { NULL, "pcctwo", DV_DULL }; -struct pcctworeg *sys_pcc2 = NULL; - -int pcc2bus; - -int pcctwo_print(void *args, const char *bus); -int pcctwo_scan(struct device *parent, void *child, void *args); +int pcctwo_print(void *args, const char *bus); +int pcctwo_scan(struct device *parent, void *child, void *args); int pcctwomatch(parent, vcf, args) @@ -81,31 +70,73 @@ pcctwomatch(parent, vcf, args) void *vcf, *args; { struct confargs *ca = args; - struct pcctworeg *pcc2; + bus_space_handle_t ioh; + int rc; + u_int8_t chipid; /* Bomb if wrong cpu */ switch (brdtyp) { case BRD_187: case BRD_8120: - pcc2 = (struct pcctworeg *)(IIOV(ca->ca_paddr) + PCC2_PCC2CHIP_OFF); - break; - case BRD_197: /* pcctwo is a child of buswitch XXX smurph */ - pcc2 = (struct pcctworeg *)(IIOV(ca->ca_paddr)); + case BRD_197: break; default: - /* Bomb if wrong board */ - return (0); + return 0; } - if (badvaddr((vaddr_t)pcc2, 4)) { - printf("==> pcctwo: failed address check.\n"); - return (0); + if (bus_space_map(ca->ca_iot, ca->ca_paddr + PCC2_BASE, PCC2_SIZE, + 0, &ioh) != 0) + return 0; + rc = badvaddr((vaddr_t)bus_space_vaddr(ca->ca_iot, ioh), 4); + if (rc == 0) { + chipid = bus_space_read_1(ca->ca_iot, ioh, PCCTWO_CHIPID); + if (chipid != PCC2_ID) { +#ifdef DEBUG + printf("==> pcctwo: wrong chip id %x.\n", chipid); + rc = -1; +#endif + } } - if (pcc2->pcc2_chipid != PCC2_CHIPID) { - printf("==> pcctwo: wrong chip id %x.\n", pcc2->pcc2_chipid); - return (0); + bus_space_unmap(ca->ca_iot, ioh, PCC2_SIZE); + + return rc == 0; +} + +void +pcctwoattach(parent, self, args) + struct device *parent, *self; + void *args; +{ + struct confargs *ca = args; + struct pcctwosoftc *sc = (struct pcctwosoftc *)self; + bus_space_handle_t ioh; + u_int8_t genctl; + + sc->sc_base = ca->ca_paddr + PCC2_BASE; + + if (bus_space_map(ca->ca_iot, sc->sc_base, PCC2_SIZE, 0, &ioh) != 0) { + printf(": can't map registers!\n"); + return; } - return (1); + + sc->sc_iot = ca->ca_iot; + sc->sc_ioh = ioh; + + bus_space_write_1(sc->sc_iot, ioh, PCCTWO_VECBASE, PCC2_VECBASE); + genctl = bus_space_read_1(sc->sc_iot, ioh, PCCTWO_GENCTL); +#if NBUSSW > 0 + if (ca->ca_bustype == BUS_BUSSWITCH) { + /* Make sure the bus is mc68040 compatible */ + genctl |= PCC2_GENCTL_C040; + } +#endif + genctl |= PCC2_GENCTL_IEN; /* global irq enable */ + bus_space_write_1(sc->sc_iot, ioh, PCCTWO_GENCTL, genctl); + + printf(": rev %d\n", + bus_space_read_1(sc->sc_iot, ioh, PCCTWO_CHIPREV)); + + config_search(pcctwo_scan, self, args); } int @@ -132,17 +163,16 @@ pcctwo_scan(parent, child, args) struct confargs oca; bzero(&oca, sizeof oca); + oca.ca_iot = sc->sc_iot; oca.ca_offset = cf->cf_loc[0]; oca.ca_ipl = cf->cf_loc[1]; - if (((int)oca.ca_offset != -1) && ISIIOVA(sc->sc_vaddr + oca.ca_offset)) { - oca.ca_vaddr = sc->sc_vaddr + oca.ca_offset; - oca.ca_paddr = sc->sc_paddr + oca.ca_offset; + if (oca.ca_offset != -1) { + /* offset locator for pcctwo children is relative to segment */ + oca.ca_paddr = sc->sc_base - PCC2_BASE + oca.ca_offset; } else { - oca.ca_vaddr = (void *)-1; - oca.ca_paddr = (void *)-1; + oca.ca_paddr = -1; } oca.ca_bustype = BUS_PCCTWO; - oca.ca_master = (void *)sc->sc_pcc2; oca.ca_name = cf->cf_driver->cd_name; if ((*cf->cf_attach->ca_match)(parent, cf, &oca) == 0) return (0); @@ -150,54 +180,6 @@ pcctwo_scan(parent, child, args) return (1); } -void -pcctwoattach(parent, self, args) -struct device *parent, *self; -void *args; -{ - struct confargs *ca = args; - struct pcctwosoftc *sc = (struct pcctwosoftc *)self; - - if (sys_pcc2) - panic("pcc2 already attached!"); - - /* - * since we know ourself to land in intiobase land, - * we must adjust our address - */ - sc->sc_paddr = ca->ca_paddr; - sc->sc_vaddr = (void *)IIOV(sc->sc_paddr); - - pcc2bus = ca->ca_bustype; - - switch (pcc2bus) { - case BUS_MAIN: - sc->sc_pcc2 = (struct pcctworeg *)(sc->sc_vaddr + PCC2_PCC2CHIP_OFF); - break; -#if NBUSSW > 0 - case BUS_BUSSWITCH: - sc->sc_pcc2 = (struct pcctworeg *)sc->sc_vaddr; - /* - * fake up our address so that pcc2 child devices - * are offset of 0xFFF00000 - XXX smurph - */ - sc->sc_paddr -= PCC2_PCC2CHIP_OFF; - sc->sc_vaddr -= PCC2_PCC2CHIP_OFF; - /* make sure the bus is mc68040 compatible */ - sc->sc_pcc2->pcc2_genctl |= PCC2_GENCTL_C040; - break; -#endif - } - sys_pcc2 = sc->sc_pcc2; - - printf(": rev %d\n", sc->sc_pcc2->pcc2_chiprev); - - sc->sc_pcc2->pcc2_vecbase = PCC2_VECBASE; - sc->sc_pcc2->pcc2_genctl |= PCC2_GENCTL_IEN; /* global irq enable */ - - config_search(pcctwo_scan, self, args); -} - /* * PCC2 interrupts land in a PCC2_NVEC sized hole starting at PCC2_VECBASE */ diff --git a/sys/arch/mvme88k/dev/pcctwofunc.h b/sys/arch/mvme88k/dev/pcctwofunc.h deleted file mode 100644 index 7cbfe3abbe5..00000000000 --- a/sys/arch/mvme88k/dev/pcctwofunc.h +++ /dev/null @@ -1,9 +0,0 @@ -/* $OpenBSD: pcctwofunc.h,v 1.4 2002/03/14 01:26:39 millert Exp $ */ - -#ifndef _MVME88K_PCCTWO_H_ -#define _MVME88K_PCCTWO_H_ - -int pcctwointr_establish(int vec, struct intrhand *ih); - -#endif /* _MVME88K_PCCTWO_H_ */ - diff --git a/sys/arch/mvme88k/dev/pcctworeg.h b/sys/arch/mvme88k/dev/pcctworeg.h index 268d481ef5c..41a95b770fa 100644 --- a/sys/arch/mvme88k/dev/pcctworeg.h +++ b/sys/arch/mvme88k/dev/pcctworeg.h @@ -1,141 +1,101 @@ -/* $OpenBSD: pcctworeg.h,v 1.6 2002/01/14 21:34:39 miod Exp $ */ +/* $OpenBSD: pcctworeg.h,v 1.7 2004/04/24 19:51:48 miod Exp $ */ /* - * Memory map for PCC2 chip found in mvme1x7 boards. + * Memory map for PCC2 chip found in MVME1x7 boards. * * PCCchip2 control and status register can be accessed as bytes (8 bits), * two-bytes (16 bits), or four-bytes (32 bits). */ -struct pcctworeg { - volatile u_char pcc2_chipid; - volatile u_char pcc2_chiprev; - volatile u_char pcc2_genctl; - volatile u_char pcc2_vecbase; /* irq vector base */ - volatile u_long pcc2_t1cmp; /* timer1 compare */ - volatile u_long pcc2_t1count; /* timer1 count */ - volatile u_long pcc2_t2cmp; /* timer2 compare */ - volatile u_long pcc2_t2count; /* timer2 count */ - volatile u_char pcc2_pscalecnt; /* timer prescaler counter */ - volatile u_char pcc2_pscaleadj; /* timer prescaler adjust */ - volatile u_char pcc2_t2ctl; /* timer2 ctrl reg */ - volatile u_char pcc2_t1ctl; /* timer1 ctrl reg */ - volatile u_char pcc2_gpioirq; /* gpio irq */ - volatile u_char pcc2_gpio; /* gpio i/o */ - volatile u_char pcc2_t2irq; - volatile u_char pcc2_t1irq; - volatile u_char pcc2_sccerr; - volatile u_char pcc2_sccirq; - volatile u_char pcc2_scctx; - volatile u_char pcc2_sccrx; - volatile u_char :8; - volatile u_char :8; - volatile u_char :8; - volatile u_char pcc2_sccmoiack; - volatile u_char :8; - volatile u_char pcc2_scctxiack; - volatile u_char :8; - volatile u_char pcc2_sccrxiack; - volatile u_char pcc2_ieerr; - volatile u_char :8; - volatile u_char pcc2_ieirq; - volatile u_char pcc2_iefailirq; - volatile u_char pcc2_ncrerr; - volatile u_char :8; - volatile u_char :8; - volatile u_char pcc2_ncrirq; - volatile u_char pcc2_prtairq; - volatile u_char pcc2_prtfirq; - volatile u_char pcc2_prtsirq; - volatile u_char pcc2_prtpirq; - volatile u_char pcc2_prtbirq; - volatile u_char :8; - volatile u_char pcc2_prtstat; - volatile u_char pcc2_prtctl; - volatile u_short pcc2_speed; /* DO NOT USE */ - volatile u_short pcc2_prtdat; - volatile u_short :16; - /* The following regs are not valid on MVME197 */ - volatile u_char pcc2_ipl; - volatile u_char pcc2_mask; -}; -#define PCC2_PCC2CHIP_OFF 0x42000 -#define PCC2_CHIPID 0x20 -#define PCC2_BASE_ADDR 0xFFF42000 /* base address */ -#define PCC2_SIZE 0x1000 /* size */ -#define PCC2_CHIP_REV 0x00 - -/* General Control Register */ - +#define PCC2_BASE 0x00042000 +#define PCC2_SIZE 0x0040 + +#define PCCTWO_CHIPID 0x0000 +#define PCCTWO_CHIPREV 0x0001 +#define PCCTWO_GENCTL 0x0002 +#define PCCTWO_VECBASE 0x0003 +#define PCCTWO_T1CMP 0x0004 +#define PCCTWO_T1COUNT 0x0008 +#define PCCTWO_T2CMP 0x000c +#define PCCTWO_T2COUNT 0x0010 +#define PCCTWO_PSCALECNT 0x0014 +#define PCCTWO_PSCALEADJ 0x0015 +#define PCCTWO_T2CTL 0x0016 +#define PCCTWO_T1CTL 0x0017 +#define PCCTWO_GPIO_ICR 0x0018 +#define PCCTWO_GPIO_PCR 0x0019 +#define PCCTWO_T2ICR 0x001a +#define PCCTWO_T1ICR 0x001b +#define PCCTWO_SCCERR 0x001c +#define PCCTWO_SCCICR 0x001d +#define PCCTWO_SCCTX 0x001e +#define PCCTWO_SCCRX 0x001f +#define PCCTWO_SCCMOIACK 0x0023 +#define PCCTWO_SCCTXIACK 0x0025 +#define PCCTWO_SCCRXIACK 0x0027 +#define PCCTWO_IEERR 0x0028 +#define PCCTWO_IEICR 0x002a +#define PCCTWO_IEBERR 0x002b +#define PCCTWO_SCSIERR 0x002c +#define PCCTWO_SCSIICR 0x002f +#define PCCTWO_PRTICR 0x0030 +#define PCCTWO_PTRFICR 0x0031 +#define PCCTWO_PTRSICR 0x0032 +#define PCCTWO_PTRPICR 0x0033 +#define PCCTWO_PRTBICR 0x0034 +#define PCCTWO_PRTSTATUS 0x0036 +#define PCCTWO_PRTCTL 0x0037 +#define PCCTWO_SPEED 0x0038 +#define PCCTWO_PRTDATA 0x003a +/* The following registers are not valid on MVME197 */ +#define PCCTWO_IPL 0x003e +#define PCCTWO_MASK 0x003f + +#define PCC2_ID 0x20 /* value at CHIPID */ + +/* General Control Register */ #define PCC2_DR0 0x80 #define PCC2_C040 0x04 #define PCC2_MIEN 0x02 #define PCC2_FAST 0x01 /* Top 4 bits of the PCC2 VBR. Will be the top 4 bits of the vector */ - #define PCC2_VECT 0x50 /* Bottom 4 bits of the vector returned during IACK cycle */ -#define PPBSY 0x00 /* lowest */ -#define PPSE 0x01 -#define PPSEL 0x02 -#define PPFLT 0x03 -#define PPACK 0x04 -#define SCSIIRQ 0x05 -#define LANCERR 0x06 -#define LANCIRQ 0x07 -#define TIMER1IRQ 0x08 -#define TIMER2IRQ 0x09 -#define GPIOIRQ 0x0a -#define SRXEIRQ 0x0c -#define SMOIRQ 0x0d -#define STxIRQ 0x0e -#define SRxIRQ 0x0f - +#define PCC2V_PPBUSY 0x00 /* lowest */ +#define PCC2V_PPPE 0x01 +#define PCC2V_PPSELECT 0x02 +#define PCC2V_PPFAULT 0x03 +#define PCC2V_PPACK 0x04 +#define PCC2V_SCSI 0x05 +#define PCC2V_IEFAIL 0x06 +#define PCC2V_IE 0x07 +#define PCC2V_TIMER2 0x08 +#define PCC2V_TIMER1 0x09 +#define PCC2V_GPIO 0x0a +#define PCC2V_SCC_RXE 0x0c +#define PCC2V_SCC_M (PCC2V_SCC_RXE + 1) +#define PCC2V_SCC_TX (PCC2V_SCC_M + 1) +#define PCC2V_SCC_RX (PCC2V_SCC_TX + 1) /* * Vaddrs for interrupt mask and pri registers */ -extern u_char *volatile pcc2intr_mask; -extern u_char *volatile pcc2intr_ipl; - -/* - * points to system's PCCTWO. This is not active until the pcctwo0 - * device has been attached. - */ -extern struct pcctworeg *sys_pcc2; +extern u_int8_t *volatile pcc2intr_mask; +extern u_int8_t *volatile pcc2intr_ipl; /* * We lock off our interrupt vector at 0x50. */ #define PCC2_VECBASE 0x50 -#define PCC2_NVEC 16 - -/* - * Vectors we use - */ -#define PCC2V_NCR 0x05 -#define PCC2V_IEFAIL 0x06 -#define PCC2V_IE 0x07 -#define PCC2V_TIMER2 0x08 -#define PCC2V_TIMER1 0x09 -#define PCC2V_GPIO 0x0a -#define PCC2V_SCC_RXE 0x0c -#define PCC2V_SCC_M 0x0d -#define PCC2V_SCC_TX 0x0e -#define PCC2V_SCC_RX 0x0f +#define PCC2_NVEC 0x10 #define PCC2_TCTL_CEN 0x01 #define PCC2_TCTL_COC 0x02 #define PCC2_TCTL_COVF 0x04 #define PCC2_TCTL_OVF 0xf0 -#define PCC2_TICTL_CEN 0x01 -#define PCC2_TICTL_COC 0x02 -#define PCC2_TICTL_COVF 0x04 -#define PCC2_TTCTL_OVF_MASK (1 << 4) /* overflow bits mask */ - #define PCC2_GPIO_PLTY 0x80 #define PCC2_GPIO_EL 0x40 @@ -143,10 +103,11 @@ extern struct pcctworeg *sys_pcc2; #define PCC2_GPIOCR_O 0x1 #define PCC2_SCC_AVEC 0x08 -#define PCC2_SCCRX_INHIBIT (0 << 6) -#define PCC2_SCCRX_SNOOP (1 << 6) -#define PCC2_SCCRX_INVAL (2 << 6) -#define PCC2_SCCRX_RESV (3 << 6) + +#define PCC2_SC_INHIBIT (0 << 6) +#define PCC2_SC_SNOOP (1 << 6) +#define PCC2_SC_INVAL (2 << 6) +#define PCC2_SC_RESV (3 << 6) #define pcc2_timer_us2lim(us) (us) /* timer increments in "us" */ @@ -156,19 +117,13 @@ extern struct pcctworeg *sys_pcc2; #define PCC2_IRQ_INT 0x20 /* Tick Timer Interrupt Control Register */ - -#define PCC2_TTIRQ_INT 0x20 -#define PCC2_TTIRQ_IEN 0x10 -#define PCC2_TTIRQ_ICLR 0x08 -#define PCC2_TTIRQ_IL 0x07 /* mask for IL2-IL0 */ +#define PCC2_TTIRQ_INT 0x20 +#define PCC2_TTIRQ_IEN 0x10 +#define PCC2_TTIRQ_ICLR 0x08 +#define PCC2_TTIRQ_IL 0x07 /* mask for IL2-IL0 */ #define PCC2_IEERR_SCLR 0x01 #define PCC2_GENCTL_FAST 0x01 #define PCC2_GENCTL_IEN 0x02 #define PCC2_GENCTL_C040 0x03 - -#define PCC2_SC_INHIBIT (0 << 6) -#define PCC2_SC_SNOOP (1 << 6) -#define PCC2_SC_INVAL (2 << 6) -#define PCC2_SC_RESV (3 << 6) diff --git a/sys/arch/mvme88k/dev/pcctwovar.h b/sys/arch/mvme88k/dev/pcctwovar.h new file mode 100644 index 00000000000..7e4f57fcf7d --- /dev/null +++ b/sys/arch/mvme88k/dev/pcctwovar.h @@ -0,0 +1,41 @@ +/* $OpenBSD: pcctwovar.h,v 1.1 2004/04/24 19:51:48 miod Exp $ */ +/* + * Copyright (c) 2004, Miodrag Vallat. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _MVME88K_PCCTWOVAR_H_ +#define _MVME88K_PCCTWOVAR_H_ + +struct pcctwosoftc { + struct device sc_dev; + + paddr_t sc_base; + + bus_space_tag_t sc_iot; + bus_space_handle_t sc_ioh; +}; + +int pcctwointr_establish(int vec, struct intrhand *ih); + +#endif /* _MVME88K_PCCTWOVAR_H_ */ diff --git a/sys/arch/mvme88k/dev/sram.c b/sys/arch/mvme88k/dev/sram.c index 39f91c8216a..abb15eb3170 100644 --- a/sys/arch/mvme88k/dev/sram.c +++ b/sys/arch/mvme88k/dev/sram.c @@ -1,4 +1,4 @@ -/* $OpenBSD: sram.c,v 1.16 2004/04/15 21:35:59 miod Exp $ */ +/* $OpenBSD: sram.c,v 1.17 2004/04/24 19:51:48 miod Exp $ */ /* * Copyright (c) 1995 Theo de Raadt @@ -43,10 +43,11 @@ #include <uvm/uvm_extern.h> struct sramsoftc { - struct device sc_dev; - void * sc_paddr; - void * sc_vaddr; - int sc_len; + struct device sc_dev; + paddr_t sc_base; + size_t sc_len; + bus_space_tag_t sc_iot; + bus_space_handle_t sc_ioh; }; void sramattach(struct device *, struct device *, void *); @@ -65,15 +66,10 @@ srammatch(parent, vcf, args) struct device *parent; void *vcf, *args; { - struct confargs *ca = args; - - if (brdtyp != BRD_187 && brdtyp != BRD_8120) /* The only one... */ + if (brdtyp != BRD_187 && brdtyp != BRD_8120) /* The only ones... */ return (0); - ca->ca_paddr = (void *)0xffe00000; - ca->ca_vaddr = (void *)0xffe00000; - - return (!badvaddr((vaddr_t)ca->ca_vaddr, 1)); + return (1); } void @@ -83,28 +79,20 @@ sramattach(parent, self, args) { struct confargs *ca = args; struct sramsoftc *sc = (struct sramsoftc *)self; + bus_space_handle_t ioh; - switch (brdtyp) { -#ifdef MVME187 - case BRD_187: - case BRD_8120: - sc->sc_len = 128*1024; /* always 128K */ - break; -#endif - default: - sc->sc_len = 0; - break; + sc->sc_iot = ca->ca_iot; + sc->sc_base = ca->ca_paddr; + sc->sc_len = 128 * 1024; /* always 128K */ + + if (bus_space_map(sc->sc_iot, sc->sc_base, sc->sc_len, 0, &ioh) != 0) { + printf(": can't map memory!\n"); + return; } - printf(": len %d", sc->sc_len); + sc->sc_ioh = ioh; - sc->sc_paddr = ca->ca_paddr; - sc->sc_vaddr = mapiodev((void *)sc->sc_paddr, sc->sc_len); - if (sc->sc_vaddr == NULL) { - sc->sc_len = 0; - printf(" -- failed to map"); - } - printf("\n"); + printf(": %dKB\n", sc->sc_len / 1024); } /*ARGSUSED*/ @@ -165,7 +153,8 @@ sramrw(dev, uio, flags) int unit = minor(dev); struct sramsoftc *sc = (struct sramsoftc *) sram_cd.cd_devs[unit]; - return (memdevrw(sc->sc_vaddr, sc->sc_len, uio, flags)); + return memdevrw(bus_space_vaddr(sc->sc_iot, sc->sc_ioh), + sc->sc_len, uio, flags); } paddr_t @@ -183,5 +172,5 @@ srammmap(dev, off, prot) /* allow access only in RAM */ if (off < 0 || off > sc->sc_len) return (-1); - return (atop(sc->sc_paddr + off)); + return (atop(sc->sc_base + off)); } diff --git a/sys/arch/mvme88k/dev/ssh.c b/sys/arch/mvme88k/dev/ssh.c index 0512b281923..af797585519 100644 --- a/sys/arch/mvme88k/dev/ssh.c +++ b/sys/arch/mvme88k/dev/ssh.c @@ -1,4 +1,4 @@ -/* $OpenBSD: ssh.c,v 1.26 2004/03/26 00:04:51 miod Exp $ */ +/* $OpenBSD: ssh.c,v 1.27 2004/04/24 19:51:48 miod Exp $ */ /* * Copyright (c) 1994 Michael L. Hitch @@ -49,6 +49,7 @@ #include <uvm/uvm_extern.h> +#include <machine/bus.h> #include <machine/autoconf.h> #include <machine/cmmu.h> #include <machine/pmap.h> @@ -61,11 +62,8 @@ #include <mvme88k/dev/sshreg.h> #include <mvme88k/dev/sshvar.h> -#include "pcctwo.h" -#if NPCCTWO > 0 -#include <mvme88k/dev/pcctwofunc.h> #include <mvme88k/dev/pcctworeg.h> -#endif +#include <mvme88k/dev/pcctwovar.h> int sshmatch(struct device *, void *, void *); void sshattach(struct device *, struct device *, void *); @@ -211,7 +209,7 @@ sshmatch(pdp, vcf, args) { struct confargs *ca = args; - if (badvaddr((vaddr_t)IIOV(ca->ca_vaddr), 4) == 0) + if (badvaddr(ca->ca_paddr, 4) == 0) return (1); /* @@ -233,7 +231,7 @@ sshmatch(pdp, vcf, args) dio.blk_cnt = 1; bugdiskrd(&dio); - if (badvaddr((vaddr_t)IIOV(ca->ca_vaddr), 4) == 0) + if (badvaddr(ca->ca_paddr, 4) == 0) return (1); } @@ -251,7 +249,7 @@ sshattach(parent, self, auxp) int tmp; extern int cpuspeed; - sc->sc_sshp = rp = ca->ca_vaddr; + sc->sc_sshp = rp = (void *)ca->ca_paddr; /* * ssh uses sc_clock_freq to define the dcntl & ctest7 reg values @@ -287,30 +285,24 @@ sshattach(parent, self, auxp) sc->sc_ih.ih_wantframe = 0; sc->sc_ih.ih_ipl = ca->ca_ipl; - sshinitialize(sc); + sshinitialize(sc); /* XXX move later? */ - switch (ca->ca_bustype) { -#if NPCCTWO > 0 - case BUS_PCCTWO: - { - /* - * Disable caching for the softc. Actually, I want - * to disable cache for acb structures, but they are - * part of softc, and I am disabling the entire softc - * just in case. - */ + pcctwointr_establish(PCC2V_SCSI, &sc->sc_ih); - struct pcctworeg *pcc2 = (struct pcctworeg *)ca->ca_master; + /* + * Disable caching for the softc. Actually, I want to disable cache + * for acb structures, but they are part of softc, and I am disabling + * the entire softc just in case. + */ + pmap_cache_ctrl(pmap_kernel(), trunc_page((vaddr_t)sc), + round_page((vaddr_t)sc + sizeof(*sc)), CACHE_INH); - pmap_cache_ctrl(pmap_kernel(), trunc_page((vaddr_t)sc), - round_page((vaddr_t)sc + sizeof(*sc)), CACHE_INH); + /* enable device interrupts */ + { + struct pcctwosoftc *pcctwo = (struct pcctwosoftc *)parent; - pcctwointr_establish(PCC2V_NCR, &sc->sc_ih); - /* enable interrupts at ca_ipl */ - pcc2->pcc2_ncrirq = ca->ca_ipl | PCC2_IRQ_IEN; - break; - } -#endif + bus_space_write_1(pcctwo->sc_iot, pcctwo->sc_ioh, + PCCTWO_SCSIICR, PCC2_IRQ_IEN | (ca->ca_ipl & PCC2_IRQ_IPL)); } evcnt_attach(&sc->sc_dev, "intr", &sc->sc_intrcnt); @@ -363,6 +355,7 @@ ssh_dmaintr(arg) sc->sc_intrcnt.ev_count++; return (1); } + /* * dummy routine to debug while loops */ @@ -776,7 +769,7 @@ sshinitialize(sc) sc->sc_tcp[0] = 3000 / sc->sc_clock_freq; #endif - sshreset (sc); + sshreset(sc); } void @@ -1518,8 +1511,10 @@ ssh_checkintr(sc, istat, dstat, sstat0, status) #endif /* XXX assumes it was not select */ if (sc->sc_nexus == NULL) { +#if 0 printf("%s: reselect interrupted, sc_nexus == NULL\n", sc->sc_dev.dv_xname); +#endif #if 0 ssh_dump(sc); #ifdef DDB diff --git a/sys/arch/mvme88k/dev/syscon.c b/sys/arch/mvme88k/dev/syscon.c index 680a6e19f17..be60b4043d5 100644 --- a/sys/arch/mvme88k/dev/syscon.c +++ b/sys/arch/mvme88k/dev/syscon.c @@ -1,4 +1,4 @@ -/* $OpenBSD: syscon.c,v 1.18 2004/04/16 23:36:48 miod Exp $ */ +/* $OpenBSD: syscon.c,v 1.19 2004/04/24 19:51:48 miod Exp $ */ /* * Copyright (c) 1999 Steve Murphree, Jr. * All rights reserved. @@ -39,46 +39,26 @@ #include <machine/board.h> #include <machine/frame.h> -#include <mvme88k/dev/sysconfunc.h> #include <mvme88k/dev/sysconreg.h> -struct sysconreg syscon_reg = { - (unsigned int *volatile)IEN0_REG, (unsigned int *volatile)IEN1_REG, - (unsigned int *volatile)IEN2_REG, (unsigned int *volatile)IEN3_REG, - (unsigned int *volatile)IENALL_REG, (unsigned int *volatile)IST_REG, - (unsigned int *volatile)SETSWI_REG, (unsigned int *volatile)CLRSWI_REG, - (unsigned int *volatile)ISTATE_REG, (unsigned int *volatile)CLRINT_REG, - (unsigned char *volatile)GLB0, (unsigned char *volatile)GLB1, - (unsigned char *volatile)GLB2, (unsigned char *volatile)GLB3, - (unsigned int *volatile)UCSR_REG, (unsigned int *volatile)GLBRES_REG, - (unsigned int *volatile)CCSR_REG, (unsigned int *volatile)ERROR_REG, - (unsigned int *volatile)PCNFA_REG, (unsigned int *volatile)PCNFB_REG, - (unsigned int *volatile)EXTAD_REG, (unsigned int *volatile)EXTAM_REG, - (unsigned int *volatile)WHOAMI_REG, (unsigned int *volatile)WMAD_REG, - (unsigned int *volatile)RMAD_REG, (unsigned int *volatile)WVAD_REG, - (unsigned int *volatile)RVAD_REG, (unsigned int *volatile)CIO_PORTC, - (unsigned int *volatile)CIO_PORTB, (unsigned int *volatile)CIO_PORTA, - (unsigned int *volatile)CIO_CTRL - }; - struct sysconsoftc { struct device sc_dev; - void *sc_vaddr; /* Utility I/O space */ - void *sc_paddr; - struct sysconreg *sc_syscon; /* the actual registers */ + struct intrhand sc_abih; /* `abort' switch */ struct intrhand sc_acih; /* `ac fail' */ struct intrhand sc_sfih; /* `sys fail' */ struct intrhand sc_m188ih; /* `m188 interrupt' */ }; -void sysconattach(struct device *, struct device *, void *); -int sysconmatch(struct device *, void *, void *); -void setupiackvectors(void); -int sysconabort(void *); -int sysconacfail(void *); -int sysconsysfail(void *); -int sysconm188(void *); +void sysconattach(struct device *, struct device *, void *); +int sysconmatch(struct device *, void *, void *); + +int syscon_print(void *, const char *); +int syscon_scan(struct device *, void *, void *); +int sysconabort(void *); +int sysconacfail(void *); +int sysconsysfail(void *); +int sysconm188(void *); struct cfattach syscon_ca = { sizeof(struct sysconsoftc), sysconmatch, sysconattach @@ -88,32 +68,15 @@ struct cfdriver syscon_cd = { NULL, "syscon", DV_DULL }; -struct sysconreg *sys_syscon; - -int syscon_print(void *args, const char *bus); -int syscon_scan(struct device *parent, void *child, void *args); - int sysconmatch(parent, vcf, args) struct device *parent; void *vcf, *args; { - struct confargs *ca = args; - struct sysconreg *syscon; - /* Don't match if wrong cpu */ if (brdtyp != BRD_188) return (0); - /* Only allow one instance */ - if (sys_syscon != NULL) - return (0); - - /* - * Uh, MVME188 better have on of these, so always match if it - * is a MVME188... - */ - syscon = (struct sysconreg *)(IIOV(ca->ca_paddr)); return (1); } @@ -137,21 +100,18 @@ syscon_scan(parent, child, args) void *child, *args; { struct cfdata *cf = child; - struct sysconsoftc *sc = (struct sysconsoftc *)parent; - struct confargs oca; + struct confargs oca, *ca = args; bzero(&oca, sizeof oca); + oca.ca_iot = ca->ca_iot; oca.ca_offset = cf->cf_loc[0]; oca.ca_ipl = cf->cf_loc[1]; - if ((oca.ca_offset != -1) && ISIIOVA(sc->sc_vaddr + oca.ca_offset)) { - oca.ca_vaddr = sc->sc_vaddr + oca.ca_offset; - oca.ca_paddr = sc->sc_paddr + oca.ca_offset; + if (oca.ca_offset != -1) { + oca.ca_paddr = ca->ca_paddr + oca.ca_offset; } else { - oca.ca_vaddr = (void *)-1; - oca.ca_paddr = (void *)-1; + oca.ca_paddr = -1; } oca.ca_bustype = BUS_SYSCON; - oca.ca_master = (void *)sc->sc_syscon; oca.ca_name = cf->cf_driver->cd_name; if ((*cf->cf_attach->ca_match)(parent, cf, &oca) == 0) return (0); @@ -164,18 +124,8 @@ sysconattach(parent, self, args) struct device *parent, *self; void *args; { - struct confargs *ca = args; struct sysconsoftc *sc = (struct sysconsoftc *)self; - /* - * since we know ourself to land in intiobase land, - * we must adjust our address - */ - sc->sc_paddr = ca->ca_paddr; - sc->sc_vaddr = (void *)IIOV(sc->sc_paddr); - sc->sc_syscon = &syscon_reg; - sys_syscon = sc->sc_syscon; - printf("\n"); /* @@ -215,11 +165,11 @@ sysconintr_establish(vec, ih) struct intrhand *ih; { #ifdef DIAGNOSTIC - if (vec < SYSCON_VECT || vec >= SYSCON_VECT + SYSCON_NVEC) + if (vec < 0 || vec >= SYSCON_NVEC) panic("sysconintr_establish: illegal vector 0x%x\n", vec); #endif - return (intr_establish(vec, ih)); + return (intr_establish(SYSCON_VECT + vec, ih)); } int diff --git a/sys/arch/mvme88k/dev/sysconfunc.h b/sys/arch/mvme88k/dev/sysconfunc.h deleted file mode 100644 index eab59f3f24c..00000000000 --- a/sys/arch/mvme88k/dev/sysconfunc.h +++ /dev/null @@ -1,8 +0,0 @@ -/* $OpenBSD: sysconfunc.h,v 1.2 2002/03/14 01:26:39 millert Exp $ */ - -#ifndef _MVME88K_SYSCON_H_ -#define _MVME88K_SYSCON_H_ - -int sysconintr_establish(int vec, struct intrhand *ih); - -#endif /* _MVME88K_SYSCON_H_ */ diff --git a/sys/arch/mvme88k/dev/sysconreg.h b/sys/arch/mvme88k/dev/sysconreg.h index e0b12f8d44e..385a486a6ba 100644 --- a/sys/arch/mvme88k/dev/sysconreg.h +++ b/sys/arch/mvme88k/dev/sysconreg.h @@ -1,62 +1,45 @@ -/* $OpenBSD: sysconreg.h,v 1.5 2004/04/16 23:36:48 miod Exp $ */ +/* $OpenBSD: sysconreg.h,v 1.6 2004/04/24 19:51:48 miod Exp $ */ /* - * Memory map for SYSCON found in mvme188 board set. - * No specific chips are found here like the PCCTWO - * on MVME1x7. All chips are included in this one - * map/device so that devices don't run rampant in - * the config files. I may change this later XXX smurph. + * Copyright (c) 2004, Miodrag Vallat. + * Copyright (c) 1999 Steve Murphree, Jr. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ -#include <machine/board.h> - -struct sysconreg { - unsigned int *volatile ien0; - unsigned int *volatile ien1; - unsigned int *volatile ien2; - unsigned int *volatile ien3; - unsigned int *volatile ienall; - unsigned int *volatile ist; - unsigned int *volatile setswi; - unsigned int *volatile clrswi; - unsigned int *volatile istate; - unsigned int *volatile clrint; - unsigned char *volatile global0; - unsigned char *volatile global1; - unsigned char *volatile global2; - unsigned char *volatile global3; - unsigned int *volatile ucsr; - unsigned int *volatile glbres; - unsigned int *volatile ccsr; - unsigned int *volatile error; - unsigned int *volatile pcnfa; - unsigned int *volatile pcnfb; - unsigned int *volatile extad; - unsigned int *volatile extam; - unsigned int *volatile whoami; - unsigned int *volatile wmad; - unsigned int *volatile rmad; - unsigned int *volatile wvad; - unsigned int *volatile rvad; - unsigned int *volatile cio_portc; - unsigned int *volatile cio_portb; - unsigned int *volatile cio_porta; - unsigned int *volatile cio_ctrl; -}; - -extern struct sysconreg *sys_syscon; - /* * Map syscon interrupts a la PCC2 */ #define SYSCON_VECT 0x50 #define SYSCON_NVEC 0x10 -#define SYSCV_ABRT 0x52 -#define SYSCV_SYSF 0x53 -#define SYSCV_ACF 0x54 -#define SYSCV_SCC 0x55 -#define SYSCV_TIMER4 0x56 -#define SYSCV_TIMER3 0x57 -#define SYSCV_TIMER2 0x58 -#define SYSCV_TIMER1 0x59 +#define SYSCV_ABRT 0x02 +#define SYSCV_SYSF 0x03 +#define SYSCV_ACF 0x04 +#define SYSCV_SCC 0x05 +#define SYSCV_TIMER4 0x06 +#define SYSCV_TIMER3 0x07 +#define SYSCV_TIMER2 0x08 +#define SYSCV_TIMER1 0x09 + +int sysconintr_establish(int, struct intrhand *); diff --git a/sys/arch/mvme88k/dev/vme.c b/sys/arch/mvme88k/dev/vme.c index 5535cb0ddbc..feef760dcf3 100644 --- a/sys/arch/mvme88k/dev/vme.c +++ b/sys/arch/mvme88k/dev/vme.c @@ -1,5 +1,6 @@ -/* $OpenBSD: vme.c,v 1.33 2004/04/16 23:35:50 miod Exp $ */ +/* $OpenBSD: vme.c,v 1.34 2004/04/24 19:51:48 miod Exp $ */ /* + * Copyright (c) 2004, Miodrag Vallat. * Copyright (c) 1999 Steve Murphree, Jr. * Copyright (c) 1995 Theo de Raadt * All rights reserved. @@ -47,23 +48,18 @@ #include <mvme88k/dev/sysconreg.h> #endif -int vmematch(struct device *, void *, void *); -void vmeattach(struct device *, struct device *, void *); +int vmematch(struct device *, void *, void *); +void vmeattach(struct device *, struct device *, void *); -void vme2chip_init(struct vmesoftc *); -u_long vme2chip_map(u_long, int, int); -int vme2abort(void *); -int sysconabort(void *); -int vmeprint(void *, const char *); -void *vmemap(struct vmesoftc *sc, off_t vmeaddr, int len, int bustype); -void vmeunmap(void *, int); - -void vmesyscon_init(struct vmesoftc *); +void vme2chip_init(struct vmesoftc *); +void vmesyscon_init(struct vmesoftc *); +u_long vme2chip_map(u_long, int); +int vme2abort(void *); +int sysconabort(void *); +int vmeprint(void *, const char *); int vmebustype; -int vmevecbase; - -struct vme2reg *sys_vme2; +unsigned int vmevecbase; struct cfattach vme_ca = { sizeof(struct vmesoftc), vmematch, vmeattach @@ -73,151 +69,83 @@ struct cfdriver vme_cd = { NULL, "vme", DV_DULL }; -int -vmematch(parent, cf, args) - struct device *parent; - void *cf; - void *args; -{ - return (1); -} - /* - * make local addresses 1G-2G correspond to VME addresses 3G-4G, - * as D32 + * bus_space routines for VME mappings */ -#define VME2_D32STARTPHYS (1*1024*1024*1024UL) -#define VME2_D32ENDPHYS (2*1024*1024*1024UL) -#define VME2_D32STARTVME (3*1024*1024*1024UL) -#define VME2_D32BITSVME (3*1024*1024*1024UL) +int vme_map(bus_addr_t, bus_size_t, int, bus_space_handle_t *); +void vme_unmap(bus_space_handle_t, bus_size_t); +int vme_subregion(bus_space_handle_t, bus_size_t, bus_size_t, + bus_space_handle_t *); +void * vme_vaddr(bus_space_handle_t); + +const struct mvme88k_bus_space_tag vme_bustag = { + vme_map, + vme_unmap, + vme_subregion, + vme_vaddr +}; /* - * make local addresses 3G-3.75G correspond to VME addresses 3G-3.75G, - * as D16 + * VME space mapping functions */ -#define VME2_D16STARTPHYS (3*1024*1024*1024UL) -#define VME2_D16ENDPHYS (3*1024*1024*1024UL + 768*1024*1024UL) -#define VME2_A32D16STARTPHYS (0xFF000000UL) -#define VME2_A32D16ENDPHYS (0xFF7FFFFFUL) - -/* - * Returns a physical address mapping for a VME address & length. - * Note: on some hardware it is not possible to create certain - * mappings, ie. the MVME147 cannot do 32 bit accesses to VME bus - * addresses from 0 to physmem. - */ -void * -vmepmap(sc, vmeaddr, len, bustype) - struct device *sc; - off_t vmeaddr; - int len; - int bustype; +int +vme_map(bus_addr_t addr, bus_size_t size, int flags, bus_space_handle_t *ret) { - u_int32_t base = (u_int32_t)vmeaddr; + vaddr_t map; - len = roundup(len, NBPG); - switch (vmebustype) { -#if NPCCTWO > 0 || NSYSCON > 0 - case BUS_PCCTWO: - case BUS_SYSCON: - switch (bustype) { - case BUS_VMES: /* D16 VME Transfers */ -#ifdef DEBUG - printf("base 0x%8llx/0x%8x len 0x%x\n", - vmeaddr, base, len); -#endif - base = vme2chip_map(base, len, 16); - if (base == NULL) { - printf("%s: cannot map pa 0x%x len 0x%x\n", - sc->dv_xname, base, len); - return (NULL); - } - break; - case BUS_VMEL: /* D32 VME Transfers */ -#ifdef DEBUG - printf("base 0x%8llx/0x%8x len 0x%x\n", - vmeaddr, base, len); -#endif - base = vme2chip_map(base, len, 32); - if (base == NULL) { - printf("%s: cannot map pa 0x%x len 0x%x\n", - sc->dv_xname, base, len); - return (NULL); - } - break; - } - break; +#if 0 + map = iomap_mapin(addr, size, 0); +#else + map = (vaddr_t)mapiodev((void *)addr, size); #endif - } - return ((void *)base); -} - -/* if successful, returns the va of a vme bus mapping */ -void * -vmemap(sc, vmeaddr, len, bustype) - struct vmesoftc *sc; - off_t vmeaddr; - int len; - int bustype; -{ - void *pa, *va; + if (map == NULL) + return ENOMEM; - pa = vmepmap((struct device *)sc, vmeaddr, len, bustype); - if (pa == NULL) - return (NULL); - va = mapiodev(pa, len); - return (va); + *ret = (bus_space_handle_t)map; + return 0; } void -vmeunmap(va, len) - void *va; - int len; +vme_unmap(bus_space_handle_t handle, bus_size_t size) { - unmapiodev(va, len); +#if 0 + iomap_mapout(handle, size); +#else + unmapiodev((void *)handle, size); +#endif } int -vmerw(sc, uio, flags, bus) - struct device *sc; - struct uio *uio; - int flags; - int bus; +vme_subregion(bus_space_handle_t handle, bus_addr_t offset, bus_size_t size, + bus_space_handle_t *ret) { - vaddr_t v; - int c; - struct iovec *iov; - void *vme; - int error = 0; + *ret = handle + offset; + return (0); +} - while (uio->uio_resid > 0 && error == 0) { - iov = uio->uio_iov; - if (iov->iov_len == 0) { - uio->uio_iov++; - uio->uio_iovcnt--; - if (uio->uio_iovcnt < 0) - panic("vmerw"); - continue; - } +void * +vme_vaddr(bus_space_handle_t handle) +{ + return (void *)handle; +} - v = uio->uio_offset; - c = min(iov->iov_len, MAXPHYS); - if ((v & PGOFSET) + c > NBPG) /* max NBPG at a time */ - c = NBPG - (v & PGOFSET); - if (c == 0) - return (0); - vme = vmemap((struct vmesoftc *)sc, v & ~PGOFSET, - NBPG, BUS_VMES); - if (vme == NULL) { - error = EFAULT; /* XXX? */ - continue; - } - error = uiomove((void *)vme + (v & PGOFSET), c, uio); - vmeunmap(vme, NBPG); - } - return (error); +/* + * Configuration glue + */ + +int +vmematch(parent, cf, args) + struct device *parent; + void *cf; + void *args; +{ +#ifdef MVME187 + if (brdtyp == BRD_8120) + return (0); +#endif + return (1); } int @@ -227,7 +155,7 @@ vmeprint(args, bus) { struct confargs *ca = args; - printf(" addr 0x%x", ca->ca_offset); + printf(" addr 0x%x", ca->ca_paddr); if (ca->ca_ipl > 0) printf(" ipl %d", ca->ca_ipl); if (ca->ca_vec > 0) @@ -242,49 +170,20 @@ vmescan(parent, child, args, bustype) int bustype; { struct cfdata *cf = child; - struct vmesoftc *sc = (struct vmesoftc *)parent; struct confargs oca; - size_t len; bzero(&oca, sizeof oca); + oca.ca_iot = &vme_bustag; oca.ca_bustype = bustype; - oca.ca_paddr = (void *)cf->cf_loc[0]; - oca.ca_len = cf->cf_loc[1]; - oca.ca_vec = cf->cf_loc[2]; - oca.ca_ipl = cf->cf_loc[3]; - if (oca.ca_ipl > 0 && oca.ca_vec == -1) + oca.ca_paddr = cf->cf_loc[0]; + oca.ca_vec = cf->cf_loc[1]; + oca.ca_ipl = cf->cf_loc[2]; + if (oca.ca_ipl > 0 && oca.ca_vec < 0) oca.ca_vec = vme_findvec(-1); - if (oca.ca_len == -1) - oca.ca_len = PAGE_SIZE; - len = oca.ca_len; - - oca.ca_offset = (u_int)oca.ca_paddr; - oca.ca_vaddr = vmemap(sc, (vaddr_t)oca.ca_paddr, oca.ca_len, - oca.ca_bustype); - if (oca.ca_vaddr == NULL) - oca.ca_vaddr = (void *)-1; /* XXX */ - oca.ca_master = (void *)sc; oca.ca_name = cf->cf_driver->cd_name; - if ((*cf->cf_attach->ca_match)(parent, cf, &oca) == 0) { - if (oca.ca_vaddr != (void *)-1) - vmeunmap(oca.ca_vaddr, len); - return (0); - } - /* - * Map the whole space the driver is interested in. - */ - if (len != oca.ca_len) { - vmeunmap(oca.ca_vaddr, len); - if (oca.ca_len != 0) { - if (vmemap(sc, (vaddr_t)oca.ca_paddr, oca.ca_len, - oca.ca_bustype) == NULL) { - printf("%s: can't map VME space\n", - oca.ca_name); - return (0); - } - } - } + if ((*cf->cf_attach->ca_match)(parent, cf, &oca) == 0) + return (0); config_attach(parent, cf, &oca, vmeprint); return (1); @@ -298,25 +197,40 @@ vmeattach(parent, self, args) struct vmesoftc *sc = (struct vmesoftc *)self; struct confargs *ca = args; - sc->sc_vaddr = ca->ca_vaddr; + /* + * This is a waste if we are attached to SYSCON - but then obio + * mappings are free... + */ + sc->sc_iot = ca->ca_iot; + if (bus_space_map(sc->sc_iot, ca->ca_paddr, PAGE_SIZE, 0, + &sc->sc_ioh) != 0) { + printf(": can't map registers!\n"); + return; + } + vmebustype = ca->ca_bustype; switch (ca->ca_bustype) { #if NPCCTWO > 0 case BUS_PCCTWO: { - struct vme2reg *vme2; - - vme2 = (struct vme2reg *)sc->sc_vaddr; - /* Sanity check that the Bug is set up right */ - if (VME2_GET_VBR1(vme2) >= 0xF0) { - panic("Correct the VME Vector Base Registers in the Bug ROM.\nSuggested values are 0x60 for VME Vec0 and 0x70 for VME Vec1."); + u_int32_t vbr; + + /* Sanity check that the BUG is set up right */ + vbr = bus_space_read_4(sc->sc_iot, sc->sc_ioh, VME2_VBR); + vmevecbase = VME2_GET_VBR1(vbr) + 0x10; + if (vmevecbase >= 0x100) { + panic("Correct the VME Vector Base Registers " + "in the Bug ROM.\n" + "Suggested values are 0x60 for VME Vec0 and " + "0x70 for VME Vec1."); } - vmevecbase = VME2_GET_VBR1(vme2) + 0x10; - printf(": vector base 0x%x", vmevecbase); - if (vme2->vme2_tctl & VME2_TCTL_SCON) - printf(", system controller"); + + if ((bus_space_read_4(sc->sc_iot, sc->sc_ioh, VME2_TCTL) & + VME2_TCTL_SCON) != 0) + printf(": system controller"); printf("\n"); + vme2chip_init(sc); } break; @@ -331,6 +245,7 @@ vmeattach(parent, self, args) if (!ISSET(sconc, M188_SYSCONNEG)) printf(": system controller"); printf("\n"); + vmesyscon_init(sc); } break; @@ -349,6 +264,139 @@ vme_findvec(int skip) } /* + * make local addresses 1G-2G correspond to VME addresses 3G-4G, + * as D32 + */ + +#define VME2_D32STARTPHYS (1*1024*1024*1024UL) +#define VME2_D32ENDPHYS (2*1024*1024*1024UL) +#define VME2_D32STARTVME (3*1024*1024*1024UL) +#define VME2_D32BITSVME (3*1024*1024*1024UL) + +/* + * make local addresses 3G-3.75G correspond to VME addresses 3G-3.75G, + * as D16 + */ +#define VME2_D16STARTPHYS (3*1024*1024*1024UL) +#define VME2_D16ENDPHYS (3*1024*1024*1024UL + 768*1024*1024UL) +#define VME2_A32D16STARTPHYS (0xff000000UL) +#define VME2_A32D16ENDPHYS (0xff7fffffUL) + + +/* + * Returns a physical address mapping for a VME address & length. + * Note: on some hardware it is not possible to create certain + * mappings, ie. the MVME147 cannot do 32 bit accesses to VME bus + * addresses from 0 to physmem. + */ +void * +vmepmap(sc, vmeaddr, bustype) + struct device *sc; + off_t vmeaddr; + int bustype; +{ + u_int32_t base = (u_int32_t)vmeaddr; /* wrap around 4GB */ + + switch (vmebustype) { +#if NPCCTWO > 0 || NSYSCON > 0 + case BUS_PCCTWO: + case BUS_SYSCON: + switch (bustype) { + case BUS_VMES: /* D16 VME Transfers */ +#ifdef DEBUG + printf("base 0x%8llx/0x%8x\n", + vmeaddr, base); +#endif + base = vme2chip_map(base, 16); +#ifdef DEBUG + if (base == NULL) { + printf("%s: cannot map pa 0x%x\n", + sc->dv_xname, base); + } +#endif + break; + case BUS_VMEL: /* D32 VME Transfers */ +#ifdef DEBUG + printf("base 0x%8llx/0x%8x\n", + vmeaddr, base); +#endif + base = vme2chip_map(base, 32); +#ifdef DEBUG + if (base == NULL) { + printf("%s: cannot map pa 0x%x\n", + sc->dv_xname, base); + } +#endif + break; + } + break; +#endif + default: + return NULL; + } + return ((void *)base); +} + +static void *vmemap(struct vmesoftc *, off_t); +static void vmeunmap(void *); + +/* if successful, returns the va of a vme bus mapping */ +static __inline__ void * +vmemap(struct vmesoftc *sc, off_t vmeaddr) +{ + void *pa; + + pa = vmepmap((struct device *)sc, vmeaddr, BUS_VMES); + if (pa == NULL) + return (NULL); + return mapiodev(pa, PAGE_SIZE); +} + +static __inline__ void +vmeunmap(void *va) +{ + unmapiodev(va, PAGE_SIZE); +} + +int +vmerw(sc, uio, flags, bus) + struct device *sc; + struct uio *uio; + int flags; + int bus; +{ + vaddr_t v; + int c; + struct iovec *iov; + void *vme; + int error = 0; + + while (uio->uio_resid > 0 && error == 0) { + iov = uio->uio_iov; + if (iov->iov_len == 0) { + uio->uio_iov++; + uio->uio_iovcnt--; + if (uio->uio_iovcnt < 0) + panic("vmerw"); + continue; + } + + v = uio->uio_offset; + c = min(iov->iov_len, MAXPHYS); + if ((v & PGOFSET) + c > PAGE_SIZE) /* max 1 page at a time */ + c = PAGE_SIZE - (v & PGOFSET); + if (c == 0) + return 0; + vme = vmemap((struct vmesoftc *)sc, v & ~PGOFSET); + if (vme == NULL) + return EACCES; + error = uiomove((void *)vme + (v & PGOFSET), c, uio); + vmeunmap(vme); + } + return error; +} + +/* * On the VMEbus, only one cpu may be configured to respond to any * particular vme ipl. Therefore, it wouldn't make sense to globally * enable all the interrupts all the time -- it would not be possible @@ -377,30 +425,18 @@ vmeintr_establish(vec, ih) struct intrhand *ih; { struct vmesoftc *sc = (struct vmesoftc *) vme_cd.cd_devs[0]; -#if NPCCTWO > 0 - struct vme2reg *vme2; -#endif -#if NSYSCON > 0 - struct sysconreg *syscon; -#endif - int x; switch (vmebustype) { #if NPCCTWO > 0 case BUS_PCCTWO: - vme2 = (struct vme2reg *)sc->sc_vaddr; - vme2->vme2_irqen = vme2->vme2_irqen | - VME2_IRQ_VME(ih->ih_ipl); - break; -#endif -#if NSYSCON > 0 - case BUS_SYSCON: - syscon = (struct sysconreg *)sc->sc_vaddr; + bus_space_write_4(sc->sc_iot, sc->sc_ioh, VME2_IRQEN, + bus_space_read_4(sc->sc_iot, sc->sc_ioh, VME2_IRQEN) | + VME2_IRQ_VME(ih->ih_ipl)); break; #endif } - x = (intr_establish(vec, ih)); - return (x); + + return intr_establish(vec, ih); } #if NPCCTWO > 0 @@ -408,70 +444,75 @@ void vme2chip_init(sc) struct vmesoftc *sc; { - struct vme2reg *vme2 = (struct vme2reg *)sc->sc_vaddr; - u_long ctl; - - sys_vme2 = vme2; + u_int32_t ctl, irqen, master, master4mod; /* turn off SYSFAIL LED */ - vme2->vme2_tctl &= ~VME2_TCTL_SYSFAIL; + bus_space_write_4(sc->sc_iot, sc->sc_ioh, VME2_TCTL, + bus_space_read_4(sc->sc_iot, sc->sc_ioh, VME2_TCTL) & + ~VME2_TCTL_SYSFAIL); /* * Display the VMEChip2 decoder status. */ printf("%s: using BUG parameters\n", sc->sc_dev.dv_xname); - ctl = vme2->vme2_gcsrctl; + ctl = bus_space_read_4(sc->sc_iot, sc->sc_ioh, VME2_GCSRCTL); if (ctl & VME2_GCSRCTL_MDEN1) { + master = bus_space_read_4(sc->sc_iot, sc->sc_ioh, VME2_MASTER1); printf("%s: 1phys 0x%08lx-0x%08lx to VME 0x%08lx-0x%08lx\n", - sc->sc_dev.dv_xname, - vme2->vme2_master1 << 16, vme2->vme2_master1 & 0xffff0000, - vme2->vme2_master1 << 16, vme2->vme2_master1 & 0xffff0000); + sc->sc_dev.dv_xname, master << 16, master & 0xffff0000, + master << 16, master & 0xffff0000); } if (ctl & VME2_GCSRCTL_MDEN2) { + master = bus_space_read_4(sc->sc_iot, sc->sc_ioh, VME2_MASTER2); printf("%s: 2phys 0x%08lx-0x%08lx to VME 0x%08lx-0x%08lx\n", - sc->sc_dev.dv_xname, - vme2->vme2_master2 << 16, vme2->vme2_master2 & 0xffff0000, - vme2->vme2_master2 << 16, vme2->vme2_master2 & 0xffff0000); + sc->sc_dev.dv_xname, master << 16, master & 0xffff0000, + master << 16, master & 0xffff0000); } if (ctl & VME2_GCSRCTL_MDEN3) { + master = bus_space_read_4(sc->sc_iot, sc->sc_ioh, VME2_MASTER3); printf("%s: 3phys 0x%08lx-0x%08lx to VME 0x%08lx-0x%08lx\n", - sc->sc_dev.dv_xname, - vme2->vme2_master3 << 16, vme2->vme2_master3 & 0xffff0000, - vme2->vme2_master3 << 16, vme2->vme2_master3 & 0xffff0000); + sc->sc_dev.dv_xname, master << 16, master & 0xffff0000, + master << 16, master & 0xffff0000); } if (ctl & VME2_GCSRCTL_MDEN4) { + master = bus_space_read_4(sc->sc_iot, sc->sc_ioh, VME2_MASTER4); + master4mod = bus_space_read_4(sc->sc_iot, sc->sc_ioh, + VME2_MASTER4MOD); printf("%s: 4phys 0x%08lx-0x%08lx to VME 0x%08lx-0x%08lx\n", - sc->sc_dev.dv_xname, - vme2->vme2_master4 << 16, vme2->vme2_master4 & 0xffff0000, - (vme2->vme2_master4 << 16) + (vme2->vme2_master4mod << 16), - (vme2->vme2_master4 & 0xffff0000) + - (vme2->vme2_master4mod & 0xffff0000)); + sc->sc_dev.dv_xname, master << 16, master & 0xffff0000, + (master << 16) + (master4mod << 16), + (master & 0xffff0000) + (master4mod & 0xffff0000)); } /* * Map the VME irq levels to the cpu levels 1:1. * This is rather inflexible, but much easier. */ - vme2->vme2_irql4 = (7 << VME2_IRQL4_VME7SHIFT) | - (6 << VME2_IRQL4_VME6SHIFT) | (5 << VME2_IRQL4_VME5SHIFT) | - (4 << VME2_IRQL4_VME4SHIFT) | (3 << VME2_IRQL4_VME3SHIFT) | - (2 << VME2_IRQL4_VME2SHIFT) | (1 << VME2_IRQL4_VME1SHIFT); + bus_space_write_4(sc->sc_iot, sc->sc_ioh, VME2_IRQL4, + (7 << VME2_IRQL4_VME7SHIFT) | (6 << VME2_IRQL4_VME6SHIFT) | + (5 << VME2_IRQL4_VME5SHIFT) | (4 << VME2_IRQL4_VME4SHIFT) | + (3 << VME2_IRQL4_VME3SHIFT) | (2 << VME2_IRQL4_VME2SHIFT) | + (1 << VME2_IRQL4_VME1SHIFT)); printf("%s: vme to cpu irq level 1:1\n",sc->sc_dev.dv_xname); /* Enable the reset switch */ - vme2->vme2_tctl |= VME2_TCTL_RSWE; + bus_space_write_4(sc->sc_iot, sc->sc_ioh, VME2_TCTL, VME2_TCTL_RSWE | + bus_space_read_4(sc->sc_iot, sc->sc_ioh, VME2_TCTL)); /* Set Watchdog timeout to about 1 minute */ - vme2->vme2_tcr |= VME2_TCR_64S; + bus_space_write_4(sc->sc_iot, sc->sc_ioh, VME2_TCR, VME2_TCR_64S | + bus_space_read_4(sc->sc_iot, sc->sc_ioh, VME2_TCR)); /* Enable VMEChip2 Interrupts */ - vme2->vme2_vbr |= VME2_IOCTL1_MIEN; + bus_space_write_4(sc->sc_iot, sc->sc_ioh, VME2_VBR, VME2_IOCTL1_MIEN | + bus_space_read_4(sc->sc_iot, sc->sc_ioh, VME2_VBR)); + /* * Map the Software VME irq levels to the cpu level 7. */ - vme2->vme2_irql3 = (7 << VME2_IRQL3_SW7SHIFT) | - (7 << VME2_IRQL3_SW6SHIFT) | (7 << VME2_IRQL3_SW5SHIFT) | - (7 << VME2_IRQL3_SW4SHIFT) | (7 << VME2_IRQL3_SW3SHIFT) | - (7 << VME2_IRQL3_SW2SHIFT) | (7 << VME2_IRQL3_SW1SHIFT) | - (7 << VME2_IRQL3_SW0SHIFT); + bus_space_write_4(sc->sc_iot, sc->sc_ioh, VME2_IRQL3, + (7 << VME2_IRQL3_SW7SHIFT) | (7 << VME2_IRQL3_SW6SHIFT) | + (7 << VME2_IRQL3_SW5SHIFT) | (7 << VME2_IRQL3_SW4SHIFT) | + (7 << VME2_IRQL3_SW3SHIFT) | (7 << VME2_IRQL3_SW2SHIFT) | + (7 << VME2_IRQL3_SW1SHIFT)); /* * pseudo driver, abort interrupt handler @@ -481,13 +522,17 @@ vme2chip_init(sc) sc->sc_abih.ih_wantframe = 1; sc->sc_abih.ih_ipl = IPL_NMI; intr_establish(110, &sc->sc_abih); - vme2->vme2_irqen |= VME2_IRQ_AB; + + irqen = bus_space_read_4(sc->sc_iot, sc->sc_ioh, VME2_IRQEN); + irqen |= VME2_IRQ_AB; + /* bus_space_write_4(sc->sc_iot, sc->sc_ioh, VME2_IRQEN, irqen); */ /* * Enable ACFAIL interrupt, but disable Timer 1 interrupt - we * prefer it without for delay(). */ - vme2->vme2_irqen = (vme2->vme2_irqen | VME2_IRQ_ACF) & ~VME2_IRQ_TIC1; + irqen = (irqen | VME2_IRQ_ACF) & ~VME2_IRQ_TIC1; + bus_space_write_4(sc->sc_iot, sc->sc_ioh, VME2_IRQEN, irqen); } #endif /* NPCCTWO */ @@ -512,20 +557,29 @@ vmesyscon_init(sc) * XXX smurph - This is bogus, get rid of it! Should check vme/syscon for offsets. */ u_long -vme2chip_map(base, len, dwidth) +vme2chip_map(base, dwidth) u_long base; - int len, dwidth; + int dwidth; { + /* + * Since we are checking range for one page only, no need to check + * for address wraparound. + */ switch (dwidth) { case 16: + if (base < VME2_D16STARTPHYS || + base + PAGE_SIZE > VME2_D16ENDPHYS) + return NULL; break; case 32: if (base < VME2_D32STARTPHYS || - base + (u_long)len > VME2_D32ENDPHYS) - return (NULL); + base + PAGE_SIZE > VME2_D32ENDPHYS) + return NULL; break; + default: + return NULL; } - return (base); + return base; } #if NPCCTWO > 0 @@ -535,17 +589,16 @@ vme2abort(eframe) { struct frame *frame = eframe; - struct vmesoftc *sc = (struct vmesoftc *) vme_cd.cd_devs[0]; - struct vme2reg *vme2 = (struct vme2reg *)sc->sc_vaddr; + struct vmesoftc *sc = (struct vmesoftc *)vme_cd.cd_devs[0]; - if ((vme2->vme2_irqstat & VME2_IRQ_AB) == 0) { + if ((bus_space_read_4(sc->sc_iot, sc->sc_ioh, VME2_IRQSTAT) & + VME2_IRQ_AB) == 0) { printf("%s: abort irq not set\n", sc->sc_dev.dv_xname); return (0); } - vme2->vme2_irqclr = VME2_IRQ_AB; + bus_space_write_4(sc->sc_iot, sc->sc_ioh, VME2_IRQCLR, VME2_IRQ_AB); nmihand(frame); return (1); } #endif - diff --git a/sys/arch/mvme88k/dev/vme.h b/sys/arch/mvme88k/dev/vme.h index 531465cf583..455a94d8a96 100644 --- a/sys/arch/mvme88k/dev/vme.h +++ b/sys/arch/mvme88k/dev/vme.h @@ -1,4 +1,4 @@ -/* $OpenBSD: vme.h,v 1.14 2004/04/16 23:35:50 miod Exp $ */ +/* $OpenBSD: vme.h,v 1.15 2004/04/24 19:51:48 miod Exp $ */ /* * Copyright (c) 1995 Theo de Raadt @@ -26,54 +26,85 @@ */ #ifndef __MVEME88K_DEV_VME_H__ -#define __MVEME88K_DEV_VME_H__ +#define __MVEME88K_DEV_VME_H__ struct vmesoftc { - struct device sc_dev; - void * sc_vaddr; - struct intrhand sc_abih; /* `abort' switch */ + struct device sc_dev; + bus_space_tag_t sc_iot; + bus_space_handle_t sc_ioh; + struct intrhand sc_abih; /* `abort' switch */ }; /* - * XXX: this chip has some rather inane access rules! + * XXX: this chip has some rather insane access rules! */ -struct vme2reg { -/*00*/ volatile u_long vme2_slaveaddr1; -/*04*/ volatile u_long vme2_slaveaddr2; -#define VME2_SADDR_END 0xffff0000 /* VME address END & START */ -#define VME2_SADDR_START 0x0000ffff -/*08*/ volatile u_long vme2_slavelmod1; -/*0c*/ volatile u_long vme2_slavelmod2; -#define VME2_SADDR_LADDR 0xffff0000 /* local base address */ -#define VME2_SADDR_SIZE(mem) (0x1000 - (mem) >> 16) /* encoding of size */ -/*10*/ volatile u_long vme2_slavectl; -#define VME2_SLAVE_CHOOSE(bits, num) ((bits) << (16*((num)-1))) -#define VME2_SLAVECTL_WP 0x00000100 /* write posting */ -#define VME2_SLAVECTL_SNP_NO 0x00000000 /* no snooping */ -#define VME2_SLAVECTL_SNP_SINK 0x00000200 /* sink data */ -#define VME2_SLAVECTL_SNP_INVAL 0x00000400 /* invalidate */ -#define VME2_SLAVECTL_ADDER 0x00000800 /* use adder */ -#define VME2_SLAVECTL_SUP 0x00000080 /* modifier bit */ -#define VME2_SLAVECTL_USR 0x00000040 /* modifier bit */ -#define VME2_SLAVECTL_A32 0x00000020 /* modifier bit */ -#define VME2_SLAVECTL_A24 0x00000010 /* modifier bit */ -#define VME2_SLAVECTL_D64 0x00000008 /* modifier bit */ -#define VME2_SLAVECTL_BLK 0x00000004 /* modifier bit */ -#define VME2_SLAVECTL_PGM 0x00000002 /* modifier bit */ -#define VME2_SLAVECTL_DAT 0x00000001 /* modifier bit */ -/*14*/ volatile u_long vme2_master1; -/*18*/ volatile u_long vme2_master2; -/*1c*/ volatile u_long vme2_master3; -/*20*/ volatile u_long vme2_master4; -/*24*/ volatile u_long vme2_master4mod; -/*28*/ volatile u_long vme2_masterctl; -#define VME2_MASTERCTL_4SHIFT 24 -#define VME2_MASTERCTL_3SHIFT 16 -#define VME2_MASTERCTL_2SHIFT 8 -#define VME2_MASTERCTL_1SHIFT 0 -#define VME2_MASTERCTL_D16 0x80 -#define VME2_MASTERCTL_WP 0x40 -#define VME2_MASTERCTL_AM 0x3f + +#define VME2_BASE 0xfff40000 + +#define VME2_SADDR1 0x0000 +#define VME2_SADDR2 0x0004 +#define VME2_SLAVELMOD1 0x0008 +#define VME2_SLAVELMOD2 0x000c +#define VME2_SLAVECTL 0x0010 +#define VME2_MASTER1 0x0014 +#define VME2_MASTER2 0x0018 +#define VME2_MASTER3 0x001c +#define VME2_MASTER4 0x0020 +#define VME2_MASTER4MOD 0x0024 +#define VME2_MASTERCTL 0x0028 +#define VME2_GCSRCTL 0x002c +#define VME2_DMACTL 0x0030 +#define VME2_DMAMODE 0x0034 +#define VME2_DMALADDR 0x0038 +#define VME2_DMAVMEADDR 0x003c +#define VME2_DMACOUNT 0x0040 +#define VME2_DMATABLE 0x0044 +#define VME2_DMASTAT 0x0048 +#define VME2_TCR 0x004c +#define VME2_T1CMP 0x0050 +#define VME2_T1COUNT 0x0054 +#define VME2_T2CMP 0x0058 +#define VME2_T2COUNT 0x005c +#define VME2_TCTL 0x0060 +#define VME2_PRESCALE 0x0064 +#define VME2_IRQSTAT 0x0068 +#define VME2_IRQEN 0x006c +#define VME2_SETSOFTIRQ 0x0070 +#define VME2_IRQCLR 0x0074 +#define VME2_IRQL1 0x0078 +#define VME2_IRQL2 0x007c +#define VME2_IRQL3 0x0080 +#define VME2_IRQL4 0x0084 +#define VME2_VBR 0x0088 +#define VME2_MISC 0x008c + +#define VME2_SADDR_END 0xffff0000 /* VME address END & START */ +#define VME2_SADDR_START 0x0000ffff +#define VME2_SADDR_LADDR 0xffff0000 /* local base address */ +#define VME2_SADDR_SIZE(mem) (0x1000 - (mem) >> 16) /* encoding of size */ + +#define VME2_SLAVE_CHOOSE(bits, num) ((bits) << (16*((num)-1))) +#define VME2_SLAVECTL_WP 0x00000100 /* write posting */ +#define VME2_SLAVECTL_SNP_NO 0x00000000 /* no snooping */ +#define VME2_SLAVECTL_SNP_SINK 0x00000200 /* sink data */ +#define VME2_SLAVECTL_SNP_INVAL 0x00000400 /* invalidate */ +#define VME2_SLAVECTL_ADDER 0x00000800 /* use adder */ +#define VME2_SLAVECTL_SUP 0x00000080 /* modifier bit */ +#define VME2_SLAVECTL_USR 0x00000040 /* modifier bit */ +#define VME2_SLAVECTL_A32 0x00000020 /* modifier bit */ +#define VME2_SLAVECTL_A24 0x00000010 /* modifier bit */ +#define VME2_SLAVECTL_D64 0x00000008 /* modifier bit */ +#define VME2_SLAVECTL_BLK 0x00000004 /* modifier bit */ +#define VME2_SLAVECTL_PGM 0x00000002 /* modifier bit */ +#define VME2_SLAVECTL_DAT 0x00000001 /* modifier bit */ + +#define VME2_MASTERCTL_4SHIFT 24 +#define VME2_MASTERCTL_3SHIFT 16 +#define VME2_MASTERCTL_2SHIFT 8 +#define VME2_MASTERCTL_1SHIFT 0 +#define VME2_MASTERCTL_D16 0x80 +#define VME2_MASTERCTL_WP 0x40 +#define VME2_MASTERCTL_AM 0x3f #define VME2_MASTERCTL_AM24SB 0x3f /* A24 Supervisory Block Transfer */ #define VME2_MASTERCTL_AM24SP 0x3e /* A24 Supervisory Program Access */ #define VME2_MASTERCTL_AM24SD 0x3d /* A24 Supervisory Data Access */ @@ -89,190 +120,170 @@ struct vme2reg { #define VME2_MASTERCTL_AM32UP 0x0a /* A32 Non-priv. Program Access */ #define VME2_MASTERCTL_AM32UD 0x09 /* A32 Non-priv Data Access */ -#define VME2_MASTERCTL_ALL 0xff -/*2c*/ volatile u_long vme2_gcsrctl; -#define VME2_GCSRCTL_OFF 0xf0000000 -#define VME2_GCSRCTL_MDEN4 0x00080000 -#define VME2_GCSRCTL_MDEN3 0x00040000 -#define VME2_GCSRCTL_MDEN2 0x00020000 -#define VME2_GCSRCTL_MDEN1 0x00010000 -#define VME2_GCSRCTL_I2EN 0x00008000 /* F decode (A24D16/A32D16) on */ -#define VME2_GCSRCTL_I2WP 0x00004000 /* F decode write post */ -#define VME2_GCSRCTL_I2SU 0x00002000 /* F decode is supervisor */ -#define VME2_GCSRCTL_I2PD 0x00001000 /* F decode is program */ -#define VME2_GCSRCTL_I1EN 0x00000800 /* short decode (A16Dx) on */ -#define VME2_GCSRCTL_I1D16 0x00000400 /* short decode is D16 */ -#define VME2_GCSRCTL_I1WP 0x00000200 /* short decode write post */ -#define VME2_GCSRCTL_I1SU 0x00000100 /* short decode is supervisor */ -#define VME2_GCSRCTL_ROMSIZE 0x000000c0 /* size of ROM */ -#define VME2_GCSRCTL_ROMBSPD 0x00000038 /* speed of ROM */ -#define VME2_GCSRCTL_ROMASPD 0x00000007 /* speed of ROM */ -/*30*/ volatile u_long vme2_dmactl; -/*34*/ volatile u_long vme2_dmamode; -/*38*/ volatile u_long vme2_dmaladdr; -/*3c*/ volatile u_long vme2_dmavmeaddr; -/*40*/ volatile u_long vme2_dmacount; -/*44*/ volatile u_long vme2_dmatable; -/*48*/ volatile u_long vme2_dmastat; -/*4c*/ volatile u_long vme2_tcr; -#define VME2_TCR_1MS (1 << 8) /* Watchdog 1 ms */ -#define VME2_TCR_2MS (2 << 8) /* Watchdog 2 ms */ -#define VME2_TCR_4MS (3 << 8) /* Watchdog 4 ms */ -#define VME2_TCR_8MS (4 << 8) /* Watchdog 8 ms */ -#define VME2_TCR_16MS (5 << 8) /* Watchdog 16 ms */ -#define VME2_TCR_32MS (6 << 8) /* Watchdog 32 ms */ -#define VME2_TCR_64MS (7 << 8) /* Watchdog 64 ms */ -#define VME2_TCR_128MS (8 << 8) /* Watchdog 128 ms */ -#define VME2_TCR_256MS (9 << 8) /* Watchdog 256 ms */ -#define VME2_TCR_512MS (10 << 8) /* Watchdog 512 ms */ -#define VME2_TCR_1S (11 << 8) /* Watchdog 1 s */ -#define VME2_TCR_4S (12 << 8) /* Watchdog 4 s */ -#define VME2_TCR_16S (13 << 8) /* Watchdog 16 s */ -#define VME2_TCR_32S (14 << 8) /* Watchdog 32 s */ -#define VME2_TCR_64S (15 << 8) /* Watchdog 64 s */ -/*50*/ volatile u_long vme2_t1cmp; -/*54*/ volatile u_long vme2_t1count; -/*58*/ volatile u_long vme2_t2cmp; -/*5c*/ volatile u_long vme2_t2count; -/*60*/ volatile u_long vme2_tctl; -#define VME2_TCTL1_CEN 0x01 -#define VME2_TCTL1_COC 0x02 -#define VME2_TCTL1_COVF 0x04 -#define VME2_TCTL1_OVF 0xf0 -#define VME2_TCTL2_CEN (0x01 << 8) -#define VME2_TCTL2_COC (0x02 << 8) -#define VME2_TCTL2_COVF (0x04 << 8) -#define VME2_TCTL2_OVF (0xf0 << 8) -#define VME2_TCTL_WDEN 0x00010000 /* Watchdog Enable */ -#define VME2_TCTL_WDRSE 0x00020000 /* Watchdog Reset Enable */ -#define VME2_TCTL_WDSL 0x00040000 /* local or system reset */ -#define VME2_TCTL_WDBFE 0x00080000 /* Watchdog Board Fail Enable */ -#define VME2_TCTL_WDTO 0x00100000 /* Watchdog Timeout Status */ -#define VME2_TCTL_WDCC 0x00200000 /* Watchdog Clear Counter */ -#define VME2_TCTL_WDCS 0x00400000 /* Watchdog Clear Timeout */ -#define VME2_TCTL_SRST 0x00800000 /* system reset */ -#define VME2_TCTL_RSWE 0x01000000 /* Reset Switch Enable */ -#define VME2_TCTL_BDFLO 0x02000000 /* Assert Board Fail */ -#define VME2_TCTL_CPURS 0x04000000 /* Clear Power-up Reset bit */ -#define VME2_TCTL_PURS 0x08000000 /* Power-up Reset bit */ -#define VME2_TCTL_BDFLI 0x10000000 /* Board Fail Status*/ -#define VME2_TCTL_SYSFAIL 0x20000000 /* light SYSFAIL led */ -#define VME2_TCTL_SCON 0x40000000 /* we are SCON */ -/*64*/ volatile u_long vme2_prescale; -/*68*/ volatile u_long vme2_irqstat; -/*6c*/ volatile u_long vme2_irqen; -/*70*/ volatile u_long vme2_setsoftirq; /* VME2_IRQ_SWx only */ -/*74*/ volatile u_long vme2_irqclr; /* except VME2_IRQ_VMEx */ -#define VME2_IRQ_ACF 0x80000000 -#define VME2_IRQ_AB 0x40000000 -#define VME2_IRQ_SYSF 0x20000000 -#define VME2_IRQ_MWP 0x10000000 -#define VME2_IRQ_PE 0x08000000 -#define VME2_IRQ_V1IE 0x04000000 -#define VME2_IRQ_TIC2 0x02000000 -#define VME2_IRQ_TIC1 0x01000000 -#define VME2_IRQ_VIA 0x00800000 -#define VME2_IRQ_DMA 0x00400000 -#define VME2_IRQ_SIG3 0x00200000 -#define VME2_IRQ_SIG2 0x00100000 -#define VME2_IRQ_SIG1 0x00080000 -#define VME2_IRQ_SIG0 0x00040000 -#define VME2_IRQ_LM1 0x00020000 -#define VME2_IRQ_LM0 0x00010000 -#define VME2_IRQ_SW7 0x00008000 -#define VME2_IRQ_SW6 0x00004000 -#define VME2_IRQ_SW5 0x00002000 -#define VME2_IRQ_SW4 0x00001000 -#define VME2_IRQ_SW3 0x00000800 -#define VME2_IRQ_SW2 0x00000400 -#define VME2_IRQ_SW1 0x00000200 -#define VME2_IRQ_SW0 0x00000100 -#define VME2_IRQ_SW(x) ((1 << (x))) << 8) -#define VME2_IRQ_SPARE 0x00000080 -#define VME2_IRQ_VME7 0x00000040 -#define VME2_IRQ_VME6 0x00000020 -#define VME2_IRQ_VME5 0x00000010 -#define VME2_IRQ_VME4 0x00000008 -#define VME2_IRQ_VME3 0x00000004 -#define VME2_IRQ_VME2 0x00000002 -#define VME2_IRQ_VME1 0x00000001 -#define VME2_IRQ_VME(x) (1 << ((x) - 1)) -/*78*/ volatile u_long vme2_irql1; -#define VME2_IRQL1_ACFSHIFT 28 -#define VME2_IRQL1_ABSHIFT 24 -#define VME2_IRQL1_SYSFSHIFT 20 -#define VME2_IRQL1_WPESHIFT 16 -#define VME2_IRQL1_PESHIFT 12 -#define VME2_IRQL1_V1IESHIFT 8 -#define VME2_IRQL1_TIC2SHIFT 4 -#define VME2_IRQL1_TIC1SHIFT 0 -/*7c*/ volatile u_long vme2_irql2; -#define VME2_IRQL2_VIASHIFT 28 -#define VME2_IRQL2_DMASHIFT 24 -#define VME2_IRQL2_SIG3SHIFT 20 -#define VME2_IRQL2_SIG2SHIFT 16 -#define VME2_IRQL2_SIG1SHIFT 12 -#define VME2_IRQL2_SIG0SHIFT 8 -#define VME2_IRQL2_LM1SHIFT 4 -#define VME2_IRQL2_LM0SHIFT 0 -/*80*/ volatile u_long vme2_irql3; -#define VME2_IRQL3_SW7SHIFT 28 -#define VME2_IRQL3_SW6SHIFT 24 -#define VME2_IRQL3_SW5SHIFT 20 -#define VME2_IRQL3_SW4SHIFT 16 -#define VME2_IRQL3_SW3SHIFT 12 -#define VME2_IRQL3_SW2SHIFT 8 -#define VME2_IRQL3_SW1SHIFT 4 -#define VME2_IRQL3_SW0SHIFT 0 -/*84*/ volatile u_long vme2_irql4; -#define VME2_IRQL4_SPARESHIFT 28 -#define VME2_IRQL4_VME7SHIFT 24 -#define VME2_IRQL4_VME6SHIFT 20 -#define VME2_IRQL4_VME5SHIFT 16 -#define VME2_IRQL4_VME4SHIFT 12 -#define VME2_IRQL4_VME3SHIFT 8 -#define VME2_IRQL4_VME2SHIFT 4 -#define VME2_IRQL4_VME1SHIFT 0 -/*88*/ volatile u_long vme2_vbr; -#define VME2_SYSFAIL (1 << 22) -#define VME2_IOCTL1_MIEN (1 << 23) -#define VME2_VBR_0SHIFT 28 -#define VME2_VBR_1SHIFT 24 -#define VME2_SET_VBR0(x) ((x) << VME2_VBR_0SHIFT) -#define VME2_SET_VBR1(x) ((x) << VME2_VBR_1SHIFT) -#define VME2_GET_VBR0(x) ((((x)->vme2_vbr >> 28) & 0xf) << 4) -#define VME2_GET_VBR1(x) ((((x)->vme2_vbr >> 24) & 0xf) << 4) -#define VME2_VBR_GPOXXXX 0x00ffffff -/*8c*/ volatile u_long vme2_misc; -#define VME2_MISC_MPIRQEN 0x00000080 /* do not set */ -#define VME2_MISC_REVEROM 0x00000040 /* 167: dis eprom. 166: en flash */ -#define VME2_MISC_DISSRAM 0x00000020 /* do not set */ -#define VME2_MISC_DISMST 0x00000010 -#define VME2_MISC_NOELBBSY 0x00000008 /* do not set */ -#define VME2_MISC_DISBSYT 0x00000004 /* do not set */ -#define VME2_MISC_ENINT 0x00000002 /* do not set */ -#define VME2_MISC_DISBGN 0x00000001 /* do not set */ -}; +#define VME2_MASTERCTL_ALL 0xff + +#define VME2_GCSRCTL_OFF 0xf0000000 +#define VME2_GCSRCTL_MDEN4 0x00080000 +#define VME2_GCSRCTL_MDEN3 0x00040000 +#define VME2_GCSRCTL_MDEN2 0x00020000 +#define VME2_GCSRCTL_MDEN1 0x00010000 +#define VME2_GCSRCTL_I2EN 0x00008000 /* F decode (A24D16/A32D16) on */ +#define VME2_GCSRCTL_I2WP 0x00004000 /* F decode write post */ +#define VME2_GCSRCTL_I2SU 0x00002000 /* F decode is supervisor */ +#define VME2_GCSRCTL_I2PD 0x00001000 /* F decode is program */ +#define VME2_GCSRCTL_I1EN 0x00000800 /* short decode (A16Dx) on */ +#define VME2_GCSRCTL_I1D16 0x00000400 /* short decode is D16 */ +#define VME2_GCSRCTL_I1WP 0x00000200 /* short decode write post */ +#define VME2_GCSRCTL_I1SU 0x00000100 /* short decode is supervisor */ +#define VME2_GCSRCTL_ROMSIZE 0x000000c0 /* size of ROM */ +#define VME2_GCSRCTL_ROMBSPD 0x00000038 /* speed of ROM */ +#define VME2_GCSRCTL_ROMASPD 0x00000007 /* speed of ROM */ + +#define VME2_TCR_1MS (1 << 8) /* Watchdog 1 ms */ +#define VME2_TCR_2MS (2 << 8) /* Watchdog 2 ms */ +#define VME2_TCR_4MS (3 << 8) /* Watchdog 4 ms */ +#define VME2_TCR_8MS (4 << 8) /* Watchdog 8 ms */ +#define VME2_TCR_16MS (5 << 8) /* Watchdog 16 ms */ +#define VME2_TCR_32MS (6 << 8) /* Watchdog 32 ms */ +#define VME2_TCR_64MS (7 << 8) /* Watchdog 64 ms */ +#define VME2_TCR_128MS (8 << 8) /* Watchdog 128 ms */ +#define VME2_TCR_256MS (9 << 8) /* Watchdog 256 ms */ +#define VME2_TCR_512MS (10 << 8) /* Watchdog 512 ms */ +#define VME2_TCR_1S (11 << 8) /* Watchdog 1 s */ +#define VME2_TCR_4S (12 << 8) /* Watchdog 4 s */ +#define VME2_TCR_16S (13 << 8) /* Watchdog 16 s */ +#define VME2_TCR_32S (14 << 8) /* Watchdog 32 s */ +#define VME2_TCR_64S (15 << 8) /* Watchdog 64 s */ + +#define VME2_TCTL1_CEN 0x01 +#define VME2_TCTL1_COC 0x02 +#define VME2_TCTL1_COVF 0x04 +#define VME2_TCTL1_OVF 0xf0 +#define VME2_TCTL2_CEN (0x01 << 8) +#define VME2_TCTL2_COC (0x02 << 8) +#define VME2_TCTL2_COVF (0x04 << 8) +#define VME2_TCTL2_OVF (0xf0 << 8) +#define VME2_TCTL_WDEN 0x00010000 /* Watchdog Enable */ +#define VME2_TCTL_WDRSE 0x00020000 /* Watchdog Reset Enable */ +#define VME2_TCTL_WDSL 0x00040000 /* local or system reset */ +#define VME2_TCTL_WDBFE 0x00080000 /* Watchdog Board Fail Enable */ +#define VME2_TCTL_WDTO 0x00100000 /* Watchdog Timeout Status */ +#define VME2_TCTL_WDCC 0x00200000 /* Watchdog Clear Counter */ +#define VME2_TCTL_WDCS 0x00400000 /* Watchdog Clear Timeout */ +#define VME2_TCTL_SRST 0x00800000 /* system reset */ +#define VME2_TCTL_RSWE 0x01000000 /* Reset Switch Enable */ +#define VME2_TCTL_BDFLO 0x02000000 /* Assert Board Fail */ +#define VME2_TCTL_CPURS 0x04000000 /* Clear Power-up Reset bit */ +#define VME2_TCTL_PURS 0x08000000 /* Power-up Reset bit */ +#define VME2_TCTL_BDFLI 0x10000000 /* Board Fail Status*/ +#define VME2_TCTL_SYSFAIL 0x20000000 /* light SYSFAIL led */ +#define VME2_TCTL_SCON 0x40000000 /* we are SCON */ -#define VME2_A16D32BASE 0xffff0000UL -#define VME2_A16D32LEN 0x00010000UL -#define VME2_A32D16BASE 0xf1000000UL -#define VME2_A32D16LEN 0x01000000UL -#define VME2_A16D16BASE 0xffff0000UL -#define VME2_A16D16LEN 0x00010000UL -#define VME2_A24D16BASE 0xf0000000UL -#define VME2_A24D16LEN 0x01000000UL -#define VME2_A16BASE 0xffff0000UL -#define VME2_A24BASE 0xff000000UL +#define VME2_IRQ_ACF 0x80000000 +#define VME2_IRQ_AB 0x40000000 +#define VME2_IRQ_SYSF 0x20000000 +#define VME2_IRQ_MWP 0x10000000 +#define VME2_IRQ_PE 0x08000000 +#define VME2_IRQ_V1IE 0x04000000 +#define VME2_IRQ_TIC2 0x02000000 +#define VME2_IRQ_TIC1 0x01000000 +#define VME2_IRQ_VIA 0x00800000 +#define VME2_IRQ_DMA 0x00400000 +#define VME2_IRQ_SIG3 0x00200000 +#define VME2_IRQ_SIG2 0x00100000 +#define VME2_IRQ_SIG1 0x00080000 +#define VME2_IRQ_SIG0 0x00040000 +#define VME2_IRQ_LM1 0x00020000 +#define VME2_IRQ_LM0 0x00010000 +#define VME2_IRQ_SW7 0x00008000 +#define VME2_IRQ_SW6 0x00004000 +#define VME2_IRQ_SW5 0x00002000 +#define VME2_IRQ_SW4 0x00001000 +#define VME2_IRQ_SW3 0x00000800 +#define VME2_IRQ_SW2 0x00000400 +#define VME2_IRQ_SW1 0x00000200 +#define VME2_IRQ_SW0 0x00000100 +#define VME2_IRQ_SW(x) ((1 << (x))) << 8) +#define VME2_IRQ_SPARE 0x00000080 +#define VME2_IRQ_VME7 0x00000040 +#define VME2_IRQ_VME6 0x00000020 +#define VME2_IRQ_VME5 0x00000010 +#define VME2_IRQ_VME4 0x00000008 +#define VME2_IRQ_VME3 0x00000004 +#define VME2_IRQ_VME2 0x00000002 +#define VME2_IRQ_VME1 0x00000001 +#define VME2_IRQ_VME(x) (1 << ((x) - 1)) -void *vmepmap(struct device *sc, off_t vmeaddr, int len, int bustype); +#define VME2_IRQL1_ACFSHIFT 28 +#define VME2_IRQL1_ABSHIFT 24 +#define VME2_IRQL1_SYSFSHIFT 20 +#define VME2_IRQL1_WPESHIFT 16 +#define VME2_IRQL1_PESHIFT 12 +#define VME2_IRQL1_V1IESHIFT 8 +#define VME2_IRQL1_TIC2SHIFT 4 +#define VME2_IRQL1_TIC1SHIFT 0 + +#define VME2_IRQL2_VIASHIFT 28 +#define VME2_IRQL2_DMASHIFT 24 +#define VME2_IRQL2_SIG3SHIFT 20 +#define VME2_IRQL2_SIG2SHIFT 16 +#define VME2_IRQL2_SIG1SHIFT 12 +#define VME2_IRQL2_SIG0SHIFT 8 +#define VME2_IRQL2_LM1SHIFT 4 +#define VME2_IRQL2_LM0SHIFT 0 + +#define VME2_IRQL3_SW7SHIFT 28 +#define VME2_IRQL3_SW6SHIFT 24 +#define VME2_IRQL3_SW5SHIFT 20 +#define VME2_IRQL3_SW4SHIFT 16 +#define VME2_IRQL3_SW3SHIFT 12 +#define VME2_IRQL3_SW2SHIFT 8 +#define VME2_IRQL3_SW1SHIFT 4 +#define VME2_IRQL3_SW0SHIFT 0 + +#define VME2_IRQL4_SPARESHIFT 28 +#define VME2_IRQL4_VME7SHIFT 24 +#define VME2_IRQL4_VME6SHIFT 20 +#define VME2_IRQL4_VME5SHIFT 16 +#define VME2_IRQL4_VME4SHIFT 12 +#define VME2_IRQL4_VME3SHIFT 8 +#define VME2_IRQL4_VME2SHIFT 4 +#define VME2_IRQL4_VME1SHIFT 0 + +#define VME2_SYSFAIL (1 << 22) +#define VME2_IOCTL1_MIEN (1 << 23) +#define VME2_VBR_0SHIFT 28 +#define VME2_VBR_1SHIFT 24 +#define VME2_SET_VBR0(x) ((x) << VME2_VBR_0SHIFT) +#define VME2_SET_VBR1(x) ((x) << VME2_VBR_1SHIFT) +#define VME2_GET_VBR0(x) ((((x) >> 28) & 0xf) << 4) +#define VME2_GET_VBR1(x) ((((x) >> 24) & 0xf) << 4) +#define VME2_VBR_GPOXXXX 0x00ffffff + +#define VME2_MISC_MPIRQEN 0x00000080 /* do not set */ +#define VME2_MISC_REVEROM 0x00000040 /* 167: dis eprom. 166: en flash */ +#define VME2_MISC_DISSRAM 0x00000020 /* do not set */ +#define VME2_MISC_DISMST 0x00000010 +#define VME2_MISC_NOELBBSY 0x00000008 /* do not set */ +#define VME2_MISC_DISBSYT 0x00000004 /* do not set */ +#define VME2_MISC_ENINT 0x00000002 /* do not set */ +#define VME2_MISC_DISBGN 0x00000001 /* do not set */ + +#define VME2_A16D32BASE 0xffff0000UL +#define VME2_A16D32LEN 0x00010000UL +#define VME2_A32D16BASE 0xf1000000UL +#define VME2_A32D16LEN 0x01000000UL +#define VME2_A16D16BASE 0xffff0000UL +#define VME2_A16D16LEN 0x00010000UL +#define VME2_A24D16BASE 0xf0000000UL +#define VME2_A24D16LEN 0x01000000UL +#define VME2_A16BASE 0xffff0000UL +#define VME2_A24BASE 0xff000000UL + +void *vmepmap(struct device *sc, off_t vmeaddr, int bustype); int vmerw(struct device *sc, struct uio *uio, int flags, int bus); int vmeintr_establish(int vec, struct intrhand *ih); int vme_findvec(int); int vmescan(struct device *, void *, void *, int); -/* D16 access functions */ -void d16_bcopy(const void *, void *, size_t); -void d16_bzero(void *, size_t); - #endif /* __MVEME88K_DEV_VME_H__ */ diff --git a/sys/arch/mvme88k/dev/vmel.c b/sys/arch/mvme88k/dev/vmel.c index 90b061543cc..77e464d63d4 100644 --- a/sys/arch/mvme88k/dev/vmel.c +++ b/sys/arch/mvme88k/dev/vmel.c @@ -1,4 +1,4 @@ -/* $OpenBSD: vmel.c,v 1.14 2004/01/14 20:50:48 miod Exp $ */ +/* $OpenBSD: vmel.c,v 1.15 2004/04/24 19:51:48 miod Exp $ */ /* * Copyright (c) 1995 Theo de Raadt @@ -44,8 +44,9 @@ * functions will decide how many address bits are relevant. */ -void vmelattach(struct device *, struct device *, void *); -int vmelmatch(struct device *, void *, void *); +void vmelattach(struct device *, struct device *, void *); +int vmelmatch(struct device *, void *, void *); +int vmelscan(struct device *, void *, void *); struct cfattach vmel_ca = { sizeof(struct device), vmelmatch, vmelattach @@ -55,8 +56,6 @@ struct cfdriver vmel_cd = { NULL, "vmel", DV_DULL }; -int vmelscan(struct device *, void *, void *); - int vmelmatch(parent, cf, args) struct device *parent; @@ -160,7 +159,7 @@ vmelmmap(dev, off, prot) struct device *sc = (struct device *)vmel_cd.cd_devs[unit]; void * pa; - pa = vmepmap(sc->dv_parent, off, NBPG, BUS_VMEL); + pa = vmepmap(sc->dv_parent, off, BUS_VMEL); #ifdef DEBUG printf("vmel %llx pa %p\n", off, pa); #endif diff --git a/sys/arch/mvme88k/dev/vmes.c b/sys/arch/mvme88k/dev/vmes.c index d33313e5e5a..4e6ae197e86 100644 --- a/sys/arch/mvme88k/dev/vmes.c +++ b/sys/arch/mvme88k/dev/vmes.c @@ -1,4 +1,4 @@ -/* $OpenBSD: vmes.c,v 1.17 2004/01/14 20:50:48 miod Exp $ */ +/* $OpenBSD: vmes.c,v 1.18 2004/04/24 19:51:48 miod Exp $ */ /* * Copyright (c) 1995 Theo de Raadt @@ -32,6 +32,7 @@ #include <sys/kernel.h> #include <sys/device.h> +#include <machine/bus.h> #include <machine/autoconf.h> #include <machine/conf.h> #include <machine/cpu.h> @@ -44,8 +45,9 @@ * functions will decide how many address bits are relevant. */ -void vmesattach(struct device *, struct device *, void *); -int vmesmatch(struct device *, void *, void *); +void vmesattach(struct device *, struct device *, void *); +int vmesmatch(struct device *, void *, void *); +int vmesscan(struct device *, void *, void *); struct cfattach vmes_ca = { sizeof(struct device), vmesmatch, vmesattach @@ -55,7 +57,9 @@ struct cfdriver vmes_cd = { NULL, "vmes", DV_DULL }; -int vmesscan(struct device *, void *, void *); +/* + * Configuration glue + */ int vmesmatch(parent, cf, args) @@ -160,7 +164,7 @@ vmesmmap(dev, off, prot) struct device *sc = (struct device *)vmes_cd.cd_devs[unit]; void * pa; - pa = vmepmap(sc->dv_parent, off, NBPG, BUS_VMES); + pa = vmepmap(sc->dv_parent, off, BUS_VMES); #ifdef DEBUG printf("vmes %llx pa %p\n", off, pa); #endif @@ -168,42 +172,3 @@ vmesmmap(dev, off, prot) return (-1); return (atop(pa)); } - -/* - * Specific D16 access functions - * - * D16 cards will trigger bus errors on attempting to read or write more - * than 16 bits on the bus. Given how the m88k processor works, this means - * basically that all long (D32) accesses must be carefully taken care of. - * - * Since the kernels bcopy() and bzero() routines will use 32 bit accesses - * for performance, here are specific D16-compatible routines. They expect - * pointers to be 16-bit aligned. - */ - -void -d16_bcopy(const void *src, void *dst, size_t len) -{ - const u_int16_t *s = (const u_int16_t *)src; - u_int16_t *d = (u_int16_t *)dst; - size_t l = len; - - l >>= 1; - while (l-- != 0) - *d++ = *s++; - if (len & 1) - *(u_int8_t *)d = *(u_int8_t *)s; -} - -void -d16_bzero(void *dst, size_t len) -{ - u_int16_t *d = (u_int16_t *)dst; - size_t l = len; - - l >>= 1; - while (l-- != 0) - *d++ = 0; - if (len & 1) - *(u_int8_t *)d = 0; -} diff --git a/sys/arch/mvme88k/dev/vs.c b/sys/arch/mvme88k/dev/vs.c index 5f85255d125..5725ad301d1 100644 --- a/sys/arch/mvme88k/dev/vs.c +++ b/sys/arch/mvme88k/dev/vs.c @@ -1,4 +1,4 @@ -/* $OpenBSD: vs.c,v 1.30 2004/04/16 23:35:50 miod Exp $ */ +/* $OpenBSD: vs.c,v 1.31 2004/04/24 19:51:48 miod Exp $ */ /* * Copyright (c) 1999 Steve Murphree, Jr. @@ -37,6 +37,9 @@ * MVME328S scsi adaptor driver */ +/* This card lives in D16 space */ +#define __BUS_SPACE_RESTRICT_D16__ + #include <sys/param.h> #include <sys/systm.h> #include <sys/device.h> @@ -112,8 +115,16 @@ vsmatch(pdp, vcf, args) void *vcf, *args; { struct confargs *ca = args; + bus_space_tag_t iot = ca->ca_iot; + bus_space_handle_t ioh; + int rc; + + if (bus_space_map(iot, ca->ca_paddr, PAGE_SIZE, 0, &ioh) != 0) + return 0; + rc = badvaddr((vaddr_t)bus_space_vaddr(iot, ioh), 1); + bus_space_unmap(iot, ioh, PAGE_SIZE); - return (!badvaddr((unsigned)ca->ca_vaddr, 1)); + return rc == 0; } void @@ -126,6 +137,8 @@ vsattach(parent, self, args) struct vsreg *rp; int evec; int tmp; + bus_space_tag_t iot = ca->ca_iot; + bus_space_handle_t ioh; /* get the next available vector for the error interrupt */ evec = vme_findvec(ca->ca_vec); @@ -137,9 +150,14 @@ vsattach(parent, self, args) if (ca->ca_ipl < 0) ca->ca_ipl = IPL_BIO; + if (bus_space_map(iot, ca->ca_paddr, PAGE_SIZE, 0, &ioh) != 0) { + printf(": can't map registers!\n"); + return; + } + printf(" vec 0x%x", evec); - sc->sc_vsreg = rp = ca->ca_vaddr; + sc->sc_vsreg = rp = (void *)bus_space_vaddr(iot, ioh); sc->sc_ipl = ca->ca_ipl; sc->sc_nvec = ca->ca_vec; diff --git a/sys/arch/mvme88k/dev/vx.c b/sys/arch/mvme88k/dev/vx.c index 82bc6b6861b..4bc9b005991 100644 --- a/sys/arch/mvme88k/dev/vx.c +++ b/sys/arch/mvme88k/dev/vx.c @@ -1,4 +1,4 @@ -/* $OpenBSD: vx.c,v 1.28 2004/04/16 23:36:27 miod Exp $ */ +/* $OpenBSD: vx.c,v 1.29 2004/04/24 19:51:48 miod Exp $ */ /* * Copyright (c) 1999 Steve Murphree, Jr. * All rights reserved. @@ -26,6 +26,9 @@ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* This card lives in D16 space */ +#define __BUS_SPACE_RESTRICT_D16__ + #include <sys/param.h> #include <sys/ioctl.h> #include <sys/proc.h> @@ -65,14 +68,13 @@ struct vxsoftc { struct evcnt sc_intrcnt; struct vx_info sc_info[NVXPORTS]; struct vxreg *vx_reg; - unsigned int board_addr; + vaddr_t board_addr; struct channel *channel; char channel_number; struct packet sc_bppwait_pkt; void *sc_bppwait_pktp; struct intrhand sc_ih_c; struct intrhand sc_ih_s; - int sc_ipl; int sc_vec; struct envelope *elist_head, *elist_tail; struct packet *plist_head, *plist_tail; @@ -152,13 +154,17 @@ vxmatch(struct device *parent, void *self, void *aux) { struct vxreg *vx_reg; struct confargs *ca = aux; + bus_space_tag_t iot = ca->ca_iot; + bus_space_handle_t ioh; + int rc; - ca->ca_ipl = IPL_TTY; - ca->ca_len = 0x10000; /* we know this */ - - vx_reg = (struct vxreg *)ca->ca_vaddr; + if (bus_space_map(iot, ca->ca_paddr, 0x10000, 0, &ioh) != 0) + return 0; + vx_reg = (struct vxreg *)bus_space_vaddr(iot, ioh); + rc = badvaddr((vaddr_t)&vx_reg->ipc_cr, 1); + bus_space_unmap(iot, ioh, 0x10000); - return (!badvaddr((vaddr_t)&vx_reg->ipc_cr, 1)); + return rc == 0; } void @@ -166,6 +172,8 @@ vxattach(struct device *parent, struct device *self, void *aux) { struct vxsoftc *sc = (struct vxsoftc *)self; struct confargs *ca = aux; + bus_space_tag_t iot = ca->ca_iot; + bus_space_handle_t ioh; if (ca->ca_vec < 0) { printf(": no more interrupts!\n"); @@ -174,11 +182,15 @@ vxattach(struct device *parent, struct device *self, void *aux) if (ca->ca_ipl < 0) ca->ca_ipl = IPL_TTY; + if (bus_space_map(iot, ca->ca_paddr, 0x10000, 0, &ioh) != 0) { + printf(": can't map registers!\n"); + return; + } + /* set up dual port memory and registers and init */ - sc->board_addr = (unsigned int)ca->ca_vaddr; + sc->board_addr = (vaddr_t)bus_space_vaddr(iot, ioh); sc->vx_reg = (struct vxreg *)sc->board_addr; sc->channel = (struct channel *)(sc->board_addr + 0x0100); - sc->sc_ipl = ca->ca_ipl; sc->sc_vec = ca->ca_vec; printf("\n"); @@ -197,7 +209,7 @@ vxattach(struct device *parent, struct device *self, void *aux) sc->sc_ih_c.ih_fn = vx_intr; sc->sc_ih_c.ih_arg = sc; sc->sc_ih_c.ih_wantframe = 0; - sc->sc_ih_c.ih_ipl = ca->ca_ipl; + sc->sc_ih_c.ih_ipl = IPL_TTY; vmeintr_establish(ca->ca_vec, &sc->sc_ih_c); evcnt_attach(&sc->sc_dev, "intr", &sc->sc_intrcnt); @@ -1242,7 +1254,7 @@ create_channels(struct vxsoftc *sc) sc->channel->status_pipe_head_ptr_h; sc->channel->status_pipe_tail_ptr_l = sc->channel->status_pipe_head_ptr_l; - sc->channel->interrupt_level = sc->sc_ipl; + sc->channel->interrupt_level = IPL_TTY; sc->channel->interrupt_vec = sc->sc_vec; sc->channel->channel_priority = 0; sc->channel->channel_number = 0; @@ -1472,7 +1484,7 @@ vx_init(struct vxsoftc *sc) init.command_pipe_number = sc->channel_number; /* return status on the same channel */ init.status_pipe_number = sc->channel_number; - init.interrupt_level = sc->sc_ipl; + init.interrupt_level = IPL_TTY; init.interrupt_vec = sc->sc_vec; init.init_info_ptr_h = HI(INIT_INFO_AREA); init.init_info_ptr_l = LO(INIT_INFO_AREA); diff --git a/sys/arch/mvme88k/include/autoconf.h b/sys/arch/mvme88k/include/autoconf.h index eabfd015e33..10ab457ea94 100644 --- a/sys/arch/mvme88k/include/autoconf.h +++ b/sys/arch/mvme88k/include/autoconf.h @@ -1,4 +1,4 @@ -/* $OpenBSD: autoconf.h,v 1.12 2004/04/14 20:18:17 miod Exp $ */ +/* $OpenBSD: autoconf.h,v 1.13 2004/04/24 19:51:48 miod Exp $ */ /* * Copyright (c) 1999, Steve Murphree, Jr. * Copyright (c) 1996 Nivas Madhur @@ -37,21 +37,19 @@ #ifndef _MVME88K_AUTOCONF_H_ #define _MVME88K_AUTOCONF_H_ +#include <machine/bus.h> + struct confargs { - int ca_bustype; - void *ca_vaddr; - void *ca_paddr; - int ca_offset; - int ca_len; - int ca_ipl; - int ca_vec; - char *ca_name; - void *ca_master; /* points to bus-dependent data */ + bus_space_tag_t ca_iot; /* bus access */ + int ca_bustype; /* bus type */ + paddr_t ca_paddr; /* physical address */ + int ca_offset; /* offset from parent */ + int ca_ipl; /* interrupt level */ + int ca_vec; /* mandatory interrupt vector */ + const char *ca_name; /* device name */ }; #define BUS_MAIN 0 -#define BUS_MC 1 -#define BUS_PCC 2 #define BUS_PCCTWO 3 #define BUS_VMES 4 #define BUS_VMEL 5 @@ -59,7 +57,7 @@ struct confargs { #define BUS_BUSSWITCH 7 /* the following are from the prom/bootblocks */ -extern void *bootaddr; /* PA of boot device */ +extern paddr_t bootaddr; /* PA of boot device */ extern int bootpart; /* boot partition (disk) */ extern struct device *bootdv; /* boot device */ diff --git a/sys/arch/mvme88k/include/bus.h b/sys/arch/mvme88k/include/bus.h new file mode 100644 index 00000000000..909ed9402ea --- /dev/null +++ b/sys/arch/mvme88k/include/bus.h @@ -0,0 +1,749 @@ +/* $OpenBSD: bus.h,v 1.1 2004/04/24 19:51:48 miod Exp $ */ +/* + * Copyright (c) 2004, Miodrag Vallat. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * Simple mvme88k bus_space implementation. + * + * Currently, we only need specific handling for 32 bit read/writes in D16 + * space, and this choice is made at compile time. As a result, all the + * implementation can go through macros or inline functions, except for + * the management functions. + */ + +#ifndef _MVME88K_BUS_H_ +#define _MVME88K_BUS_H_ + +#include <machine/types.h> +#include <machine/asm_macro.h> + +typedef u_int32_t bus_addr_t; +typedef u_int32_t bus_size_t; + +typedef u_int32_t bus_space_handle_t; + +struct mvme88k_bus_space_tag { + int (*bs_map)(bus_addr_t, bus_size_t, int, bus_space_handle_t *); + void (*bs_unmap)(bus_space_handle_t, bus_size_t); + int (*bs_subregion)(bus_space_handle_t, bus_size_t, bus_size_t, + bus_space_handle_t *); + void * (*bs_vaddr)(bus_space_handle_t); + /* alloc, free not implemented yet */ +}; + +typedef const struct mvme88k_bus_space_tag *bus_space_tag_t; + +#define BUS_SPACE_BARRIER_READ 0 +#define BUS_SPACE_BARRIER_WRITE 1 + +/* + * General bus_space function set + */ + +#define bus_space_map(t,a,s,f,r) ((t)->bs_map(a,s,f,r)) +#define bus_space_unmap(t,h,s) ((t)->bs_unmap(h,s)) +#define bus_space_subregion(t,h,o,s,r) ((t)->bs_subregion(h,o,s,r)) +#define bus_space_vaddr(t,h) ((t)->bs_vaddr(h)) + +static void bus_space_barrier(bus_space_tag_t, bus_space_handle_t, + bus_addr_t, bus_size_t, int); + +static __inline__ void +bus_space_barrier(bus_space_tag_t tag, bus_space_handle_t handle, + bus_addr_t offset, bus_size_t size, int flags) +{ + flush_pipeline(); /* overkill? */ +} + +/* + * Read/Write/Region functions for D8 and D16 access. + * Most of these are straightforward and assume that everything is properly + * aligned. + */ + +#define bus_space_read_1(tag, handle, offset) \ + ((void)(tag), *(volatile u_int8_t *)((handle) + (offset))) +#define bus_space_read_2(tag, handle, offset) \ + ((void)(tag), *(volatile u_int16_t *)((handle) + (offset))) + +static void bus_space_read_multi_1(bus_space_tag_t, bus_space_handle_t, + bus_addr_t, u_int8_t *, size_t); + +static __inline__ void +bus_space_read_multi_1(bus_space_tag_t tag, bus_space_handle_t handle, + bus_addr_t offset, u_int8_t *dest, size_t count) +{ + offset += handle; + while ((int)--count >= 0) + *dest++ = bus_space_read_1(tag, 0, offset); +} + +static void bus_space_read_multi_2(bus_space_tag_t, bus_space_handle_t, + bus_addr_t, u_int16_t *, size_t); + +static __inline__ void +bus_space_read_multi_2(bus_space_tag_t tag, bus_space_handle_t handle, + bus_addr_t offset, u_int16_t *dest, size_t count) +{ + offset += handle; + while ((int)--count >= 0) + *dest++ = bus_space_read_2(tag, 0, offset); +} + +static void bus_space_read_raw_multi_2(bus_space_tag_t, bus_space_handle_t, + bus_addr_t, u_int8_t *, size_t); + +static __inline__ void +bus_space_read_raw_multi_2(bus_space_tag_t tag, bus_space_handle_t handle, + bus_addr_t offset, u_int8_t *dest, size_t size) +{ + offset += handle; + size >>= 1; + while ((int)--size >= 0) { + *(u_int16_t *)dest = + bus_space_read_2(tag, 0, offset); + dest += 2; + } +} + +static void bus_space_read_region_1(bus_space_tag_t, bus_space_handle_t, + bus_addr_t, u_int8_t *, size_t); + +static __inline__ void +bus_space_read_region_1(bus_space_tag_t tag, bus_space_handle_t handle, + bus_addr_t offset, u_int8_t *dest, size_t count) +{ + offset += handle; + while ((int)--count >= 0) + *dest++ = bus_space_read_1(tag, 0, offset++); +} + +static void bus_space_read_region_2(bus_space_tag_t, bus_space_handle_t, + bus_addr_t, u_int16_t *, size_t); + +static __inline__ void +bus_space_read_region_2(bus_space_tag_t tag, bus_space_handle_t handle, + bus_addr_t offset, u_int16_t *dest, size_t count) +{ + offset += handle; + while ((int)--count >= 0) { + *dest++ = bus_space_read_2(tag, 0, offset); + offset += 2; + } +} + +static void bus_space_read_raw_region_2(bus_space_tag_t, bus_space_handle_t, + bus_addr_t, u_int8_t *, size_t); + +static __inline__ void +bus_space_read_raw_region_2(bus_space_tag_t tag, bus_space_handle_t handle, + bus_addr_t offset, u_int8_t *dest, size_t size) +{ + size >>= 1; + offset += handle; + while ((int)--size >= 0) { + *(u_int16_t *)dest = bus_space_read_2(tag, 0, offset); + offset += 2; + dest += 2; + } +} + +#define bus_space_write_1(tag, handle, offset, value) \ + ((void)(tag), *(volatile u_int8_t *)((handle) + (offset)) = (value)) +#define bus_space_write_2(tag, handle, offset, value) \ + ((void)(tag), *(volatile u_int16_t *)((handle) + (offset)) = (value)) + +static void bus_space_write_multi_1(bus_space_tag_t, bus_space_handle_t, + bus_addr_t, u_int8_t *, size_t); + +static __inline__ void +bus_space_write_multi_1(bus_space_tag_t tag, bus_space_handle_t handle, + bus_addr_t offset, u_int8_t *dest, size_t count) +{ + offset += handle; + while ((int)--count >= 0) + bus_space_write_1(tag, 0, offset, *dest++); +} + +static void bus_space_write_multi_2(bus_space_tag_t, bus_space_handle_t, + bus_addr_t, u_int16_t *, size_t); + +static __inline__ void +bus_space_write_multi_2(bus_space_tag_t tag, bus_space_handle_t handle, + bus_addr_t offset, u_int16_t *dest, size_t count) +{ + offset += handle; + while ((int)--count >= 0) + bus_space_write_2(tag, 0, offset, *dest++); +} + +static void bus_space_write_raw_multi_2(bus_space_tag_t, bus_space_handle_t, + bus_addr_t, u_int8_t *, size_t); + +static __inline__ void +bus_space_write_raw_multi_2(bus_space_tag_t tag, bus_space_handle_t handle, + bus_addr_t offset, u_int8_t *dest, size_t size) +{ + offset += handle; + size >>= 1; + while ((int)--size >= 0) { + bus_space_write_2(tag, 0, offset, *(u_int16_t *)dest); + dest += 2; + } +} + +static void bus_space_set_multi_1(bus_space_tag_t, bus_space_handle_t, + bus_addr_t, u_int8_t, size_t); + +static __inline__ void +bus_space_set_multi_1(bus_space_tag_t tag, bus_space_handle_t handle, + bus_addr_t offset, u_int8_t value, size_t count) +{ + offset += handle; + while ((int)--count >= 0) + bus_space_write_1(tag, 0, offset, value); +} + +static void bus_space_set_multi_2(bus_space_tag_t, bus_space_handle_t, + bus_addr_t, u_int16_t, size_t); + +static __inline__ void +bus_space_set_multi_2(bus_space_tag_t tag, bus_space_handle_t handle, + bus_addr_t offset, u_int16_t value, size_t count) +{ + offset += handle; + while ((int)--count >= 0) + bus_space_write_2(tag, 0, offset, value); +} + +static void bus_space_write_region_1(bus_space_tag_t, bus_space_handle_t, + bus_addr_t, u_int8_t *, size_t); + +static __inline__ void +bus_space_write_region_1(bus_space_tag_t tag, bus_space_handle_t handle, + bus_addr_t offset, u_int8_t *dest, size_t count) +{ + offset += handle; + while ((int)--count >= 0) + bus_space_write_1(tag, 0, offset++, *dest++); +} + +static void bus_space_write_region_2(bus_space_tag_t, bus_space_handle_t, + bus_addr_t, u_int16_t *, size_t); + +static __inline__ void +bus_space_write_region_2(bus_space_tag_t tag, bus_space_handle_t handle, + bus_addr_t offset, u_int16_t *dest, size_t count) +{ + offset += handle; + while ((int)--count >= 0) { + bus_space_write_2(tag, 0, offset, *dest++); + offset += 2; + } +} + +static void bus_space_write_raw_region_2(bus_space_tag_t, bus_space_handle_t, + bus_addr_t, u_int8_t *, size_t); + +static __inline__ void +bus_space_write_raw_region_2(bus_space_tag_t tag, bus_space_handle_t handle, + bus_addr_t offset, u_int8_t *dest, size_t size) +{ + offset += handle; + size >>= 1; + while ((int)--size >= 0) { + bus_space_write_2(tag, 0, offset, *(u_int16_t *)dest); + offset += 2; + dest += 2; + } +} + +static void bus_space_set_region_1(bus_space_tag_t, bus_space_handle_t, + bus_addr_t, u_int8_t, size_t); + +static __inline__ void +bus_space_set_region_1(bus_space_tag_t tag, bus_space_handle_t handle, + bus_addr_t offset, u_int8_t value, size_t count) +{ + offset += handle; + while ((int)--count >= 0) + bus_space_write_1(tag, 0, offset++, value); +} + +static void bus_space_set_region_2(bus_space_tag_t, bus_space_handle_t, + bus_addr_t, u_int16_t, size_t); + +static __inline__ void +bus_space_set_region_2(bus_space_tag_t tag, bus_space_handle_t handle, + bus_addr_t offset, u_int16_t value, size_t count) +{ + offset += handle; + while ((int)--count >= 0) { + bus_space_write_2(tag, 0, offset, value); + offset += 2; + } +} + +static void bus_space_copy_1(bus_space_tag_t, bus_space_handle_t, bus_addr_t, + bus_space_handle_t, bus_addr_t, bus_size_t); + +static __inline__ void +bus_space_copy_1(bus_space_tag_t tag, bus_space_handle_t h1, bus_addr_t o1, + bus_space_handle_t h2, bus_addr_t o2, bus_size_t count) +{ + o1 += h1; + o2 += h2; + while ((int)--count >= 0) { + *((volatile u_int8_t *)o1)++ = *((volatile u_int8_t *)o2)++; + } +} + +static void bus_space_copy_2(bus_space_tag_t, bus_space_handle_t, bus_addr_t, + bus_space_handle_t, bus_addr_t, bus_size_t); + +static __inline__ void +bus_space_copy_2(bus_space_tag_t tag, bus_space_handle_t h1, bus_addr_t o1, + bus_space_handle_t h2, bus_addr_t o2, bus_size_t count) +{ + o1 += h1; + o2 += h2; + while ((int)--count >= 0) { + *(volatile u_int16_t *)o1 = *(volatile u_int16_t *)o2; + o1 += 2; + o2 += 2; + } +} + +/* + * Unrestricted D32 access + */ + +#ifndef __BUS_SPACE_RESTRICT_D16__ + +#define bus_space_read_4(tag, handle, offset) \ + ((void)(tag), *(volatile u_int32_t *)((handle) + (offset))) + +static void bus_space_read_multi_4(bus_space_tag_t, bus_space_handle_t, + bus_addr_t, u_int32_t *, size_t); + +static __inline__ void +bus_space_read_multi_4(bus_space_tag_t tag, bus_space_handle_t handle, + bus_addr_t offset, u_int32_t *dest, size_t count) +{ + offset += handle; + while ((int)--count >= 0) + *dest++ = bus_space_read_4(tag, 0, offset); +} + +static void bus_space_read_raw_multi_4(bus_space_tag_t, bus_space_handle_t, + bus_addr_t, u_int8_t *, size_t); + +static __inline__ void +bus_space_read_raw_multi_4(bus_space_tag_t tag, bus_space_handle_t handle, + bus_addr_t offset, u_int8_t *dest, size_t size) +{ + offset += handle; + size >>= 2; + while ((int)--size >= 0) { + *(u_int32_t *)dest = + bus_space_read_4(tag, 0, offset); + dest += 4; + } +} + +static void bus_space_read_region_4(bus_space_tag_t, bus_space_handle_t, + bus_addr_t, u_int32_t *, size_t); + +static __inline__ void +bus_space_read_region_4(bus_space_tag_t tag, bus_space_handle_t handle, + bus_addr_t offset, u_int32_t *dest, size_t count) +{ + offset += handle; + while ((int)--count >= 0) { + *dest++ = bus_space_read_4(tag, 0, offset); + offset += 4; + } +} + +static void bus_space_read_raw_region_4(bus_space_tag_t, bus_space_handle_t, + bus_addr_t, u_int8_t *, size_t); + +static __inline__ void +bus_space_read_raw_region_4(bus_space_tag_t tag, bus_space_handle_t handle, + bus_addr_t offset, u_int8_t *dest, size_t size) +{ + size >>= 2; + offset += handle; + while ((int)--size >= 0) { + *(u_int32_t *)dest = bus_space_read_4(tag, 0, offset); + offset += 4; + dest += 4; + } +} + +#define bus_space_write_4(tag, handle, offset, value) \ + ((void)(tag), *(volatile u_int32_t *)((handle) + (offset)) = (value)) + +static void bus_space_write_multi_4(bus_space_tag_t, bus_space_handle_t, + bus_addr_t, u_int32_t *, size_t); + +static __inline__ void +bus_space_write_multi_4(bus_space_tag_t tag, bus_space_handle_t handle, + bus_addr_t offset, u_int32_t *dest, size_t count) +{ + offset += handle; + while ((int)--count >= 0) + bus_space_write_4(tag, 0, offset, *dest++); +} + +static void bus_space_write_raw_multi_4(bus_space_tag_t, bus_space_handle_t, + bus_addr_t, u_int8_t *, size_t); + +static __inline__ void +bus_space_write_raw_multi_4(bus_space_tag_t tag, bus_space_handle_t handle, + bus_addr_t offset, u_int8_t *dest, size_t size) +{ + offset += handle; + size >>= 2; + while ((int)--size >= 0) { + bus_space_write_4(tag, 0, offset, *(u_int32_t *)dest); + dest += 4; + } +} + +static void bus_space_set_multi_4(bus_space_tag_t, bus_space_handle_t, + bus_addr_t, u_int32_t, size_t); + +static __inline__ void +bus_space_set_multi_4(bus_space_tag_t tag, bus_space_handle_t handle, + bus_addr_t offset, u_int32_t value, size_t count) +{ + offset += handle; + while ((int)--count >= 0) + bus_space_write_4(tag, 0, offset, value); +} + +static void bus_space_write_region_4(bus_space_tag_t, bus_space_handle_t, + bus_addr_t, u_int32_t *, size_t); + +static __inline__ void +bus_space_write_region_4(bus_space_tag_t tag, bus_space_handle_t handle, + bus_addr_t offset, u_int32_t *dest, size_t count) +{ + offset += handle; + while ((int)--count >= 0) { + bus_space_write_4(tag, 0, offset, *dest++); + offset += 4; + } +} + +static void bus_space_write_raw_region_4(bus_space_tag_t, bus_space_handle_t, + bus_addr_t, u_int8_t *, size_t); + +static __inline__ void +bus_space_write_raw_region_4(bus_space_tag_t tag, bus_space_handle_t handle, + bus_addr_t offset, u_int8_t *dest, size_t size) +{ + offset += handle; + size >>= 2; + while ((int)--size >= 0) { + bus_space_write_4(tag, 0, offset, *(u_int32_t *)dest); + offset += 4; + dest += 4; + } +} + +static void bus_space_set_region_4(bus_space_tag_t, bus_space_handle_t, + bus_addr_t, u_int32_t, size_t); + +static __inline__ void +bus_space_set_region_4(bus_space_tag_t tag, bus_space_handle_t handle, + bus_addr_t offset, u_int32_t value, size_t count) +{ + offset += handle; + while ((int)--count >= 0) { + bus_space_write_4(tag, 0, offset, value); + offset += 4; + } +} + +static void bus_space_copy_4(bus_space_tag_t, bus_space_handle_t, bus_addr_t, + bus_space_handle_t, bus_addr_t, bus_size_t); + +static __inline__ void +bus_space_copy_4(bus_space_tag_t tag, bus_space_handle_t h1, bus_addr_t o1, + bus_space_handle_t h2, bus_addr_t o2, bus_size_t count) +{ + o1 += h1; + o2 += h2; + while ((int)--count >= 0) { + *(volatile u_int32_t *)o1 = *(volatile u_int32_t *)o2; + o1 += 4; + o2 += 4; + } +} + +#else /* __BUS_SPACE_RESTRICT_D16__ */ + +/* + * Restricted D32 access - done through two adjacent D16 access. + * + * The speed of the basic read and write routines is critical. + * This implementation uses a temporary variable on stack, and does + * two 16 bit load&store sequences. Since the stack is in Dcache, this + * is faster and spills fewer register than a register-only sequence + * (which would need to ld.h into two distinct registers, then extu + * the second one into itself, and or both in the result register). + */ + +static u_int32_t d16_read_4(vaddr_t); +static void d16_write_4(vaddr_t, u_int32_t); + +static __inline__ u_int32_t +d16_read_4(vaddr_t va) +{ + u_int32_t tmp; + + *(u_int16_t *)&tmp = *(volatile u_int16_t *)va; + *(u_int16_t *)((vaddr_t)&tmp + 2) = *(volatile u_int16_t *)(va + 2); + + return tmp; +} + +static __inline__ void +d16_write_4(vaddr_t va, u_int32_t value) +{ + u_int32_t tmp = value; + + *(volatile u_int16_t *)va = *(u_int16_t *)&tmp; + *(volatile u_int16_t *)(va + 2) = *(u_int16_t *)((vaddr_t)&tmp + 2); +} + +#define bus_space_read_4(tag, handle, offset) \ + ((void)(tag), d16_read_4((handle) + (offset))) + +static void bus_space_read_multi_4(bus_space_tag_t, bus_space_handle_t, + bus_addr_t, u_int32_t *, size_t); + +static __inline__ void +bus_space_read_multi_4(bus_space_tag_t tag, bus_space_handle_t handle, + bus_addr_t offset, u_int32_t *dest, size_t count) +{ + offset += handle; + while ((int)--count >= 0) + *dest++ = bus_space_read_4(tag, 0, offset); +} + +static void bus_space_read_raw_multi_4(bus_space_tag_t, bus_space_handle_t, + bus_addr_t, u_int8_t *, size_t); + +static __inline__ void +bus_space_read_raw_multi_4(bus_space_tag_t tag, bus_space_handle_t handle, + bus_addr_t offset, u_int8_t *dest, size_t size) +{ + offset += handle; + size >>= 1; + while ((int)--size >= 0) { + *(u_int16_t *)dest = bus_space_read_2(tag, 0, offset); + dest += 2; + } +} + +static void bus_space_read_region_4(bus_space_tag_t, bus_space_handle_t, + bus_addr_t, u_int32_t *, size_t); + +static __inline__ void +bus_space_read_region_4(bus_space_tag_t tag, bus_space_handle_t handle, + bus_addr_t offset, u_int32_t *__dest, size_t count) +{ + u_int16_t *dest = (u_int16_t *)__dest; + + offset += handle; + count <<= 1; + while ((int)--count >= 0) { + *dest++ = bus_space_read_2(tag, 0, offset); + offset += 2; + } +} + +static void bus_space_read_raw_region_4(bus_space_tag_t, bus_space_handle_t, + bus_addr_t, u_int8_t *, size_t); + +static __inline__ void +bus_space_read_raw_region_4(bus_space_tag_t tag, bus_space_handle_t handle, + bus_addr_t offset, u_int8_t *dest, size_t size) +{ + size >>= 1; + offset += handle; + while ((int)--size >= 0) { + *(u_int16_t *)dest = bus_space_read_2(tag, 0, offset); + offset += 2; + dest += 2; + } +} + +#define bus_space_write_4(tag, handle, offset, value) \ + ((void)(tag), d16_write_4((handle) + (offset), (value))) + +static void bus_space_write_multi_4(bus_space_tag_t, bus_space_handle_t, + bus_addr_t, u_int32_t *, size_t); + +static __inline__ void +bus_space_write_multi_4(bus_space_tag_t tag, bus_space_handle_t handle, + bus_addr_t offset, u_int32_t *dest, size_t count) +{ + offset += handle; + while ((int)--count >= 0) + bus_space_write_4(tag, 0, offset, *dest++); +} + +static void bus_space_write_raw_multi_4(bus_space_tag_t, bus_space_handle_t, + bus_addr_t, u_int8_t *, size_t); + +static __inline__ void +bus_space_write_raw_multi_4(bus_space_tag_t tag, bus_space_handle_t handle, + bus_addr_t offset, u_int8_t *dest, size_t size) +{ + offset += handle; + size >>= 1; + while ((int)--size >= 0) { + bus_space_write_2(tag, 0, offset, *(u_int16_t *)dest); + dest += 2; + } +} + +static void bus_space_set_multi_4(bus_space_tag_t, bus_space_handle_t, + bus_addr_t, u_int32_t, size_t); + +static __inline__ void +bus_space_set_multi_4(bus_space_tag_t tag, bus_space_handle_t handle, + bus_addr_t offset, u_int32_t value, size_t count) +{ + offset += handle; + while ((int)--count >= 0) + bus_space_write_4(tag, 0, offset, value); +} + +static void bus_space_write_region_4(bus_space_tag_t, bus_space_handle_t, + bus_addr_t, u_int32_t *, size_t); + +static __inline__ void +bus_space_write_region_4(bus_space_tag_t tag, bus_space_handle_t handle, + bus_addr_t offset, u_int32_t *__dest, size_t count) +{ + u_int16_t *dest = (u_int16_t *)__dest; + + offset += handle; + count <<= 1; + while ((int)--count >= 0) { + bus_space_write_2(tag, 0, offset, *dest++); + offset += 2; + } +} + +static void bus_space_write_raw_region_4(bus_space_tag_t, bus_space_handle_t, + bus_addr_t, u_int8_t *, size_t); + +static __inline__ void +bus_space_write_raw_region_4(bus_space_tag_t tag, bus_space_handle_t handle, + bus_addr_t offset, u_int8_t *dest, size_t size) +{ + offset += handle; + size >>= 1; + while ((int)--size >= 0) { + bus_space_write_2(tag, 0, offset, *(u_int16_t *)dest); + offset += 2; + dest += 2; + } +} + +static void bus_space_set_region_4(bus_space_tag_t, bus_space_handle_t, + bus_addr_t, u_int32_t, size_t); + +static __inline__ void +bus_space_set_region_4(bus_space_tag_t tag, bus_space_handle_t handle, + bus_addr_t offset, u_int32_t value, size_t count) +{ + offset += handle; + while ((int)--count >= 0) { + bus_space_write_4(tag, 0, offset, value); + offset += 4; + } +} + +static void bus_space_copy_4(bus_space_tag_t, bus_space_handle_t, bus_addr_t, + bus_space_handle_t, bus_addr_t, bus_size_t); + +static __inline__ void +bus_space_copy_4(bus_space_tag_t tag, bus_space_handle_t h1, bus_addr_t o1, + bus_space_handle_t h2, bus_addr_t o2, bus_size_t count) +{ + o1 += h1; + o2 += h2; + count <<= 1; + while ((int)--count >= 0) { + *(volatile u_int16_t *)o1 = *(volatile u_int16_t *)o2; + o1 += 2; + o2 += 2; + } +} + +/* + * Extra D16 access functions + * + * D16 cards will trigger bus errors on attempting to read or write more + * than 16 bits on the bus. Given how the m88k processor works, this means + * basically that all long (D32) accesses must be carefully taken care of. + * + * Since the kernels bcopy() and bzero() routines will use 32 bit accesses + * for performance, here are specific D16-compatible routines. They expect + * pointers to be 16-bit aligned. + */ + +static void d16_bcopy(const void *, void *, size_t); +static void d16_bzero(void *, size_t); + +static __inline__ void +d16_bcopy(const void *src, void *dst, size_t len) +{ + extern const struct mvme88k_bus_space_tag vme_bustag; + bus_space_write_region_2(&vme_bustag, 0, (vaddr_t)dst/*XXX*/, (void *)src, len / 2); + if (len & 1) + bus_space_write_1(&vme_bustag, 0, dst + len - 1, + *(u_int8_t *)((vaddr_t)src + len - 1)); +} + +static __inline__ void +d16_bzero(void *dst, size_t len) +{ + extern const struct mvme88k_bus_space_tag vme_bustag; + bus_space_set_region_2(&vme_bustag, 0, (vaddr_t)dst/*XXX*/, 0, len / 2); + if (len & 1) + bus_space_write_1(&vme_bustag, 0, dst + len - 1, 0); +} + +#endif /* __BUS_SPACE_RESTRICT_D16__ */ + +#endif /* _MVME88K_BUS_H_ */ diff --git a/sys/arch/mvme88k/include/cpu.h b/sys/arch/mvme88k/include/cpu.h index a85294dc3f3..def1dd03795 100644 --- a/sys/arch/mvme88k/include/cpu.h +++ b/sys/arch/mvme88k/include/cpu.h @@ -1,4 +1,4 @@ -/* $OpenBSD: cpu.h,v 1.24 2004/01/12 07:46:16 miod Exp $ */ +/* $OpenBSD: cpu.h,v 1.25 2004/04/24 19:51:48 miod Exp $ */ /* * Copyright (c) 1996 Nivas Madhur * Copyright (c) 1992, 1993 @@ -86,30 +86,6 @@ struct clockframe { */ #include <machine/intr.h> -/* - * Internal IO space (iiomapsize). - * - * Internal IO space is mapped in the kernel from ``OBIO_START'' to - * ``intiolimit'' (defined in locore.s). Since it is always mapped, - * conversion between physical and kernel virtual addresses is easy. - */ - -#ifdef VIRTMAP -/* This will do non 1:1 phys/virt memory mapping in the future - SPM */ -#define ISIIOVA(va) \ - ((char *)(va) >= intiobase && (char *)(va) < intiolimit) -#define IIOV(pa) ((int)(pa)-(int)iiomapbase+(int)intiobase) -#define IIOP(va) ((int)(va)-(int)intiobase+(int)iiomapbase) -#define IIOPOFF(pa) ((int)(pa)-(int)iiomapbase) - -#else - -#define ISIIOVA(va) 1 -#define IIOV(pa) ((pa)) -#define IIOP(va) ((va)) -#define IIOPOFF(pa) ((int)(pa)-(int)OBIO_START) -#endif - #define SIR_NET 1 #define SIR_CLOCK 2 diff --git a/sys/arch/mvme88k/include/m88410.h b/sys/arch/mvme88k/include/m88410.h index ca22e47727b..2c10126d87e 100644 --- a/sys/arch/mvme88k/include/m88410.h +++ b/sys/arch/mvme88k/include/m88410.h @@ -1,4 +1,4 @@ -/* $OpenBSD: m88410.h,v 1.9 2004/04/14 20:16:51 miod Exp $ */ +/* $OpenBSD: m88410.h,v 1.10 2004/04/24 19:51:48 miod Exp $ */ /* * Copyright (c) 2001 Steve Murphree, Jr. * All rights reserved. @@ -30,44 +30,43 @@ * */ -#ifndef __MACHINE_M88410_H__ -#define __MACHINE_M88410_H__ +#ifndef __M88410_H__ +#define __M88410_H__ + +#ifdef _KERNEL /* - * mc88410 External Cache Controller definitions + * MC88410 External Cache Controller definitions * This is only available on MVME197DP/SP models. */ -#ifndef _LOCORE - #include <machine/asm_macro.h> #include <machine/psl.h> -#ifdef _KERNEL #include <mvme88k/dev/busswreg.h> -#endif -#define XCC_NOP "0x0" -#define XCC_FLUSH_PAGE "0x1" -#define XCC_FLUSH_ALL "0x2" -#define XCC_INVAL_ALL "0x3" -#define XCC_ADDR 0xFF800000 +#define XCC_NOP "0x00" +#define XCC_FLUSH_PAGE "0x01" +#define XCC_FLUSH_ALL "0x02" +#define XCC_INVAL_ALL "0x03" +#define XCC_ADDR 0xff800000 static __inline__ void mc88410_flush_page(paddr_t physaddr) { paddr_t xccaddr = XCC_ADDR | (physaddr >> PGSHIFT); m88k_psr_type psr; - struct bussw_reg *bs = (struct bussw_reg *)BS_BASE; - u_short bs_gcsr = bs->bs_gcsr; - u_short bs_romcr = bs->bs_romcr; + u_int16_t bs_gcsr, bs_romcr; + bs_gcsr = *(volatile u_int16_t *)(BS_BASE + BS_GCSR); + bs_romcr = *(volatile u_int16_t *)(BS_BASE + BS_ROMCR); psr = get_psr(); /* mask misaligned exceptions */ set_psr(psr | PSR_MXM); /* clear WEN0 and WEN1 in ROMCR (disables writes to FLASH) */ - bs->bs_romcr &= ~(BS_ROMCR_WEN0 | BS_ROMCR_WEN1) ; - /* set XCC bit in GCSR (0xFF8xxxxx now decodes to mc88410) */ - bs->bs_gcsr |= BS_GCSR_XCC; + *(volatile u_int16_t *)(BS_BASE + BS_ROMCR) = + bs_romcr & ~(BS_ROMCR_WEN0 | BS_ROMCR_WEN1); + /* set XCC bit in GCSR (0xff8xxxxx now decodes to mc88410) */ + *(volatile u_int16_t *)(BS_BASE + BS_GCSR) = bs_gcsr | BS_GCSR_XCC; /* load the value of upper32 into r2 */ __asm__ __volatile__("or r2,r0," XCC_FLUSH_PAGE); @@ -80,88 +79,91 @@ mc88410_flush_page(paddr_t physaddr) __asm__ __volatile__("st.d r2,r4,0"); /* spin until the operation starts */ - while ((bs->bs_xccr & BS_XCC_FBSY) == 0) + while ((*(volatile u_int32_t *)(BS_BASE + BS_XCCR) & BS_XCC_FBSY) == 0) ; /* restore PSR and friends */ set_psr(psr); flush_pipeline(); - bs->bs_gcsr = bs_gcsr; - bs->bs_romcr = bs_romcr; + *(volatile u_int16_t *)(BS_BASE + BS_GCSR) = bs_gcsr; + *(volatile u_int16_t *)(BS_BASE + BS_ROMCR) = bs_romcr; } static __inline__ void mc88410_flush(void) { m88k_psr_type psr; - struct bussw_reg *bs = (struct bussw_reg *)BS_BASE; - u_short bs_gcsr = bs->bs_gcsr; - u_short bs_romcr = bs->bs_romcr; + u_int16_t bs_gcsr, bs_romcr; + bs_gcsr = *(volatile u_int16_t *)(BS_BASE + BS_GCSR); + bs_romcr = *(volatile u_int16_t *)(BS_BASE + BS_ROMCR); psr = get_psr(); /* mask misaligned exceptions */ set_psr(psr | PSR_MXM); /* clear WEN0 and WEN1 in ROMCR (disables writes to FLASH) */ - bs->bs_romcr &= ~(BS_ROMCR_WEN0 | BS_ROMCR_WEN1) ; + *(volatile u_int16_t *)(BS_BASE + BS_ROMCR) = + bs_romcr & ~(BS_ROMCR_WEN0 | BS_ROMCR_WEN1); /* set XCC bit in GCSR (0xFF8xxxxx now decodes to mc88410) */ - bs->bs_gcsr |= BS_GCSR_XCC; + *(volatile u_int16_t *)(BS_BASE + BS_GCSR) = bs_gcsr | BS_GCSR_XCC; /* load the value of upper32 into r2 */ __asm__ __volatile__("or r2,r0," XCC_FLUSH_ALL); /* load the value of lower32 into r3 (always 0) */ __asm__ __volatile__("or r3,r0,r0"); /* load the value of xccaddr into r4 */ - __asm__ __volatile__("or.u r5,r0,hi16(0xFF800000)"); - __asm__ __volatile__("or r4,r5,r0"); /* r4 is now 0xFF800000 */ + __asm__ __volatile__("or.u r5,r0,hi16(0xff800000)"); + __asm__ __volatile__("or r4,r5,r0"); /* make the double write. bang! */ __asm__ __volatile__("st.d r2,r4,0"); /* spin until the operation starts */ - while ((bs->bs_xccr & BS_XCC_FBSY) == 0) + while ((*(volatile u_int32_t *)(BS_BASE + BS_XCCR) & BS_XCC_FBSY) == 0) ; /* restore PSR and friends */ set_psr(psr); flush_pipeline(); - bs->bs_gcsr = bs_gcsr; - bs->bs_romcr = bs_romcr; + *(volatile u_int16_t *)(BS_BASE + BS_GCSR) = bs_gcsr; + *(volatile u_int16_t *)(BS_BASE + BS_ROMCR) = bs_romcr; } static __inline__ void mc88410_inval(void) { m88k_psr_type psr; - struct bussw_reg *bs = (struct bussw_reg *)BS_BASE; - u_short bs_gcsr = bs->bs_gcsr; - u_short bs_romcr = bs->bs_romcr; + u_int16_t bs_gcsr, bs_romcr; + + bs_gcsr = *(volatile u_int16_t *)(BS_BASE + BS_GCSR); + bs_romcr = *(volatile u_int16_t *)(BS_BASE + BS_ROMCR); psr = get_psr(); /* mask misaligned exceptions */ set_psr(psr | PSR_MXM); /* clear WEN0 and WEN1 in ROMCR (disables writes to FLASH) */ - bs->bs_romcr &= ~(BS_ROMCR_WEN0 | BS_ROMCR_WEN1) ; + *(volatile u_int16_t *)(BS_BASE + BS_ROMCR) = + bs_romcr & ~(BS_ROMCR_WEN0 | BS_ROMCR_WEN1); /* set XCC bit in GCSR (0xFF8xxxxx now decodes to mc88410) */ - bs->bs_gcsr |= BS_GCSR_XCC; + *(volatile u_int16_t *)(BS_BASE + BS_GCSR) = bs_gcsr | BS_GCSR_XCC; /* load the value of upper32 into r2 */ __asm__ __volatile__("or r2,r0," XCC_INVAL_ALL); /* load the value of lower32 into r3 (always 0) */ __asm__ __volatile__("or r3,r0,r0"); /* load the value of xccaddr into r4 */ - __asm__ __volatile__("or.u r5,r0,hi16(0xFF800000)"); - __asm__ __volatile__("or r4,r5,r0"); /* r4 is now 0xFF800000 */ + __asm__ __volatile__("or.u r5,r0,hi16(0xff800000)"); + __asm__ __volatile__("or r4,r5,r0"); /* make the double write. bang! */ __asm__ __volatile__("st.d r2,r4,0"); /* spin until the operation starts */ - while ((bs->bs_xccr & BS_XCC_FBSY) == 0) + while ((*(volatile u_int32_t *)(BS_BASE + BS_XCCR) & BS_XCC_FBSY) == 0) ; /* restore PSR and friends */ set_psr(psr); flush_pipeline(); - bs->bs_gcsr = bs_gcsr; - bs->bs_romcr = bs_romcr; + *(volatile u_int16_t *)(BS_BASE + BS_GCSR) = bs_gcsr; + *(volatile u_int16_t *)(BS_BASE + BS_ROMCR) = bs_romcr; } static __inline__ void @@ -174,11 +176,9 @@ mc88410_sync(void) static __inline__ int mc88410_present(void) { - struct bussw_reg *bs = (struct bussw_reg *)BS_BASE; - - return (bs->bs_gcsr & BS_GCSR_B410); + return (*(volatile u_int16_t *)(BS_BASE + BS_GCSR)) & BS_GCSR_B410; } -#endif /* _LOCORE */ +#endif /* _KERNEL */ -#endif /* __MACHINE_M88410_H__ */ +#endif /* __M88410_H__ */ diff --git a/sys/arch/mvme88k/mvme88k/autoconf.c b/sys/arch/mvme88k/mvme88k/autoconf.c index 5a678f06759..cbb6b84c7de 100644 --- a/sys/arch/mvme88k/mvme88k/autoconf.c +++ b/sys/arch/mvme88k/mvme88k/autoconf.c @@ -1,4 +1,4 @@ -/* $OpenBSD: autoconf.c,v 1.26 2004/04/14 20:18:18 miod Exp $ */ +/* $OpenBSD: autoconf.c,v 1.27 2004/04/24 19:51:49 miod Exp $ */ /* * Copyright (c) 1998 Steve Murphree, Jr. * Copyright (c) 1996 Nivas Madhur @@ -65,7 +65,7 @@ struct device *getdisk(char *, int, int, dev_t *); int cold = 1; /* 1 if still booting */ -void *bootaddr; +paddr_t bootaddr; int bootpart; struct device *bootdv; /* set by device drivers (if found) */ diff --git a/sys/arch/mvme88k/mvme88k/machdep.c b/sys/arch/mvme88k/mvme88k/machdep.c index 1d75354a0dd..8e09f434dd9 100644 --- a/sys/arch/mvme88k/mvme88k/machdep.c +++ b/sys/arch/mvme88k/mvme88k/machdep.c @@ -1,4 +1,4 @@ -/* $OpenBSD: machdep.c,v 1.140 2004/04/16 23:35:53 miod Exp $ */ +/* $OpenBSD: machdep.c,v 1.141 2004/04/24 19:51:49 miod Exp $ */ /* * Copyright (c) 1998, 1999, 2000, 2001 Steve Murphree, Jr. * Copyright (c) 1996 Nivas Madhur @@ -1064,26 +1064,26 @@ m188_reset() { volatile int cnt; - *sys_syscon->ien0 = 0; - *sys_syscon->ien1 = 0; - *sys_syscon->ien2 = 0; - *sys_syscon->ien3 = 0; + *(volatile u_int32_t *)IEN0_REG = 0; + *(volatile u_int32_t *)IEN1_REG = 0; + *(volatile u_int32_t *)IEN2_REG = 0; + *(volatile u_int32_t *)IEN3_REG = 0; - if (*sys_syscon->global1 & M188_SYSCONNEG) { + if ((*(volatile u_int8_t *)GLB1) & M188_SYSCONNEG) { /* Force only a local reset */ - *sys_syscon->global1 |= M188_LRST; + *(volatile u_int8_t *)GLB1 |= M188_LRST; } else { /* Force a complete VMEbus reset */ - *sys_syscon->glbres = 1; + *(volatile u_int32_t *)GLBRES_REG = 1; } - *sys_syscon->ucsr |= 0x2000; /* clear SYSFAIL* */ + *(volatile u_int32_t *)UCSR_REG |= 0x2000; /* clear SYSFAIL */ for (cnt = 0; cnt < 5*1024*1024; cnt++) ; - *sys_syscon->ucsr |= 0x2000; /* clear SYSFAIL* */ + *(volatile u_int32_t *)UCSR_REG |= 0x2000; /* clear SYSFAIL */ printf("reset failed\n"); - for (;;); /* just in case we survived... */ + for (;;); /* NOTREACHED */ } #endif /* MVME188 */ @@ -1414,7 +1414,8 @@ intr_establish(int vec, struct intrhand *ihand) if ((intr = intr_handlers[vec]) != NULL) { if (intr->ih_ipl != ihand->ih_ipl) { #if DIAGNOSTIC - panic("intr_establish: there are other handlers with vec (0x%x) at ipl %x, but you want it at %x", + panic("intr_establish: there are other handlers with " + "vec (0x%x) at ipl %x, but you want it at %x", intr->ih_ipl, vec, ihand->ih_ipl); #endif /* DIAGNOSTIC */ return (INTR_EST_BADIPL); @@ -1449,8 +1450,7 @@ intr_establish(int vec, struct intrhand *ihand) */ /* Hard coded vector table for onboard devices. */ - -unsigned obio_vec[32] = { +const unsigned int obio_vec[32] = { 0,0,0,0,0,0,0,0, 0,0,0,0,0,0,0,0, 0,SYSCV_SCC,0,0,SYSCV_SYSF,SYSCV_TIMER2,0,0, @@ -1541,13 +1541,13 @@ m188_ext_int(u_int v, struct trapframe *eframe) /* find the first bit set in the current mask */ intbit = ff1(cur_mask); if (OBIO_INTERRUPT_MASK & (1 << intbit)) { - vec = obio_vec[intbit]; + vec = SYSCON_VECT + obio_vec[intbit]; if (vec == 0) { panic("unknown onboard interrupt: mask = 0x%b", 1 << intbit, IST_STRING); } } else if (HW_FAILURE_MASK & (1 << intbit)) { - vec = obio_vec[intbit]; + vec = SYSCON_VECT + obio_vec[intbit]; if (vec == 0) { panic("unknown hardware failure: mask = 0x%b", 1 << intbit, IST_STRING); |