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authorBrad Smith <brad@cvs.openbsd.org>2006-10-17 22:28:08 +0000
committerBrad Smith <brad@cvs.openbsd.org>2006-10-17 22:28:08 +0000
commita4de7aa4833c26ca1dd050309f0f32d2f091a689 (patch)
tree33ec49e9673ae53065a62e7547057970518c4bd5 /sys
parente97741005e22db58b39ae79eb38000dcf11f905c (diff)
disable the firmware fastboot feature on 5752/5755 and 5787 ASICs,
eliminates firmware timeouts. Tested by pedro la peu <pedro at am-gen dot org> with a 5752 ASIC and Benjamin Black <ben at layer8 dot net> with a 5787 ASIC.
Diffstat (limited to 'sys')
-rw-r--r--sys/dev/pci/if_bge.c7
-rw-r--r--sys/dev/pci/if_bgereg.h4
2 files changed, 9 insertions, 2 deletions
diff --git a/sys/dev/pci/if_bge.c b/sys/dev/pci/if_bge.c
index 4906b15eda6..07c4794ba4e 100644
--- a/sys/dev/pci/if_bge.c
+++ b/sys/dev/pci/if_bge.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: if_bge.c,v 1.189 2006/10/15 06:49:19 brad Exp $ */
+/* $OpenBSD: if_bge.c,v 1.190 2006/10/17 22:28:07 brad Exp $ */
/*
* Copyright (c) 2001 Wind River Systems
@@ -2063,6 +2063,11 @@ bge_reset(struct bge_softc *sc)
BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_PCISTATE_RW);
+ if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5752 ||
+ BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 ||
+ BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5787)
+ CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0);
+
reset = BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1);
if (sc->bge_flags & BGE_PCIE) {
diff --git a/sys/dev/pci/if_bgereg.h b/sys/dev/pci/if_bgereg.h
index 0758d63b6a6..2b0ac15cccc 100644
--- a/sys/dev/pci/if_bgereg.h
+++ b/sys/dev/pci/if_bgereg.h
@@ -1,4 +1,4 @@
-/* $OpenBSD: if_bgereg.h,v 1.65 2006/10/15 06:49:19 brad Exp $ */
+/* $OpenBSD: if_bgereg.h,v 1.66 2006/10/17 22:28:07 brad Exp $ */
/*
* Copyright (c) 2001 Wind River Systems
@@ -1688,6 +1688,8 @@
#define BGE_MDI_CTL 0x6844
#define BGE_EE_DELAY 0x6848
+#define BGE_FASTBOOT_PC 0x6894
+
/*
* TLP Control Register
* Applicable to BCM5721 and BCM5751 only