Much better register description and values. No functional change yet - but

this code does not look like a bingo game chart anymore.

2 files changed, 503 insertions, 130 deletions

diff --git a/sys/dev/pcmcia/cfxga.c b/sys/dev/pcmcia/cfxga.c
index 1eca9c713ec..1a4897f627a 100644
--- a/sys/dev/pcmcia/cfxga.c
+++ b/sys/dev/pcmcia/cfxga.c
@@ -1,15 +1,15 @@
-/*	$OpenBSD: cfxga.c,v 1.1 2006/04/16 20:45:00 miod Exp $	*/
+/*	$OpenBSD: cfxga.c,v 1.2 2006/11/26 17:04:22 miod Exp $	*/
 
 /*
- * Copyright (c) 2005 Matthieu Herrb and Miodrag Vallat
+ * Copyright (c) 2005, 2006, Matthieu Herrb and Miodrag Vallat
  *
  * Permission to use, copy, modify, and distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
  * copyright notice and this permission notice appear in all copies.
  *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHORS DISCLAIM ALL WARRANTIES
  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR
  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
@@ -17,8 +17,8 @@
  */
 
 /*
- * Work-in-progress display driver for the Colorgraphic CompactFlash
- * ``VoyagerVGA'' card.
+ * Display driver for the Colorgraphic CompactFlash ``VoyagerVGA'' card.
+ * based upon the Epson S1D13806 graphics chip.
  *
  * Our goals are:
  * - to provide a somewhat usable emulation mode for extra text display.
@@ -46,7 +46,13 @@
 
 #include <dev/pcmcia/cfxgareg.h>
 
-/* #define CFXGADEBUG */
+/* Old defines, biting the dust soon */
+#define	CROP_SOLIDFILL			0x0c0c
+#define	CROP_EXTCOPY			0x000c
+
+/*
+#define CFXGADEBUG
+*/
 
 #ifdef CFXGADEBUG
 #define	DPRINTF(arg) printf arg
@@ -165,10 +171,16 @@ u_int	cfxga_wait(struct cfxga_softc *, u_int, u_int);
 #define	cfxga_repaint_screen(sc) \
 	cfxga_memory_rop(sc, sc->sc_active, CROP_EXTCOPY, 0, 0, 640, 480)
 
-#define	cfxga_read(sc, addr) \
+#define	cfxga_read_1(sc, addr) \
+	bus_space_read_1((sc)->sc_pmemh.memt, (sc)->sc_pmemh.memh, \
+	    (sc)->sc_offset + (addr))
+#define	cfxga_read_2(sc, addr) \
 	bus_space_read_2((sc)->sc_pmemh.memt, (sc)->sc_pmemh.memh, \
 	    (sc)->sc_offset + (addr))
-#define	cfxga_write(sc, addr, val) \
+#define	cfxga_write_1(sc, addr, val) \
+	bus_space_write_1((sc)->sc_pmemh.memt, (sc)->sc_pmemh.memh, \
+	    (sc)->sc_offset + (addr), (val))
+#define	cfxga_write_2(sc, addr, val) \
 	bus_space_write_2((sc)->sc_pmemh.memt, (sc)->sc_pmemh.memh, \
 	    (sc)->sc_offset + (addr), (val))
 
@@ -279,7 +291,8 @@ cfxga_match(struct device *parent, void *match, void *aux)
 	if (rc != 0)
 		goto out2;
 
-	id = bus_space_read_1(h.memt, h.memh, ptr) & CR_ID_MASK;
+	id = (bus_space_read_1(h.memt, h.memh, ptr + CFREG_REV) &
+	    CR_PRODUCT_MASK) >> CR_PRODUCT_SHIFT;
 
 	pcmcia_mem_unmap(pa->pf, win);
 out2:
@@ -292,7 +305,7 @@ out:
 	 * Be sure to return a value greater than pccom's if we match,
 	 * otherwise it can win due to the way config(8) will order devices...
 	 */
-	return (id == CR_ID ? 10 : 0);
+	return (id == PRODUCT_S1D13806 ? 10 : 0);
 }
 
 int
@@ -424,7 +437,7 @@ cfxga_alloc_screen(void *v, const struct wsscreen_descr *type, void **cookiep,
 	ri->ri_stride = 640 * 16 / 8;
 	/* ri->ri_flg = RI_FULLCLEAR; */
 
-	/* swap B and R */
+	/* swap B and R at 16 bpp */
 	ri->ri_rnum = 5;
 	ri->ri_rpos = 11;
 	ri->ri_gnum = 6;
@@ -468,14 +481,14 @@ void
 cfxga_burner(void *v, u_int on, u_int flags)
 {
 	struct cfxga_softc *sc = (void *)v;
-	u_int16_t ven;
+	u_int8_t mode;
 
-	ven = cfxga_read(sc, CFREG_VIDEO);
+	mode = cfxga_read_1(sc, CFREG_MODE) & LCD_MODE_SWIVEL_BIT_0;
 
 	if (on)
-		cfxga_write(sc, CFREG_VIDEO, ven | CV_VIDEO_VGA);
+		cfxga_write_1(sc, CFREG_MODE, mode | MODE_CRT);
 	else
-		cfxga_write(sc, CFREG_VIDEO, ven & ~CV_VIDEO_VGA);
+		cfxga_write_1(sc, CFREG_MODE, mode | MODE_NO_DISPLAY);
 }
 
 void
@@ -591,62 +604,58 @@ void
 cfxga_reset_video(struct cfxga_softc *sc)
 {
 	/* reset controller */
-	cfxga_write(sc, CFREG_BLT_CTRL, 0);
-	cfxga_write(sc, CFREG_RESET, CR_RESET);
+	cfxga_write_2(sc, CFREG_REV, 0x8080);
+	/* need to write to both REV and MISC at the same time */
+	cfxga_write_2(sc, CFREG_REV, 0x80 | (CM_REGSEL << 8));
+	delay(25000);	/* maintain reset for a short while */
+	/* need to write to both REV and MISC at the same time */
+	cfxga_write_2(sc, CFREG_REV, 0 | (CM_MEMSEL << 8));
 	delay(25000);
-	cfxga_write(sc, CFREG_RESET, 0);
-	delay(25000);
-	cfxga_write(sc, CFREG_BLT_CTRL, 0);
-	(void)cfxga_read(sc, CFREG_BLT_DATA);
+
+	cfxga_write_2(sc, CFREG_BITBLT_CONTROL, 0);
+	(void)cfxga_read_1(sc, CFREG_BITBLT_DATA);
 
 	/*
-	 * Setup video mode - magic values taken from the linux so-called
-	 * driver source.
+	 * Setup video mode.
 	 */
 
-	/* clock */
-	cfxga_write(sc, 0x10, 2);
-	cfxga_write(sc, 0x14, 0);
-	cfxga_write(sc, 0x1c, 2);
-	/* memory configuration */
-	cfxga_write(sc, 0x20, 0x0380);
-	cfxga_write(sc, 0x2a, 0x100);
-	/* CRT and TV settings */
-	cfxga_write(sc, 0x62, 0);
-	cfxga_write(sc, 0x64, 0);
-	cfxga_write(sc, 0x68, 0);
-	cfxga_write(sc, 0x6a, 0);
-	/* cursor */
-	cfxga_write(sc, 0x80, 0);
-	cfxga_write(sc, 0x82, 0x259);
-	cfxga_write(sc, 0x84, 0x190);
-	cfxga_write(sc, 0x86, 0);
-	cfxga_write(sc, 0x88, 0);
-	cfxga_write(sc, 0x8a, 0x3f1f);
-	cfxga_write(sc, 0x8c, 0x1f);
-	cfxga_write(sc, 0x8e, 0);
-	/* unknown */
-	cfxga_write(sc, 0x1f0, 0x210);
-	cfxga_write(sc, 0x1f4, 0);
+	cfxga_write_2(sc, CFREG_MEMCLK, MEMCLK_SRC_CLK3);
+	cfxga_write_1(sc, CFREG_LCD_PCLK, LCD_PCLK_SRC_CLKI | LCD_PCLK_DIV_1);
+	cfxga_write_1(sc, CFREG_MPLUG_CLK,
+	    MPLUG_PCLK_SRC_CLKI2 | MPLUG_PCLK_DIV_1);
+	/* MEMCNF and DRAM_RFRSH need to be programmed at the same time */
+	cfxga_write_2(sc, CFREG_MEMCNF,
+	    MEMCNF_SDRAM_INIT | (DRAM_RFRSH_50MHZ << 8));
+	cfxga_write_2(sc, CFREG_DRAM_TIMING, DRAM_TIMING_50MHZ);
+
+	cfxga_write_2(sc, CFREG_CRT_START_LOW, 0);
+	cfxga_write_1(sc, CFREG_CRT_START_HIGH, 0);
+	cfxga_write_1(sc, CFREG_CRT_PANNING, PIXEL_PANNING_MASK_15BPP);
+	cfxga_write_1(sc, CFREG_CRT_FIFO_THRESHOLD_HIGH, 0);
+	cfxga_write_1(sc, CFREG_CRT_FIFO_THRESHOLD_LOW, 0);
+
+	cfxga_write_1(sc, CFREG_CRT_CURSOR_CONTROL, CURSOR_INACTIVE);
+
+	cfxga_write_1(sc, CFREG_POWER_CONF, 0);
+	cfxga_write_1(sc, CFREG_WATCHDOG, 0);
 
 	/* 640x480x72x16 specific values */
-	/* gpio */
-	cfxga_write(sc, 0x04, 0x07);
-	cfxga_write(sc, 0x08, 0x1ffe);
-	/* more clock */
-	cfxga_write(sc, 0x18, 0);
-	cfxga_write(sc, 0x1e, 2);
-	/* more CRT and TV settings */
-	cfxga_write(sc, 0x50, 0x4f);
-	cfxga_write(sc, 0x52, 0x217);
-	cfxga_write(sc, 0x54, 0x4);
-	cfxga_write(sc, 0x56, 0x1df);
-	cfxga_write(sc, 0x58, 0x827);
-	cfxga_write(sc, 0x5a, 0x1202);
-	cfxga_write(sc, 0x60, 5);
-	cfxga_write(sc, 0x66, 640);
-
-	cfxga_write(sc, CFREG_VIDEO, CV_VIDEO_VGA);
+	cfxga_write_1(sc, CFREG_CRTTV_PCLK, CRT_PCLK_SRC_CLKI | CRT_PCLK_DIV_1);
+	cfxga_write_1(sc, CFREG_WSTATE, WSTATE_MCLK);
+	cfxga_write_1(sc, CFREG_CRT_HWIDTH, (640 / 8) - 1);
+	/* HNDISP and HSTART need to be programmed at the same time */
+	cfxga_write_2(sc, CFREG_CRT_HNDISP, 23 | (2 << 8));
+	cfxga_write_1(sc, CFREG_CRT_HPULSE, 4);
+	cfxga_write_2(sc, CFREG_CRT_VHEIGHT, 480 - 1);
+	/* VNDISP and VSTART need to be programmed at the same time */
+	cfxga_write_2(sc, CFREG_CRT_VNDISP, 39 | (8 << 8));
+	cfxga_write_1(sc, CFREG_CRT_VPULSE, 2);
+	cfxga_write_1(sc, CFREG_TV_CONTROL,
+	    TV_LUMINANCE_FILTER | TV_SVIDEO_OUTPUT);
+	cfxga_write_1(sc, CFREG_CRT_MODE, CRT_MODE_16BPP);
+	cfxga_write_2(sc, CFREG_CRT_MEMORY, 640);
+
+	cfxga_write_1(sc, CFREG_MODE, MODE_CRT);
 	delay(25000);
 }
 
@@ -666,8 +675,7 @@ cfxga_wait(struct cfxga_softc *sc, u_int mask, u_int result)
 	u_int tries;
 
 	for (tries = 100000; tries != 0; tries--) {
-		if ((bus_space_read_1(sc->sc_pmemh.memt, sc->sc_pmemh.memh,
-		    sc->sc_offset + CFREG_BLT_CTRL) & mask) == result)
+		if ((cfxga_read_1(sc, CFREG_BITBLT_CONTROL) & mask) == result)
 			break;
 		delay(10);
 	}
@@ -685,7 +693,7 @@ cfxga_memory_rop(struct cfxga_softc *sc, struct cfxga_screen *scr, u_int rop,
 	pos = (y * 640 + x) * (16 / 8);
 	data = (u_int16_t *)(scr->scr_mem + pos);
 
-	if (cfxga_wait(sc, CC_BLT_BUSY, 0) == 0) {
+	if (cfxga_wait(sc, BITBLT_ACTIVE, 0) == 0) {
 		DPRINTF(("%s: not ready\n", __func__));
 		if (ISSET(sc->sc_state, CS_RESET))
 			return (EAGAIN);
@@ -697,31 +705,38 @@ cfxga_memory_rop(struct cfxga_softc *sc, struct cfxga_screen *scr, u_int rop,
 			return (0);
 		}
 	}
-	(void)cfxga_read(sc, CFREG_BLT_DATA);
-
-	cfxga_write(sc, CFREG_BLT_ROP, rop);
-	cfxga_write(sc, CFREG_BLT_UNK1, 0);
-	cfxga_write(sc, CFREG_BLT_UNK2, 0);
-	cfxga_write(sc, CFREG_BLT_SRCLOW, pos);
-	cfxga_write(sc, CFREG_BLT_SRCHIGH, pos >> 16);
-	cfxga_write(sc, CFREG_BLT_STRIDE, 640);
-	cfxga_write(sc, CFREG_BLT_WIDTH, cx - 1);
-	cfxga_write(sc, CFREG_BLT_HEIGHT, cy - 1);
-	cfxga_write(sc, CFREG_BLT_CTRL, CC_BLT_BUSY | CC_BPP_16);
-
-	(void)cfxga_wait(sc, CC_BLT_BUSY, CC_BLT_BUSY);
+	(void)cfxga_read_1(sc, CFREG_BITBLT_DATA);
+
+#if 0
+	cfxga_write_1(sc, CFREG_BITBLT_ROP, rop);
+	cfxga_write_1(sc, CFREG_BITBLT_OPERATION, OP_WRITE_ROP);
+		/* unless we prefer OP_SOLID_FILL */
+#else
+	cfxga_write_2(sc, CFREG_BITBLT_ROP, rop);
+#endif
+	cfxga_write_2(sc, CFREG_BITBLT_SRC_LOW, 0);
+	cfxga_write_2(sc, CFREG_BITBLT_SRC_HIGH, 0);
+	cfxga_write_2(sc, CFREG_BITBLT_DST_LOW, pos);
+	cfxga_write_2(sc, CFREG_BITBLT_DST_HIGH, pos >> 16);
+	cfxga_write_2(sc, CFREG_BITBLT_OFFSET, 640);
+	cfxga_write_2(sc, CFREG_BITBLT_WIDTH, cx - 1);
+	cfxga_write_2(sc, CFREG_BITBLT_HEIGHT, cy - 1);
+	cfxga_write_2(sc, CFREG_BITBLT_CONTROL,
+	    BITBLT_ACTIVE | BITBLT_COLOR_16);
+
+	(void)cfxga_wait(sc, BITBLT_ACTIVE, BITBLT_ACTIVE);
 	while (cy-- != 0) {
 		for (x = 0; x < cx; x++) {
-			cfxga_write(sc, CFREG_BLT_DATA, *data++);
+			cfxga_write_2(sc, CFREG_BITBLT_DATA, *data++);
 
 			/*
 			 * Let the cheap breathe.
 			 * If this is not enough to let it recover,
 			 * abort the operation.
 			 */
-			if (cfxga_wait(sc, CC_FIFO_BUSY, 0) == 0) {
+			if (cfxga_wait(sc, BITBLT_FIFO_FULL, 0) == 0) {
 				DPRINTF(("%s: abort\n", __func__));
-				cfxga_write(sc, CFREG_BLT_CTRL, 0);
+				cfxga_write_2(sc, CFREG_BITBLT_CONTROL, 0);
 				return (EINTR);
 			}
 		}
@@ -739,7 +754,7 @@ cfxga_standalone_rop(struct cfxga_softc *sc, u_int rop, int x, int y,
 
 	pos = (y * 640 + x) * (16 / 8);
 
-	if (cfxga_wait(sc, CC_BLT_BUSY, 0) == 0) {
+	if (cfxga_wait(sc, BITBLT_ACTIVE, 0) == 0) {
 		DPRINTF(("%s: not ready\n", __func__));
 		if (ISSET(sc->sc_state, CS_RESET))
 			return (EAGAIN);
@@ -752,16 +767,23 @@ cfxga_standalone_rop(struct cfxga_softc *sc, u_int rop, int x, int y,
 		}
 	}
 
-	cfxga_write(sc, CFREG_BLT_ROP, rop);
-	cfxga_write(sc, CFREG_BLT_UNK1, 0);
-	cfxga_write(sc, CFREG_BLT_UNK2, 0);
-	cfxga_write(sc, CFREG_BLT_SRCLOW, pos);
-	cfxga_write(sc, CFREG_BLT_SRCHIGH, pos >> 16);
-	cfxga_write(sc, CFREG_BLT_STRIDE, 640);
-	cfxga_write(sc, CFREG_BLT_WIDTH, cx - 1);
-	cfxga_write(sc, CFREG_BLT_HEIGHT, cy - 1);
-	cfxga_write(sc, CFREG_BLT_SRCCOLOR, srccolor);
-	cfxga_write(sc, CFREG_BLT_CTRL, CC_BLT_BUSY | CC_BPP_16);
+#if 0
+	cfxga_write_1(sc, CFREG_BITBLT_ROP, rop);
+	cfxga_write_1(sc, CFREG_BITBLT_OPERATION, OP_WRITE_ROP);
+		/* unless we prefer OP_SOLID_FILL */
+#else
+	cfxga_write_2(sc, CFREG_BITBLT_ROP, rop);
+#endif
+	cfxga_write_2(sc, CFREG_BITBLT_SRC_LOW, 0);
+	cfxga_write_2(sc, CFREG_BITBLT_SRC_HIGH, 0);
+	cfxga_write_2(sc, CFREG_BITBLT_DST_LOW, pos);
+	cfxga_write_2(sc, CFREG_BITBLT_DST_HIGH, pos >> 16);
+	cfxga_write_2(sc, CFREG_BITBLT_OFFSET, 640);
+	cfxga_write_2(sc, CFREG_BITBLT_WIDTH, cx - 1);
+	cfxga_write_2(sc, CFREG_BITBLT_HEIGHT, cy - 1);
+	cfxga_write_2(sc, CFREG_BITBLT_FG, srccolor);
+	cfxga_write_2(sc, CFREG_BITBLT_CONTROL,
+	    BITBLT_ACTIVE | BITBLT_COLOR_16);
 
 	return (0);
 }
diff --git a/sys/dev/pcmcia/cfxgareg.h b/sys/dev/pcmcia/cfxgareg.h
index c925c6a750e..993e6d43a6d 100644
--- a/sys/dev/pcmcia/cfxgareg.h
+++ b/sys/dev/pcmcia/cfxgareg.h
@@ -1,15 +1,15 @@
-/*	$OpenBSD: cfxgareg.h,v 1.1 2006/04/16 20:45:00 miod Exp $	*/
+/*	$OpenBSD: cfxgareg.h,v 1.2 2006/11/26 17:04:22 miod Exp $	*/
 
 /*
- * Copyright (c) 2005 Matthieu Herrb and Miodrag Vallat
+ * Copyright (c) 2005, 2006, Matthieu Herrb and Miodrag Vallat
  *
  * Permission to use, copy, modify, and distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
  * copyright notice and this permission notice appear in all copies.
  *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHORS DISCLAIM ALL WARRANTIES
  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR
  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
@@ -17,38 +17,389 @@
  */
 
 /*
- * (very scarce) registers layout. Actual chip documentation would be immensely
- * appreciated.
+ * S1D13806 Registers.
+ * Registers larger than 8 bits are little-endian.
  */
-#define	CFREG_RESET		0x0000	/* reset and ID register */
-#define	CR_RESET			0x8080
-#define	CR_ID_MASK			0x00fc
-#define	CR_ID				0x001c
-
-#define	CFREG_BLT_CTRL		0x0100	/* control/status */
-#define	CC_FIFO_BUSY			0x0010
-#define	CC_BLT_BUSY			0x0080
-#define	CC_BPP_8			0x0000
-#define	CC_BPP_16			0x0180
-#define	CFREG_BLT_ROP		0x0102	/* raster op */
-#if 0
-#define	CROP_SRCXORDST			0x0606	/* not so right... */
-#endif
-#define	CROP_SOLIDFILL			0x0c0c
-#define	CROP_EXTCOPY			0x000c
-#define	CFREG_BLT_UNK1		0x0104
-#define	CFREG_BLT_UNK2		0x0106
-#define	CFREG_BLT_SRCLOW	0x0108
-#define	CFREG_BLT_SRCHIGH	0x010a
-#define	CFREG_BLT_STRIDE	0x010c
-#define	CFREG_BLT_WIDTH		0x0110
-#define	CFREG_BLT_HEIGHT	0x0112
-#define	CFREG_BLT_SRCCOLOR	0x0118
-
-#define	CFREG_VIDEO		0x01fc
-#define	CV_VIDEO_VGA			0x0002
-
-#define	CFREG_BLT_DATA		0x0400
+
+/* Revision code register - RO */
+#define	CFREG_REV			0x0000
+#define	CR_REV_MASK		0x03	/* revision code */
+#define	CR_REV_SHIFT		0
+#define	CR_PRODUCT_MASK		0xfc	/* product code */
+#define	CR_PRODUCT_SHIFT	2
+#define	PRODUCT_S1D13806	0x07
+
+/* Miscellaneous register - RW */
+#define	CFREG_MISC			0x0001
+#define	CM_MEMSEL		0x00
+#define	CM_REGSEL		0x80	/* register/memory select */
+
+/* General IO pins configuration register - RW, 12 bits */
+#define	CFREG_GPIO_CONF			0x0004
+
+/* General IO pins control register - RW, 12 bits */
+#define	CFREG_GPIO_CTRL			0x0008
+
+/* Configuration status register - RO */
+#define	CFREG_STATUS			0x000c
+
+/* Memory clock configuration register - RW, needs 16 bits access */
+#define	CFREG_MEMCLK			0x0010
+#define	MEMCLK_DIVIDE		0x10
+#define	MEMCLK_SRC_CLKI		0x00
+#define	MEMCLK_SRC_BUSCLK	0x01
+#define	MEMCLK_SRC_CLK3		0x02
+
+/* LCD Pixel clock configuration register - RW */
+#define	CFREG_LCD_PCLK			0x0014
+#define	LCD_PCLK_SRC_CLKI	0x00
+#define	LCD_PCLK_SRC_BUSCLK	0x01
+#define	LCD_PCLK_SRC_CLKI2	0x02
+#define	LCD_PCLK_SRC_MCLK	0x03
+#define	LCD_PCLK_DIV_1		0x00
+#define	LCD_PCLK_DIV_2		0x10
+#define	LCD_PCLK_DIV_3		0x20
+#define	LCD_PCLK_DIV_4		0x30
+
+/* CRT/TV Pixel clock configuration register - RW */
+#define	CFREG_CRTTV_PCLK		0x0018
+#define	CRT_PCLK_SRC_CLKI	0x00
+#define	CRT_PCLK_SRC_BUSCLK	0x01
+#define	CRT_PCLK_SRC_CLKI2	0x02
+#define	CRT_PCLK_SRC_MCLK	0x03
+#define	CRT_PCLK_DIV_1		0x00
+#define	CRT_PCLK_DIV_2		0x10
+#define	CRT_PCLK_DIV_3		0x20
+#define	CRT_PCLK_DIV_4		0x30
+#define	CRT_PCLK_DOUBLE		0x80
+
+/* MediaPlug clock configuration register - RW */
+#define	CFREG_MPLUG_CLK			0x001c
+#define	MPLUG_PCLK_SRC_CLKI	0x00
+#define	MPLUG_PCLK_SRC_BUSCLK	0x01
+#define	MPLUG_PCLK_SRC_CLKI2	0x02
+#define	MPLUG_PCLK_SRC_MCLK	0x03
+#define	MPLUG_PCLK_DIV_1	0x00
+#define	MPLUG_PCLK_DIV_2	0x10
+#define	MPLUG_PCLK_DIV_3	0x20
+#define	MPLUG_PCLK_DIV_4	0x30
+
+/* CPU to memory wait state select register - RW */
+#define	CFREG_WSTATE			0x001e
+#define	WSTATE_NONE		0x00
+#define	WSTATE_DUAL_MCLK	0x01
+#define	WSTATE_MCLK		0x02
+
+/* Memory configuration register - RW */
+#define	CFREG_MEMCNF			0x0020
+#define	MEMCNF_SDRAM_INIT	0x80
+
+/* DRAM refresh rate register - RW */
+#define	CFREG_DRAM_RFRSH		0x0021
+#define	DRAM_RFRSH_8MHZ		0x00
+#define	DRAM_RFRSH_16MHZ	0x01
+#define	DRAM_RFRSH_32MHZ	0x02
+#define	DRAM_RFRSH_50MHZ	0x03
+
+/* DRAM timing control register - RW, 10 bits */
+#define	CFREG_DRAM_TIMING		0x002a
+#define	DRAM_TIMING_33MHZ	0x0311
+#define	DRAM_TIMING_44MHZ	0x0200
+#define	DRAM_TIMING_50MHZ	0x0100
+
+/* Panel type register - RW */
+#define	CFREG_PANEL			0x0030
+#define	PANEL_PASSIVE		0x00
+#define	PANEL_TFT		0x01
+#define	PANEL_SINGLE		0x00
+#define	PANEL_DUAL		0x02
+#define	PANEL_MONO		0x00
+#define	PANEL_COLOR		0x04
+#define	PANEL_FORMAT_1X		0x00
+#define	PANEL_FORMAT_2X		0x08
+#define	PANEL_WIDTH_4_9		0x00	/* passive: 4 bits, TDT: 9/2x9 bits */
+#define	PANEL_WIDTH_8_12	0x10	/* passive: 8 bits, TDT: 12/2x12 bits */
+#define	PANEL_WIDTH_16_18	0x20	/* passive: 16 bits, TDT: 18 bits */
+
+/* MOD rate register - RW */
+#define	CFREG_MODRATE			0x0031
+
+/* LCD horizontal display width register - RW */
+#define	CFREG_LCD_HWIDTH		0x0032
+
+/* LCD horizontal non-display period register - RW */
+#define	CFREG_LCD_HNDISP		0x0034
+
+/* TFT FPLINE start position register - RW */
+#define	CFREG_TFT_FPLINE_START		0x0035
+
+/* TFT FPLINE pulse width register - RW */
+#define	CFREG_TFT_FPLINE_WIDTH		0x0036
+#define	TFT_FPLINE_POL_TFT_LOW		0x00
+#define	TFT_FPLINE_POL_TFT_HIGH		0x80
+#define	TFT_FPLINE_POL_PASSIVE_LOW	0x80
+#define	TFT_FPLINE_POL_PASSIVE_HIGH	0x00
+
+/* LCD vertical display height - RW, 10 bits */
+#define	CFREG_LCD_VHEIGHT		0x0038
+
+/* LCD vertical non-display period register - RW */
+#define	CFREG_LCD_VNDISP		0x003a
+#define	CFREG_LCD_VNDP_STATUS	0x80			/* read only */
+
+/* TFT FPFRAME start position register - RW */
+#define	CFREG_TFT_FPFRAME_START		0x003b
+
+/* TFT FPFRAME pulse width register - RW */
+#define	CFREG_TFT_FPFRAME_WIDTH		0x003c
+#define	TFT_FPFRAME_POL_TFT_LOW		0x00
+#define	TFT_FPFRAME_POL_TFT_HIGH	0x80
+#define	TFT_FPFRAME_POL_PASSIVE_LOW	0x80
+#define	TFT_FPFRAME_POL_PASSIVE_HIGH	0x00
+
+/* LCD line count register - RO */
+#define	CFREG_LCD_LINECNT		0x003e
+
+/* LCD display mode register - RW */
+#define	CFREG_LCD_MODE			0x0040
+#define	LCD_MODE_4BPP		0x02
+#define	LCD_MODE_8BPP		0x03
+#define	LCD_MODE_15BPP		0x04
+#define	LCD_MODE_16BPP		0x05
+#define	LCD_MODE_SWIVEL_BIT1	0x10
+#define	LCD_MODE_BLANK		0x80
+
+/* LCD miscellaneous register - RW */
+#define	CFREG_LCD_MISC			0x0041
+#define	LCD_MISC_DUAL_PANEL_BUFFER_DISABLE	0x01
+#define	LCD_MISC_DITHERING_DISABLE		0x02
+
+/* LCD display start address - RW, 20 bits */
+#define	CFREG_LCD_START_LOW		0x0042
+#define	CFREG_LCD_START_HIGH		0x0044
+
+/* LCD memory address register - RW, 11 bits */
+#define	CFREG_LCD_MEMORY		0x0046
+
+/* LCD pixel panning register - RW */
+#define	CFREG_LCD_PANNING		0x0048
+#define	PIXEL_PANNING_MASK_4BPP			0x03
+#define	PIXEL_PANNING_MASK_8BPP			0x01
+#define	PIXEL_PANNING_MASK_15BPP		0x00
+
+/* LCD display FIFO high threshold control register - RW */
+#define	CFREG_LCD_FIFO_THRESHOLD_HIGH	0x004a
+
+/* LCD display FIFO low threshold control register - RW */
+#define	CFREG_LCD_FIFO_THRESHOLD_LOW	0x004b
+
+/* CRT/TV horizontal display width register - RW */
+#define	CFREG_CRT_HWIDTH		0x0050
+
+/* CRT/TV horizontal non-display period register - RW */
+#define	CFREG_CRT_HNDISP		0x0052
+
+/* CRT/TV HRTC start position register - RW */
+#define	CFREG_CRT_HSTART		0x0053
+
+/* CRT/TV HRTC pulse width register - RW */
+#define	CFREG_CRT_HPULSE		0x0054
+#define	HRTC_POLARITY		0x80
+
+/* CRT/TV vertical display height register - RW, 10 bits */
+#define	CFREG_CRT_VHEIGHT		0x0056
+
+/* CRT/TV vertical non-display period register - RW */
+#define	CFREG_CRT_VNDISP		0x0058
+#define	CFREG_CRT_VNDP_STATUS	0x80			/* RO */
+
+/* CRT/TV VRTC start position register - RW */
+#define	CFREG_CRT_VSTART		0x0059
+
+/* CRT VRTC pulse width register - RW */
+#define	CFREG_CRT_VPULSE		0x005a
+
+/* TV output control register - RW */
+#define	CFREG_TV_CONTROL		0x005b
+#define	TV_NTSC_OUTPUT		0x00
+#define	TV_PAL_OUTPUT		0x01
+#define	TV_COMPOSITE_OUTPUT	0x00
+#define	TV_SVIDEO_OUTPUT	0x02
+#define	TV_DAC_OUTPUT_HIGH	0x00	/* 9.2 mA IREF */
+#define	TV_DAC_OUTPUT_LOW	0x08	/* 4.6 mA IREF - CRT only */
+#define	TV_LUMINANCE_FILTER	0x10
+#define	TV_CHROMINANCE_FILTER	0x20
+
+/* CRT/TV line count register - RW */
+#define	CFREG_CRT_LINECNT		0x005e
+
+/* CRT/TV display mode register - RW */
+#define	CFREG_CRT_MODE			0x0060
+#define	CRT_MODE_4BPP		0x02
+#define	CRT_MODE_8BPP		0x03
+#define	CRT_MODE_15BPP		0x04
+#define	CRT_MODE_16BPP		0x05
+#define	CRT_MODE_BLANK		0x80
+
+/* CRT/TV display start address - RW, 20 bits */
+#define	CFREG_CRT_START_LOW		0x0062
+#define	CFREG_CRT_START_HIGH		0x0064
+
+/* CRT/TV memory address register - RW, 11 bits */
+#define	CFREG_CRT_MEMORY		0x0066
+
+/* CRT/TV pixel panning register - RW */
+#define	CFREG_CRT_PANNING		0x0068
+
+/* CRT/TV display FIFO high threshold control register - RW */
+#define	CFREG_CRT_FIFO_THRESHOLD_HIGH	0x006a
+
+/* CRT/TV display FIFO low threshold control register - RW */
+#define	CFREG_CRT_FIFO_THRESHOLD_LOW	0x006b
+
+/* LCD ink/cursor control register - RW */
+#define	CFREG_LCD_CURSOR_CONTROL	0x0070
+#define	CURSOR_INACTIVE		0x00
+#define	CURSOR_CURSOR		0x01
+#define	CURSOR_INK		0x02
+
+/* LCD ink/cursor start address register - RW */
+#define	CFREG_LCD_CURSOR_ADDRESS	0x0071
+
+/* LCD cursor X position register - RW, 10 bits + sign */
+#define	CFREG_LCD_CURSOR_X		0x0072
+#define	LCD_CURSOR_X_SIGN	0x8000
+
+/* LCD cursor Y position register - RW, 10 bits + sign */
+#define	CFREG_LCD_CURSOR_Y		0x0074
+#define	LCD_CURSOR_Y_SIGN	0x8000
+
+/* LCD ink/cursor color registers - RW */
+#define	CFREG_LCD_CURSOR_B0		0x0076	/* 5 bits */
+#define	CFREG_LCD_CURSOR_G0		0x0077	/* 6 bits */
+#define	CFREG_LCD_CURSOR_R0		0x0078	/* 5 bits */
+#define	CFREG_LCD_CURSOR_B1		0x007a	/* 5 bits */
+#define	CFREG_LCD_CURSOR_G1		0x007b	/* 6 bits */
+#define	CFREG_LCD_CURSOR_R1		0x007c	/* 5 bits */
+
+/* LCD ink/cursor FIFO threshold register - RW */
+#define	CFREG_LCD_CURSOR_FIFO		0x007e
+
+/* CRT/TV ink/cursor control register - RW */
+#define	CFREG_CRT_CURSOR_CONTROL	0x0080
+
+/* CRT/TV ink/cursor start address register - RW */
+#define	CFREG_CRT_CURSOR_ADDRESS	0x0081
+
+/* CRT/TV cursor X position register - RW, 10 bits + sign */
+#define	CFREG_CRT_CURSOR_X		0x0082
+#define	CRT_CURSOR_X_SIGN	0x8000
+
+/* CRT/TV cursor Y position register - RW, 10 bits + sign */
+#define	CFREG_CRT_CURSOR_Y		0x0084
+#define	CRT_CURSOR_Y_SIGN	0x8000
+
+/* CRT/TV ink/cursor color registers - RW */
+#define	CFREG_CRT_CURSOR_B0		0x0086	/* 5 bits */
+#define	CFREG_CRT_CURSOR_G0		0x0087	/* 6 bits */
+#define	CFREG_CRT_CURSOR_R0		0x0088	/* 5 bits */
+#define	CFREG_CRT_CURSOR_B1		0x008a	/* 5 bits */
+#define	CFREG_CRT_CURSOR_G1		0x008b	/* 6 bits */
+#define	CFREG_CRT_CURSOR_R1		0x008c	/* 5 bits */
+
+/* CRT/TV ink/cursor FIFO threshold register - RW */
+#define	CFREG_CRT_CURSOR_FIFO		0x008e
+
+/* Bitblt control register - RW, 16 bits */
+#define	CFREG_BITBLT_CONTROL		0x0100
+#define	BITBLT_SRC_LINEAR	0x0001
+#define	BITBLT_DST_LINEAR	0x0002
+#define	BITBLT_FIFO_FULL	0x0010			/* RO */
+#define	BITBLT_FIFO_HALF_FULL	0x0020			/* RO */
+#define	BITBLT_FIFO_NOT_EMPTY	0x0040			/* RO */
+#define	BITBLT_ACTIVE		0x0080
+#define	BITBLT_COLOR_8		0x0000
+#define	BITBLT_COLOR_16		0x0100
+
+/* Bitblt ROP code / color expansion register - RW */
+#define	CFREG_BITBLT_ROP		0x0102
+#define	CFREG_COLOR_EXPANSION		0x0102
+#define	ROP_ZERO		0x00
+#define	ROP_DST			0x0a
+#define	ROP_SRC			0x0c
+#define	ROP_ONES		0x0f
+
+/* Bitblt operation register - RW */
+#define	CFREG_BITBLT_OPERATION		0x103
+#define	OP_WRITE_ROP				0x00
+#define	OP_READ					0x01
+#define	OP_MOVE_POSITIVE_ROP			0x02
+#define	OP_MOVE_NEGATIVE_ROP			0x03
+#define	OP_TRANSPARENT_WRITE			0x04
+#define	OP_TRANSPARENT_MOVE_POSITIVE		0x05
+#define	OP_PATTERN_FILL_ROP			0x06
+#define	OP_PATTERN_FILL_TRANSPARENCY		0x07
+#define	OP_COLOR_EXPANSION			0x08
+#define	OP_COLOR_EXPANSION_TRANSPARENCY		0x09
+#define	OP_MOVE_COLOR_EXPANSION			0x0a
+#define	OP_MOVE_COLOR_EXPANSION_TRANSPARENCY	0x0b
+#define	OP_SOLID_FILL				0x0c
+
+/* Bitblt source address register - RW, 21 bits */
+#define	CFREG_BITBLT_SRC_LOW		0x104
+#define	CFREG_BITBLT_SRC_HIGH		0x106
+
+/* Bitblt destination start address register - RW, 21 bits */
+#define	CFREG_BITBLT_DST_LOW		0x108
+#define	CFREG_BITBLT_DST_HIGH		0x10a
+
+/* Bitblt memory address offset register - RW, 11 bits */
+#define	CFREG_BITBLT_OFFSET		0x10c
+
+/* Bitblt width register - RW, 10 bits */
+#define	CFREG_BITBLT_WIDTH		0x110
+
+/* Bitblt height register - RW, 10 bits */
+#define	CFREG_BITBLT_HEIGHT		0x112
+
+/* Bitblt color registers - RW, 16 bits */
+#define	CFREG_BITBLT_BG			0x114
+#define	CFREG_BITBLT_FG			0x118
+
+/* Lookup table mode register - RW */
+#define	CFREG_LUT_MODE			0x1e0
+#define	LUT_BOTH		0x00	/* read LCD, write LCD and CRT/TV */
+#define	LUT_LCD			0x01	/* read LCD, write LCD */
+#define	LUT_CRT			0x02	/* read CRT/TV, write CRT/TV */
+
+/* LUT address register - RW */
+#define	CFREG_LUT_ADDRESS		0x1e2
+
+/* LUT data register - RW */
+#define	CFREG_LUT_DATA			0x1e4	/* data in the high 4 bits */
+
+/* Power save configuration register - RW */
+#define	CFREG_POWER_CONF		0x1f0
+#define	POWERSAVE_ENABLE	0x01
+
+/* Power save status register - RW */
+#define	CFREG_POWER_STATUS		0x1f1
+#define	POWERSAVE_STATUS	0x01
+#define	LCD_POWERSAVE_STATUS	0x02
+
+/* CPU to memory access watchdog timer register - RW */
+#define	CFREG_WATCHDOG			0x1f4
+
+/* Display mode register - RW */
+#define	CFREG_MODE			0x1fc
+#define	MODE_NO_DISPLAY		0x00
+#define	MODE_LCD		0x01	/* can be combined with all modes */
+#define	MODE_CRT		0x02
+#define	MODE_TV_NO_FLICKER	0x04
+#define	MODE_TV_FLICKER		0x06
+#define	LCD_MODE_SWIVEL_BIT_0	0x40
+
+#define	CFREG_BITBLT_DATA		0x0400
 
 #ifdef	_KERNEL
 #define	CFXGA_MEM_RANGE		0x0800