registred -> registered

2 files changed, 5 insertions, 5 deletions

diff --git a/sys/arch/mips64/mips64/interrupt.c b/sys/arch/mips64/mips64/interrupt.c
index 79b27137d88..5f8abe02a6e 100644
--- a/sys/arch/mips64/mips64/interrupt.c
+++ b/sys/arch/mips64/mips64/interrupt.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: interrupt.c,v 1.31 2007/07/16 20:20:08 miod Exp $ */
+/*	$OpenBSD: interrupt.c,v 1.32 2007/10/14 18:52:10 miod Exp $ */
 
 /*
  * Copyright (c) 2001-2004 Opsycon AB  (www.opsycon.se / www.opsycon.com)
@@ -89,7 +89,7 @@ int netisr;
  *  Basically there are <n> interrupt inputs to the processor and
  *  typically the HW designer ties these interrupts to various
  *  sources in the HW. The low level code does not deal with interrupts
- *  in more than it dispatches handling to the code that has registred
+ *  in more than it dispatches handling to the code that has registered
  *  an interrupt handler for that particular interrupt. More than one
  *  handler can register to an interrupt input and one handler may register
  *  for more than one interrupt input. A handler is only called once even
@@ -132,7 +132,7 @@ void softintr(void);
  * Handle an interrupt. Both kernel and user mode is handled here.
  *
  * The interrupt handler is called with the CR_INT bits set that
- * was given when the handlers was registred that needs servicing.
+ * was given when the handlers was registered that needs servicing.
  * The handler should return a similar word with a mask indicating
  * which CR_INT bits that has been served.
  */
diff --git a/sys/arch/sgi/include/intr.h b/sys/arch/sgi/include/intr.h
index 16c3de6d5f7..9550d125a21 100644
--- a/sys/arch/sgi/include/intr.h
+++ b/sys/arch/sgi/include/intr.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: intr.h,v 1.18 2007/06/20 16:50:41 miod Exp $ */
+/*	$OpenBSD: intr.h,v 1.19 2007/10/14 18:52:11 miod Exp $ */
 
 /*
  * Copyright (c) 2001-2004 Opsycon AB  (www.opsycon.se / www.opsycon.com)
@@ -41,7 +41,7 @@
  *  The IMASK_EXTERNAL define is used to select whether the CPU
  *  interrupt mask should be controlled by the cpl mask value
  *  or not. If the mask is external, the CPU mask is never changed
- *  from the value it gets when interrupt dispatchers are registred.
+ *  from the value it gets when interrupt dispatchers are registered.
  *  When an external masking register is used dedicated interrupt
  *  handlers must be written as well as ipending handlers.
  */