destatic radeondrm almost completely. I'm sick of ddb lying to me.

shaves a few bytes, but that's just gravy.

3 files changed, 290 insertions, 149 deletions

diff --git a/sys/dev/pci/drm/radeon_cp.c b/sys/dev/pci/drm/radeon_cp.c
index b22a2ad9336..d993d79151d 100644
--- a/sys/dev/pci/drm/radeon_cp.c
+++ b/sys/dev/pci/drm/radeon_cp.c
@@ -38,10 +38,43 @@
 #include "radeon_microcode.h"
 #define RADEON_FIFO_DEBUG	0
 
-static int radeon_do_cleanup_cp(struct drm_device * dev);
-static void radeon_do_cp_start(drm_radeon_private_t * dev_priv);
-
-static u32 R500_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
+int	radeon_do_cleanup_cp(struct drm_device *);
+void	radeon_do_cp_start(drm_radeon_private_t *);
+void	radeon_do_cp_reset(drm_radeon_private_t *);
+void	radeon_do_cp_stop(drm_radeon_private_t *);
+void	radeon_do_cp_flush(drm_radeon_private_t * dev_priv);
+int	radeon_do_engine_reset(struct drm_device *);
+void	radeon_cp_init_ring_buffer(struct drm_device *, drm_radeon_private_t *);
+int	radeon_do_init_cp(struct drm_device *, drm_radeon_init_t *);
+int	radeon_do_resume_cp(struct drm_device *);
+void	radeon_cp_load_microcode(drm_radeon_private_t *);
+int	radeon_cp_get_buffers(struct drm_device *dev, struct drm_file *,
+	    struct drm_dma *);
+
+u32	R500_READ_MCIND(drm_radeon_private_t *, int );
+u32	RS480_READ_MCIND(drm_radeon_private_t *, int);
+u32	RS690_READ_MCIND(drm_radeon_private_t *, int);
+u32	IGP_READ_MCIND(drm_radeon_private_t *, int);
+u32	radeon_read_fb_location(drm_radeon_private_t *);
+void	radeon_write_fb_location(drm_radeon_private_t *, u32);
+void	radeon_write_fb_location(drm_radeon_private_t *, u32);
+void	radeon_write_agp_location(drm_radeon_private_t *, u32);
+void	radeon_write_agp_base(drm_radeon_private_t *, u64);
+int	RADEON_READ_PLL(struct drm_device * , int);
+u32	RADEON_READ_PCIE(drm_radeon_private_t *, int);
+
+int	radeon_do_pixcache_flush(drm_radeon_private_t *);
+int	radeon_do_wait_for_fifo(drm_radeon_private_t *, int);
+int	radeon_do_wait_for_idle(drm_radeon_private_t *);
+void	radeon_init_pipes(drm_radeon_private_t *);
+void	radeon_test_writeback(drm_radeon_private_t *);
+void	radeon_set_igpgart(drm_radeon_private_t *, int);
+void	radeon_set_pciegart(drm_radeon_private_t *, int);
+void	radeon_set_pcigart(drm_radeon_private_t *, int);
+
+
+u32
+R500_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
 {
 	u32 ret;
 	RADEON_WRITE(R520_MC_IND_INDEX, 0x7f0000 | (addr & 0xff));
@@ -50,7 +83,8 @@ static u32 R500_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
 	return ret;
 }
 
-static u32 RS480_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
+u32
+RS480_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
 {
 	u32 ret;
 	RADEON_WRITE(RS480_NB_MC_INDEX, addr & 0xff);
@@ -59,7 +93,8 @@ static u32 RS480_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
 	return ret;
 }
 
-static u32 RS690_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
+u32
+RS690_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
 {
 	u32 ret;
 	RADEON_WRITE(RS690_MC_INDEX, (addr & RS690_MC_INDEX_MASK));
@@ -68,7 +103,8 @@ static u32 RS690_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
 	return ret;
 }
 
-static u32 IGP_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
+u32
+IGP_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
 {
         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
 	    return RS690_READ_MCIND(dev_priv, addr);
@@ -76,7 +112,8 @@ static u32 IGP_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
 	    return RS480_READ_MCIND(dev_priv, addr);
 }
 
-u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv)
+u32
+radeon_read_fb_location(drm_radeon_private_t *dev_priv)
 {
 
 	if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
@@ -89,7 +126,8 @@ u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv)
 		return RADEON_READ(RADEON_MC_FB_LOCATION);
 }
 
-static void radeon_write_fb_location(drm_radeon_private_t *dev_priv, u32 fb_loc)
+void
+radeon_write_fb_location(drm_radeon_private_t *dev_priv, u32 fb_loc)
 {
 	if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
 		R500_WRITE_MCIND(RV515_MC_FB_LOCATION, fb_loc);
@@ -101,7 +139,8 @@ static void radeon_write_fb_location(drm_radeon_private_t *dev_priv, u32 fb_loc)
 		RADEON_WRITE(RADEON_MC_FB_LOCATION, fb_loc);
 }
 
-static void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_loc)
+void
+radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_loc)
 {
 	if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
 		R500_WRITE_MCIND(RV515_MC_AGP_LOCATION, agp_loc);
@@ -113,7 +152,8 @@ static void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_lo
 		RADEON_WRITE(RADEON_MC_AGP_LOCATION, agp_loc);
 }
 
-static void radeon_write_agp_base(drm_radeon_private_t *dev_priv, u64 agp_base)
+void
+radeon_write_agp_base(drm_radeon_private_t *dev_priv, u64 agp_base)
 {
 	u32 agp_base_hi = upper_32_bits(agp_base);
 	u32 agp_base_lo = agp_base & 0xffffffff;
@@ -138,7 +178,8 @@ static void radeon_write_agp_base(drm_radeon_private_t *dev_priv, u64 agp_base)
 	}
 }
 
-static int RADEON_READ_PLL(struct drm_device * dev, int addr)
+int
+RADEON_READ_PLL(struct drm_device *dev, int addr)
 {
 	drm_radeon_private_t *dev_priv = dev->dev_private;
 
@@ -146,14 +187,16 @@ static int RADEON_READ_PLL(struct drm_device * dev, int addr)
 	return RADEON_READ(RADEON_CLOCK_CNTL_DATA);
 }
 
-static u32 RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr)
+u32
+RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr)
 {
 	RADEON_WRITE8(RADEON_PCIE_INDEX, addr & 0xff);
 	return RADEON_READ(RADEON_PCIE_DATA);
 }
 
 #if RADEON_FIFO_DEBUG
-static void radeon_status(drm_radeon_private_t * dev_priv)
+static void
+radeon_status(drm_radeon_private_t *dev_priv)
 {
 	printk("%s:\n", __FUNCTION__);
 	printk("RBBM_STATUS = 0x%08x\n",
@@ -179,7 +222,8 @@ static void radeon_status(drm_radeon_private_t * dev_priv)
  * Engine, FIFO control
  */
 
-static int radeon_do_pixcache_flush(drm_radeon_private_t * dev_priv)
+int
+radeon_do_pixcache_flush(drm_radeon_private_t *dev_priv)
 {
 	u32 tmp;
 	int i;
@@ -210,7 +254,8 @@ static int radeon_do_pixcache_flush(drm_radeon_private_t * dev_priv)
 	return EBUSY;
 }
 
-static int radeon_do_wait_for_fifo(drm_radeon_private_t * dev_priv, int entries)
+int
+radeon_do_wait_for_fifo(drm_radeon_private_t *dev_priv, int entries)
 {
 	int i;
 
@@ -234,7 +279,8 @@ static int radeon_do_wait_for_fifo(drm_radeon_private_t * dev_priv, int entries)
 	return EBUSY;
 }
 
-static int radeon_do_wait_for_idle(drm_radeon_private_t * dev_priv)
+int
+radeon_do_wait_for_idle(drm_radeon_private_t *dev_priv)
 {
 	int i, ret;
 
@@ -263,7 +309,8 @@ static int radeon_do_wait_for_idle(drm_radeon_private_t * dev_priv)
 	return EBUSY;
 }
 
-static void radeon_init_pipes(drm_radeon_private_t * dev_priv)
+void
+radeon_init_pipes(drm_radeon_private_t *dev_priv)
 {
 	uint32_t gb_tile_config, gb_pipe_sel = 0;
 
@@ -312,7 +359,8 @@ static void radeon_init_pipes(drm_radeon_private_t * dev_priv)
  */
 
 /* Load the microcode for the CP */
-static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv)
+void
+radeon_cp_load_microcode(drm_radeon_private_t *dev_priv)
 {
 	int i;
 	DRM_DEBUG("\n");
@@ -395,7 +443,8 @@ static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv)
  * prior to a wait for idle, as it informs the engine that the command
  * stream is ending.
  */
-static void radeon_do_cp_flush(drm_radeon_private_t * dev_priv)
+void
+radeon_do_cp_flush(drm_radeon_private_t *dev_priv)
 {
 	DRM_DEBUG("\n");
 #if 0
@@ -408,7 +457,8 @@ static void radeon_do_cp_flush(drm_radeon_private_t * dev_priv)
 
 /* Wait for the CP to go idle.
  */
-int radeon_do_cp_idle(drm_radeon_private_t * dev_priv)
+int
+radeon_do_cp_idle(drm_radeon_private_t *dev_priv)
 {
 	RING_LOCALS;
 	DRM_DEBUG("\n");
@@ -427,7 +477,8 @@ int radeon_do_cp_idle(drm_radeon_private_t * dev_priv)
 
 /* Start the Command Processor.
  */
-static void radeon_do_cp_start(drm_radeon_private_t * dev_priv)
+void
+radeon_do_cp_start(drm_radeon_private_t *dev_priv)
 {
 	RING_LOCALS;
 	DRM_DEBUG("\n");
@@ -458,7 +509,8 @@ static void radeon_do_cp_start(drm_radeon_private_t * dev_priv)
  * commands, so you must wait for the CP command stream to complete
  * before calling this routine.
  */
-static void radeon_do_cp_reset(drm_radeon_private_t * dev_priv)
+void
+radeon_do_cp_reset(drm_radeon_private_t *dev_priv)
 {
 	u32 cur_read_ptr;
 	DRM_DEBUG("\n");
@@ -473,7 +525,8 @@ static void radeon_do_cp_reset(drm_radeon_private_t * dev_priv)
  * commands, so you must flush the command stream and wait for the CP
  * to go idle before calling this routine.
  */
-static void radeon_do_cp_stop(drm_radeon_private_t * dev_priv)
+void
+radeon_do_cp_stop(drm_radeon_private_t *dev_priv)
 {
 	DRM_DEBUG("\n");
 
@@ -484,7 +537,8 @@ static void radeon_do_cp_stop(drm_radeon_private_t * dev_priv)
 
 /* Reset the engine.  This will stop the CP if it is running.
  */
-static int radeon_do_engine_reset(struct drm_device * dev)
+int
+radeon_do_engine_reset(struct drm_device *dev)
 {
 	drm_radeon_private_t *dev_priv = dev->dev_private;
 	u32 clock_cntl_index = 0, mclk_cntl = 0, rbbm_soft_reset;
@@ -549,8 +603,9 @@ static int radeon_do_engine_reset(struct drm_device * dev)
 	return 0;
 }
 
-static void radeon_cp_init_ring_buffer(struct drm_device * dev,
-				       drm_radeon_private_t * dev_priv)
+void
+radeon_cp_init_ring_buffer(struct drm_device *dev,
+    drm_radeon_private_t *dev_priv)
 {
 	u32 ring_start, cur_read_ptr;
 	u32 tmp;
@@ -697,7 +752,8 @@ static void radeon_cp_init_ring_buffer(struct drm_device * dev,
 
 }
 
-static void radeon_test_writeback(drm_radeon_private_t * dev_priv)
+void
+radeon_test_writeback(drm_radeon_private_t *dev_priv)
 {
 	u32 tmp;
 
@@ -734,7 +790,8 @@ static void radeon_test_writeback(drm_radeon_private_t * dev_priv)
 }
 
 /* Enable or disable IGP GART on the chip */
-static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on)
+void
+radeon_set_igpgart(drm_radeon_private_t *dev_priv, int on)
 {
 	u32 temp;
 
@@ -804,7 +861,8 @@ static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on)
 	}
 }
 
-static void radeon_set_pciegart(drm_radeon_private_t * dev_priv, int on)
+void
+radeon_set_pciegart(drm_radeon_private_t *dev_priv, int on)
 {
 	u32 tmp = RADEON_READ_PCIE(dev_priv, RADEON_PCIE_TX_GART_CNTL);
 	if (on) {
@@ -834,7 +892,8 @@ static void radeon_set_pciegart(drm_radeon_private_t * dev_priv, int on)
 }
 
 /* Enable or disable PCI GART on the chip */
-static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on)
+void
+radeon_set_pcigart(drm_radeon_private_t *dev_priv, int on)
 {
 	u32 tmp;
 
@@ -875,7 +934,8 @@ static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on)
 	}
 }
 
-static int radeon_do_init_cp(struct drm_device * dev, drm_radeon_init_t * init)
+int
+radeon_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init)
 {
 	drm_radeon_private_t *dev_priv = dev->dev_private;
 
@@ -1225,7 +1285,8 @@ static int radeon_do_init_cp(struct drm_device * dev, drm_radeon_init_t * init)
 	return 0;
 }
 
-static int radeon_do_cleanup_cp(struct drm_device * dev)
+int
+radeon_do_cleanup_cp(struct drm_device *dev)
 {
 	drm_radeon_private_t *dev_priv = dev->dev_private;
 	DRM_DEBUG("\n");
@@ -1279,7 +1340,8 @@ static int radeon_do_cleanup_cp(struct drm_device * dev)
  *
  * Charl P. Botha <http://cpbotha.net>
  */
-static int radeon_do_resume_cp(struct drm_device * dev)
+int
+radeon_do_resume_cp(struct drm_device *dev)
 {
 	drm_radeon_private_t *dev_priv = dev->dev_private;
 
@@ -1312,7 +1374,8 @@ static int radeon_do_resume_cp(struct drm_device * dev)
 	return 0;
 }
 
-int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_priv)
+int
+radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_priv)
 {
 	drm_radeon_init_t *init = data;
 
@@ -1333,7 +1396,8 @@ int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_pri
 	return EINVAL;
 }
 
-int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_priv)
+int
+radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_priv)
 {
 	drm_radeon_private_t *dev_priv = dev->dev_private;
 	DRM_DEBUG("\n");
@@ -1358,7 +1422,8 @@ int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_pr
 /* Stop the CP.  The engine must have been idled before calling this
  * routine.
  */
-int radeon_cp_stop(struct drm_device *dev, void *data, struct drm_file *file_priv)
+int
+radeon_cp_stop(struct drm_device *dev, void *data, struct drm_file *file_priv)
 {
 	drm_radeon_private_t *dev_priv = dev->dev_private;
 	drm_radeon_cp_stop_t *stop = data;
@@ -1398,7 +1463,8 @@ int radeon_cp_stop(struct drm_device *dev, void *data, struct drm_file *file_pri
 	return 0;
 }
 
-void radeon_do_release(struct drm_device * dev)
+void
+radeon_do_release(struct drm_device *dev)
 {
 	drm_radeon_private_t *dev_priv = dev->dev_private;
 	int i, ret;
@@ -1446,7 +1512,8 @@ void radeon_do_release(struct drm_device * dev)
 
 /* Just reset the CP ring.  Called as part of an X Server engine reset.
  */
-int radeon_cp_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
+int
+radeon_cp_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
 {
 	drm_radeon_private_t *dev_priv = dev->dev_private;
 	DRM_DEBUG("\n");
@@ -1466,7 +1533,8 @@ int radeon_cp_reset(struct drm_device *dev, void *data, struct drm_file *file_pr
 	return 0;
 }
 
-int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_priv)
+int
+radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_priv)
 {
 	drm_radeon_private_t *dev_priv = dev->dev_private;
 	DRM_DEBUG("\n");
@@ -1478,13 +1546,16 @@ int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_pri
 
 /* Added by Charl P. Botha to call radeon_do_resume_cp().
  */
-int radeon_cp_resume(struct drm_device *dev, void *data, struct drm_file *file_priv)
+int
+radeon_cp_resume(struct drm_device *dev, void *data, struct drm_file *file_priv)
 {
 
 	return radeon_do_resume_cp(dev);
 }
 
-int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
+int
+radeon_engine_reset(struct drm_device *dev, void *data,
+    struct drm_file *file_priv)
 {
 	DRM_DEBUG("\n");
 
@@ -1499,7 +1570,9 @@ int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_file *fil
 
 /* KW: Deprecated to say the least:
  */
-int radeon_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv)
+int
+radeon_fullscreen(struct drm_device *dev, void *data,
+    struct drm_file *file_priv)
 {
 	return 0;
 }
@@ -1525,7 +1598,8 @@ int radeon_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_
  * they can't get the lock.
  */
 
-struct drm_buf *radeon_freelist_get(struct drm_device * dev)
+struct drm_buf *
+radeon_freelist_get(struct drm_device *dev)
 {
 	struct drm_device_dma *dma = dev->dma;
 	drm_radeon_private_t *dev_priv = dev->dev_private;
@@ -1601,7 +1675,8 @@ struct drm_buf *radeon_freelist_get(struct drm_device * dev)
 }
 #endif
 
-void radeon_freelist_reset(struct drm_device * dev)
+void
+radeon_freelist_reset(struct drm_device *dev)
 {
 	struct drm_device_dma *dma = dev->dma;
 	drm_radeon_private_t *dev_priv = dev->dev_private;
@@ -1619,7 +1694,8 @@ void radeon_freelist_reset(struct drm_device * dev)
  * CP command submission
  */
 
-int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n)
+int
+radeon_wait_ring(drm_radeon_private_t *dev_priv, int n)
 {
 	drm_radeon_ring_buffer_t *ring = &dev_priv->ring;
 	int i;
@@ -1651,9 +1727,9 @@ int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n)
 	return EBUSY;
 }
 
-static int radeon_cp_get_buffers(struct drm_device *dev,
-				 struct drm_file *file_priv,
-				 struct drm_dma * d)
+int
+radeon_cp_get_buffers(struct drm_device *dev, struct drm_file *file_priv,
+    struct drm_dma * d)
 {
 	int i;
 	struct drm_buf *buf;
@@ -1677,7 +1753,9 @@ static int radeon_cp_get_buffers(struct drm_device *dev,
 	return 0;
 }
 
-int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv)
+int
+radeon_cp_buffers(struct drm_device *dev, void *data,
+    struct drm_file *file_priv)
 {
 	struct drm_device_dma *dma = dev->dma;
 	int ret = 0;
@@ -1713,7 +1791,8 @@ int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_
 /* Create mappings for registers and framebuffer so userland doesn't necessarily
  * have to find them.
  */
-int radeon_driver_firstopen(struct drm_device *dev)
+int
+radeon_driver_firstopen(struct drm_device *dev)
 {
 	int ret;
 	drm_local_map_t *map;
diff --git a/sys/dev/pci/drm/radeon_irq.c b/sys/dev/pci/drm/radeon_irq.c
index 895de9c2082..ac129f0bbf0 100644
--- a/sys/dev/pci/drm/radeon_irq.c
+++ b/sys/dev/pci/drm/radeon_irq.c
@@ -35,7 +35,13 @@
 #include "radeon_drm.h"
 #include "radeon_drv.h"
 
-void radeon_irq_set_state(struct drm_device *dev, u32 mask, int state)
+void	r500_vbl_irq_set_state(struct drm_device *, u32, int);
+u_int32_t	radeon_acknowledge_irqs(drm_radeon_private_t *, u32 *);
+int	radeon_emit_irq(struct drm_device *);
+int	radeon_wait_irq(struct drm_device *, int);
+
+void
+radeon_irq_set_state(struct drm_device *dev, u32 mask, int state)
 {
 	drm_radeon_private_t *dev_priv = dev->dev_private;
 
@@ -47,7 +53,8 @@ void radeon_irq_set_state(struct drm_device *dev, u32 mask, int state)
 	RADEON_WRITE(RADEON_GEN_INT_CNTL, dev_priv->irq_enable_reg);
 }
 
-static void r500_vbl_irq_set_state(struct drm_device *dev, u32 mask, int state)
+void
+r500_vbl_irq_set_state(struct drm_device *dev, u32 mask, int state)
 {
 	drm_radeon_private_t *dev_priv = dev->dev_private;
 
@@ -127,7 +134,8 @@ void radeon_disable_vblank(struct drm_device *dev, int crtc)
 	}
 }
 
-static __inline__ u32 radeon_acknowledge_irqs(drm_radeon_private_t * dev_priv, u32 *r500_disp_int)
+u_int32_t
+radeon_acknowledge_irqs(drm_radeon_private_t *dev_priv, u32 *r500_disp_int)
 {
 	u32 irqs = RADEON_READ(RADEON_GEN_INT_STATUS);
 	u32 irq_mask = RADEON_SW_INT_TEST;
@@ -216,7 +224,8 @@ irqreturn_t radeon_driver_irq_handler(DRM_IRQ_ARGS)
 	return IRQ_HANDLED;
 }
 
-static int radeon_emit_irq(struct drm_device * dev)
+int
+radeon_emit_irq(struct drm_device * dev)
 {
 	drm_radeon_private_t *dev_priv = dev->dev_private;
 	unsigned int ret;
@@ -234,7 +243,8 @@ static int radeon_emit_irq(struct drm_device * dev)
 	return ret;
 }
 
-static int radeon_wait_irq(struct drm_device * dev, int swi_nr)
+int
+radeon_wait_irq(struct drm_device * dev, int swi_nr)
 {
 	drm_radeon_private_t *dev_priv =
 	    (drm_radeon_private_t *) dev->dev_private;
diff --git a/sys/dev/pci/drm/radeon_state.c b/sys/dev/pci/drm/radeon_state.c
index d5df6daf571..678c9316bc7 100644
--- a/sys/dev/pci/drm/radeon_state.c
+++ b/sys/dev/pci/drm/radeon_state.c
@@ -33,14 +33,72 @@
 #include "radeon_drm.h"
 #include "radeon_drv.h"
 
+typedef struct {
+	unsigned int start;
+	unsigned int finish;
+	unsigned int prim;
+	unsigned int numverts;
+	unsigned int offset;
+	unsigned int vc_format;
+} drm_radeon_tcl_prim_t;
+
+int	radeon_check_and_fixup_offset(drm_radeon_private_t *, struct drm_file *,
+	    u32 *);
+int	radeon_check_and_fixup_packets(drm_radeon_private_t *,
+	    struct drm_file *, int, u32 *);
+int	radeon_check_and_fixup_packet3(drm_radeon_private_t *,
+	    struct drm_file *, drm_radeon_kcmd_buffer_t *, unsigned int *);
+void	radeon_emit_clip_rect(drm_radeon_private_t *, struct drm_clip_rect *);
+int	radeon_emit_state(drm_radeon_private_t *, struct drm_file *,
+	    drm_radeon_context_regs_t *, drm_radeon_texture_regs_t *,
+	    unsigned int);
+int	radeon_emit_state2(drm_radeon_private_t *, struct drm_file *,
+	    drm_radeon_state_t *);
+void	radeon_clear_box(drm_radeon_private_t *, int, int, int, int,
+	    int, int, int);
+void	radeon_cp_performance_boxes(drm_radeon_private_t *);
+void	radeon_cp_dispatch_clear(struct drm_device *, drm_radeon_clear_t *,
+	    drm_radeon_clear_rect_t *);
+void	radeon_cp_dispatch_swap(struct drm_device *);
+void	radeon_cp_dispatch_flip(struct drm_device *);
+int	bad_prim_vertex_nr(int, int);
+void	radeon_cp_dispatch_vertex(struct drm_device *, struct drm_buf *,
+	    drm_radeon_tcl_prim_t *);
+void	radeon_cp_discard_buffer(struct drm_device *, struct drm_buf *);
+void	radeon_cp_dispatch_indirect(struct drm_device *, struct drm_buf *,
+	    int, int);
+void	radeon_cp_dispatch_indices(struct drm_device *, struct drm_buf *,
+	    drm_radeon_tcl_prim_t *);
+int	radeon_cp_dispatch_texture(struct drm_device *, struct drm_file *,
+	    drm_radeon_texture_t *, drm_radeon_tex_image_t *);
+void	radeon_cp_dispatch_stipple(struct drm_device *, u32 *);
+int	radeon_emit_wait(struct drm_device *, int);
+void	radeon_apply_surface_regs(int, drm_radeon_private_t *);
+int	alloc_surface(drm_radeon_surface_alloc_t *, drm_radeon_private_t *,
+	    struct drm_file *);
+int	free_surface(struct drm_file *, drm_radeon_private_t *, int);
+void	radeon_surfaces_release(struct drm_file *, drm_radeon_private_t *);
+int	radeon_do_init_pageflip(struct drm_device *);
+int	radeon_emit_packets(drm_radeon_private_t *, struct drm_file *,
+	    drm_radeon_cmd_header_t, drm_radeon_kcmd_buffer_t *);
+int	radeon_emit_scalars(drm_radeon_private_t *, drm_radeon_cmd_header_t,
+	    drm_radeon_kcmd_buffer_t *);
+int	radeon_emit_scalars2(drm_radeon_private_t *, drm_radeon_cmd_header_t,
+	    drm_radeon_kcmd_buffer_t *);
+int	radeon_emit_vectors(drm_radeon_private_t *, drm_radeon_cmd_header_t,
+	    drm_radeon_kcmd_buffer_t *);
+int	radeon_emit_veclinear(drm_radeon_private_t *, drm_radeon_cmd_header_t,
+	    drm_radeon_kcmd_buffer_t *);
+int	radeon_emit_packet3(struct drm_device *, struct drm_file *,
+	    drm_radeon_kcmd_buffer_t *);
+int	radeon_emit_packet3_cliprect(struct drm_device *, struct drm_file *,
+	    drm_radeon_kcmd_buffer_t *, int);
 /* ================================================================
  * Helper functions for client state checking and fixup
  */
 
-static __inline__ int radeon_check_and_fixup_offset(drm_radeon_private_t *
-						    dev_priv,
-						    struct drm_file *file_priv,
-						    u32 * offset)
+int radeon_check_and_fixup_offset(drm_radeon_private_t *dev_priv,
+    struct drm_file *file_priv, u32 *offset)
 {
 	u64 off = *offset;
 	u32 fb_end = dev_priv->fb_location + dev_priv->fb_size - 1;
@@ -88,10 +146,9 @@ static __inline__ int radeon_check_and_fixup_offset(drm_radeon_private_t *
 	return EINVAL;
 }
 
-static __inline__ int radeon_check_and_fixup_packets(drm_radeon_private_t *
-						     dev_priv,
-						     struct drm_file *file_priv,
-						     int id, u32 *data)
+int
+radeon_check_and_fixup_packets(drm_radeon_private_t *dev_priv,
+    struct drm_file *file_priv, int id, u32 *data)
 {
 	switch (id) {
 
@@ -262,12 +319,10 @@ static __inline__ int radeon_check_and_fixup_packets(drm_radeon_private_t *
 	return 0;
 }
 
-static __inline__ int radeon_check_and_fixup_packet3(drm_radeon_private_t *
-						     dev_priv,
-						     struct drm_file *file_priv,
-						     drm_radeon_kcmd_buffer_t *
-						     cmdbuf,
-						     unsigned int *cmdsz)
+int
+radeon_check_and_fixup_packet3(drm_radeon_private_t *dev_priv,
+    struct drm_file *file_priv, drm_radeon_kcmd_buffer_t *cmdbuf,
+    unsigned int *cmdsz)
 {
 	u32 *cmd = (u32 *) cmdbuf->buf;
 	u32 offset, narrays;
@@ -426,8 +481,8 @@ static __inline__ int radeon_check_and_fixup_packet3(drm_radeon_private_t *
  * CP hardware state programming functions
  */
 
-static __inline__ void radeon_emit_clip_rect(drm_radeon_private_t * dev_priv,
-					     struct drm_clip_rect * box)
+void
+radeon_emit_clip_rect(drm_radeon_private_t *dev_priv, struct drm_clip_rect *box)
 {
 	RING_LOCALS;
 
@@ -444,11 +499,10 @@ static __inline__ void radeon_emit_clip_rect(drm_radeon_private_t * dev_priv,
 
 /* Emit 1.1 state
  */
-static int radeon_emit_state(drm_radeon_private_t * dev_priv,
-			     struct drm_file *file_priv,
-			     drm_radeon_context_regs_t * ctx,
-			     drm_radeon_texture_regs_t * tex,
-			     unsigned int dirty)
+int
+radeon_emit_state(drm_radeon_private_t * dev_priv, struct drm_file *file_priv,
+    drm_radeon_context_regs_t * ctx, drm_radeon_texture_regs_t * tex,
+    unsigned int dirty)
 {
 	RING_LOCALS;
 	DRM_DEBUG("dirty=0x%08x\n", dirty);
@@ -613,9 +667,9 @@ static int radeon_emit_state(drm_radeon_private_t * dev_priv,
 
 /* Emit 1.2 state
  */
-static int radeon_emit_state2(drm_radeon_private_t * dev_priv,
-			      struct drm_file *file_priv,
-			      drm_radeon_state_t * state)
+int
+radeon_emit_state2(drm_radeon_private_t * dev_priv, struct drm_file *file_priv,
+    drm_radeon_state_t * state)
 {
 	RING_LOCALS;
 
@@ -744,8 +798,9 @@ static struct {
  * Performance monitoring functions
  */
 
-static void radeon_clear_box(drm_radeon_private_t * dev_priv,
-			     int x, int y, int w, int h, int r, int g, int b)
+void
+radeon_clear_box(drm_radeon_private_t * dev_priv, int x, int y, int w,
+    int h, int r, int g, int b)
 {
 	u32 color;
 	RING_LOCALS;
@@ -793,7 +848,8 @@ static void radeon_clear_box(drm_radeon_private_t * dev_priv,
 	ADVANCE_RING();
 }
 
-static void radeon_cp_performance_boxes(drm_radeon_private_t * dev_priv)
+void
+radeon_cp_performance_boxes(drm_radeon_private_t *dev_priv)
 {
 	/* Collapse various things into a wait flag -- trying to
 	 * guess if userspase slept -- better just to have them tell us.
@@ -850,9 +906,9 @@ static void radeon_cp_performance_boxes(drm_radeon_private_t * dev_priv)
  * CP command dispatch functions
  */
 
-static void radeon_cp_dispatch_clear(struct drm_device * dev,
-				     drm_radeon_clear_t * clear,
-				     drm_radeon_clear_rect_t * depth_boxes)
+void
+radeon_cp_dispatch_clear(struct drm_device * dev, drm_radeon_clear_t * clear,
+    drm_radeon_clear_rect_t * depth_boxes)
 {
 	drm_radeon_private_t *dev_priv = dev->dev_private;
 	drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
@@ -1344,7 +1400,8 @@ static void radeon_cp_dispatch_clear(struct drm_device * dev,
 	ADVANCE_RING();
 }
 
-static void radeon_cp_dispatch_swap(struct drm_device * dev)
+void
+radeon_cp_dispatch_swap(struct drm_device *dev)
 {
 	drm_radeon_private_t *dev_priv = dev->dev_private;
 	drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
@@ -1421,7 +1478,8 @@ static void radeon_cp_dispatch_swap(struct drm_device * dev)
 	ADVANCE_RING();
 }
 
-static void radeon_cp_dispatch_flip(struct drm_device * dev)
+void
+radeon_cp_dispatch_flip(struct drm_device *dev)
 {
 	drm_radeon_private_t *dev_priv = dev->dev_private;
 	struct drm_sarea *sarea = (struct drm_sarea *) dev_priv->sarea->handle;
@@ -1467,7 +1525,8 @@ static void radeon_cp_dispatch_flip(struct drm_device * dev)
 	ADVANCE_RING();
 }
 
-static int bad_prim_vertex_nr(int primitive, int nr)
+int
+bad_prim_vertex_nr(int primitive, int nr)
 {
 	switch (primitive & RADEON_PRIM_TYPE_MASK) {
 	case RADEON_PRIM_TYPE_NONE:
@@ -1490,18 +1549,9 @@ static int bad_prim_vertex_nr(int primitive, int nr)
 	}
 }
 
-typedef struct {
-	unsigned int start;
-	unsigned int finish;
-	unsigned int prim;
-	unsigned int numverts;
-	unsigned int offset;
-	unsigned int vc_format;
-} drm_radeon_tcl_prim_t;
-
-static void radeon_cp_dispatch_vertex(struct drm_device * dev,
-				      struct drm_buf * buf,
-				      drm_radeon_tcl_prim_t * prim)
+void
+radeon_cp_dispatch_vertex(struct drm_device * dev, struct drm_buf * buf,
+    drm_radeon_tcl_prim_t * prim)
 {
 	drm_radeon_private_t *dev_priv = dev->dev_private;
 	drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
@@ -1545,7 +1595,8 @@ static void radeon_cp_dispatch_vertex(struct drm_device * dev,
 	} while (i < nbox);
 }
 
-static void radeon_cp_discard_buffer(struct drm_device * dev, struct drm_buf * buf)
+void
+radeon_cp_discard_buffer(struct drm_device * dev, struct drm_buf * buf)
 {
 	drm_radeon_private_t *dev_priv = dev->dev_private;
 	drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
@@ -1562,8 +1613,9 @@ static void radeon_cp_discard_buffer(struct drm_device * dev, struct drm_buf * b
 	buf->used = 0;
 }
 
-static void radeon_cp_dispatch_indirect(struct drm_device * dev,
-					struct drm_buf * buf, int start, int end)
+void
+radeon_cp_dispatch_indirect(struct drm_device *dev, struct drm_buf *buf,
+    int start, int end)
 {
 	drm_radeon_private_t *dev_priv = dev->dev_private;
 	RING_LOCALS;
@@ -1596,9 +1648,9 @@ static void radeon_cp_dispatch_indirect(struct drm_device * dev,
 	}
 }
 
-static void radeon_cp_dispatch_indices(struct drm_device * dev,
-				       struct drm_buf * elt_buf,
-				       drm_radeon_tcl_prim_t * prim)
+void
+radeon_cp_dispatch_indices(struct drm_device *dev, struct drm_buf *elt_buf,
+    drm_radeon_tcl_prim_t * prim)
 {
 	drm_radeon_private_t *dev_priv = dev->dev_private;
 	drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
@@ -1654,10 +1706,9 @@ static void radeon_cp_dispatch_indices(struct drm_device * dev,
 
 #define RADEON_MAX_TEXTURE_SIZE RADEON_BUFFER_SIZE
 
-static int radeon_cp_dispatch_texture(struct drm_device * dev,
-				      struct drm_file *file_priv,
-				      drm_radeon_texture_t * tex,
-				      drm_radeon_tex_image_t * image)
+int
+radeon_cp_dispatch_texture(struct drm_device *dev, struct drm_file *file_priv,
+    drm_radeon_texture_t *tex, drm_radeon_tex_image_t *image)
 {
 	drm_radeon_private_t *dev_priv = dev->dev_private;
 	struct drm_buf *buf;
@@ -1897,7 +1948,8 @@ static int radeon_cp_dispatch_texture(struct drm_device * dev,
 	return 0;
 }
 
-static void radeon_cp_dispatch_stipple(struct drm_device * dev, u32 * stipple)
+void
+radeon_cp_dispatch_stipple(struct drm_device *dev, u32 *stipple)
 {
 	drm_radeon_private_t *dev_priv = dev->dev_private;
 	int i;
@@ -1917,8 +1969,8 @@ static void radeon_cp_dispatch_stipple(struct drm_device * dev, u32 * stipple)
 	ADVANCE_RING();
 }
 
-static void radeon_apply_surface_regs(int surf_index,
-				      drm_radeon_private_t *dev_priv)
+void
+radeon_apply_surface_regs(int surf_index, drm_radeon_private_t *dev_priv)
 {
 	radeon_do_cp_idle(dev_priv);
 
@@ -1941,9 +1993,9 @@ static void radeon_apply_surface_regs(int surf_index,
  * freed, we suddenly need two surfaces to store A and C, which might
  * not always be available.
  */
-static int alloc_surface(drm_radeon_surface_alloc_t *new,
-			 drm_radeon_private_t *dev_priv,
-			 struct drm_file *file_priv)
+int
+alloc_surface(drm_radeon_surface_alloc_t *new, drm_radeon_private_t *dev_priv,
+    struct drm_file *file_priv)
 {
 	struct radeon_virt_surface *s;
 	int i;
@@ -2037,9 +2089,9 @@ static int alloc_surface(drm_radeon_surface_alloc_t *new,
 	return -1;
 }
 
-static int free_surface(struct drm_file *file_priv,
-			drm_radeon_private_t * dev_priv,
-			int lower)
+int
+free_surface(struct drm_file *file_priv, drm_radeon_private_t * dev_priv,
+    int lower)
 {
 	struct radeon_virt_surface *s;
 	int i;
@@ -2074,8 +2126,9 @@ static int free_surface(struct drm_file *file_priv,
 	return 1;
 }
 
-static void radeon_surfaces_release(struct drm_file *file_priv,
-				    drm_radeon_private_t * dev_priv)
+void
+radeon_surfaces_release(struct drm_file *file_priv,
+    drm_radeon_private_t *dev_priv)
 {
 	int i;
 	for (i = 0; i < 2 * RADEON_MAX_SURFACES; i++) {
@@ -2147,7 +2200,8 @@ int radeon_cp_clear(struct drm_device *dev, void *data, struct drm_file *file_pr
 
 /* Not sure why this isn't set all the time:
  */
-static int radeon_do_init_pageflip(struct drm_device * dev)
+int
+radeon_do_init_pageflip(struct drm_device *dev)
 {
 	drm_radeon_private_t *dev_priv = dev->dev_private;
 	RING_LOCALS;
@@ -2605,10 +2659,9 @@ int radeon_cp_vertex2(struct drm_device *dev, void *data, struct drm_file *file_
 	return 0;
 }
 
-static int radeon_emit_packets(drm_radeon_private_t * dev_priv,
-			       struct drm_file *file_priv,
-			       drm_radeon_cmd_header_t header,
-			       drm_radeon_kcmd_buffer_t *cmdbuf)
+int
+radeon_emit_packets(drm_radeon_private_t * dev_priv, struct drm_file *file_priv,
+    drm_radeon_cmd_header_t header, drm_radeon_kcmd_buffer_t *cmdbuf)
 {
 	int id = (int)header.packet.packet_id;
 	int sz, reg;
@@ -2641,9 +2694,9 @@ static int radeon_emit_packets(drm_radeon_private_t * dev_priv,
 	return 0;
 }
 
-static __inline__ int radeon_emit_scalars(drm_radeon_private_t *dev_priv,
-					  drm_radeon_cmd_header_t header,
-					  drm_radeon_kcmd_buffer_t *cmdbuf)
+int
+radeon_emit_scalars(drm_radeon_private_t *dev_priv,
+    drm_radeon_cmd_header_t header, drm_radeon_kcmd_buffer_t *cmdbuf)
 {
 	int sz = header.scalars.count;
 	int start = header.scalars.offset;
@@ -2663,12 +2716,11 @@ static __inline__ int radeon_emit_scalars(drm_radeon_private_t *dev_priv,
 
 /* God this is ugly
  */
-static __inline__ int radeon_emit_scalars2(drm_radeon_private_t *dev_priv,
-					   drm_radeon_cmd_header_t header,
-					   drm_radeon_kcmd_buffer_t *cmdbuf)
+int
+radeon_emit_scalars2(drm_radeon_private_t *dev_priv,
+    drm_radeon_cmd_header_t header, drm_radeon_kcmd_buffer_t *cmdbuf)
 {
-	int sz = header.scalars.count;
-	int start = ((unsigned int)header.scalars.offset) + 0x100;
+	int sz = header.scalars.count; int start = ((unsigned int)header.scalars.offset) + 0x100;
 	int stride = header.scalars.stride;
 	RING_LOCALS;
 
@@ -2683,9 +2735,9 @@ static __inline__ int radeon_emit_scalars2(drm_radeon_private_t *dev_priv,
 	return 0;
 }
 
-static __inline__ int radeon_emit_vectors(drm_radeon_private_t *dev_priv,
-					  drm_radeon_cmd_header_t header,
-					  drm_radeon_kcmd_buffer_t *cmdbuf)
+int
+radeon_emit_vectors(drm_radeon_private_t *dev_priv,
+    drm_radeon_cmd_header_t header, drm_radeon_kcmd_buffer_t *cmdbuf)
 {
 	int sz = header.vectors.count;
 	int start = header.vectors.offset;
@@ -2705,9 +2757,9 @@ static __inline__ int radeon_emit_vectors(drm_radeon_private_t *dev_priv,
 	return 0;
 }
 
-static __inline__ int radeon_emit_veclinear(drm_radeon_private_t *dev_priv,
-					  drm_radeon_cmd_header_t header,
-					  drm_radeon_kcmd_buffer_t *cmdbuf)
+int
+radeon_emit_veclinear(drm_radeon_private_t *dev_priv,
+    drm_radeon_cmd_header_t header, drm_radeon_kcmd_buffer_t *cmdbuf)
 {
 	int sz = header.veclinear.count * 4;
 	int start = header.veclinear.addr_lo | (header.veclinear.addr_hi << 8);
@@ -2731,9 +2783,9 @@ static __inline__ int radeon_emit_veclinear(drm_radeon_private_t *dev_priv,
 	return 0;
 }
 
-static int radeon_emit_packet3(struct drm_device * dev,
-			       struct drm_file *file_priv,
-			       drm_radeon_kcmd_buffer_t *cmdbuf)
+int
+radeon_emit_packet3(struct drm_device * dev, struct drm_file *file_priv,
+    drm_radeon_kcmd_buffer_t *cmdbuf)
 {
 	drm_radeon_private_t *dev_priv = dev->dev_private;
 	unsigned int cmdsz;
@@ -2757,10 +2809,9 @@ static int radeon_emit_packet3(struct drm_device * dev,
 	return 0;
 }
 
-static int radeon_emit_packet3_cliprect(struct drm_device *dev,
-					struct drm_file *file_priv,
-					drm_radeon_kcmd_buffer_t *cmdbuf,
-					int orig_nbox)
+int
+radeon_emit_packet3_cliprect(struct drm_device *dev, struct drm_file *file_priv,
+    drm_radeon_kcmd_buffer_t *cmdbuf, int orig_nbox)
 {
 	drm_radeon_private_t *dev_priv = dev->dev_private;
 	struct drm_clip_rect box;
@@ -2819,7 +2870,8 @@ static int radeon_emit_packet3_cliprect(struct drm_device *dev,
 	return 0;
 }
 
-static int radeon_emit_wait(struct drm_device * dev, int flags)
+int
+radeon_emit_wait(struct drm_device *dev, int flags)
 {
 	drm_radeon_private_t *dev_priv = dev->dev_private;
 	RING_LOCALS;