diff options
| author | Ted Unangst <tedu@cvs.openbsd.org> | 2003-07-25 17:41:20 +0000 |
|---|---|---|
| committer | Ted Unangst <tedu@cvs.openbsd.org> | 2003-07-25 17:41:20 +0000 |
| commit | e1e6b78824fba1bdd61d26c625547546d5c1f316 (patch) | |
| tree | fafc160af37be7e9b9bb42957cfef139d770a631 /sys | |
| parent | 57f801c356db9d406f52988585828c01cf650e91 (diff) | |
make sure SYSENTER registers are 0 at boot time. should fix an unusual
DOS reported by Michal Zalewski to bugtraq. ok mickey@ toby@
Diffstat (limited to 'sys')
| -rw-r--r-- | sys/arch/i386/i386/machdep.c | 8 | ||||
| -rw-r--r-- | sys/arch/i386/include/specialreg.h | 5 |
2 files changed, 11 insertions, 2 deletions
diff --git a/sys/arch/i386/i386/machdep.c b/sys/arch/i386/i386/machdep.c index c185f43599f..fd6d0a6dccd 100644 --- a/sys/arch/i386/i386/machdep.c +++ b/sys/arch/i386/i386/machdep.c @@ -1,4 +1,4 @@ -/* $OpenBSD: machdep.c,v 1.237 2003/07/07 03:07:19 tedu Exp $ */ +/* $OpenBSD: machdep.c,v 1.238 2003/07/25 17:41:19 tedu Exp $ */ /* $NetBSD: machdep.c,v 1.214 1996/11/10 03:16:17 thorpej Exp $ */ /*- @@ -1261,6 +1261,12 @@ intel686_cpu_setup(cpu_device, model, step) cpu_feature &= ~CPUID_SYS2; /* + * Make sure SYSENTER is disabled. + */ + if (cpu_feature & CPUID_SYS2) + wrmsr(MSR_SYSENTER_CS, 0); + + /* * Disable the Pentium3 serial number. */ if ((model == 7) && (cpu_feature & CPUID_SER)) { diff --git a/sys/arch/i386/include/specialreg.h b/sys/arch/i386/include/specialreg.h index a3d004b7b3d..4876dec9eae 100644 --- a/sys/arch/i386/include/specialreg.h +++ b/sys/arch/i386/include/specialreg.h @@ -1,4 +1,4 @@ -/* $OpenBSD: specialreg.h,v 1.14 2003/06/06 11:11:54 andreas Exp $ */ +/* $OpenBSD: specialreg.h,v 1.15 2003/07/25 17:41:18 tedu Exp $ */ /* $NetBSD: specialreg.h,v 1.7 1994/10/27 04:16:26 cgd Exp $ */ /*- @@ -160,6 +160,9 @@ #define MSR_BBL_CR_TRIG 0x11a /* PII+ only */ #define MSR_BBL_CR_BUSY 0x11b /* PII+ only */ #define MSR_BBL_CR_CTR3 0x11e /* PII+ only */ +#define MSR_SYSENTER_CS 0x174 +#define MSR_SYSENTER_ESP 0x175 +#define MSR_SYSENTER_EIP 0x176 #define MSR_MCG_CAP 0x179 #define MSR_MCG_STATUS 0x17a #define MSR_MCG_CTL 0x17b |