diff options
| author | Damien Bergamini <damien@cvs.openbsd.org> | 2010-04-23 16:05:40 +0000 |
|---|---|---|
| committer | Damien Bergamini <damien@cvs.openbsd.org> | 2010-04-23 16:05:40 +0000 |
| commit | ee0e634d028cb2c2b2f77a79b55b44b35c3bf07f (patch) | |
| tree | 030be86200412fa9c2ebe8eb1ae31ab19971d5d8 /sys | |
| parent | 38fc778c9782dbaa70fa6da92cfd8daaaa43d6fe (diff) | |
give AR9287 some chance to work.
Diffstat (limited to 'sys')
| -rw-r--r-- | sys/dev/ic/ar9287.c | 20 |
1 files changed, 13 insertions, 7 deletions
diff --git a/sys/dev/ic/ar9287.c b/sys/dev/ic/ar9287.c index bd05d37ba3e..86943b898e9 100644 --- a/sys/dev/ic/ar9287.c +++ b/sys/dev/ic/ar9287.c @@ -1,4 +1,4 @@ -/* $OpenBSD: ar9287.c,v 1.8 2010/04/20 22:05:43 tedu Exp $ */ +/* $OpenBSD: ar9287.c,v 1.9 2010/04/23 16:05:39 damien Exp $ */ /*- * Copyright (c) 2009 Damien Bergamini <damien.bergamini@free.fr> @@ -115,14 +115,14 @@ ar9287_setup(struct athn_softc *sc) /* Determine if open loop power control should be used. */ if (eep->baseEepHeader.openLoopPwrCntl) sc->flags |= ATHN_FLAG_OLPC; - if (AR_SREV_9287_10(sc)) - sc->rx_gain = &ar9287_1_0_rx_gain; - else + + if (AR_SREV_9287_11_OR_LATER(sc)) { sc->rx_gain = &ar9287_1_1_rx_gain; - if (AR_SREV_9287_10(sc)) - sc->tx_gain = &ar9287_1_0_tx_gain; - else sc->tx_gain = &ar9287_1_1_tx_gain; + } else { + sc->rx_gain = &ar9287_1_0_rx_gain; + sc->tx_gain = &ar9287_1_0_tx_gain; + } } void @@ -434,6 +434,8 @@ ar9287_set_txpower(struct athn_softc *sc, struct ieee80211_channel *c, int16_t pwr = 0, max_ant_gain, power[ATHN_POWER_COUNT]; int i; + ar9287_set_power_calib(sc, c); + /* Compute transmit power reduction due to antenna gain. */ max_ant_gain = MAX(modal->antennaGainCh[0], modal->antennaGainCh[1]); /* XXX */ @@ -589,6 +591,10 @@ ar9287_1_2_setup_async_fifo(struct athn_softc *sc) { uint32_t reg; + /* + * MAC runs at 117MHz (instead of 88/44MHz) when ASYNC FIFO is + * enabled, so the following counters have to be changed. + */ AR_WRITE(sc, AR_D_GBL_IFS_SIFS, AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR); AR_WRITE(sc, AR_D_GBL_IFS_SLOT, AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR); AR_WRITE(sc, AR_D_GBL_IFS_EIFS, AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR); |