summaryrefslogtreecommitdiff
path: root/sys
diff options
context:
space:
mode:
authorJonathan Gray <jsg@cvs.openbsd.org>2007-02-13 00:21:00 +0000
committerJonathan Gray <jsg@cvs.openbsd.org>2007-02-13 00:21:00 +0000
commit14517278b70afa7a95339e5eb088515b4226d098 (patch)
tree4323cdd9f47771a8ab8e56248a0e049309146d84 /sys
parente54c4c41ee6b9d3584866e3234367d7a78ee457f (diff)
Check for some CPUID flags found on newer Intel processors.
ok tom@ gwk@ krw@
Diffstat (limited to 'sys')
-rw-r--r--sys/arch/amd64/amd64/identcpu.c12
-rw-r--r--sys/arch/amd64/include/specialreg.h10
2 files changed, 19 insertions, 3 deletions
diff --git a/sys/arch/amd64/amd64/identcpu.c b/sys/arch/amd64/amd64/identcpu.c
index 307a4c66849..e3eb37eb4fe 100644
--- a/sys/arch/amd64/amd64/identcpu.c
+++ b/sys/arch/amd64/amd64/identcpu.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: identcpu.c,v 1.9 2006/03/16 02:55:52 dlg Exp $ */
+/* $OpenBSD: identcpu.c,v 1.10 2007/02/13 00:20:59 jsg Exp $ */
/* $NetBSD: identcpu.c,v 1.1 2003/04/26 18:39:28 fvdl Exp $ */
/*
@@ -91,7 +91,15 @@ const struct {
{ CPUID_3DNOW2, "3DNOW2" },
{ CPUID_3DNOW, "3DNOW" }
}, cpu_cpuid_ecxfeatures[] = {
- { CPUIDECX_SSE3, "SSE3" }
+ { CPUIDECX_SSE3, "SSE3" },
+ { CPUIDECX_MWAIT, "MWAIT" },
+ { CPUIDECX_DSCPL, "DS-CPL" },
+ { CPUIDECX_VMX, "VMX" },
+ { CPUIDECX_EST, "EST" },
+ { CPUIDECX_TM2, "TM2" },
+ { CPUIDECX_CNXTID, "CNXT-ID" },
+ { CPUIDECX_CX16, "CX16" },
+ { CPUIDECX_XTPR, "xTPR" }
};
int
diff --git a/sys/arch/amd64/include/specialreg.h b/sys/arch/amd64/include/specialreg.h
index c4a044c9aa4..d8982d03f90 100644
--- a/sys/arch/amd64/include/specialreg.h
+++ b/sys/arch/amd64/include/specialreg.h
@@ -1,4 +1,4 @@
-/* $OpenBSD: specialreg.h,v 1.5 2006/03/07 05:21:40 jsg Exp $ */
+/* $OpenBSD: specialreg.h,v 1.6 2007/02/13 00:20:59 jsg Exp $ */
/* $NetBSD: specialreg.h,v 1.1 2003/04/26 18:39:48 fvdl Exp $ */
/* $NetBSD: x86/specialreg.h,v 1.2 2003/04/25 21:54:30 fvdl Exp $ */
@@ -123,6 +123,14 @@
#define CPUID_SBF 0x80000000 /* signal break on FERR */
#define CPUIDECX_SSE3 0x00000001 /* streaming SIMD extensions #3 */
+#define CPUIDECX_MWAIT 0x00000008 /* Monitor/Mwait */
+#define CPUIDECX_DSCPL 0x00000010 /* CPL Qualified Debug Store */
+#define CPUIDECX_VMX 0x00000020 /* Virtual Machine Extensions */
+#define CPUIDECX_EST 0x00000080 /* enhanced SpeedStep */
+#define CPUIDECX_TM2 0x00000100 /* thermal monitor 2 */
+#define CPUIDECX_CNXTID 0x00000400 /* Context ID */
+#define CPUIDECX_CX16 0x00002000 /* has CMPXCHG16B instruction */
+#define CPUIDECX_XTPR 0x00004000 /* xTPR Update Control */
/*
* AMD/VIA processor specific flags.