KNF and ANSIfy.

1 files changed, 270 insertions, 266 deletions

diff --git a/sys/arch/m88k/m88k/db_disasm.c b/sys/arch/m88k/m88k/db_disasm.c
index c27ed1db370..85b38161246 100644
--- a/sys/arch/m88k/m88k/db_disasm.c
+++ b/sys/arch/m88k/m88k/db_disasm.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: db_disasm.c,v 1.2 2004/09/30 21:48:56 miod Exp $	*/
+/*	$OpenBSD: db_disasm.c,v 1.3 2005/05/15 14:12:22 miod Exp $	*/
 /*
  * Mach Operating System
  * Copyright (c) 1993-1991 Carnegie Mellon University
@@ -174,25 +174,22 @@ void onimmed(int, const char *, long);
 
 /* Handlers immediate integer arithmetic instructions */
 void
-oimmed(int inst, const char  *opcode, long iadr)
+oimmed(int inst, const char *opcode, long iadr)
 {
 	int Linst = inst & 0177777;
 	int Hinst = inst >> 16;
 	int H6inst = Hinst >> 10;
 	int rs1 = Hinst & 037;
-	int rd = ( Hinst >> 5 ) & 037;
+	int rd = (Hinst >> 5) & 037;
 
-	if (( H6inst > 017 ) && ( H6inst < 030 ) && ( H6inst & 01) == 1 )
-		db_printf("\t%s.u",opcode);
-	else {
-		db_printf("\t%s",opcode);
-		db_printf("  ");
-	}
+	if (H6inst > 017 && H6inst < 030 && (H6inst & 01) == 1)
+		db_printf("\t%s.u", opcode);
+	else
+		db_printf("\t%s  ", opcode);
 	db_printf("\t\tr%-3d,r%-3d,", rd, rs1);
 	printval(Linst);
 }
 
-
 /* Handles instructions dealing with control registers */
 void
 ctrlregs(int inst, const char *opcode, long iadr)
@@ -202,24 +199,23 @@ ctrlregs(int inst, const char *opcode, long iadr)
 	int rd = (inst >> 21) & 037;
 	int rs1 = (inst >> 16) & 037;
 
-	db_printf("\t%s",opcode);
+	db_printf("\t%s", opcode);
 
-	if ( L6inst == 010 || L6inst == 011 )
+	if (L6inst == 010 || L6inst == 011)
 		db_printf("\t\tr%-3d,%s", rd,
-			  CPU_IS88100 ? m88100_ctrlreg[creg] : m88110_ctrlreg[creg]);
-	else if ( L6inst == 020 || L6inst == 021 )
+		    CPU_IS88100 ? m88100_ctrlreg[creg] : m88110_ctrlreg[creg]);
+	else if (L6inst == 020 || L6inst == 021)
 		db_printf("\t\tr%-3d,%s", rs1,
-			  CPU_IS88100 ? m88100_ctrlreg[creg] : m88110_ctrlreg[creg]);
+		    CPU_IS88100 ? m88100_ctrlreg[creg] : m88110_ctrlreg[creg]);
 	else
 		db_printf("\t\tr%-3d,r%-3d,%s", rd, rs1,
-			  CPU_IS88100 ? m88100_ctrlreg[creg] : m88110_ctrlreg[creg]);
+		    CPU_IS88100 ? m88100_ctrlreg[creg] : m88110_ctrlreg[creg]);
 }
 
-
 void
 printsod(int t)
 {
-	if ( t == 0 )
+	if (t == 0)
 		db_printf("s");
 	else
 		db_printf("d");
@@ -230,119 +226,129 @@ void
 sindou(int inst, const char *opcode, long iadr)
 {
 	int rs2 = inst & 037;
-	int td = ( inst >> 5 ) & 03;
-	int t2 = ( inst >> 7 ) & 03;
-	int t1 = ( inst >> 9 ) & 03;
-	int rs1 = ( inst >> 16 ) & 037;
-	int rd = ( inst >> 21 ) & 037;
-	int checkbits  = ( inst >> 11 ) & 037;
-
-	db_printf("\t%s.",opcode);
+	int td = (inst >> 5) & 03;
+	int t2 = (inst >> 7) & 03;
+	int t1 = (inst >> 9) & 03;
+	int rs1 = (inst >> 16) & 037;
+	int rd = (inst >> 21) & 037;
+	int checkbits = (inst >> 11) & 037;
+
+	db_printf("\t%s.", opcode);
 	printsod(td);
-	if (( checkbits > 010 && checkbits < 014 ) || ( checkbits == 04 )) {
+	if ((checkbits > 010 && checkbits < 014) || checkbits == 04) {
 		printsod(t2);
 		db_printf(" ");
-		if ( checkbits == 012 || checkbits == 013 )
+		if (checkbits == 012 || checkbits == 013)
 			db_printf("\t\tr%-3d,r%-3d", rd, rs2);
 		else
 			db_printf("\t\tr%-3d,r%-3d", rd, rs2);
 	} else {
-		printsod(t1);printsod(t2);
+		printsod(t1);
+		printsod(t2);
 		db_printf("\t\tr%-3d,r%-3d,r%-3d", rd, rs1, rs2);
 	}
 }
 
-
 void
 jump(int inst, const char *opcode, long iadr)
 {
 	int rs2 = inst & 037;
-	int Nbit = ( inst >> 10 ) & 01;
+	int Nbit = (inst >> 10) & 01;
 
-	db_printf("\t%s",opcode);
-	if ( Nbit == 1 )
+	db_printf("\t%s", opcode);
+	if (Nbit == 1)
 		db_printf(".n");
 	else
 		db_printf("  ");
-	db_printf("\t\tr%-3d",rs2);
+	db_printf("\t\tr%-3d", rs2);
 }
 
-
 /* Handles ff1, ff0, tbnd and rte instructions */
 void
 instset(int inst, const char *opcode, long iadr)
 {
 	int rs2 = inst & 037;
-	int rs1 = ( inst >> 16 ) & 037;
-	int rd = ( inst >> 21 ) & 037;
-	int checkbits = ( inst >> 10 ) & 077;
-	int H6inst = ( inst >> 26 ) & 077;
-
-	db_printf("\t%s",opcode);
-	if ( H6inst == 076 ) {
-		db_printf("\t\tr%-3d,",rs1);
+	int rs1 = (inst >> 16) & 037;
+	int rd = (inst >> 21) & 037;
+	int checkbits = (inst >> 10) & 077;
+	int H6inst = (inst >> 26) & 077;
+
+	db_printf("\t%s", opcode);
+	if (H6inst == 076) {
+		db_printf("\t\tr%-3d,", rs1);
 		printval(inst & 0177777);
-	} else if (( checkbits == 072 ) || ( checkbits == 073 ))
+	} else if (checkbits == 072 || checkbits == 073)
 		db_printf("\t\tr%-3d,r%-3d", rd, rs2);
-	else if ( checkbits == 076 )
-		db_printf("\t\tr%-3d,r%-3d",rs1,rs2);
+	else if (checkbits == 076)
+		db_printf("\t\tr%-3d,r%-3d", rs1, rs2);
 }
 
 void
-symofset(int  disp, int  bit, int iadr)
+symofset(int disp, int bit, int iadr)
 {
 	long addr;
 
-	if ( disp & (1 << (bit-1)) ) {
+	if (disp & (1 << (bit - 1))) {
 		/* negative value */
 		addr = iadr + ((disp << 2) | (~0 << bit));
 	} else {
 		addr = iadr + (disp << 2);
 	}
-	db_printsym(addr,DB_STGY_PROC, db_printf);
-	return;
+	db_printsym(addr, DB_STGY_PROC, db_printf);
 }
 
 void
 obranch(int inst, const char *opcode, long iadr)
 {
-	int cond = ( inst >> 26 ) & 01;
-	int disp = inst &0377777777;
+	int cond = (inst >> 26) & 01;
+	int disp = inst & 0377777777;
 
-	if ( cond == 0 ) {
-		db_printf("\t%s\t\t",opcode);
-		symofset(disp, 26, iadr);
-	} else {
-		db_printf("\t%s.n\t\t",opcode);
-		symofset(disp, 26, iadr);
-	}
+	if (cond == 0)
+		db_printf("\t%s\t\t", opcode);
+	else
+		db_printf("\t%s.n\t\t", opcode);
+	symofset(disp, 26, iadr);
 }
 
-
 /* Handles branch on conditions instructions */
 void
 brcond(int inst, const char *opcode, long iadr)
 {
-	int cond = ( inst >> 26 ) & 1;
-	int match = ( inst >> 21 ) & 037;
-	int rs = ( inst >> 16 ) & 037;
-	int disp = ( inst & 0177777 );
+	int cond = (inst >> 26) & 1;
+	int match = (inst >> 21) & 037;
+	int rs = (inst >> 16) & 037;
+	int disp = inst & 0177777;
 
-	if ( cond == 0 )
+	if (cond == 0)
 		db_printf("\t%s\t\t", opcode);
 	else
 		db_printf("\t%s.n\t\t", opcode);
-	if ( ( ( inst >> 27 ) & 03 ) == 1 )
+	if (((inst >> 27) & 03) == 1) {
 		switch (match) {
-		case 1 : db_printf("%s,", condname[0]); break;
-		case 2 : db_printf("%s,", condname[1]); break;
-		case 3 : db_printf("%s,", condname[2]); break;
-		case 12: db_printf("%s,", condname[3]); break;
-		case 13: db_printf("%s,", condname[4]); break;
-		case 14: db_printf("%s,", condname[5]); break;
-		default: printval(match);
+		case 1:
+			db_printf("%s,", condname[0]);
+			break;
+		case 2:
+			db_printf("%s,", condname[1]);
+			break;
+		case 3:
+			db_printf("%s,", condname[2]);
+			break;
+		case 12:
+			db_printf("%s,", condname[3]);
+			break;
+		case 13:
+			db_printf("%s,", condname[4]);
+			break;
+		case 14:
+			db_printf("%s,", condname[5]);
+			break;
+		default:
+			printval(match);
 			db_printf(",");
-		} else {
+			break;
+		}
+	} else {
 		printval(match);
 		db_printf(",");
 	}
@@ -351,26 +357,40 @@ brcond(int inst, const char *opcode, long iadr)
 	symofset(disp, 16, iadr);
 }
 
-
 void
 otrap(int inst, const char *opcode, long iadr)
 {
 	int vecno = inst & 0777;
-	int match = ( inst >> 21 ) & 037;
-	int rs = ( inst >> 16 ) & 037;
+	int match = (inst >> 21) & 037;
+	int rs = (inst >> 16) & 037;
 
-	db_printf("\t%s\t",opcode);
-	if ( ( ( inst >> 12 ) & 017 ) == 0xe )
+	db_printf("\t%s\t", opcode);
+	if (((inst >> 12) & 017) == 0xe) {
 		switch (match) {
-		case 1 : db_printf("%s,", condname[0]);break;
-		case 2 : db_printf("%s,", condname[1]);break;
-		case 3 : db_printf("%s,", condname[2]);break;
-		case 12: db_printf("%s,", condname[3]);break;
-		case 13: db_printf("%s,", condname[4]);break;
-		case 14: db_printf("%s,", condname[5]);break;
-		default: printval(match);
+		case 1:
+			db_printf("%s,", condname[0]);
+			break;
+		case 2:
+			db_printf("%s,", condname[1]);
+			break;
+		case 3:
+			db_printf("%s,", condname[2]);
+			break;
+		case 12:
+			db_printf("%s,", condname[3]);
+			break;
+		case 13:
+			db_printf("%s,", condname[4]);
+			break;
+		case 14:
+			db_printf("%s,", condname[5]);
+			break;
+		default:
+			printval(match);
 			db_printf(",");
-		} else {
+			break;
+		}
+	} else {
 		printval(match);
 		db_printf(",");
 	}
@@ -378,123 +398,108 @@ otrap(int inst, const char *opcode, long iadr)
 	printval(vecno);
 }
 
-
 /* Handles 10 bit immediate bit field operations */
 void
 obit(int inst, const char *opcode, long iadr)
 {
-	int rs = ( inst >> 16 ) & 037;
-	int rd = ( inst >> 21 ) & 037;
-	int width = ( inst >> 5 ) & 037;
-	int offset = ( inst & 037 );
+	int rs = (inst >> 16) & 037;
+	int rd = (inst >> 21) & 037;
+	int width = (inst >> 5) & 037;
+	int offset = inst & 037;
 
 	db_printf("\t%s\t\tr%-3d,r%-3d,", opcode, rd, rs);
-	if ( ( ( inst >> 10 ) & 077 ) == 052 ) {
-		db_printf("<");
-		printval(offset);
-		db_printf(">");
-	} else {
+	if (((inst >> 10) & 077) != 052)
 		printval(width);
-		db_printf("<");
-		printval(offset);
-		db_printf(">");
-	}
+	db_printf("<");
+	printval(offset);
+	db_printf(">");
 }
 
-
 /* Handles triadic mode bit field instructions */
 void
 bitman(int inst, const char *opcode, long iadr)
 {
-
-	int rs1 = ( inst >> 16 ) & 037;
-	int rd  = ( inst >> 21 ) & 037;
+	int rs1 = (inst >> 16) & 037;
+	int rd = (inst >> 21) & 037;
 	int rs2 = inst & 037;
 
 	db_printf("\t%s\t\tr%-3d,r%-3d,r%-3d", opcode, rd, rs1, rs2);
 }
 
-
 /* Handles immediate load/store/exchange instructions */
 void
 immem(int inst, const char *opcode, long iadr)
 {
-	int immed  = inst & 0xFFFF;
-	int rd     = (inst >> 21) & 037;
-	int rs     = (inst >> 16) & 037;
+	int immed = inst & 0xFFFF;
+	int rd = (inst >> 21) & 037;
+	int rs = (inst >> 16) & 037;
 	int st_lda = (inst >> 28) & 03;
-	int aryno  = (inst >> 26) & 03;
+	int aryno = (inst >> 26) & 03;
 	char c = ' ';
 
 	if (!st_lda) {
-		if ((aryno == 0) || (aryno == 01))
+		if (aryno == 0 || aryno == 01)
 			opcode = "xmem";
 		else
 			opcode = "ld";
 		if (aryno == 0)
 			aryno = 03;
-		if (!(aryno == 01))
+		if (aryno != 01)
 			c = 'u';
-	} else
+	} else {
 		if (st_lda == 01)
-		opcode = "ld";
+			opcode = "ld";
+	}
 
-	db_printf("\t%s%s%c\t\tr%-3d,r%-3d,", opcode, instwidth[aryno],
-		  c, rd, rs);
+	db_printf("\t%s%s%c\t\tr%-3d,r%-3d,",
+	    opcode, instwidth[aryno], c, rd, rs);
 	printval(immed);
 }
 
-
 /* Handles triadic mode load/store/exchange instructions */
 void
 nimmem(int inst, const char *opcode, long iadr)
 {
-	int scaled  = (inst >> 9) & 01;
-	int rd      = (inst >> 21) & 037;
-	int rs1     = (inst >> 16) & 037;
-	int rs2     = inst & 037;
-	int st_lda  = (inst >> 12) & 03;
-	int aryno   = (inst >> 10) & 03;
+	int scaled = (inst >> 9) & 01;
+	int rd = (inst >> 21) & 037;
+	int rs1 = (inst >> 16) & 037;
+	int rs2 = inst & 037;
+	int st_lda = (inst >> 12) & 03;
+	int aryno = (inst >> 10) & 03;
 	int user_bit = 0;
-	int signed_fg  = 1;
-	char *user           = "    ";
-	char c = ' ';
+	int signed_fg = 1;
+	char *user = "    ";
 
 	if (!st_lda) {
-		if ((aryno == 0) || (aryno == 01))
+		if (aryno == 0 || aryno == 01)
 			opcode = "xmem";
 		else
 			opcode = "ld";
 		if (aryno == 0)
 			aryno = 03;
-		if (!(aryno == 01)) {
-			c = 'u';
+		if (aryno != 01)
 			signed_fg = 0;
-		}
-	} else
+	} else {
 		if (st_lda == 01)
-		opcode = "ld";
+			opcode = "ld";
+	}
 
-	if (!(st_lda == 03)) {
+	if (st_lda != 03) {
 		user_bit = (inst >> 8) & 01;
 		if (user_bit)
 			user = ".usr";
 	}
 
-	if (user_bit && signed_fg && (aryno == 01)) {
-		if (st_lda)
-			db_printf("\t%s%s\tr%-3d,r%-3d", opcode,
-				  user, rd, rs1);
-		else
-			db_printf("\t%s%s\tr%-3d,r%-3d", opcode,
-				  user, rd, rs1);
-	} else
+	if (user_bit && signed_fg && aryno == 01)
+		db_printf("\t%s%s\tr%-3d,r%-3d", opcode, user, rd, rs1);
+	else {
 		if (user_bit && signed_fg)
-		db_printf("\t%s%s%s\tr%-3d,r%-3d", opcode,
-			  instwidth[aryno], user, rd, rs1);
-	else
-		db_printf("\t%s%s%c%s\tr%-3d,r%-3d", opcode,
-			  instwidth[aryno], c, user, rd, rs1);
+			db_printf("\t%s%s%s\tr%-3d,r%-3d",
+			    opcode, instwidth[aryno], user, rd, rs1);
+		else
+			db_printf("\t%s%su%s\tr%-3d,r%-3d",
+			    opcode, instwidth[aryno], user, rd, rs1);
+	}
 
 	if (scaled)
 		db_printf("[r%-3d]", rs2);
@@ -502,14 +507,13 @@ nimmem(int inst, const char *opcode, long iadr)
 		db_printf(",r%-3d", rs2);
 }
 
-
 /* Handles triadic mode logical instructions */
 void
 lognim(int inst, const char *opcode, long iadr)
 {
-	int rd   = (inst >> 21) & 037;
-	int rs1  = (inst >> 16) & 037;
-	int rs2  = inst & 037;
+	int rd = (inst >> 21) & 037;
+	int rs1 = (inst >> 16) & 037;
+	int rs2 = inst & 037;
 	int complemt = (inst >> 10) & 01;
 	char *c = "  ";
 
@@ -519,18 +523,17 @@ lognim(int inst, const char *opcode, long iadr)
 	db_printf("\t%s%s\t\tr%-3d,r%-3d,r%-3d", opcode, c, rd, rs1, rs2);
 }
 
-
 /* Handles triadic mode arithmetic instructions */
 void
 onimmed(int inst, const char *opcode, long iadr)
 {
-	int rd   = (inst >> 21) & 037;
-	int rs1  = (inst >> 16) & 037;
-	int rs2  = inst & 037;
+	int rd = (inst >> 21) & 037;
+	int rs1 = (inst >> 16) & 037;
+	int rs2 = inst & 037;
 	int carry = (inst >> 8) & 03;
 	int nochar = (inst >> 10) & 07;
 	int nodecode = (inst >> 11) & 01;
-	char *tab, *c ;
+	const char *tab, *c;
 
 	if (nochar > 02)
 		tab = "\t\t";
@@ -538,21 +541,24 @@ onimmed(int inst, const char *opcode, long iadr)
 		tab = "\t";
 
 	if (!nodecode) {
-		if (carry == 01)
+		switch (carry) {
+		case 01:
 			c = ".co ";
-		else
-			if (carry == 02)
+			break;
+		case 02:
 			c = ".ci ";
-		else
-			if (carry == 03)
+			break;
+		case 03:
 			c = ".cio";
-		else
+			break;
+		default:
 			c = "    ";
+			break;
+		}
 	} else
 		c = "    ";
 
-	db_printf("\t%s%s%sr%-3d,r%-3d,r%-3d", opcode, c,
-		  tab, rd, rs1, rs2);
+	db_printf("\t%s%s%sr%-3d,r%-3d,r%-3d", opcode, c, tab, rd, rs1, rs2);
 }
 
 static const struct opdesc {
@@ -560,130 +566,128 @@ static const struct opdesc {
 	void (*opfun)(int, const char *, long);
 	const char *farg;
 } opdecode[] = {
-
 	/* ORDER IS IMPORTANT BELOW */
-
-	{   0xF0000000U, 0x00000000U, immem, NULL},
-	{   0xF0000000U, 0x10000000U, immem, NULL},
-	{   0xF0000000U, 0x20000000U, immem, "st"},
-	{   0xF0000000U, 0x30000000U, immem, "lda"},
-
-	{   0xF8000000U, 0x40000000U, oimmed, "and"},
-	{   0xF8000000U, 0x48000000U, oimmed, "mask"},
-	{   0xF8000000U, 0x50000000U, oimmed, "xor"},
-	{   0xF8000000U, 0x58000000U, oimmed, "or"},
-	{   0xFC000000U, 0x60000000U, oimmed, "addu"},
-	{   0xFC000000U, 0x64000000U, oimmed, "subu"},
-	{   0xFC000000U, 0x68000000U, oimmed, "divu"},
-	{   0xFC000000U, 0x6C000000U, oimmed, "mul"},
-	{   0xFC000000U, 0x70000000U, oimmed, "add"},
-	{   0xFC000000U, 0x74000000U, oimmed, "sub"},
-	{   0xFC000000U, 0x78000000U, oimmed, "div"},
-	{   0xFC000000U, 0x7C000000U, oimmed, "cmp"},
-
-	{   0xFC00F800U, 0x80004000U, ctrlregs, "ldcr"},
-	{   0xFC00F800U, 0x80004800U, ctrlregs, "fldcr"},
-	{   0xFC00F800U, 0x80008000U, ctrlregs, "stcr"},
-	{   0xFC00F800U, 0x80008800U, ctrlregs, "fstcr"},
-	{   0xFC00F800U, 0x8000C000U, ctrlregs, "xcr"},
-	{   0xFC00F800U, 0x8000C800U, ctrlregs, "fxcr"},
-
-	{   0xFC00F800U, 0x84000000U, sindou, "fmul"},
-	{   0xFC1FFF80U, 0x84002000U, sindou, "flt"},
-	{   0xFC00F800U, 0x84002800U, sindou, "fadd"},
-	{   0xFC00F800U, 0x84003000U, sindou, "fsub"},
-	{   0xFC00F860U, 0x84003800U, sindou, "fcmp"},
-	{   0xFC1FFE60U, 0x84004800U, sindou, "int"},
-	{   0xFC1FFE60U, 0x84005000U, sindou, "nint"},
-	{   0xFC1FFE60U, 0x84005800U, sindou, "trnc"},
-	{   0xFC00F800U, 0x84007000U, sindou, "fdiv"},
-
-	{   0xF8000000U, 0xC0000000U, obranch, "br"},
-	{   0xF8000000U, 0xC8000000U, obranch, "bsr"},
-
-	{   0xF8000000U, 0xD0000000U, brcond, "bb0"},
-	{   0xF8000000U, 0xD8000000U, brcond, "bb1"},
-	{   0xF8000000U, 0xE8000000U, brcond, "bcnd"},
-
-	{   0xFC00FC00U, 0xF0008000U, obit, "clr"},
-	{   0xFC00FC00U, 0xF0008800U, obit, "set"},
-	{   0xFC00FC00U, 0xF0009000U, obit, "ext"},
-	{   0xFC00FC00U, 0xF0009800U, obit, "extu"},
-	{   0xFC00FC00U, 0xF000A000U, obit, "mak"},
-	{   0xFC00FC00U, 0xF000A800U, obit, "rot"},
-
-	{   0xFC00FE00U, 0xF000D000U, otrap, "tb0"},
-	{   0xFC00FE00U, 0xF000D800U, otrap, "tb1"},
-	{   0xFC00FE00U, 0xF000E800U, otrap, "tcnd"},
-
-	{   0xFC00F2E0U, 0xF4000000U, nimmem, NULL},
-	{   0xFC00F2E0U, 0xF4000200U, nimmem, NULL},
-	{   0xFC00F2E0U, 0xF4001000U, nimmem, NULL},
-	{   0xFC00F2E0U, 0xF4001200U, nimmem, NULL},
-	{   0xFC00F2E0U, 0xF4002000U, nimmem, "st"},
-	{   0xFC00F2E0U, 0xF4002200U, nimmem, "st"},
-	{   0xFC00F2E0U, 0xF4003000U, nimmem, "lda"},
-	{   0xFC00F2E0U, 0xF4003200U, nimmem, "lda"},
-
-	{   0xFC00FBE0U, 0xF4004000U, lognim, "and"},
-	{   0xFC00FBE0U, 0xF4005000U, lognim, "xor"},
-	{   0xFC00FBE0U, 0xF4005800U, lognim, "or"},
-
-	{   0xFC00FCE0U, 0xF4006000U, onimmed, "addu"},
-	{   0xFC00FCE0U, 0xF4006400U, onimmed, "subu"},
-	{   0xFC00FCE0U, 0xF4006800U, onimmed, "divu"},
-	{   0xFC00FCE0U, 0xF4006C00U, onimmed, "mul"},
-	{   0xFC00FCE0U, 0xF4007000U, onimmed, "add"},
-	{   0xFC00FCE0U, 0xF4007400U, onimmed, "sub"},
-	{   0xFC00FCE0U, 0xF4007800U, onimmed, "div"},
-	{   0xFC00FCE0U, 0xF4007C00U, onimmed, "cmp"},
-
-	{   0xFC00FFE0U, 0xF4008000U, bitman, "clr"},
-	{   0xFC00FFE0U, 0xF4008800U, bitman, "set"},
-	{   0xFC00FFE0U, 0xF4009000U, bitman, "ext"},
-	{   0xFC00FFE0U, 0xF4009800U, bitman, "extu"},
-	{   0xFC00FFE0U, 0xF400A000U, bitman, "mak"},
-	{   0xFC00FFE0U, 0xF400A800U, bitman, "rot"},
-
-	{   0xFC00FBE0U, 0xF400C000U, jump, "jmp"},
-	{   0xFC00FBE0U, 0xF400C800U, jump, "jsr"},
-
-	{   0xFC00FFE0U, 0xF400E800U, instset, "ff1"},
-	{   0xFC00FFE0U, 0xF400EC00U, instset, "ff0"},
-	{   0xFC00FFE0U, 0xF400F800U, instset, "tbnd"},
-	{   0xFC00FFE0U, 0xF400FC00U, instset, "rte"},
-	{   0xFC000000U, 0xF8000000U, instset, "tbnd"},
-	{   0, 0, NULL, NULL}
+	{ 0xf0000000,	0x00000000,	immem,		NULL },
+	{ 0xf0000000,	0x10000000,	immem,		NULL },
+	{ 0xf0000000,	0x20000000,	immem,		"st" },
+	{ 0xf0000000,	0x30000000,	immem,		"lda" },
+
+	{ 0xf8000000,	0x40000000,	oimmed,		"and" },
+	{ 0xf8000000,	0x48000000,	oimmed,		"mask" },
+	{ 0xf8000000,	0x50000000,	oimmed,		"xor" },
+	{ 0xf8000000,	0x58000000,	oimmed,		"or" },
+	{ 0xfc000000,	0x60000000,	oimmed,		"addu" },
+	{ 0xfc000000,	0x64000000,	oimmed,		"subu" },
+	{ 0xfc000000,	0x68000000,	oimmed,		"divu" },
+	{ 0xfc000000,	0x6c000000,	oimmed,		"mul" },
+	{ 0xfc000000,	0x70000000,	oimmed,		"add" },
+	{ 0xfc000000,	0x74000000,	oimmed,		"sub" },
+	{ 0xfc000000,	0x78000000,	oimmed,		"div" },
+	{ 0xfc000000,	0x7c000000,	oimmed,		"cmp" },
+
+	{ 0xfc00f800,	0x80004000,	ctrlregs,	"ldcr" },
+	{ 0xfc00f800,	0x80004800,	ctrlregs,	"fldcr" },
+	{ 0xfc00f800,	0x80008000,	ctrlregs,	"stcr" },
+	{ 0xfc00f800,	0x80008800,	ctrlregs,	"fstcr" },
+	{ 0xfc00f800,	0x8000c000,	ctrlregs,	"xcr" },
+	{ 0xfc00f800,	0x8000c800,	ctrlregs,	"fxcr" },
+
+	{ 0xfc00f800,	0x84000000,	sindou,		"fmul" },
+	{ 0xfc1fff80,	0x84002000,	sindou,		"flt" },
+	{ 0xfc00f800,	0x84002800,	sindou,		"fadd" },
+	{ 0xfc00f800,	0x84003000,	sindou,		"fsub" },
+	{ 0xfc00f860,	0x84003800,	sindou,		"fcmp" },
+	{ 0xfc1ffe60,	0x84004800,	sindou,		"int" },
+	{ 0xfc1ffe60,	0x84005000,	sindou,		"nint" },
+	{ 0xfc1ffe60,	0x84005800,	sindou,		"trnc" },
+	{ 0xfc00f800,	0x84007000,	sindou,		"fdiv" },
+
+	{ 0xf8000000,	0xc0000000,	obranch,	"br" },
+	{ 0xf8000000,	0xc8000000,	obranch,	"bsr" },
+
+	{ 0xf8000000,	0xd0000000,	brcond,		"bb0" },
+	{ 0xf8000000,	0xd8000000,	brcond,		"bb1" },
+	{ 0xf8000000,	0xe8000000,	brcond,		"bcnd" },
+
+	{ 0xfc00fc00,	0xf0008000,	obit,		"clr" },
+	{ 0xfc00fc00,	0xf0008800,	obit,		"set" },
+	{ 0xfc00fc00,	0xf0009000,	obit,		"ext" },
+	{ 0xfc00fc00,	0xf0009800,	obit,		"extu" },
+	{ 0xfc00fc00,	0xf000a000,	obit,		"mak" },
+	{ 0xfc00fc00,	0xf000a800,	obit,		"rot" },
+
+	{ 0xfc00fe00,	0xf000d000,	otrap,		"tb0" },
+	{ 0xfc00fe00,	0xf000d800,	otrap,		"tb1" },
+	{ 0xfc00fe00,	0xf000e800,	otrap,		"tcnd" },
+
+	{ 0xfc00f2e0,	0xf4000000,	nimmem,		NULL },
+	{ 0xfc00f2e0,	0xf4000200,	nimmem,		NULL },
+	{ 0xfc00f2e0,	0xf4001000,	nimmem,		NULL },
+	{ 0xfc00f2e0,	0xf4001200,	nimmem,		NULL },
+	{ 0xfc00f2e0,	0xf4002000,	nimmem,		"st" },
+	{ 0xfc00f2e0,	0xf4002200,	nimmem,		"st" },
+	{ 0xfc00f2e0,	0xf4003000,	nimmem,		"lda" },
+	{ 0xfc00f2e0,	0xf4003200,	nimmem,		"lda" },
+
+	{ 0xfc00fbe0,	0xf4004000,	lognim,		"and" },
+	{ 0xfc00fbe0,	0xf4005000,	lognim,		"xor" },
+	{ 0xfc00fbe0,	0xf4005800,	lognim,		"or" },
+
+	{ 0xfc00fce0,	0xf4006000,	onimmed,	"addu" },
+	{ 0xfc00fce0,	0xf4006400,	onimmed,	"subu" },
+	{ 0xfc00fce0,	0xf4006800,	onimmed,	"divu" },
+	{ 0xfc00fce0,	0xf4006c00,	onimmed,	"mul" },
+	{ 0xfc00fce0,	0xf4007000,	onimmed,	"add" },
+	{ 0xfc00fce0,	0xf4007400,	onimmed,	"sub" },
+	{ 0xfc00fce0,	0xf4007800,	onimmed,	"div" },
+	{ 0xfc00fce0,	0xf4007c00,	onimmed,	"cmp" },
+
+	{ 0xfc00ffe0,	0xf4008000,	bitman,		"clr" },
+	{ 0xfc00ffe0,	0xf4008800,	bitman,		"set" },
+	{ 0xfc00ffe0,	0xf4009000,	bitman,		"ext" },
+	{ 0xfc00ffe0,	0xf4009800,	bitman,		"extu" },
+	{ 0xfc00ffe0,	0xf400a000,	bitman,		"mak" },
+	{ 0xfc00ffe0,	0xf400a800,	bitman,		"rot" },
+
+	{ 0xfc00fbe0,	0xf400c000,	jump,		"jmp" },
+	{ 0xfc00fbe0,	0xf400c800,	jump,		"jsr" },
+
+	{ 0xfc00ffe0,	0xf400e800,	instset,	"ff1" },
+	{ 0xfc00ffe0,	0xf400ec00,	instset,	"ff0" },
+	{ 0xfc00ffe0,	0xf400f800,	instset,	"tbnd" },
+	{ 0xfc00ffe0,	0xf400fc00,	instset,	"rte" },
+	{ 0xfc000000,	0xf8000000,	instset,	"tbnd" },
+	{ 0,		0,		NULL,		NULL }
 };
 
-static const char *badop = "\t???";
-
 int
 m88k_print_instruction(unsigned iadr, long inst)
 {
 	const struct opdesc *p;
 
-	/* this messes up "orb" instructions ever so slightly, */
-	/* but keeps us in sync between routines... */
+	/*
+	 * This messes up "orb" instructions ever so slightly,
+	 * but keeps us in sync between routines...
+	 */
 	if (inst == 0) {
-		db_printf ("\t.word 0");
+		db_printf("\t.word 0");
 	} else {
 		for (p = opdecode; p->mask; p++)
 			if ((inst & p->mask) == p->match) {
-				(*p->opfun) (inst, p->farg, iadr);
+				(*p->opfun)(inst, p->farg, iadr);
 				break;
 			}
 		if (!p->mask)
-			db_printf (badop);
+			db_printf("\t.word 0x%x", inst);
 	}
 
-	return iadr+4;
+	return (iadr + 4);
 }
 
 db_addr_t
 db_disasm(db_addr_t loc, boolean_t altfmt)
 {
 	m88k_print_instruction(loc, db_get_value(loc, 4, FALSE));
-	db_printf ("\n");
-	return loc+4;
+	db_printf("\n");
+	return (loc + 4);
 }