KNF and remove function/line number references from log messages

no functional change

1 files changed, 225 insertions, 277 deletions

diff --git a/sys/dev/pci/if_san_xilinx.c b/sys/dev/pci/if_san_xilinx.c
index f0ee028ef88..994a2135158 100644
--- a/sys/dev/pci/if_san_xilinx.c
+++ b/sys/dev/pci/if_san_xilinx.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: if_san_xilinx.c,v 1.13 2005/09/14 05:08:05 canacar Exp $	*/
+/*	$OpenBSD: if_san_xilinx.c,v 1.14 2005/09/17 15:10:31 canacar Exp $	*/
 
 /*-
  * Copyright (c) 2001-2004 Sangoma Technologies (SAN)
@@ -300,14 +300,12 @@ wan_xilinx_init(sdla_t *card)
 	/* TE1 Make special hardware initialization for T1/E1 board */
 
 	if (IS_TE1(&card->fe_te.te_cfg)) {
-
 		card->write_front_end_reg = write_front_end_reg;
 		card->read_front_end_reg = read_front_end_reg;
 		card->te_enable_timer = enable_timer;
 		card->te_link_state = handle_front_end_state;
-	} else {
+	} else
 		card->front_end_status = FE_CONNECTED;
-	}
 
 	/* WARNING: After this point the init function
 	 * must return with 0.  The following bind
@@ -330,9 +328,9 @@ wan_xilinx_init(sdla_t *card)
 
 	/* allocate and initialize private data */
 	sc = malloc(sizeof(xilinx_softc_t), M_DEVBUF, M_NOWAIT);
-	if (sc == NULL) {
+	if (sc == NULL)
 		return (NULL);
-	}
+
 	memset(sc, 0, sizeof(xilinx_softc_t));
 	ifp = (struct ifnet *)&sc->common.ifp;
 	ifp->if_softc = sc;
@@ -342,9 +340,8 @@ wan_xilinx_init(sdla_t *card)
 		return (NULL);
 	}
 
-
 	strlcpy(sc->if_name, ifp->if_xname, IFNAMSIZ);
-	sc->first_time_slot=-1;
+	sc->first_time_slot = -1;
 	sc->time_slot_map = 0;
 
 	IFQ_SET_MAXLEN(&sc->wp_tx_free_list, MAX_TX_BUF);
@@ -361,6 +358,7 @@ wan_xilinx_init(sdla_t *card)
 	xilinx_delay(1);
 
 	ifmedia_init(&sc->common.ifm, 0, wan_ifmedia_upd, wan_ifmedia_sts);
+
 	if (IS_TE1(&card->fe_te.te_cfg)) {
 		ifmedia_add(&sc->common.ifm, IFM_TDM|IFM_TDM_T1, 0, NULL);
 		ifmedia_add(&sc->common.ifm, IFM_TDM|IFM_TDM_T1_AMI, 0, NULL);
@@ -382,6 +380,7 @@ wan_xilinx_init(sdla_t *card)
 		 * front end types.
 		 */
 	}
+
 	return (sc);
 }
 
@@ -416,9 +415,11 @@ wan_xilinx_release(sdla_t* card, struct ifnet* ifp)
 		m_freem(sc->rx_dma_mbuf);
 		sc->rx_dma_mbuf = NULL;
 	}
+
 	wanpipe_generic_unregister(ifp);
 	ifp->if_softc = NULL;
 	free(sc, M_DEVBUF);
+
 	return (0);
 }
 
@@ -431,7 +432,6 @@ wan_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmreq)
 	WAN_ASSERT1(common == NULL);
 	ifm = &common->ifm;
 	ifmreq->ifm_active = ifm->ifm_cur->ifm_media;
-	return;
 }
 
 static int
@@ -443,6 +443,7 @@ wan_ifmedia_upd(struct ifnet *ifp)
 	WAN_ASSERT(common == NULL);
 	WAN_ASSERT(common->card == NULL);
 	card = (sdla_t *)common->card;
+
 	if (IS_TE1(&card->fe_te.te_cfg))
 		return (sdla_te_setcfg(ifp, &common->ifm));
 
@@ -465,11 +466,13 @@ wan_xilinx_up(struct ifnet *ifp)
 	WAN_ASSERT(sc == NULL);
 	WAN_ASSERT(sc->common.card == NULL);
 	card = (sdla_t *)sc->common.card;
-	if (card->state != WAN_DISCONNECTED) {
+
+	if (card->state != WAN_DISCONNECTED)
 		return (0);
-	}
+
 	sc->time_slot_map = card->fe_te.te_cfg.active_ch;
 	sc->dma_mtu = xilinx_valid_mtu(ifp->if_mtu+100);
+
 	if (!sc->dma_mtu) {
 		log(LOG_INFO, "%s:%s: Error invalid MTU %d\n",
 		    card->devname, sc->if_name, ifp->if_mtu);
@@ -481,14 +484,12 @@ wan_xilinx_up(struct ifnet *ifp)
 	    card->devname, card->u.xilinx.dma_per_ch, sc->dma_mtu);
 #endif
 	err = aft_alloc_rx_dma_buff(card, sc, card->u.xilinx.dma_per_ch);
-	if (err) {
+	if (err)
 		return (EINVAL);
-	}
 
 	err = xilinx_chip_configure(card);
-	if (err) {
+	if (err)
 		return (EINVAL);
-	}
 
 	card->isr = &wp_xilinx_isr;
 
@@ -511,6 +512,7 @@ wan_xilinx_up(struct ifnet *ifp)
 	sc->ignore_modem = 0x0F;
 	bit_clear((u_int8_t *)&card->critical, CARD_DOWN);
 	port_set_state(card, WAN_CONNECTING);
+
 	return (err);
 }
 
@@ -522,9 +524,9 @@ wan_xilinx_down(struct ifnet *ifp)
 	struct mbuf	*m;
 	int		s;
 
-	if (card->state == WAN_DISCONNECTED) {
+	if (card->state == WAN_DISCONNECTED)
 		return (0);
-	}
+
 	xilinx_dev_close(card, sc);
 
 	/* Disable DMA ENGINE before we perform
@@ -537,9 +539,8 @@ wan_xilinx_down(struct ifnet *ifp)
 	timeout_del(&card->u.xilinx.led_timer);
 
 	/* TE1 - Unconfiging, only on shutdown */
-	if (IS_TE1(&card->fe_te.te_cfg)) {
+	if (IS_TE1(&card->fe_te.te_cfg))
 		sdla_te_unconfig(card);
-	}
 
 	s = splnet();
 
@@ -600,11 +601,10 @@ wan_xilinx_send(struct mbuf* m, struct ifnet* ifp)
 	 * attempt to send any more packets until we clear
 	 * this condition */
 
-	if (m == NULL) {
+	if (m == NULL)
 		/* This should never happen. Just a sanity check.
 		 */
 		return (EINVAL);
-	}
 
 	if (card->state != WAN_CONNECTED) {
 		/*
@@ -615,7 +615,6 @@ wan_xilinx_send(struct mbuf* m, struct ifnet* ifp)
 		return (EINVAL);
 
 	} else {
-
 		if (IF_QFULL(&sc->wp_tx_pending_list)) {
 			int err;
 #ifdef DEBUG_TX
@@ -627,13 +626,13 @@ wan_xilinx_send(struct mbuf* m, struct ifnet* ifp)
 			 * from tx_pending queue (first)
 			 */
 			err = xilinx_dma_tx(card, sc);
-			if (!err && !IF_QFULL(&sc->wp_tx_pending_list)) {
+			if (!err && !IF_QFULL(&sc->wp_tx_pending_list))
 				/*
 				 * On success, we have place for the new
 				 * tx packet, try to send it now!
 				 */
 				goto wan_xilinx_dma_tx_try;
-			}
+
 			/*
 			 * Tx pedning queue is full. I can't accept new
 			 * tx packet, drop this packet and set interface
@@ -641,6 +640,7 @@ wan_xilinx_send(struct mbuf* m, struct ifnet* ifp)
 			 */
 			m_freem(m);
 			ifp->if_flags |= IFF_OACTIVE;
+
 			return (EBUSY);
 		} else {
 wan_xilinx_dma_tx_try:
@@ -661,59 +661,55 @@ wan_xilinx_ioctl(struct ifnet *ifp, int cmd, struct ifreq *ifr)
 	wan_udp_pkt_t	*wan_udp_pkt;
 	int err = 0;
 
-	if (!sc) {
+	if (!sc)
 		return (ENODEV);
-	}
+
 	card = (sdla_t *)sc->common.card;
 
-	switch (cmd)
-	{
-		case SIOC_WANPIPE_PIPEMON:
+	switch (cmd) {
+	case SIOC_WANPIPE_PIPEMON:
 
-			if ((err = suser(curproc, 0)) != 0)
-				break;
+		if ((err = suser(curproc, 0)) != 0)
+			break;
 
-			if (IF_QFULL(&sc->udp_queue)) {
-				return (EBUSY);
-			}
+		if (IF_QFULL(&sc->udp_queue))
+			return (EBUSY);
 
-			/*
-			 * For performance reasons test the critical
-			 * here before spin lock
-			 */
-			if (bit_test((u_int8_t *)&card->in_isr, 0)) {
-				return (EBUSY);
-			}
+		/*
+		 * For performance reasons test the critical
+		 * here before spin lock
+		 */
+		if (bit_test((u_int8_t *)&card->in_isr, 0))
+			return (EBUSY);
 
-			m = wan_mbuf_alloc(sizeof(wan_udp_pkt_t));
-			if (m == NULL) {
-				return (ENOMEM);
-			}
-			wan_udp_pkt = mtod(m, wan_udp_pkt_t *);
-			if (copyin(ifr->ifr_data, &wan_udp_pkt->wan_udp_hdr,
-			    sizeof(wan_udp_hdr_t))) {
-				m_freem(m);
-				return (EFAULT);
-			}
-			IF_ENQUEUE(&sc->udp_queue, m);
+		m = wan_mbuf_alloc(sizeof(wan_udp_pkt_t));
+		if (m == NULL)
+			return (ENOMEM);
 
-			process_udp_mgmt_pkt(card, ifp, sc, 1);
+		wan_udp_pkt = mtod(m, wan_udp_pkt_t *);
+		if (copyin(ifr->ifr_data, &wan_udp_pkt->wan_udp_hdr,
+		    sizeof(wan_udp_hdr_t))) {
+			m_freem(m);
+			return (EFAULT);
+		}
+		IF_ENQUEUE(&sc->udp_queue, m);
 
-			if (copyout(&wan_udp_pkt->wan_udp_hdr, ifr->ifr_data,
-			    sizeof(wan_udp_hdr_t))) {
-				m_freem(m);
-				return (EFAULT);
-			}
+		process_udp_mgmt_pkt(card, ifp, sc, 1);
 
-			IF_DEQUEUE(&sc->udp_queue, m);
+		if (copyout(&wan_udp_pkt->wan_udp_hdr, ifr->ifr_data,
+		    sizeof(wan_udp_hdr_t))) {
 			m_freem(m);
-			return (0);
+			return (EFAULT);
+		}
 
-		default:
-			if (card->ioctl) {
-				err = card->ioctl(ifp, cmd, ifr);
-			}
-			break;
+		IF_DEQUEUE(&sc->udp_queue, m);
+		m_freem(m);
+		return (0);
+
+	default:
+		if (card->ioctl)
+			err = card->ioctl(ifp, cmd, ifr);
+		break;
 	}
 
 	return (err);
@@ -804,7 +800,6 @@ process_udp_mgmt_pkt(sdla_t* card, struct ifnet* ifp,
 			break;
 
 		case DISABLE_TRACING:
-
 			wan_udp_pkt->wan_udp_return_code = WAN_CMD_OK;
 
 			if (bit_test((u_int8_t *)
@@ -818,7 +813,6 @@ process_udp_mgmt_pkt(sdla_t* card, struct ifnet* ifp,
 				IF_PURGE(&trace_info->ifq);
 				log(LOG_INFO, "%s: Disabling ADSL trace\n",
 				    card->devname);
-
 			} else {
 				/*
 				 * set return code to line trace already
@@ -830,7 +824,6 @@ process_udp_mgmt_pkt(sdla_t* card, struct ifnet* ifp,
 			break;
 
 		case GET_TRACE_INFO:
-
 			if (bit_test((u_int8_t *)
 			    &trace_info->tracing_enabled, 0)) {
 				trace_info->trace_timeout = ticks;
@@ -869,9 +862,8 @@ process_udp_mgmt_pkt(sdla_t* card, struct ifnet* ifp,
 				    &wan_udp_pkt->wan_udp_data[buffer_length]);
 				buffer_length += m0->m_pkthdr.len;
 				IF_DEQUEUE(&trace_info->ifq, m0);
-				if (m0) {
+				if (m0)
 					m_freem(m0);
-				}
 				wan_udp_pkt->wan_udp_aft_num_frames++;
 			}
 			/* set the data length and return code */
@@ -897,8 +889,8 @@ process_udp_mgmt_pkt(sdla_t* card, struct ifnet* ifp,
 
 			if (IS_TE1(&card->fe_te.te_cfg)) {
 				sdla_te_udp(card,
-					    &wan_udp_pkt->wan_udp_cmd,
-					    &wan_udp_pkt->wan_udp_data[0]);
+				    &wan_udp_pkt->wan_udp_cmd,
+				    &wan_udp_pkt->wan_udp_data[0]);
 			} else {
 				if (wan_udp_pkt->wan_udp_command ==
 				    WAN_GET_MEDIA_TYPE) {
@@ -938,7 +930,6 @@ process_udp_mgmt_pkt(sdla_t* card, struct ifnet* ifp,
 
 	wan_udp_pkt->wan_udp_request_reply = UDPMGMT_REPLY;
 	return (1);
-
 }
 
 /*
@@ -1051,12 +1042,10 @@ xilinx_chip_configure(sdla_t *card)
 	DELAY(10);
 
 	err = aft_core_ready(card);
-	if (err != 0) {
+	if (err != 0)
 		log(LOG_INFO, "%s: WARNING: HDLC Core Not Ready: B4 TE CFG!\n",
 		    card->devname);
 
-	}
-
 	log(LOG_INFO, "%s: Configuring A101 PMC T1/E1/J1 Front End\n",
 	    card->devname);
 
@@ -1080,12 +1069,12 @@ xilinx_chip_configure(sdla_t *card)
 
 		sdla_bus_write_4(card->hw, XILINX_CHIP_CFG_REG, reg);
 		return (err);
-	} else {
+	}
+
 #ifdef DEBUG_INIT
-		log(LOG_INFO, "%s: HDLC Core Ready 0x%08X\n",
-		    card->devname, reg);
+	log(LOG_INFO, "%s: HDLC Core Ready 0x%08X\n",
+	    card->devname, reg);
 #endif
- }
 
 	xilinx_delay(1);
 
@@ -1187,9 +1176,8 @@ xilinx_dev_configure(sdla_t *card, xilinx_softc_t *sc)
 
 	sc->logic_ch_num=-1;
 
-	if (!IS_TE1(&card->fe_te.te_cfg)) {
+	if (!IS_TE1(&card->fe_te.te_cfg))
 		return (EINVAL);
-	}
 
 	if (IS_E1(&card->fe_te.te_cfg)) {
 		log(LOG_DEBUG, "%s: Time Slot Orig 0x%lX  Shifted 0x%lX\n",
@@ -1239,8 +1227,8 @@ xilinx_dev_configure(sdla_t *card, xilinx_softc_t *sc)
 #endif
 			if (bit_test((u_int8_t *)
 			    &card->u.xilinx.time_slot_map, i)) {
-				log(LOG_INFO, "%s: Channel/Time "
-				    "Slot resource conflict!\n", card->devname);
+				log(LOG_INFO, "%s: Channel/Time Slot "
+				    "resource conflict!\n", card->devname);
 				log(LOG_INFO, "%s: %s: Channel/Time Slot "
 				    "%ld, aready in use!\n",
 				    card->devname, sc->if_name, (i+1));
@@ -1257,9 +1245,8 @@ xilinx_dev_configure(sdla_t *card, xilinx_softc_t *sc)
 
 	sc->logic_ch_num = request_xilinx_logical_channel_num(card,
 	    sc, &free_logic_ch);
-	if (sc->logic_ch_num == -1) {
+	if (sc->logic_ch_num == -1)
 		return (EBUSY);
-	}
 
 	xilinx_delay(1);
 
@@ -1270,30 +1257,28 @@ xilinx_dev_configure(sdla_t *card, xilinx_softc_t *sc)
 
 			sdla_bus_read_4(card->hw,
 			    XILINX_TIMESLOT_HDLC_CHAN_REG, &reg);
-			reg&=~TIMESLOT_BIT_MASK;
+			reg &= ~TIMESLOT_BIT_MASK;
 
 			/* FIXME do not hardcode !*/
-			reg &= HDLC_LCH_TIMESLOT_MASK; /* mask not valid bits */
-
+			reg &= HDLC_LCH_TIMESLOT_MASK; /* mask not valid bits*/
 
 			/* Select a Timeslot for configuration */
 			sdla_bus_write_4(card->hw,
 			    XILINX_TIMESLOT_HDLC_CHAN_REG,
 			    (reg | (i << TIMESLOT_BIT_SHIFT)));
 
-
-			reg = sc->logic_ch_num&CONTROL_RAM_DATA_MASK;
+			reg = sc->logic_ch_num & CONTROL_RAM_DATA_MASK;
 
 #ifdef TRUE_FIFO_SIZE
-			reg |= (sc->fifo_size_code&HDLC_FIFO_SIZE_MASK) <<
+			reg |= (sc->fifo_size_code & HDLC_FIFO_SIZE_MASK) <<
 			    HDLC_FIFO_SIZE_SHIFT;
 #else
-			reg |= (HARD_FIFO_CODE&HDLC_FIFO_SIZE_MASK) <<
-			    HDLC_FIFO_SIZE_SHIFT;
+			reg |= (HARD_FIFO_CODE &
+			    HDLC_FIFO_SIZE_MASK) << HDLC_FIFO_SIZE_SHIFT;
 #endif /* TRUE_FIFO_SIZE */
 
-			reg |= (sc->fifo_base_addr&HDLC_FIFO_BASE_ADDR_MASK) <<
-			    HDLC_FIFO_BASE_ADDR_SHIFT;
+			reg |= (sc->fifo_base_addr & HDLC_FIFO_BASE_ADDR_MASK)
+			    << HDLC_FIFO_BASE_ADDR_SHIFT;
 
 #ifdef DEBUG_INIT
 			log(LOG_INFO, "Setting Timeslot %ld to logic "
@@ -1322,7 +1307,7 @@ xilinx_dev_configure(sdla_t *card, xilinx_softc_t *sc)
 				/* Select a Timeslot for configuration */
 				sdla_bus_write_4(card->hw,
 				    XILINX_TIMESLOT_HDLC_CHAN_REG,
-				    (reg|(i<<TIMESLOT_BIT_SHIFT)));
+				    (reg | (i << TIMESLOT_BIT_SHIFT)));
 
 				reg = free_logic_ch&CONTROL_RAM_DATA_MASK;
 
@@ -1385,11 +1370,11 @@ xilinx_dev_configure(sdla_t *card, xilinx_softc_t *sc)
 	/* Select an HDLC logic channel for configuration */
 	sdla_bus_read_4(card->hw, XILINX_TIMESLOT_HDLC_CHAN_REG, &reg);
 
-	reg&=~HDLC_LOGIC_CH_BIT_MASK;
-	reg&= HDLC_LCH_TIMESLOT_MASK;         /* mask not valid bits */
+	reg &= ~HDLC_LOGIC_CH_BIT_MASK;
+	reg &= HDLC_LCH_TIMESLOT_MASK;         /* mask not valid bits */
 
 	sdla_bus_write_4(card->hw, XILINX_TIMESLOT_HDLC_CHAN_REG,
-	    (reg|(sc->logic_ch_num&HDLC_LOGIC_CH_BIT_MASK)));
+	    (reg | (sc->logic_ch_num & HDLC_LOGIC_CH_BIT_MASK)));
 
 	reg = 0;
 
@@ -1421,10 +1406,10 @@ xilinx_dev_unconfigure(sdla_t *card, xilinx_softc_t *sc)
 
 		sdla_bus_read_4(card->hw, XILINX_TIMESLOT_HDLC_CHAN_REG, &reg);
 		reg &= ~HDLC_LOGIC_CH_BIT_MASK;
-		reg &= HDLC_LCH_TIMESLOT_MASK;         /* mask not valid bits */
+		reg &= HDLC_LCH_TIMESLOT_MASK;	/* mask not valid bits */
 
 		sdla_bus_write_4(card->hw, XILINX_TIMESLOT_HDLC_CHAN_REG,
-		    (reg | (sc->logic_ch_num&HDLC_LOGIC_CH_BIT_MASK)));
+		    (reg | (sc->logic_ch_num & HDLC_LOGIC_CH_BIT_MASK)));
 
 		reg = 0x00020000;
 		xilinx_write_ctrl_hdlc(card, sc->first_time_slot,
@@ -1464,22 +1449,19 @@ xilinx_dev_unconfigure(sdla_t *card, xilinx_softc_t *sc)
 		 */
 		s = splnet();
 		free_xilinx_logical_channel_num(card, sc->logic_ch_num);
-		for (i = 0; i < card->u.xilinx.num_of_time_slots; i++) {
-			if (bit_test((u_int8_t *)&sc->time_slot_map, i)) {
+		for (i = 0; i < card->u.xilinx.num_of_time_slots; i++)
+			if (bit_test((u_int8_t *)&sc->time_slot_map, i))
 				--sc->num_of_time_slots;
-			}
-		}
+
 		free_fifo_baddr_and_size(card, sc);
 		splx(s);
 
 		sc->logic_ch_num = -1;
 
-		for (i = 0; i < card->u.xilinx.num_of_time_slots; i++) {
-			if (bit_test((u_int8_t *)&sc->time_slot_map, i)) {
+		for (i = 0; i < card->u.xilinx.num_of_time_slots; i++)
+			if (bit_test((u_int8_t *)&sc->time_slot_map, i))
 				bit_clear((u_int8_t *)
 				    &card->u.xilinx.time_slot_map, i);
-			}
-		}
 	}
 }
 
@@ -1500,7 +1482,8 @@ xilinx_init_rx_dev_fifo(sdla_t *card, xilinx_softc_t *sc, unsigned char wait)
 	bit_set((u_int8_t *)&reg, INIT_DMA_FIFO_CMD_BIT);
 
 #ifdef DEBUG_INIT
-	log(LOG_DEBUG, "%s: Clearing RX Fifo DmaDescr=(0x%X) Reg=(0x%X) (%s)\n",
+	log(LOG_DEBUG,
+	    "%s: Clearing RX Fifo DmaDescr=(0x%X) Reg=(0x%X) (%s)\n",
 	    sc->if_name, dma_descr, reg, __FUNCTION__);
 #endif
 
@@ -1518,19 +1501,17 @@ xilinx_init_rx_dev_fifo(sdla_t *card, xilinx_softc_t *sc, unsigned char wait)
 		}
 
 #ifdef DEBUG_INIT
-		if (timeout) {
+		if (timeout)
 			log(LOG_INFO, "%s:%s: Error: Rx fifo reset "
 			    "timedout %u us\n", card->devname,
 			    sc->if_name, i * FIFO_RESET_TIMEOUT_US);
-		} else {
+		else
 			log(LOG_INFO, "%s:%s: Rx Fifo reset "
 			    "successful %u us\n", card->devname, sc->if_name,
 			    i * FIFO_RESET_TIMEOUT_US);
-		}
 #endif
-	} else {
+	} else
 		timeout = 0;
-	}
 
 	return (timeout);
 }
@@ -1550,7 +1531,8 @@ xilinx_init_tx_dev_fifo(sdla_t *card, xilinx_softc_t *sc, unsigned char wait)
 	bit_set((u_int8_t *)&reg, INIT_DMA_FIFO_CMD_BIT);
 
 #ifdef DEBUG_INIT
-	log(LOG_DEBUG, "%s: Clearing TX Fifo DmaDescr=(0x%X) Reg=(0x%X) (%s)\n",
+	log(LOG_DEBUG,
+	    "%s: Clearing TX Fifo DmaDescr=(0x%X) Reg=(0x%X) (%s)\n",
 	    sc->if_name, dma_descr, reg, __FUNCTION__);
 #endif
 	sdla_bus_write_4(card->hw, dma_descr, reg);
@@ -1567,19 +1549,17 @@ xilinx_init_tx_dev_fifo(sdla_t *card, xilinx_softc_t *sc, unsigned char wait)
 		}
 
 #ifdef DEBUG_INIT
-		if (timeout) {
+		if (timeout)
 			log(LOG_INFO, "%s:%s: Error: Tx fifo reset "
 			    "timedout %u us\n", card->devname, sc->if_name,
 			    i * FIFO_RESET_TIMEOUT_US);
-		} else {
+		else
 			log(LOG_INFO, "%s:%s: Tx Fifo reset "
 			    "successful %u us\n", card->devname, sc->if_name,
 			    i * FIFO_RESET_TIMEOUT_US);
-		}
 #endif
-	} else {
+	} else
 		timeout = 0;
-	}
 
 	return (timeout);
 }
@@ -1629,14 +1609,14 @@ xilinx_dev_close(sdla_t *card, xilinx_softc_t *sc)
 
 	reg = 0;
 
-       /* Select an HDLC logic channel for configuration */
+	/* Select an HDLC logic channel for configuration */
 	sdla_bus_read_4(card->hw, XILINX_TIMESLOT_HDLC_CHAN_REG, &reg);
 
 	reg &= ~HDLC_LOGIC_CH_BIT_MASK;
 	reg &= HDLC_LCH_TIMESLOT_MASK;         /* mask not valid bits */
 
 	sdla_bus_write_4(card->hw, XILINX_TIMESLOT_HDLC_CHAN_REG,
-	    (reg|(sc->logic_ch_num&HDLC_LOGIC_CH_BIT_MASK)));
+	    (reg | (sc->logic_ch_num & HDLC_LOGIC_CH_BIT_MASK)));
 
 
 	reg = 0;
@@ -1653,7 +1633,8 @@ xilinx_dev_close(sdla_t *card, xilinx_softc_t *sc)
 	/* FIXME: Cleanp up Tx and Rx buffers */
 }
 
-static int xilinx_dma_rx(sdla_t *card, xilinx_softc_t *sc)
+static int
+xilinx_dma_rx(sdla_t *card, xilinx_softc_t *sc)
 {
 	u_int32_t reg;
 	unsigned long dma_descr;
@@ -1705,9 +1686,9 @@ static int xilinx_dma_rx(sdla_t *card, xilinx_softc_t *sc)
 	/* Set the 32bit alignment of the data length.
 	 * Since we are setting up for rx, set this value
 	 * to Zero */
-	reg&=~(RxDMA_LO_ALIGNMENT_BIT_MASK);
+	reg &= ~(RxDMA_LO_ALIGNMENT_BIT_MASK);
 
-	dma_descr=(sc->logic_ch_num<<4) + XILINX_RxDMA_DESCRIPTOR_LO;
+	dma_descr = (sc->logic_ch_num<<4) + XILINX_RxDMA_DESCRIPTOR_LO;
 
 #ifdef DEBUG_RX
 	log(LOG_INFO, "%s: RxDMA_LO = 0x%X, BusAddr=0x%lX "
@@ -1793,7 +1774,6 @@ xilinx_dma_tx(sdla_t *card, xilinx_softc_t *sc)
 		sc->tx_dma_mbuf = NULL;
 	}
 
-
 	/* check queue pointers before starting transmission */
 
 	/* sanity check: make sure that DMA is in ready state */
@@ -1824,9 +1804,8 @@ xilinx_dma_tx(sdla_t *card, xilinx_softc_t *sc)
 			/* FIXME: We need to split this frame into
 			 *        multiple parts.  For now though
 			 *        just drop it :) */
-			log(LOG_INFO, "%s: Tx len %d > %d (MAX TX DMA LEN) "
-			    "(%s:%d)!\n", sc->if_name, len,
-			    MAX_XILINX_TX_DMA_SIZE, __FUNCTION__, __LINE__);
+			log(LOG_INFO, "%s: Tx len %d > %d (MAX TX DMA LEN)\n",
+			    sc->if_name, len, MAX_XILINX_TX_DMA_SIZE);
 			m_freem(m);
 			bit_clear((u_int8_t *)&sc->dma_status, TX_BUSY);
 			return (EINVAL);
@@ -1834,9 +1813,8 @@ xilinx_dma_tx(sdla_t *card, xilinx_softc_t *sc)
 
 		if (mtod(m, u_int32_t)  & 0x03) {
 			/* The mbuf should already be aligned */
-			log(LOG_INFO, "%s: TX packet not aligned "
-			    "(%s:%d)!\n", sc->if_name,
-			    MAX_XILINX_TX_DMA_SIZE, __FUNCTION__, __LINE__);
+			log(LOG_INFO, "%s: TX packet not aligned!\n",
+			    sc->if_name, MAX_XILINX_TX_DMA_SIZE);
 			m_freem(m);
 			bit_clear((u_int8_t *)&sc->dma_status, TX_BUSY);
 			return (EINVAL);
@@ -1850,9 +1828,8 @@ xilinx_dma_tx(sdla_t *card, xilinx_softc_t *sc)
 		log(LOG_INFO, "%s: Error: Tx Ptr not aligned "
 		    "to 32bit boundary!\n", card->devname);
 
-		if (m) {
+		if (m)
 			m_freem(m);
-		}
 
 		bit_clear((u_int8_t *)&sc->dma_status, TX_BUSY);
 		return (EINVAL);
@@ -1876,9 +1853,8 @@ xilinx_dma_tx(sdla_t *card, xilinx_softc_t *sc)
 	reg &= ~(TxDMA_LO_ALIGNMENT_BIT_MASK);
 	reg |= (len & 0x03);
 
-	if (len & 0x03) {
+	if (len & 0x03)
 		len_align = 1;
-	}
 
 #ifdef DEBUG_TX
 	log(LOG_INFO, "%s: TXDMA_LO=0x%X PhyAddr=0x%lX DmaDescr=0x%lX (%s)\n",
@@ -1893,7 +1869,8 @@ xilinx_dma_tx(sdla_t *card, xilinx_softc_t *sc)
 	reg |= (((len >> 2) + len_align) & TxDMA_HI_DMA_DATA_LENGTH_MASK);
 
 #ifdef TRUE_FIFO_SIZE
-	reg |= (sc->fifo_size_code & DMA_FIFO_SIZE_MASK) << DMA_FIFO_SIZE_SHIFT;
+	reg |= (sc->fifo_size_code & DMA_FIFO_SIZE_MASK) <<
+	    DMA_FIFO_SIZE_SHIFT;
 #else
 
 	reg |= (HARD_FIFO_CODE & DMA_FIFO_SIZE_MASK) << DMA_FIFO_SIZE_SHIFT;
@@ -1931,18 +1908,17 @@ xilinx_dma_tx_complete(sdla_t *card, xilinx_softc_t *sc)
 	log(LOG_INFO, "%s: TX DMA complete\n", card->devname);
 #endif
 	/* DEBUGTX */
-/*      sdla_bus_read_4(card->hw, 0x78, &tmp1); */
+/*	sdla_bus_read_4(card->hw, 0x78, &tmp1); */
 
 	dma_descr = (sc->logic_ch_num << 4) + XILINX_TxDMA_DESCRIPTOR_HI;
 	sdla_bus_read_4(card->hw, dma_descr, &reg);
 
 	if (!sc->tx_dma_mbuf) {
-
-		log(LOG_INFO, "%s: Critical Error: Tx DMA intr: no tx mbuf !\n",
+		log(LOG_INFO,
+		    "%s: Critical Error: Tx DMA intr: no tx mbuf !\n",
 		    card->devname);
 		bit_clear((u_int8_t *)&sc->dma_status, TX_BUSY);
 		return;
-
 	} else {
 		sc->tx_dma_addr = 0;
 		sc->tx_dma_len = 0;
@@ -1955,7 +1931,6 @@ xilinx_dma_tx_complete(sdla_t *card, xilinx_softc_t *sc)
 		 */
 
 		if (reg & TxDMA_HI_DMA_PCI_ERROR_RETRY_TOUT) {
-
 			log(LOG_INFO, "%s:%s: PCI Error: 'Retry' "
 			    "exceeds maximum (64k): Reg=0x%X!\n",
 			    card->devname, sc->if_name, reg);
@@ -1982,10 +1957,8 @@ xilinx_dma_tx_complete(sdla_t *card, xilinx_softc_t *sc)
 
 		xilinx_process_packet(sc);
 	}
-
 }
 
-
 static void
 xilinx_tx_post_complete(sdla_t *card, xilinx_softc_t *sc, struct mbuf *m)
 {
@@ -2004,41 +1977,38 @@ xilinx_tx_post_complete(sdla_t *card, xilinx_softc_t *sc, struct mbuf *m)
 #endif
 
 		/* Checking Tx DMA Go bit. Has to be '0' */
-		if (bit_test((u_int8_t *)&reg, TxDMA_HI_DMA_GO_READY_BIT)) {
+		if (bit_test((u_int8_t *)&reg, TxDMA_HI_DMA_GO_READY_BIT))
 			log(LOG_INFO, "%s:%s: Error: TxDMA Intr: "
 			    "GO bit set on Tx intr\n",
 			    card->devname, sc->if_name);
-		}
 
-		if (reg & TxDMA_HI_DMA_DATA_LENGTH_MASK) {
+		if (reg & TxDMA_HI_DMA_DATA_LENGTH_MASK)
 			log(LOG_INFO, "%s:%s: Error: TxDMA Length "
 			"not equal 0 \n", card->devname, sc->if_name);
-		}
 
 		/* Checking Tx DMA PCI error status. Has to be '0's */
-		if (reg&TxDMA_HI_DMA_PCI_ERROR_MASK) {
+		if (reg & TxDMA_HI_DMA_PCI_ERROR_MASK) {
 
-			if (reg & TxDMA_HI_DMA_PCI_ERROR_M_ABRT) {
+			if (reg & TxDMA_HI_DMA_PCI_ERROR_M_ABRT)
 				log(LOG_INFO, "%s:%s: Tx Error: "
 				    "Abort from Master: pci fatal error!\n",
 				    card->devname, sc->if_name);
-			}
-			if (reg & TxDMA_HI_DMA_PCI_ERROR_T_ABRT) {
+
+			if (reg & TxDMA_HI_DMA_PCI_ERROR_T_ABRT)
 				log(LOG_INFO, "%s:%s: Tx Error: "
 				    "Abort from Target: pci fatal error!\n",
 				    card->devname, sc->if_name);
-			}
+
 			if (reg & TxDMA_HI_DMA_PCI_ERROR_DS_TOUT) {
 				log(LOG_INFO, "%s:%s: Tx Warning: "
 				    "PCI Latency Timeout!\n",
 				    card->devname, sc->if_name);
 				goto tx_post_ok;
 			}
-			if (reg & TxDMA_HI_DMA_PCI_ERROR_RETRY_TOUT) {
+			if (reg & TxDMA_HI_DMA_PCI_ERROR_RETRY_TOUT)
 				log(LOG_INFO, "%s:%s: Tx Error: 'Retry' "
 				    "exceeds maximum (64k): pci fatal error!\n",
 				    card->devname, sc->if_name);
-			}
 		}
 		goto tx_post_exit;
 	}
@@ -2061,9 +2031,8 @@ tx_post_exit:
 		 * If we were able to transmit and the interface is set to
 		 * OACTIVE remove this flag and let kernel try to transmit.
 		 */
-		if (ifp->if_flags & IFF_OACTIVE) {
+		if (ifp->if_flags & IFF_OACTIVE)
 			ifp->if_flags &= ~IFF_OACTIVE;
-		}
 	}
 	return;
 }
@@ -2078,7 +2047,8 @@ xilinx_dma_rx_complete(sdla_t *card, xilinx_softc_t *sc)
 	bit_clear((u_int8_t *)&sc->rx_dma, 0);
 
 	if (!sc->rx_dma_mbuf) {
-		log(LOG_INFO, "%s: Critical Error: rx_dma_mbuf\n", sc->if_name);
+		log(LOG_INFO,
+		    "%s: Critical Error: rx_dma_mbuf\n", sc->if_name);
 		return;
 	}
 
@@ -2145,37 +2115,29 @@ xilinx_rx_post_complete(sdla_t *card, xilinx_softc_t *sc,
 
 	/* Checking Rx DMA PCI error status. Has to be '0's */
 	if (rx_el->reg&RxDMA_HI_DMA_PCI_ERROR_MASK) {
-
-		if (rx_el->reg & RxDMA_HI_DMA_PCI_ERROR_M_ABRT) {
 #ifdef DEBUG_ERR
+		if (rx_el->reg & RxDMA_HI_DMA_PCI_ERROR_M_ABRT)
 			log(LOG_INFO, "%s: Rx Error: Abort from Master: "
 			    "pci fatal error!\n", card->devname);
-#endif
-		}
-		if (rx_el->reg & RxDMA_HI_DMA_PCI_ERROR_T_ABRT) {
-#ifdef DEBUG_ERR
+
+		if (rx_el->reg & RxDMA_HI_DMA_PCI_ERROR_T_ABRT)
 			log(LOG_INFO, "%s: Rx Error: Abort from Target: "
 			    "pci fatal error!\n", card->devname);
-#endif
-		}
-		if (rx_el->reg & RxDMA_HI_DMA_PCI_ERROR_DS_TOUT) {
-#ifdef DEBUG_ERR
+
+		if (rx_el->reg & RxDMA_HI_DMA_PCI_ERROR_DS_TOUT)
 			log(LOG_INFO, "%s: Rx Error: No 'DeviceSelect' "
 			    "from target: pci fatal error!\n", card->devname);
-#endif
-		}
-		if (rx_el->reg & RxDMA_HI_DMA_PCI_ERROR_RETRY_TOUT) {
-#ifdef DEBUG_ERR
+
+		if (rx_el->reg & RxDMA_HI_DMA_PCI_ERROR_RETRY_TOUT)
 			log(LOG_INFO, "%s: Rx Error: 'Retry' exceeds maximum "
 			    "(64k): pci fatal error!\n", card->devname);
-#endif
-		}
-#ifdef DEBUG_ERR
+
 		log(LOG_INFO, "%s: RXDMA PCI ERROR = 0x%x\n",
 		    card->devname, rx_el->reg);
 #endif
 		if (ifp)
-		    ifp->if_ierrors++;
+			ifp->if_ierrors++;
+
 		goto rx_comp_error;
 	}
 
@@ -2196,7 +2158,8 @@ xilinx_rx_post_complete(sdla_t *card, xilinx_softc_t *sc,
 		log(LOG_INFO, "%s: RxDMA Intr: End flag missing: "
 		    "MTU Mismatch! Reg=0x%X\n", card->devname, rx_el->reg);
 #endif
-		if (ifp) ifp->if_ierrors++;
+		if (ifp)
+			ifp->if_ierrors++;
 		goto rx_comp_error;
 
 	} else {  /* Check CRC error flag only if this is the end of Frame */
@@ -2208,7 +2171,7 @@ xilinx_rx_post_complete(sdla_t *card, xilinx_softc_t *sc,
 			    card->devname, rx_el->reg);
 #endif
 			if (ifp)
-			    ifp->if_ierrors++;
+				ifp->if_ierrors++;
 
 			bit_set((u_int8_t *)&rx_el->pkt_error,
 			    WP_CRC_ERROR_BIT);
@@ -2225,14 +2188,14 @@ xilinx_rx_post_complete(sdla_t *card, xilinx_softc_t *sc,
 #endif
 			if (ifp)
 			    ifp->if_ierrors++;
+
 			bit_set((u_int8_t *)&rx_el->pkt_error,
 			    WP_ABORT_ERROR_BIT);
 			data_error = 1;
 		}
 
-		if (data_error) {
+		if (data_error)
 			goto rx_comp_error;
-		}
 	}
 
 	len = rx_el->reg & RxDMA_HI_DMA_DATA_LENGTH_MASK;
@@ -2266,9 +2229,6 @@ xilinx_rx_post_complete(sdla_t *card, xilinx_softc_t *sc,
 		/* The rx size is big enough, thus
 		 * send this buffer up the stack
 		 * and allocate another one */
-#if 0
-		memset(&skb->cb[0], 0, sizeof(wp_rx_element_t));
-#endif
 		memset(mtod(m, caddr_t), 0, sizeof(wp_rx_element_t));
 		m->m_len += len;
 		m->m_pkthdr.len = m->m_len;
@@ -2323,9 +2283,8 @@ request_xilinx_logical_channel_num(sdla_t *card, xilinx_softc_t *sc,
 #endif
 
 	err = request_fifo_baddr_and_size(card, sc);
-	if (err) {
+	if (err)
 		return (-1);
-	}
 
 	for (i = 0; i < card->u.xilinx.num_of_time_slots; i++) {
 		if (!bit_test((u_int8_t *)&card->u.xilinx.logic_ch_map, i)) {
@@ -2335,9 +2294,8 @@ request_xilinx_logical_channel_num(sdla_t *card, xilinx_softc_t *sc,
 		}
 	}
 
-	if (logic_ch == -1) {
+	if (logic_ch == -1)
 		return (logic_ch);
-	}
 
 	for (i = 0; i < card->u.xilinx.num_of_time_slots; i++) {
 		if (!bit_test((u_int8_t *)&card->u.xilinx.logic_ch_map, i)) {
@@ -2361,7 +2319,6 @@ request_xilinx_logical_channel_num(sdla_t *card, xilinx_softc_t *sc,
 		xilinx_dma_max_logic_ch(card);
 	}
 
-
 	return (logic_ch);
 }
 
@@ -2377,9 +2334,8 @@ free_xilinx_logical_channel_num(sdla_t *card, int logic_ch)
 		card->u.xilinx.top_logic_ch = XILINX_DEFLT_ACTIVE_CH;
 
 		for (i = 0; i < card->u.xilinx.num_of_time_slots; i++) {
-			if (card->u.xilinx.dev_to_ch_map[logic_ch]) {
+			if (card->u.xilinx.dev_to_ch_map[logic_ch])
 				card->u.xilinx.top_logic_ch = i;
-			}
 		}
 
 		xilinx_dma_max_logic_ch(card);
@@ -2409,13 +2365,14 @@ xilinx_dma_max_logic_ch(sdla_t *card)
 static int
 aft_init_requeue_free_m(xilinx_softc_t *sc, struct mbuf *m)
 {
-	int			err;
+	int err;
 
-	m->m_data	= (m->m_flags & M_EXT) ? m->m_ext.ext_buf : m->m_pktdat;
+	m->m_data = (m->m_flags & M_EXT) ? m->m_ext.ext_buf : m->m_pktdat;
 	m->m_pkthdr.len	= m->m_len = 0;
 
 	memset(mtod(m, caddr_t), 0, sizeof(wp_rx_element_t));
 	IF_ENQUEUE(&sc->wp_rx_free_list, m);
+
 	return (err);
 }
 
@@ -2447,6 +2404,7 @@ enable_timer(void *card_id)
 	s = splnet();
 	sdla_te_polling(card);
 	splx(s);
+
 	return;
 }
 
@@ -2574,9 +2532,8 @@ fifo_error_interrupt(sdla_t *card, unsigned long reg)
 				struct ifnet	*ifp;
 				sc = (xilinx_softc_t *)
 				    card->u.xilinx.dev_to_ch_map[i];
-				if (!sc) {
+				if (!sc)
 					continue;
-				}
 
 				ifp = (struct ifnet *)&sc->common.ifp;
 #if 0
@@ -2584,7 +2541,8 @@ fifo_error_interrupt(sdla_t *card, unsigned long reg)
 					log(LOG_INFO, "%s: Warning: ignoring "
 					    "rx error intr: dev down "
 					    "0x%X UP=0x%X!\n", ifp->if_xname,
-					    sc->common.state, sc->ignore_modem);
+					    sc->common.state,
+					    sc->ignore_modem);
 					continue;
 				}
 #endif
@@ -2610,7 +2568,7 @@ fifo_error_interrupt(sdla_t *card, unsigned long reg)
 {
 				unsigned long dma_descr;
 				unsigned int reg;
-				dma_descr=(sc->logic_ch_num<<4) +
+				dma_descr = (sc->logic_ch_num << 4) +
 				    XILINX_RxDMA_DESCRIPTOR_HI;
 				sdla_bus_read_4(card->hw, dma_descr, &reg);
 				log(LOG_INFO, "%s: Hi Descriptor 0x%X\n",
@@ -2646,7 +2604,8 @@ front_end_interrupt(sdla_t *card, unsigned long reg)
  * Main interrupt service routine.
  * Determine the interrupt received and handle it.
  */
-static void wp_xilinx_isr(sdla_t* card)
+static void
+wp_xilinx_isr(sdla_t* card)
 {
 	int i;
 	u_int32_t reg;
@@ -2703,11 +2662,9 @@ static void wp_xilinx_isr(sdla_t* card)
 	 * Test Fifo Error Interrupt
 	 * If set shutdown all interfaces and reconfigure
 	 */
-	if (bit_test((u_int8_t *)&reg, ERROR_INTR_ENABLE_BIT)) {
-		if (bit_test((u_int8_t *)&reg, ERROR_INTR_FLAG)) {
+	if (bit_test((u_int8_t *)&reg, ERROR_INTR_ENABLE_BIT))
+		if (bit_test((u_int8_t *)&reg, ERROR_INTR_FLAG))
 			fifo_error_interrupt(card, reg);
-		}
-	}
 
 	/*
 	 * Checking for Interrupt source:
@@ -2718,16 +2675,14 @@ static void wp_xilinx_isr(sdla_t* card)
 	if (bit_test((u_int8_t *)&reg, GLOBAL_INTR_ENABLE_BIT) &&
 		bit_test((u_int8_t *)&reg, DMA_INTR_FLAG)) {
 
-
 		/* Receive DMA Engine */
 		sdla_bus_read_4(card->hw, XILINX_DMA_RX_INTR_PENDING_REG,
 		    &dma_rx_reg);
 
 		dma_rx_reg &= card->u.xilinx.active_ch_map;
 
-		if (dma_rx_reg == 0) {
+		if (dma_rx_reg == 0)
 			goto isr_rx;
-		}
 
 		for (i = 0; i < card->u.xilinx.num_of_time_slots; i++) {
 			if (bit_test((u_int8_t *)&dma_rx_reg, i) &&
@@ -2753,9 +2708,8 @@ isr_rx:
 
 		dma_tx_reg &= card->u.xilinx.active_ch_map;
 
-		if (dma_tx_reg == 0) {
+		if (dma_tx_reg == 0)
 			goto isr_tx;
-		}
 
 		for (i = 0; i < card->u.xilinx.num_of_time_slots; i++) {
 			if (bit_test((u_int8_t *)&dma_tx_reg, i) &&
@@ -2826,9 +2780,8 @@ port_set_state(sdla_t *card, int state)
 		card->state = state;
 		LIST_FOREACH(common, &card->dev_head, next) {
 			struct ifnet *ifp = (struct ifnet *)&common->ifp;
-			if (ifp) {
+			if (ifp)
 				set_chan_state(card, ifp, state);
-			}
 		}
 	}
 }
@@ -2871,6 +2824,7 @@ read_cpld(sdla_t *card, unsigned short cpld_off)
 
 	/* Restore original address */
 	sdla_bus_write_2(card->hw, XILINX_MCPU_INTERFACE_ADDR, org_off);
+
 	return (tmp);
 }
 
@@ -2899,6 +2853,7 @@ write_cpld(sdla_t *card, unsigned short off, unsigned char data)
 
 	/* Restore the original address */
 	sdla_bus_write_2(card->hw, XILINX_MCPU_INTERFACE_ADDR, org_off);
+
 	return (0);
 }
 
@@ -2963,7 +2918,8 @@ read_front_end_reg(void *card1, unsigned short off)
  *
  */
 
-static void enable_data_error_intr(sdla_t *card)
+static void
+enable_data_error_intr(sdla_t *card)
 {
 	wanpipe_common_t	*common;
 	struct ifnet		*ifp;
@@ -2982,9 +2938,8 @@ static void enable_data_error_intr(sdla_t *card)
 			continue;
 		sc = ifp->if_softc;
 #if 0
-		if (!(ifp->if_flags & IFF_UP)) {
+		if (!(ifp->if_flags & IFF_UP))
 			continue;
-		}
 #endif
 
 #ifdef DEBUG_INIT
@@ -3012,9 +2967,8 @@ static void enable_data_error_intr(sdla_t *card)
 			continue;
 		sc = ifp->if_softc;
 #if 0
-		if (!(ifp->if_flags & IFF_UP)) {
+		if (!(ifp->if_flags & IFF_UP))
 			continue;
-		}
 #endif
 
 
@@ -3102,16 +3056,17 @@ static void enable_data_error_intr(sdla_t *card)
 	return;
 }
 
-static void disable_data_error_intr(sdla_t *card, unsigned char event)
+static void
+disable_data_error_intr(sdla_t *card, unsigned char event)
 {
 	u_int32_t reg;
 
 	sdla_bus_read_4(card->hw, XILINX_CHIP_CFG_REG, &reg);
 	bit_clear((u_int8_t *)&reg, GLOBAL_INTR_ENABLE_BIT);
 	bit_clear((u_int8_t *)&reg, ERROR_INTR_ENABLE_BIT);
-	if (event == DEVICE_DOWN) {
+	if (event == DEVICE_DOWN)
 		bit_clear((u_int8_t *)&reg, FRONT_END_INTR_ENABLE_BIT);
-	}
+
 	sdla_bus_write_4(card->hw, XILINX_CHIP_CFG_REG, reg);
 
 	sdla_bus_read_4(card->hw, XILINX_DMA_CONTROL_REG, &reg);
@@ -3126,7 +3081,7 @@ xilinx_init_tx_dma_descr(sdla_t *card, xilinx_softc_t *sc)
 	unsigned long dma_descr;
 	unsigned long reg = 0;
 
-	dma_descr=(sc->logic_ch_num << 4) + XILINX_TxDMA_DESCRIPTOR_HI;
+	dma_descr = (sc->logic_ch_num << 4) + XILINX_TxDMA_DESCRIPTOR_HI;
 	sdla_bus_write_4(card->hw, dma_descr, reg);
 }
 
@@ -3140,7 +3095,8 @@ xilinx_tx_fifo_under_recover(sdla_t *card, xilinx_softc_t *sc)
 	unsigned long dma_descr;
 
 #ifdef DEBUG_ERR
-	log(LOG_INFO, "%s:%s: Tx Fifo Recovery \n", card->devname, sc->if_name);
+	log(LOG_INFO, "%s:%s: Tx Fifo Recovery \n",
+	    card->devname, sc->if_name);
 #endif
 
 	/* Initialize Tx DMA descriptor: Stop DMA */
@@ -3164,7 +3120,8 @@ xilinx_tx_fifo_under_recover(sdla_t *card, xilinx_softc_t *sc)
 	/*
 	 * Wake up the stack, because tx dma interrupt failed
 	 */
-	if (ifp) ifp->if_oerrors++;
+	if (ifp)
+		ifp->if_oerrors++;
 
 #ifdef DEBUG_ERR
 	log(LOG_INFO, "%s:%s: Tx Fifo Recovery: Restarting Transmission \n",
@@ -3178,9 +3135,8 @@ xilinx_tx_fifo_under_recover(sdla_t *card, xilinx_softc_t *sc)
 		 * to OACTIVE remove this flag and let kernel try to
 		 * transmit.
 		 */
-		if (ifp->if_flags & IFF_OACTIVE) {
+		if (ifp->if_flags & IFF_OACTIVE)
 			ifp->if_flags &= ~IFF_OACTIVE;
-		}
 	}
 	return;
 }
@@ -3193,13 +3149,12 @@ xilinx_write_ctrl_hdlc(sdla_t *card, u_int32_t timeslot,
 	u_int32_t ts_orig = timeslot;
 	unsigned long timeout = ticks;
 
-	if (timeslot == 0) {
+	if (timeslot == 0)
 		timeslot = card->u.xilinx.num_of_time_slots - 2;
-	} else if (timeslot == 1) {
+	else if (timeslot == 1)
 		timeslot = card->u.xilinx.num_of_time_slots - 1;
-	} else {
+	else
 		timeslot -= 2;
-	}
 
 	timeslot = timeslot << XILINX_CURRENT_TIMESLOT_SHIFT;
 	timeslot &= XILINX_CURRENT_TIMESLOT_MASK;
@@ -3228,9 +3183,9 @@ set_chan_state(sdla_t *card, struct ifnet *ifp, int state)
 {
 	xilinx_softc_t *sc = ifp->if_softc;
 
-	if (sc == NULL) {
+	if (sc == NULL)
 		return (0);
-	}
+
 	if (state == WAN_CONNECTED) {
 #ifdef DEBUG_INIT
 		log(LOG_INFO, "%s: Setting idle_start to 0\n", sc->if_name);
@@ -3247,7 +3202,8 @@ set_chan_state(sdla_t *card, struct ifnet *ifp, int state)
 static char fifo_size_vector[] = {1, 2, 4, 8, 16, 32};
 static char fifo_code_vector[] = {0, 1, 3, 7, 0xF, 0x1F};
 
-static int request_fifo_baddr_and_size(sdla_t *card, xilinx_softc_t *sc)
+static int
+request_fifo_baddr_and_size(sdla_t *card, xilinx_softc_t *sc)
 {
 	unsigned char req_fifo_size, fifo_size;
 	int i;
@@ -3258,47 +3214,47 @@ static int request_fifo_baddr_and_size(sdla_t *card, xilinx_softc_t *sc)
 	 */
 
 	if (IS_T1(&card->fe_te.te_cfg)) {
-
-		if (sc->num_of_time_slots == NUM_OF_T1_CHANNELS) {
+		if (sc->num_of_time_slots == NUM_OF_T1_CHANNELS)
 			req_fifo_size = 32;
-		} else if (sc->num_of_time_slots == 1) {
+		else if (sc->num_of_time_slots == 1)
 			req_fifo_size = 1;
-		} else if (sc->num_of_time_slots == 2 ||
-		    sc->num_of_time_slots == 3) {
+		else if (sc->num_of_time_slots == 2 ||
+		    sc->num_of_time_slots == 3)
 			req_fifo_size = 2;
-		} else if (sc->num_of_time_slots >= 4 &&
-		    sc->num_of_time_slots <= 7) {
+		else if (sc->num_of_time_slots >= 4 &&
+		    sc->num_of_time_slots <= 7)
 			req_fifo_size = 4;
-		} else if (sc->num_of_time_slots >= 8 &&
-		    sc->num_of_time_slots <= 15) {
+		else if (sc->num_of_time_slots >= 8 &&
+		    sc->num_of_time_slots <= 15)
 			req_fifo_size = 8;
-		} else if (sc->num_of_time_slots >= 16 &&
-		    sc->num_of_time_slots <= 23) {
+		else if (sc->num_of_time_slots >= 16 &&
+		    sc->num_of_time_slots <= 23)
 			req_fifo_size = 16;
-		} else {
+		else {
 			log(LOG_INFO, "%s: Invalid number of timeslots %d\n",
 			    card->devname, sc->num_of_time_slots);
 			return (EINVAL);
 		}
 	} else {
-		if (sc->num_of_time_slots == (NUM_OF_E1_CHANNELS-1)) {
+		if (sc->num_of_time_slots == (NUM_OF_E1_CHANNELS-1))
 			req_fifo_size = 32;
-		} else if (sc->num_of_time_slots == 1) {
+		else if (sc->num_of_time_slots == 1)
 			req_fifo_size = 1;
-		} else if (sc->num_of_time_slots == 2 ||
-		    sc->num_of_time_slots == 3) {
+		else if (sc->num_of_time_slots == 2 ||
+		    sc->num_of_time_slots == 3)
 			req_fifo_size = 2;
-		} else if (sc->num_of_time_slots >= 4 &&
-		    sc->num_of_time_slots <= 7) {
+		else if (sc->num_of_time_slots >= 4 &&
+		    sc->num_of_time_slots <= 7)
 			req_fifo_size = 4;
-		} else if (sc->num_of_time_slots >= 8 &&
-		    sc->num_of_time_slots <= 15) {
+		else if (sc->num_of_time_slots >= 8 &&
+		    sc->num_of_time_slots <= 15)
 			req_fifo_size = 8;
-		} else if (sc->num_of_time_slots >= 16 &&
-		    sc->num_of_time_slots <= 31) {
+		else if (sc->num_of_time_slots >= 16 &&
+		    sc->num_of_time_slots <= 31)
 			req_fifo_size = 16;
-		} else {
-			log(LOG_INFO, "%s:%s: Invalid number of timeslots %d\n",
+		else {
+			log(LOG_INFO,
+			    "%s:%s: Invalid number of timeslots %d\n",
 			    card->devname, sc->if_name, sc->num_of_time_slots);
 			return (EINVAL);
 		}
@@ -3310,6 +3266,7 @@ static int request_fifo_baddr_and_size(sdla_t *card, xilinx_softc_t *sc)
 #endif
 	fifo_size = map_fifo_baddr_and_size(card, req_fifo_size,
 	    &sc->fifo_base_addr);
+
 	if (fifo_size == 0 || sc->fifo_base_addr == 31) {
 		log(LOG_INFO, "%s:%s: Error: Failed to obtain fifo size %d "
 		    "or addr %d\n", card->devname, sc->if_name, fifo_size,
@@ -3330,11 +3287,10 @@ static int request_fifo_baddr_and_size(sdla_t *card, xilinx_softc_t *sc)
 		}
 	}
 
-	if (fifo_size != req_fifo_size) {
+	if (fifo_size != req_fifo_size)
 		log(LOG_INFO, "%s:%s: WARN: Failed to obtain the req "
 		    "fifo %d got %d\n", card->devname, sc->if_name,
 		    req_fifo_size, fifo_size);
-	}
 
 #ifdef DEBUG_INIT
 	log(LOG_INFO, "%s: %s:Fifo Size=%d  TS=%d Fifo Code=%d Addr=%d\n",
@@ -3354,18 +3310,16 @@ map_fifo_baddr_and_size(sdla_t *card, unsigned char fifo_size,
 	u_int32_t reg = 0;
 	int i;
 
-	for (i = 0; i < fifo_size; i++) {
+	for (i = 0; i < fifo_size; i++)
 		bit_set((u_int8_t *)&reg, i);
-	}
 
 #ifdef DEBUG_INIT
 	log(LOG_INFO, "%s: Trying to MAP 0x%X  to 0x%lX\n",
 	     card->devname, reg, card->u.xilinx.fifo_addr_map);
 #endif
 	for (i = 0; i < 32; i += fifo_size) {
-		if (card->u.xilinx.fifo_addr_map & (reg << i)) {
+		if (card->u.xilinx.fifo_addr_map & (reg << i))
 			continue;
-		}
 		card->u.xilinx.fifo_addr_map |= reg << i;
 		*addr = i;
 
@@ -3376,9 +3330,8 @@ map_fifo_baddr_and_size(sdla_t *card, unsigned char fifo_size,
 		return (fifo_size);
 	}
 
-	if (fifo_size == 1) {
+	if (fifo_size == 1)
 		return (0);
-	}
 
 	fifo_size = fifo_size >> 1;
 
@@ -3392,9 +3345,8 @@ free_fifo_baddr_and_size(sdla_t *card, xilinx_softc_t *sc)
 	u_int32_t reg = 0;
 	int i;
 
-	for (i = 0; i < sc->fifo_size; i++) {
+	for (i = 0; i < sc->fifo_size; i++)
 		bit_set((u_int8_t *)&reg, i);
-	}
 
 #ifdef DEBUG_INIT
 	log(LOG_INFO, "%s: Unmapping 0x%X from 0x%lX\n", card->devname,
@@ -3420,16 +3372,15 @@ aft_red_led_ctrl(sdla_t *card, int mode)
 
 	sdla_bus_read_4(card->hw, XILINX_CHIP_CFG_REG, &led);
 
-	if (mode == AFT_LED_ON) {
+	if (mode == AFT_LED_ON)
 		bit_clear((u_int8_t *)&led, XILINX_RED_LED);
-	} else if (mode == AFT_LED_OFF) {
+	else if (mode == AFT_LED_OFF)
 		bit_set((u_int8_t *)&led, XILINX_RED_LED);
-	} else {
-		if (bit_test((u_int8_t *)&led, XILINX_RED_LED)) {
+	else {
+		if (bit_test((u_int8_t *)&led, XILINX_RED_LED))
 			bit_clear((u_int8_t *)&led, XILINX_RED_LED);
-		} else {
+		else
 			bit_set((u_int8_t *)&led, XILINX_RED_LED);
-		}
 	}
 
 	sdla_bus_write_4(card->hw, XILINX_CHIP_CFG_REG, led);
@@ -3441,9 +3392,8 @@ aft_led_timer(void *data)
 	sdla_t *card=(sdla_t *)data;
 	unsigned int te_alarm;
 
-	if (bit_test((u_int8_t *)&card->critical, CARD_DOWN)) {
+	if (bit_test((u_int8_t *)&card->critical, CARD_DOWN))
 		return;
-	}
 
 	if (IS_TE1(&card->fe_te.te_cfg)) {
 		int s = splnet();
@@ -3502,16 +3452,14 @@ aft_core_ready(sdla_t *card)
 		if (!bit_test((u_int8_t *)&reg, HDLC_CORE_READY_FLAG_BIT)) {
 			/* The HDLC Core is not ready! we have
 			** an error. */
-			if (++cnt > 5) {
+			if (++cnt > 5)
 				return  (EINVAL);
-			} else {
+			else
 				DELAY(500);
 				/* WARNING: we cannot do this while in
 				 * critical area */
-			}
-		} else {
+		} else
 			return (0);
-		}
 	}
 
 	return (EINVAL);