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authorMiod Vallat <miod@cvs.openbsd.org>2012-03-19 19:16:07 +0000
committerMiod Vallat <miod@cvs.openbsd.org>2012-03-19 19:16:07 +0000
commit481627f6a2f06e3457bba19006d077ba39215e36 (patch)
tree9b87623e312fd39088a6b9c884028216e86656c5 /sys
parent712a8802e8c112bf702161fc0569332e99d6e60c (diff)
Use uncached addresses for all exception vectors, when copying our code (or
trampolines) to them; this makes sure there is no risk of pending writes being lost when we clear the caches. Of course, this would be a bug in the cache handling routines, but having our vectors correctly set will help debugging the issue. Tested on sgi and loongson.
Diffstat (limited to 'sys')
-rw-r--r--sys/arch/mips64/include/cpu.h10
1 files changed, 5 insertions, 5 deletions
diff --git a/sys/arch/mips64/include/cpu.h b/sys/arch/mips64/include/cpu.h
index 26da2d06345..6214091335a 100644
--- a/sys/arch/mips64/include/cpu.h
+++ b/sys/arch/mips64/include/cpu.h
@@ -1,4 +1,4 @@
-/* $OpenBSD: cpu.h,v 1.73 2012/03/15 18:57:22 miod Exp $ */
+/* $OpenBSD: cpu.h,v 1.74 2012/03/19 19:16:06 miod Exp $ */
/*-
* Copyright (c) 1992, 1993
@@ -210,10 +210,10 @@
* Location of exception vectors.
*/
#define RESET_EXC_VEC (CKSEG1_BASE + 0x1fc00000)
-#define TLB_MISS_EXC_VEC (CKSEG0_BASE + 0x00000000)
-#define XTLB_MISS_EXC_VEC (CKSEG0_BASE + 0x00000080)
-#define CACHE_ERR_EXC_VEC (CKSEG0_BASE + 0x00000100)
-#define GEN_EXC_VEC (CKSEG0_BASE + 0x00000180)
+#define TLB_MISS_EXC_VEC (CKSEG1_BASE + 0x00000000)
+#define XTLB_MISS_EXC_VEC (CKSEG1_BASE + 0x00000080)
+#define CACHE_ERR_EXC_VEC (CKSEG1_BASE + 0x00000100)
+#define GEN_EXC_VEC (CKSEG1_BASE + 0x00000180)
/*
* Coprocessor 0 registers: