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authorDavid Gwynne <dlg@cvs.openbsd.org>2013-01-30 11:15:07 +0000
committerDavid Gwynne <dlg@cvs.openbsd.org>2013-01-30 11:15:07 +0000
commit687f7b24b840e057d1f46fdd09ae51b0ee18cc26 (patch)
treee43bb122a6eabab30fc3f8f1907c8ffda1309c42 /sys
parent67d0c2db8dd70ee4d28ec2255be87769bf0e7e45 (diff)
backout 5718/5719/5720 support. the diff breaks the 5704C on my xserve g5
and i cant fix it without breaking a 5721 in another box. sthen@ agrees it is sad.
Diffstat (limited to 'sys')
-rw-r--r--sys/dev/pci/if_bge.c978
-rw-r--r--sys/dev/pci/if_bgereg.h152
2 files changed, 168 insertions, 962 deletions
diff --git a/sys/dev/pci/if_bge.c b/sys/dev/pci/if_bge.c
index 5ba2a61a1ff..8d0f8538da0 100644
--- a/sys/dev/pci/if_bge.c
+++ b/sys/dev/pci/if_bge.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: if_bge.c,v 1.316 2013/01/29 00:41:02 dlg Exp $ */
+/* $OpenBSD: if_bge.c,v 1.317 2013/01/30 11:15:06 dlg Exp $ */
/*
* Copyright (c) 2001 Wind River Systems
@@ -180,7 +180,6 @@ int bge_init_tx_ring(struct bge_softc *);
void bge_chipinit(struct bge_softc *);
int bge_blockinit(struct bge_softc *);
-u_int32_t bge_dma_swap_options(struct bge_softc *);
int bge_phy_addr(struct bge_softc *);
u_int32_t bge_readmem_ind(struct bge_softc *, int);
@@ -192,23 +191,9 @@ int bge_miibus_readreg(struct device *, int, int);
void bge_miibus_writereg(struct device *, int, int, int);
void bge_miibus_statchg(struct device *);
-#define BGE_RESET_SHUTDOWN 0
-#define BGE_RESET_START 1
-#define BGE_RESET_SUSPEND 2
-void bge_sig_post_reset(struct bge_softc *, int);
-void bge_sig_legacy(struct bge_softc *, int);
-void bge_sig_pre_reset(struct bge_softc *, int);
-void bge_stop_fw(struct bge_softc *, int);
void bge_reset(struct bge_softc *);
void bge_link_upd(struct bge_softc *);
-void bge_ape_lock_init(struct bge_softc *);
-void bge_ape_read_fw_ver(struct bge_softc *);
-int bge_ape_lock(struct bge_softc *, int);
-void bge_ape_unlock(struct bge_softc *, int);
-void bge_ape_send_event(struct bge_softc *, uint32_t);
-void bge_ape_driver_state_change(struct bge_softc *, int);
-
#ifdef BGE_DEBUG
#define DPRINTF(x) do { if (bgedebug) printf x; } while (0)
#define DPRINTFN(n,x) do { if (bgedebug >= (n)) printf x; } while (0)
@@ -257,8 +242,6 @@ const struct pci_matchid bge_devices[] = {
{ PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5715S },
{ PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5717 },
{ PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5718 },
- { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5719 },
- { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5720 },
{ PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5721 },
{ PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5722 },
{ PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5723 },
@@ -323,8 +306,6 @@ const struct pci_matchid bge_devices[] = {
#define BGE_IS_5755_PLUS(sc) ((sc)->bge_flags & BGE_5755_PLUS)
#define BGE_IS_5700_FAMILY(sc) ((sc)->bge_flags & BGE_5700_FAMILY)
#define BGE_IS_5714_FAMILY(sc) ((sc)->bge_flags & BGE_5714_FAMILY)
-#define BGE_IS_5717_PLUS(sc) ((sc)->bge_flags & BGE_5717_PLUS)
-#define BGE_IS_575X_PLUS(sc) ((sc)->bge_flags & BGE_575X_PLUS)
#define BGE_IS_JUMBO_CAPABLE(sc) ((sc)->bge_flags & BGE_JUMBO_CAPABLE)
static const struct bge_revision {
@@ -375,7 +356,6 @@ static const struct bge_revision {
{ BGE_CHIPID_BCM5715_A0, "BCM5715 A0" },
{ BGE_CHIPID_BCM5715_A1, "BCM5715 A1" },
{ BGE_CHIPID_BCM5715_A3, "BCM5715 A3" },
- { BGE_CHIPID_BCM5720_A0, "BCM5720 A0" },
{ BGE_CHIPID_BCM5755_A0, "BCM5755 A0" },
{ BGE_CHIPID_BCM5755_A1, "BCM5755 A1" },
{ BGE_CHIPID_BCM5755_A2, "BCM5755 A2" },
@@ -421,8 +401,6 @@ static const struct bge_revision bge_majorrevs[] = {
{ BGE_ASICREV_BCM5906, "unknown BCM5906" },
{ BGE_ASICREV_BCM57780, "unknown BCM57780" },
{ BGE_ASICREV_BCM5717, "unknown BCM5717" },
- { BGE_ASICREV_BCM5719, "unknown BCM5719" },
- { BGE_ASICREV_BCM5720, "unknown BCM5720" },
{ BGE_ASICREV_BCM57765, "unknown BCM57765" },
{ 0, NULL }
@@ -432,16 +410,9 @@ u_int32_t
bge_readmem_ind(struct bge_softc *sc, int off)
{
struct pci_attach_args *pa = &(sc->bge_pa);
- u_int32_t val;
-
- if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906 &&
- off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4)
- return (0);
pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MEMWIN_BASEADDR, off);
- val = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_MEMWIN_DATA);
- pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MEMWIN_BASEADDR, 0);
- return (val);
+ return (pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_MEMWIN_DATA));
}
void
@@ -449,13 +420,8 @@ bge_writemem_ind(struct bge_softc *sc, int off, int val)
{
struct pci_attach_args *pa = &(sc->bge_pa);
- if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906 &&
- off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4)
- return;
-
pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MEMWIN_BASEADDR, off);
pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MEMWIN_DATA, val);
- pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MEMWIN_BASEADDR, 0);
}
void
@@ -476,324 +442,6 @@ bge_writembx(struct bge_softc *sc, int off, int val)
CSR_WRITE_4(sc, off, val);
}
-/*
- * Clear all stale locks and select the lock for this driver instance.
- */
-void
-bge_ape_lock_init(struct bge_softc *sc)
-{
- struct pci_attach_args *pa = &(sc->bge_pa);
- uint32_t bit, regbase;
- int i;
-
- if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761)
- regbase = BGE_APE_LOCK_GRANT;
- else
- regbase = BGE_APE_PER_LOCK_GRANT;
-
- /* Clear any stale locks. */
- for (i = BGE_APE_LOCK_PHY0; i <= BGE_APE_LOCK_GPIO; i++) {
- switch (i) {
- case BGE_APE_LOCK_PHY0:
- case BGE_APE_LOCK_PHY1:
- case BGE_APE_LOCK_PHY2:
- case BGE_APE_LOCK_PHY3:
- bit = BGE_APE_LOCK_GRANT_DRIVER0;
- break;
- default:
- if (pa->pa_function != 0)
- bit = BGE_APE_LOCK_GRANT_DRIVER0;
- else
- bit = (1 << pa->pa_function);
- }
- APE_WRITE_4(sc, regbase + 4 * i, bit);
- }
-
- /* Select the PHY lock based on the device's function number. */
- switch (pa->pa_function) {
- case 0:
- sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY0;
- break;
- case 1:
- sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY1;
- break;
- case 2:
- sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY2;
- break;
- case 3:
- sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY3;
- break;
- default:
- printf("%s: PHY lock not supported on function %d\n",
- sc->bge_dev.dv_xname);
- break;
- }
-}
-
-/*
- * Check for APE firmware, set flags, and print version info.
- */
-void
-bge_ape_read_fw_ver(struct bge_softc *sc)
-{
- const char *fwtype;
- uint32_t apedata, features;
-
- /* Check for a valid APE signature in shared memory. */
- apedata = APE_READ_4(sc, BGE_APE_SEG_SIG);
- if (apedata != BGE_APE_SEG_SIG_MAGIC) {
- sc->bge_mfw_flags &= ~ BGE_MFW_ON_APE;
- return;
- }
-
- /* Check if APE firmware is running. */
- apedata = APE_READ_4(sc, BGE_APE_FW_STATUS);
- if ((apedata & BGE_APE_FW_STATUS_READY) == 0) {
- printf("%s: APE signature found but FW status not ready! "
- "0x%08x\n", sc->bge_dev.dv_xname, apedata);
- return;
- }
-
- sc->bge_mfw_flags |= BGE_MFW_ON_APE;
-
- /* Fetch the APE firwmare type and version. */
- apedata = APE_READ_4(sc, BGE_APE_FW_VERSION);
- features = APE_READ_4(sc, BGE_APE_FW_FEATURES);
- if ((features & BGE_APE_FW_FEATURE_NCSI) != 0) {
- sc->bge_mfw_flags |= BGE_MFW_TYPE_NCSI;
- fwtype = "NCSI";
- } else if ((features & BGE_APE_FW_FEATURE_DASH) != 0) {
- sc->bge_mfw_flags |= BGE_MFW_TYPE_DASH;
- fwtype = "DASH";
- } else
- fwtype = "UNKN";
-
- /* Print the APE firmware version. */
- printf(", APE firmware %s %d.%d.%d.%d", fwtype,
- (apedata & BGE_APE_FW_VERSION_MAJMSK) >> BGE_APE_FW_VERSION_MAJSFT,
- (apedata & BGE_APE_FW_VERSION_MINMSK) >> BGE_APE_FW_VERSION_MINSFT,
- (apedata & BGE_APE_FW_VERSION_REVMSK) >> BGE_APE_FW_VERSION_REVSFT,
- (apedata & BGE_APE_FW_VERSION_BLDMSK));
-}
-
-int
-bge_ape_lock(struct bge_softc *sc, int locknum)
-{
- struct pci_attach_args *pa = &(sc->bge_pa);
- uint32_t bit, gnt, req, status;
- int i, off;
-
- if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0)
- return (0);
-
- /* Lock request/grant registers have different bases. */
- if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) {
- req = BGE_APE_LOCK_REQ;
- gnt = BGE_APE_LOCK_GRANT;
- } else {
- req = BGE_APE_PER_LOCK_REQ;
- gnt = BGE_APE_PER_LOCK_GRANT;
- }
-
- off = 4 * locknum;
-
- switch (locknum) {
- case BGE_APE_LOCK_GPIO:
- /* Lock required when using GPIO. */
- if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761)
- return (0);
- if (pa->pa_function == 0)
- bit = BGE_APE_LOCK_REQ_DRIVER0;
- else
- bit = (1 << pa->pa_function);
- break;
- case BGE_APE_LOCK_GRC:
- /* Lock required to reset the device. */
- if (pa->pa_function == 0)
- bit = BGE_APE_LOCK_REQ_DRIVER0;
- else
- bit = (1 << pa->pa_function);
- break;
- case BGE_APE_LOCK_MEM:
- /* Lock required when accessing certain APE memory. */
- if (pa->pa_function == 0)
- bit = BGE_APE_LOCK_REQ_DRIVER0;
- else
- bit = (1 << pa->pa_function);
- break;
- case BGE_APE_LOCK_PHY0:
- case BGE_APE_LOCK_PHY1:
- case BGE_APE_LOCK_PHY2:
- case BGE_APE_LOCK_PHY3:
- /* Lock required when accessing PHYs. */
- bit = BGE_APE_LOCK_REQ_DRIVER0;
- break;
- default:
- return (EINVAL);
- }
-
- /* Request a lock. */
- APE_WRITE_4(sc, req + off, bit);
-
- /* Wait up to 1 second to acquire lock. */
- for (i = 0; i < 20000; i++) {
- status = APE_READ_4(sc, gnt + off);
- if (status == bit)
- break;
- DELAY(50);
- }
-
- /* Handle any errors. */
- if (status != bit) {
- printf("%s: APE lock %d request failed! "
- "request = 0x%04x[0x%04x], status = 0x%04x[0x%04x]\n",
- sc->bge_dev.dv_xname,
- locknum, req + off, bit & 0xFFFF, gnt + off,
- status & 0xFFFF);
- /* Revoke the lock request. */
- APE_WRITE_4(sc, gnt + off, bit);
- return (EBUSY);
- }
-
- return (0);
-}
-
-void
-bge_ape_unlock(struct bge_softc *sc, int locknum)
-{
- struct pci_attach_args *pa = &(sc->bge_pa);
- uint32_t bit, gnt;
- int off;
-
- if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0)
- return;
-
- if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761)
- gnt = BGE_APE_LOCK_GRANT;
- else
- gnt = BGE_APE_PER_LOCK_GRANT;
-
- off = 4 * locknum;
-
- switch (locknum) {
- case BGE_APE_LOCK_GPIO:
- if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761)
- return;
- if (pa->pa_function == 0)
- bit = BGE_APE_LOCK_GRANT_DRIVER0;
- else
- bit = (1 << pa->pa_function);
- break;
- case BGE_APE_LOCK_GRC:
- if (pa->pa_function == 0)
- bit = BGE_APE_LOCK_GRANT_DRIVER0;
- else
- bit = (1 << pa->pa_function);
- break;
- case BGE_APE_LOCK_MEM:
- if (pa->pa_function == 0)
- bit = BGE_APE_LOCK_GRANT_DRIVER0;
- else
- bit = (1 << pa->pa_function);
- break;
- case BGE_APE_LOCK_PHY0:
- case BGE_APE_LOCK_PHY1:
- case BGE_APE_LOCK_PHY2:
- case BGE_APE_LOCK_PHY3:
- bit = BGE_APE_LOCK_GRANT_DRIVER0;
- break;
- default:
- return;
- }
-
- APE_WRITE_4(sc, gnt + off, bit);
-}
-
-/*
- * Send an event to the APE firmware.
- */
-void
-bge_ape_send_event(struct bge_softc *sc, uint32_t event)
-{
- uint32_t apedata;
- int i;
-
- /* NCSI does not support APE events. */
- if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0)
- return;
-
- /* Wait up to 1ms for APE to service previous event. */
- for (i = 10; i > 0; i--) {
- if (bge_ape_lock(sc, BGE_APE_LOCK_MEM) != 0)
- break;
- apedata = APE_READ_4(sc, BGE_APE_EVENT_STATUS);
- if ((apedata & BGE_APE_EVENT_STATUS_EVENT_PENDING) == 0) {
- APE_WRITE_4(sc, BGE_APE_EVENT_STATUS, event |
- BGE_APE_EVENT_STATUS_EVENT_PENDING);
- bge_ape_unlock(sc, BGE_APE_LOCK_MEM);
- APE_WRITE_4(sc, BGE_APE_EVENT, BGE_APE_EVENT_1);
- break;
- }
- bge_ape_unlock(sc, BGE_APE_LOCK_MEM);
- DELAY(100);
- }
- if (i == 0) {
- printf("%s: APE event 0x%08x send timed out\n",
- sc->bge_dev.dv_xname, event);
- }
-}
-
-void
-bge_ape_driver_state_change(struct bge_softc *sc, int kind)
-{
- uint32_t apedata, event;
-
- if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0)
- return;
-
- switch (kind) {
- case BGE_RESET_START:
- /* If this is the first load, clear the load counter. */
- apedata = APE_READ_4(sc, BGE_APE_HOST_SEG_SIG);
- if (apedata != BGE_APE_HOST_SEG_SIG_MAGIC)
- APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, 0);
- else {
- apedata = APE_READ_4(sc, BGE_APE_HOST_INIT_COUNT);
- APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, ++apedata);
- }
- APE_WRITE_4(sc, BGE_APE_HOST_SEG_SIG,
- BGE_APE_HOST_SEG_SIG_MAGIC);
- APE_WRITE_4(sc, BGE_APE_HOST_SEG_LEN,
- BGE_APE_HOST_SEG_LEN_MAGIC);
-
- /* Add some version info if bge(4) supports it. */
- APE_WRITE_4(sc, BGE_APE_HOST_DRIVER_ID,
- BGE_APE_HOST_DRIVER_ID_MAGIC(1, 0));
- APE_WRITE_4(sc, BGE_APE_HOST_BEHAVIOR,
- BGE_APE_HOST_BEHAV_NO_PHYLOCK);
- APE_WRITE_4(sc, BGE_APE_HOST_HEARTBEAT_INT_MS,
- BGE_APE_HOST_HEARTBEAT_INT_DISABLE);
- APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE,
- BGE_APE_HOST_DRVR_STATE_START);
- event = BGE_APE_EVENT_STATUS_STATE_START;
- break;
- case BGE_RESET_SHUTDOWN:
- APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE,
- BGE_APE_HOST_DRVR_STATE_UNLOAD);
- event = BGE_APE_EVENT_STATUS_STATE_UNLOAD;
- break;
- case BGE_RESET_SUSPEND:
- event = BGE_APE_EVENT_STATUS_STATE_SUSPEND;
- break;
- default:
- return;
- }
-
- bge_ape_send_event(sc, event | BGE_APE_EVENT_STATUS_DRIVER_EVNT |
- BGE_APE_EVENT_STATUS_STATE_CHNGE);
-}
-
-
u_int8_t
bge_nvram_getbyte(struct bge_softc *sc, int addr, u_int8_t *dest)
{
@@ -939,15 +587,12 @@ bge_miibus_readreg(struct device *dev, int phy, int reg)
u_int32_t val, autopoll;
int i;
- if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0)
- return (0);
-
/* Reading with autopolling on may trigger PCI errors */
autopoll = CSR_READ_4(sc, BGE_MI_MODE);
if (autopoll & BGE_MIMODE_AUTOPOLL) {
BGE_STS_CLRBIT(sc, BGE_STS_AUTOPOLL);
BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
- DELAY(80);
+ DELAY(40);
}
CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ|BGE_MICOMM_BUSY|
@@ -973,11 +618,9 @@ done:
if (autopoll & BGE_MIMODE_AUTOPOLL) {
BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL);
BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
- DELAY(80);
+ DELAY(40);
}
- bge_ape_unlock(sc, sc->bge_phy_ape_lock);
-
if (val & BGE_MICOMM_READFAIL)
return (0);
@@ -991,20 +634,13 @@ bge_miibus_writereg(struct device *dev, int phy, int reg, int val)
u_int32_t autopoll;
int i;
- if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906 &&
- (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL))
- return;
-
- if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0)
- return;
-
/* Reading with autopolling on may trigger PCI errors */
autopoll = CSR_READ_4(sc, BGE_MI_MODE);
if (autopoll & BGE_MIMODE_AUTOPOLL) {
DELAY(40);
BGE_STS_CLRBIT(sc, BGE_STS_AUTOPOLL);
BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
- DELAY(40); /* 40 usec is supposed to be adequate */
+ DELAY(10); /* 40 usec is supposed to be adequate */
}
CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE|BGE_MICOMM_BUSY|
@@ -1023,8 +659,6 @@ bge_miibus_writereg(struct device *dev, int phy, int reg, int val)
DELAY(40);
}
- bge_ape_unlock(sc, sc->bge_phy_ape_lock);
-
if (i == 200) {
printf("%s: PHY read timed out\n", sc->bge_dev.dv_xname);
}
@@ -1035,7 +669,6 @@ bge_miibus_statchg(struct device *dev)
{
struct bge_softc *sc = (struct bge_softc *)dev;
struct mii_data *mii = &sc->bge_mii;
- u_int32_t mac_mode, rx_mode, tx_mode;
/*
* Get flow control negotiation result.
@@ -1046,33 +679,30 @@ bge_miibus_statchg(struct device *dev)
mii->mii_media_active &= ~IFM_ETH_FMASK;
}
- /* Set the port mode (MII/GMII) to match the link speed. */
- mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) &
- ~(BGE_MACMODE_PORTMODE | BGE_MACMODE_HALF_DUPLEX);
- tx_mode = CSR_READ_4(sc, BGE_TX_MODE);
- rx_mode = CSR_READ_4(sc, BGE_RX_MODE);
-
+ BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE);
if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX)
- mac_mode |= BGE_PORTMODE_GMII;
+ BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII);
else
- mac_mode |= BGE_PORTMODE_MII;
-
- /* Set MAC flow control behavior to match link flow control settings. */
- tx_mode &= ~BGE_TXMODE_FLOWCTL_ENABLE;
- rx_mode &= ~BGE_RXMODE_FLOWCTL_ENABLE;
- if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
- if (sc->bge_flowflags & IFM_ETH_TXPAUSE)
- tx_mode |= BGE_TXMODE_FLOWCTL_ENABLE;
- if (sc->bge_flowflags & IFM_ETH_RXPAUSE)
- rx_mode |= BGE_RXMODE_FLOWCTL_ENABLE;
- } else
- mac_mode |= BGE_MACMODE_HALF_DUPLEX;
+ BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII);
- CSR_WRITE_4(sc, BGE_MAC_MODE, mac_mode);
- DELAY(40);
- CSR_WRITE_4(sc, BGE_TX_MODE, tx_mode);
- CSR_WRITE_4(sc, BGE_RX_MODE, rx_mode);
+ if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX)
+ BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
+ else
+ BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
+
+ /*
+ * 802.3x flow control
+ */
+ if (sc->bge_flowflags & IFM_ETH_RXPAUSE)
+ BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_FLOWCTL_ENABLE);
+ else
+ BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_FLOWCTL_ENABLE);
+
+ if (sc->bge_flowflags & IFM_ETH_TXPAUSE)
+ BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_FLOWCTL_ENABLE);
+ else
+ BGE_CLRBIT(sc, BGE_TX_MODE, BGE_TXMODE_FLOWCTL_ENABLE);
}
/*
@@ -1528,50 +1158,6 @@ bge_iff(struct bge_softc *sc)
CSR_WRITE_4(sc, BGE_RX_MODE, rxmode);
}
-void
-bge_sig_pre_reset(struct bge_softc *sc, int type)
-{
- /* no bge_asf_mode. */
-
- if (type == BGE_RESET_START || type == BGE_RESET_SUSPEND)
- bge_ape_driver_state_change(sc, type);
-}
-
-void
-bge_sig_post_reset(struct bge_softc *sc, int type)
-{
- /* no bge_asf_mode. */
-
- if (type == BGE_RESET_SHUTDOWN)
- bge_ape_driver_state_change(sc, type);
-}
-
-void
-bge_sig_legacy(struct bge_softc *sc, int type)
-{
- /* no bge_asf_mode. */
-}
-
-void
-bge_stop_fw(struct bge_softc *sc, int type)
-{
- /* no bge_asf_mode. */
-}
-
-u_int32_t
-bge_dma_swap_options(struct bge_softc *sc)
-{
- u_int32_t dma_options = BGE_DMA_SWAP_OPTIONS;
-
- if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) {
- dma_options |= BGE_MODECTL_BYTESWAP_B2HRX_DATA |
- BGE_MODECTL_WORDSWAP_B2HRX_DATA | BGE_MODECTL_B2HRX_ENABLE |
- BGE_MODECTL_HTX2B_ENABLE;
- }
-
- return (dma_options);
-}
-
int
bge_phy_addr(struct bge_softc *sc)
{
@@ -1602,13 +1188,16 @@ void
bge_chipinit(struct bge_softc *sc)
{
struct pci_attach_args *pa = &(sc->bge_pa);
- u_int32_t dma_rw_ctl, mode_ctl;
+ u_int32_t dma_rw_ctl;
int i;
/* Set endianness before we access any non-PCI registers. */
pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL,
BGE_INIT);
+ /* Clear the MAC control register */
+ CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
+
/*
* Clear the MAC statistics block in the NIC's
* internal memory.
@@ -1679,41 +1268,19 @@ bge_chipinit(struct bge_softc *sc)
BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701)
dma_rw_ctl |= BGE_PCIDMARWCTL_USE_MRM |
BGE_PCIDMARWCTL_ASRT_ALL_BE;
-
+
if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 ||
BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704)
dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA;
- if (BGE_IS_5717_PLUS(sc)) {
- dma_rw_ctl &= ~BGE_PCIDMARWCTL_DIS_CACHE_ALIGNMENT;
- if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0)
- dma_rw_ctl &= ~BGE_PCIDMARWCTL_CRDRDR_RDMA_MRRS_MSK;
-
- /*
- * Enable HW workaround for controllers that misinterpret
- * a status tag update and leave interrupts permanently
- * disabled.
- */
- if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5717 &&
- BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM57765)
- dma_rw_ctl |= BGE_PCIDMARWCTL_TAGGED_STATUS_WA;
- }
-
pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, dma_rw_ctl);
/*
* Set up general mode register.
*/
- mode_ctl = bge_dma_swap_options(sc);
- if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) {
- /* Retain Host-2-BMC settings written by APE firmware. */
- mode_ctl |= CSR_READ_4(sc, BGE_MODE_CTL) &
- (BGE_MODECTL_BYTESWAP_B2HRX_DATA |
- BGE_MODECTL_WORDSWAP_B2HRX_DATA |
- BGE_MODECTL_B2HRX_ENABLE | BGE_MODECTL_HTX2B_ENABLE);
- }
- mode_ctl |= BGE_MODECTL_MAC_ATTN_INTR | BGE_MODECTL_HOST_SEND_BDS |
- BGE_MODECTL_TX_NO_PHDR_CSUM;
+ CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS|
+ BGE_MODECTL_MAC_ATTN_INTR|BGE_MODECTL_HOST_SEND_BDS|
+ BGE_MODECTL_TX_NO_PHDR_CSUM);
/*
* BCM5701 B5 have a bug causing data corruption when using
@@ -1723,9 +1290,7 @@ bge_chipinit(struct bge_softc *sc)
*/
if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701 &&
sc->bge_chipid == BGE_CHIPID_BCM5701_B5)
- mode_ctl |= BGE_MODECTL_FORCE_PCI32;
-
- CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl);
+ BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_FORCE_PCI32);
/*
* Disable memory write invalidate. Apparently it is not supported
@@ -1765,7 +1330,7 @@ bge_blockinit(struct bge_softc *sc)
vaddr_t rcb_addr;
int i;
bge_hostaddr taddr;
- u_int32_t dmactl, val;
+ u_int32_t val;
/*
* Initialize the memory window pointer register so that
@@ -1776,7 +1341,7 @@ bge_blockinit(struct bge_softc *sc)
CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0);
/* Configure mbuf memory pool */
- if (!BGE_IS_5705_PLUS(sc)) {
+ if (BGE_IS_5700_FAMILY(sc)) {
CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR,
BGE_BUFFPOOL_1);
@@ -1793,7 +1358,8 @@ bge_blockinit(struct bge_softc *sc)
/* Configure mbuf pool watermarks */
/* new Broadcom docs strongly recommend these: */
- if (BGE_IS_5717_PLUS(sc)) {
+ if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 ||
+ BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57765) {
CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x2a);
CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xa0);
@@ -1818,16 +1384,8 @@ bge_blockinit(struct bge_softc *sc)
CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10);
/* Enable buffer manager */
- val = BGE_BMANMODE_ENABLE | BGE_BMANMODE_LOMBUF_ATTN;
- /*
- * Change the arbitration algorithm of TXMBUF read request to
- * round-robin instead of priority based for BCM5719. When
- * TXFIFO is almost empty, RDMA will hold its request until
- * TXFIFO is not almost empty.
- */
- if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719)
- val |= BGE_BMANMODE_NO_TX_UNDERRUN;
- CSR_WRITE_4(sc, BGE_BMAN_MODE, val);
+ CSR_WRITE_4(sc, BGE_BMAN_MODE,
+ BGE_BMANMODE_ENABLE|BGE_BMANMODE_LOMBUF_ATTN);
/* Poll for buffer manager start indication */
for (i = 0; i < 2000; i++) {
@@ -1862,29 +1420,21 @@ bge_blockinit(struct bge_softc *sc)
/* Initialize the standard RX ring control block */
rcb = &sc->bge_rdata->bge_info.bge_std_rx_rcb;
BGE_HOSTADDR(rcb->bge_hostaddr, BGE_RING_DMA_ADDR(sc, bge_rx_std_ring));
- if (BGE_IS_5717_PLUS(sc))
- rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512,
- (ETHER_MAX_DIX_LEN << 2));
+ if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 ||
+ BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57765)
+ rcb->bge_maxlen_flags = (BGE_RCB_MAXLEN_FLAGS(512, 0) |
+ (ETHER_MAX_DIX_LEN << 2));
else if (BGE_IS_5705_PLUS(sc))
rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0);
else
rcb->bge_maxlen_flags =
BGE_RCB_MAXLEN_FLAGS(ETHER_MAX_DIX_LEN, 0);
- if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 ||
- BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 ||
- BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720)
- rcb->bge_nicaddr = BGE_STD_RX_RINGS_5717;
- else
- rcb->bge_nicaddr = BGE_STD_RX_RINGS;
-
+ rcb->bge_nicaddr = BGE_STD_RX_RINGS;
CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi);
CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo);
CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr);
- /* Reset the standard receive producer ring producer index. */
- bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0);
-
/*
* Initialize the Jumbo RX ring control block
* We set the 'ring disabled' bit in the flags
@@ -1898,42 +1448,28 @@ bge_blockinit(struct bge_softc *sc)
BGE_RING_DMA_ADDR(sc, bge_rx_jumbo_ring));
rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0,
BGE_RCB_FLAG_USE_EXT_RX_BD | BGE_RCB_FLAG_RING_DISABLED);
- if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 ||
- BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 ||
- BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720)
- rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS_5717;
- else
- rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS;
+ rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS;
CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI,
rcb->bge_hostaddr.bge_addr_hi);
CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO,
rcb->bge_hostaddr.bge_addr_lo);
- /* Program the jumbo receive producer ring RCB parameters. */
CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS,
rcb->bge_maxlen_flags);
- CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr);
- /* Reset the jumbo receive producer ring producer index. */
- bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0);
- }
+ CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR,
+ rcb->bge_nicaddr);
- /* Disable the mini receive producer ring RCB. */
- if (BGE_IS_5700_FAMILY(sc)) {
/* Set up dummy disabled mini ring RCB */
rcb = &sc->bge_rdata->bge_info.bge_mini_rx_rcb;
rcb->bge_maxlen_flags =
BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED);
CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS,
rcb->bge_maxlen_flags);
- /* Reset the mini receive producer ring producer index. */
- bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0);
- /* XXX why? */
bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map,
offsetof(struct bge_ring_data, bge_info),
sizeof (struct bge_gib),
BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
-
}
/* Choose de-pipeline mode for BCM5906 A0, A1 and A2. */
@@ -1955,7 +1491,8 @@ bge_blockinit(struct bge_softc *sc)
CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, 8);
CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, 8);
- if (BGE_IS_5717_PLUS(sc)) {
+ if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 ||
+ BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57765) {
CSR_WRITE_4(sc, BGE_STD_REPL_LWM, 4);
CSR_WRITE_4(sc, BGE_JUMBO_REPL_LWM, 4);
}
@@ -1978,12 +1515,7 @@ bge_blockinit(struct bge_softc *sc)
BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_tx_ring));
RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
- if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 ||
- BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 ||
- BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720)
- RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, BGE_SEND_RING_5717);
- else
- RCB_WRITE_4(sc, rcb_addr, bge_nicaddr,
+ RCB_WRITE_4(sc, rcb_addr, bge_nicaddr,
BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT));
if (BGE_IS_5700_FAMILY(sc))
RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags,
@@ -2003,6 +1535,11 @@ bge_blockinit(struct bge_softc *sc)
rcb_addr += sizeof(struct bge_rcb);
}
+ /* Initialize RX ring indexes */
+ bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0);
+ bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0);
+ bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0);
+
/*
* Set up RX return ring 0
* Note that the NIC address for RX return rings is 0x00000000.
@@ -2025,11 +1562,7 @@ bge_blockinit(struct bge_softc *sc)
BGE_TX_BACKOFF_SEED_MASK);
/* Set inter-packet gap */
- val = 0x2620;
- if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720)
- val |= CSR_READ_4(sc, BGE_TX_LENGTHS) &
- (BGE_TXLEN_JMB_FRM_LEN_MSK | BGE_TXLEN_CNT_DN_VAL_MSK);
- CSR_WRITE_4(sc, BGE_TX_LENGTHS, val);
+ CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620);
/*
* Specify which ring to use for packets that don't match
@@ -2044,7 +1577,7 @@ bge_blockinit(struct bge_softc *sc)
CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181);
/* Inialize RX list placement stats mask. */
- CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007BFFFF);
+ CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF);
CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1);
/* Disable host coalescing until we get it set up */
@@ -2068,7 +1601,7 @@ bge_blockinit(struct bge_softc *sc)
CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks);
CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds);
CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds);
- if (!(BGE_IS_5705_PLUS(sc))) {
+ if (BGE_IS_5700_FAMILY(sc)) {
CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0);
CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0);
}
@@ -2076,7 +1609,7 @@ bge_blockinit(struct bge_softc *sc)
CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0);
/* Set up address of statistics block */
- if (!(BGE_IS_5705_PLUS(sc))) {
+ if (BGE_IS_5700_FAMILY(sc)) {
CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, 0);
CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO,
BGE_RING_DMA_ADDR(sc, bge_info.bge_stats));
@@ -2094,18 +1627,8 @@ bge_blockinit(struct bge_softc *sc)
sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx = 0;
sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx = 0;
- /* Set up status block size. */
- if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 &&
- sc->bge_chipid != BGE_CHIPID_BCM5700_C0) {
- val = BGE_STATBLKSZ_FULL;
- bzero(&sc->bge_rdata->bge_status_block, BGE_STATUS_BLK_SZ);
- } else {
- val = BGE_STATBLKSZ_32BYTE;
- bzero(&sc->bge_rdata->bge_status_block, 32);
- }
-
/* Turn on host coalescing state machine */
- CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE);
+ CSR_WRITE_4(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
/* Turn on RX BD completion state machine and enable attentions */
CSR_WRITE_4(sc, BGE_RBDC_MODE,
@@ -2115,7 +1638,7 @@ bge_blockinit(struct bge_softc *sc)
CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
/* Turn on RX list selector state machine. */
- if (!(BGE_IS_5705_PLUS(sc)))
+ if (BGE_IS_5700_FAMILY(sc))
CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB |
@@ -2130,13 +1653,8 @@ bge_blockinit(struct bge_softc *sc)
else
val |= BGE_PORTMODE_MII;
- /* Allow APE to send/receive frames. */
- if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0)
- val |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN;
-
/* Turn on DMA, clear stats */
CSR_WRITE_4(sc, BGE_MAC_MODE, val);
- DELAY(40);
/* Set misc. local control, enable interrupts on attentions */
CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN);
@@ -2150,7 +1668,7 @@ bge_blockinit(struct bge_softc *sc)
#endif
/* Turn on DMA completion state machine */
- if (!(BGE_IS_5705_PLUS(sc)))
+ if (BGE_IS_5700_FAMILY(sc))
CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
val = BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS;
@@ -2164,7 +1682,6 @@ bge_blockinit(struct bge_softc *sc)
/* Turn on write DMA state machine */
CSR_WRITE_4(sc, BGE_WDMA_MODE, val);
- DELAY(40);
val = BGE_RDMAMODE_ENABLE|BGE_RDMAMODE_ALL_ATTNS;
@@ -2181,62 +1698,8 @@ bge_blockinit(struct bge_softc *sc)
if (sc->bge_flags & BGE_PCIE)
val |= BGE_RDMAMODE_FIFO_LONG_BURST;
- if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) {
- val |= CSR_READ_4(sc, BGE_RDMA_MODE) &
- BGE_RDMAMODE_H2BNC_VLAN_DET;
- /*
- * Allow multiple outstanding read requests from
- * non-LSO read DMA engine.
- */
- val &= ~BGE_RDMAMODE_MULT_DMA_RD_DIS;
- }
-
- if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 ||
- BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 ||
- BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 ||
- BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780 ||
- BGE_IS_5717_PLUS(sc)) {
- dmactl = CSR_READ_4(sc, BGE_RDMA_RSRVCTRL);
- /*
- * Adjust tx margin to prevent TX data corruption and
- * fix internal FIFO overflow.
- */
- if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 ||
- sc->bge_chipid == BGE_CHIPID_BCM5719_A0) {
- dmactl &= ~(BGE_RDMA_RSRVCTRL_FIFO_LWM_MASK |
- BGE_RDMA_RSRVCTRL_FIFO_HWM_MASK |
- BGE_RDMA_RSRVCTRL_TXMRGN_MASK);
- dmactl |= BGE_RDMA_RSRVCTRL_FIFO_LWM_1_5K |
- BGE_RDMA_RSRVCTRL_FIFO_HWM_1_5K |
- BGE_RDMA_RSRVCTRL_TXMRGN_320B;
- }
- /*
- * Enable fix for read DMA FIFO overruns.
- * The fix is to limit the number of RX BDs
- * the hardware would fetch at a fime.
- */
- CSR_WRITE_4(sc, BGE_RDMA_RSRVCTRL, dmactl |
- BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
- }
-
- if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) {
- CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL,
- CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) |
- BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K |
- BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K);
- } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) {
- /*
- * Allow 4KB burst length reads for non-LSO frames.
- * Enable 512B burst length reads for buffer descriptors.
- */
- CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL,
- CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) |
- BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_512 |
- BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K);
- }
-
+ /* Turn on read DMA state machine */
CSR_WRITE_4(sc, BGE_RDMA_MODE, val);
- DELAY(40);
/* Turn on RX data completion state machine */
CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
@@ -2248,13 +1711,12 @@ bge_blockinit(struct bge_softc *sc)
CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE);
/* Turn on Mbuf cluster free state machine */
- if (!BGE_IS_5705_PLUS(sc))
+ if (BGE_IS_5700_FAMILY(sc))
CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
/* Turn on send BD completion state machine */
CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
- /* Turn on send data completion state machine */
val = BGE_SDCMODE_ENABLE;
if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761)
@@ -2272,13 +1734,13 @@ bge_blockinit(struct bge_softc *sc)
/* Turn on send BD selector state machine */
CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
- CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007BFFFF);
+ CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF);
CSR_WRITE_4(sc, BGE_SDI_STATS_CTL,
BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER);
/* ack/clear link change events */
- CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
- BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
+ CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
+ BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
BGE_MACSTAT_LINK_CHANGED);
/* Enable PHY auto polling (for MII/GMII only) */
@@ -2351,7 +1813,7 @@ bge_attach(struct device *parent, struct device *self, void *aux)
pcireg_t pm_ctl, memtype, subid, reg;
pci_intr_handle_t ih;
const char *intrstr = NULL;
- bus_size_t size, apesize;
+ bus_size_t size;
bus_dma_segment_t seg;
int rseg, gotenaddr = 0, aspm_off;
u_int32_t hwcfg = 0;
@@ -2413,8 +1875,6 @@ bge_attach(struct device *parent, struct device *self, void *aux)
switch (PCI_PRODUCT(pa->pa_id)) {
case PCI_PRODUCT_BROADCOM_BCM5717:
case PCI_PRODUCT_BROADCOM_BCM5718:
- case PCI_PRODUCT_BROADCOM_BCM5719:
- case PCI_PRODUCT_BROADCOM_BCM5720:
sc->bge_chipid = pci_conf_read(pc, pa->pa_tag,
BGE_PCI_GEN2_PRODID_ASICREV);
break;
@@ -2477,12 +1937,6 @@ bge_attach(struct device *parent, struct device *self, void *aux)
sizeof(name)) > 0 && strcmp(name, "network") == 0)
sc->bge_flags |= BGE_NO_EEPROM;
#endif
- if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 ||
- BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 ||
- BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720 ||
- BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57765)
- sc->bge_flags |= BGE_5717_PLUS | BGE_575X_PLUS;;
-
if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 ||
BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701 ||
BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 ||
@@ -2495,13 +1949,14 @@ bge_attach(struct device *parent, struct device *self, void *aux)
sc->bge_flags |= BGE_5714_FAMILY;
/* Intentionally exclude BGE_ASICREV_BCM5906 */
- if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 ||
+ if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 ||
+ BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 ||
BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 ||
BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 ||
BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 ||
BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5787 ||
- BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780 ||
- BGE_IS_5717_PLUS(sc))
+ BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57765 ||
+ BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780)
sc->bge_flags |= BGE_5755_PLUS;
if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5750 ||
@@ -2595,55 +2050,10 @@ bge_attach(struct device *parent, struct device *self, void *aux)
sc->bge_flags |= BGE_PHY_BER_BUG;
}
- /* Identify chips with APE processor. */
- switch (BGE_ASICREV(sc->bge_chipid)) {
- case BGE_ASICREV_BCM5717:
- case BGE_ASICREV_BCM5719:
- case BGE_ASICREV_BCM5720:
- case BGE_ASICREV_BCM5761:
- sc->bge_flags |= BGE_APE;
- break;
- }
-
- /* Chips with APE need BAR2 access for APE registers/memory. */
- if ((sc->bge_flags & BGE_APE) != 0) {
- memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, BGE_PCI_BAR2);
- if (pci_mapreg_map(pa, BGE_PCI_BAR2, memtype, 0,
- &sc->bge_apetag, &sc->bge_apehandle, NULL, &apesize, 0)) {
- printf(": couldn't map BAR2 memory\n");
- goto fail_1;
- }
-
- /* Enable APE register/memory access by host driver. */
- reg = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE);
- reg |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR |
- BGE_PCISTATE_ALLOW_APE_SHMEM_WR |
- BGE_PCISTATE_ALLOW_APE_PSPACE_WR;
- pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE, reg);
-
- bge_ape_lock_init(sc);
- bge_ape_read_fw_ver(sc);
- }
-
- /* Identify the chips that use an CPMU. */
- if (BGE_IS_5717_PLUS(sc) ||
- BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 ||
- BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 ||
- BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 ||
- BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780)
- sc->bge_flags |= BGE_CPMU_PRESENT;
-
- if ((sc->bge_flags & BGE_CPMU_PRESENT) != 0)
- BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_500KHZ_CONST);
-
/* Try to reset the chip. */
DPRINTFN(5, ("bge_reset\n"));
- bge_sig_pre_reset(sc, BGE_RESET_START);
bge_reset(sc);
- bge_sig_legacy(sc, BGE_RESET_START);
- bge_sig_post_reset(sc, BGE_RESET_START);
-
bge_chipinit(sc);
#ifdef __sparc64__
@@ -2697,7 +2107,7 @@ bge_attach(struct device *parent, struct device *self, void *aux)
if (!gotenaddr) {
printf(": failed to read station address\n");
- goto fail_2;
+ goto fail_1;
}
/* Allocate the general information block and ring buffers. */
@@ -2706,7 +2116,7 @@ bge_attach(struct device *parent, struct device *self, void *aux)
if (bus_dmamem_alloc(sc->bge_dmatag, sizeof(struct bge_ring_data),
PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) {
printf(": can't alloc rx buffers\n");
- goto fail_2;
+ goto fail_1;
}
DPRINTFN(5, ("bus_dmamem_map\n"));
if (bus_dmamem_map(sc->bge_dmatag, &seg, rseg,
@@ -2714,20 +2124,20 @@ bge_attach(struct device *parent, struct device *self, void *aux)
BUS_DMA_NOWAIT)) {
printf(": can't map dma buffers (%lu bytes)\n",
sizeof(struct bge_ring_data));
- goto fail_3;
+ goto fail_2;
}
DPRINTFN(5, ("bus_dmamem_create\n"));
if (bus_dmamap_create(sc->bge_dmatag, sizeof(struct bge_ring_data), 1,
sizeof(struct bge_ring_data), 0,
BUS_DMA_NOWAIT, &sc->bge_ring_map)) {
printf(": can't create dma map\n");
- goto fail_4;
+ goto fail_3;
}
DPRINTFN(5, ("bus_dmamem_load\n"));
if (bus_dmamap_load(sc->bge_dmatag, sc->bge_ring_map, kva,
sizeof(struct bge_ring_data), NULL,
BUS_DMA_NOWAIT)) {
- goto fail_5;
+ goto fail_4;
}
DPRINTFN(5, ("bzero\n"));
@@ -2743,12 +2153,12 @@ bge_attach(struct device *parent, struct device *self, void *aux)
sc->bge_tx_max_coal_bds = 400;
/* 5705 limits RX return ring to 512 entries. */
- if (BGE_IS_5717_PLUS(sc))
+ if (BGE_IS_5700_FAMILY(sc) ||
+ BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 ||
+ BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57765)
sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT;
- else if (BGE_IS_5705_PLUS(sc))
- sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705;
else
- sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT;
+ sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705;
/* Set up ifnet structure */
ifp = &sc->arpcom.ac_if;
@@ -2809,7 +2219,7 @@ bge_attach(struct device *parent, struct device *self, void *aux)
if (bge_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET,
sizeof(hwcfg))) {
printf(": failed to read media type\n");
- goto fail_6;
+ goto fail_5;
}
hwcfg = ntohl(hwcfg);
}
@@ -2832,7 +2242,7 @@ bge_attach(struct device *parent, struct device *self, void *aux)
if (intrstr != NULL)
printf(" at %s", intrstr);
printf("\n");
- goto fail_6;
+ goto fail_5;
}
/*
@@ -2885,22 +2295,18 @@ bge_attach(struct device *parent, struct device *self, void *aux)
timeout_set(&sc->bge_rxtimeout, bge_rxtick, sc);
return;
-fail_6:
+fail_5:
bus_dmamap_unload(sc->bge_dmatag, sc->bge_ring_map);
-fail_5:
+fail_4:
bus_dmamap_destroy(sc->bge_dmatag, sc->bge_ring_map);
-fail_4:
+fail_3:
bus_dmamem_unmap(sc->bge_dmatag, kva,
sizeof(struct bge_ring_data));
-fail_3:
- bus_dmamem_free(sc->bge_dmatag, &seg, rseg);
-
fail_2:
- if ((sc->bge_flags & BGE_APE) != 0)
- bus_space_unmap(sc->bge_apetag, sc->bge_apehandle, apesize);
+ bus_dmamem_free(sc->bge_dmatag, &seg, rseg);
fail_1:
bus_space_unmap(sc->bge_btag, sc->bge_bhandle, size);
@@ -2935,57 +2341,30 @@ void
bge_reset(struct bge_softc *sc)
{
struct pci_attach_args *pa = &sc->bge_pa;
- pcireg_t cachesize, command;
- u_int32_t reset, mac_mode, mac_mode_mask, val;
- void (*write_op)(struct bge_softc *, int, int);
- int i;
-
- mac_mode_mask = BGE_MACMODE_HALF_DUPLEX | BGE_MACMODE_PORTMODE;
- if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0)
- mac_mode_mask |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN;
- mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) & mac_mode_mask;
-
- if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) &&
- BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906) {
- if (sc->bge_flags & BGE_PCIE)
- write_op = bge_writembx;
- else
- write_op = bge_writemem_ind;
- } else
- write_op = bge_writereg_ind;
-
- /* Take APE lock when performing reset. */
- bge_ape_lock(sc, BGE_APE_LOCK_GRC);
+ pcireg_t cachesize, command, pcistate, new_pcistate;
+ u_int32_t reset;
+ int i, val = 0;
/* Save some important PCI state. */
cachesize = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_CACHESZ);
command = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_CMD);
+ pcistate = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE);
pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL,
- BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR |
- BGE_PCIMISCCTL_ENDIAN_WORDSWAP | BGE_PCIMISCCTL_PCISTATE_RW);
+ BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
+ BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_PCISTATE_RW);
/* Disable fastboot on controllers that support it. */
if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5752 ||
BGE_IS_5755_PLUS(sc))
CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0);
- /*
- * Write the magic number to SRAM at offset 0xB50.
- * When firmware finishes its initialization it will
- * write ~BGE_SRAM_FW_MB_MAGIC to the same location.
- */
- bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER);
-
- reset = BGE_MISCCFG_RESET_CORE_CLOCKS | BGE_32BITTIME_66MHZ;
+ reset = BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1);
if (sc->bge_flags & BGE_PCIE) {
- if (BGE_ASICREV(sc->bge_chipid != BGE_ASICREV_BCM5785) &&
- !BGE_IS_5717_PLUS(sc)) {
- if (CSR_READ_4(sc, 0x7e2c) == 0x60) {
- /* PCI Express 1.0 system */
- CSR_WRITE_4(sc, 0x7e2c, 0x20);
- }
+ if (CSR_READ_4(sc, 0x7e2c) == 0x60) {
+ /* PCI Express 1.0 system */
+ CSR_WRITE_4(sc, 0x7e2c, 0x20);
}
if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
/*
@@ -3001,17 +2380,11 @@ bge_reset(struct bge_softc *sc)
* Set GPHY Power Down Override to leave GPHY
* powered up in D0 uninitialized.
*/
- if (BGE_IS_5705_PLUS(sc) &&
- (sc->bge_flags & BGE_CPMU_PRESENT) == 0)
+ if (BGE_IS_5705_PLUS(sc))
reset |= BGE_MISCCFG_KEEP_GPHY_POWER;
/* Issue global reset */
- write_op(sc, BGE_MISC_CFG, reset);
-
- if (sc->bge_flags & BGE_PCIE)
- DELAY(100 * 1000);
- else
- DELAY(1000);
+ bge_writereg_ind(sc, BGE_MISC_CFG, reset);
if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) {
u_int32_t status, ctrl;
@@ -3026,6 +2399,8 @@ bge_reset(struct bge_softc *sc)
sc->bge_flags |= BGE_NO_EEPROM;
}
+ DELAY(1000);
+
if (sc->bge_flags & BGE_PCIE) {
if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) {
pcireg_t v;
@@ -3045,36 +2420,26 @@ bge_reset(struct bge_softc *sc)
/* Reset some of the PCI state that got zapped by reset */
pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL,
- BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR |
- BGE_PCIMISCCTL_ENDIAN_WORDSWAP | BGE_PCIMISCCTL_PCISTATE_RW);
- val = BGE_PCISTATE_ROM_ENABLE | BGE_PCISTATE_ROM_RETRY_ENABLE;
- if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0 &&
- (sc->bge_flags & BGE_PCIX) != 0)
- val |= BGE_PCISTATE_RETRY_SAME_DMA;
- if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0)
- val |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR |
- BGE_PCISTATE_ALLOW_APE_SHMEM_WR |
- BGE_PCISTATE_ALLOW_APE_PSPACE_WR;
- pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE, val);
+ BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
+ BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_PCISTATE_RW);
pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_CACHESZ, cachesize);
pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_CMD, command);
+ bge_writereg_ind(sc, BGE_MISC_CFG, (65 << 1));
/* Enable memory arbiter. */
if (BGE_IS_5714_FAMILY(sc)) {
+ u_int32_t val;
+
val = CSR_READ_4(sc, BGE_MARB_MODE);
CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val);
} else
CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
- /* Fix up byte swapping */
- CSR_WRITE_4(sc, BGE_MODE_CTL, bge_dma_swap_options(sc));
-
- val = CSR_READ_4(sc, BGE_MAC_MODE);
- val = (val & ~mac_mode_mask) | mac_mode;
- CSR_WRITE_4(sc, BGE_MAC_MODE, val);
- DELAY(40);
-
- bge_ape_unlock(sc, BGE_APE_LOCK_GRC);
+ /*
+ * Prevent PXE restart: write a magic number to the
+ * general communications memory at 0xB50.
+ */
+ bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER);
if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) {
for (i = 0; i < BGE_TIMEOUT; i++) {
@@ -3103,12 +2468,36 @@ bge_reset(struct bge_softc *sc)
if (i >= BGE_TIMEOUT && (!(sc->bge_flags & BGE_NO_EEPROM)))
printf("%s: firmware handshake timed out\n",
sc->bge_dev.dv_xname);
- /* BCM57765 A0 needs additional time before accessing. */
- if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0)
- DELAY(10 * 1000); /* XXX */
}
/*
+ * XXX Wait for the value of the PCISTATE register to
+ * return to its original pre-reset state. This is a
+ * fairly good indicator of reset completion. If we don't
+ * wait for the reset to fully complete, trying to read
+ * from the device's non-PCI registers may yield garbage
+ * results.
+ */
+ for (i = 0; i < BGE_TIMEOUT; i++) {
+ new_pcistate = pci_conf_read(pa->pa_pc, pa->pa_tag,
+ BGE_PCI_PCISTATE);
+ if ((new_pcistate & ~BGE_PCISTATE_RESERVED) ==
+ (pcistate & ~BGE_PCISTATE_RESERVED))
+ break;
+ DELAY(10);
+ }
+ if ((new_pcistate & ~BGE_PCISTATE_RESERVED) !=
+ (pcistate & ~BGE_PCISTATE_RESERVED)) {
+ DPRINTFN(5, ("%s: pcistate failed to revert\n",
+ sc->bge_dev.dv_xname));
+ }
+
+ /* Fix up byte swapping */
+ CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS);
+
+ CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
+
+ /*
* The 5704 in TBI mode apparently needs some special
* adjustment to insure the SERDES drive level is set
* to 1.2V.
@@ -3123,19 +2512,17 @@ bge_reset(struct bge_softc *sc)
}
if (sc->bge_flags & BGE_PCIE &&
- !BGE_IS_5717_PLUS(sc) &&
sc->bge_chipid != BGE_CHIPID_BCM5750_A0 &&
- BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5785) {
+ BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5717 &&
+ BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5785 &&
+ BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM57765) {
u_int32_t v;
/* Enable PCI Express bug fix */
v = CSR_READ_4(sc, 0x7c00);
CSR_WRITE_4(sc, 0x7c00, v | (1<<25));
}
-
- if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720)
- BGE_CLRBIT(sc, BGE_CPMU_CLCK_ORIDE,
- CPMU_CLCK_ORIDE_MAC_ORIDE_EN);
+ DELAY(10000);
}
/*
@@ -3245,7 +2632,7 @@ bge_rxeof(struct bge_softc *sc)
m->m_data += ETHER_ALIGN;
}
#endif
- m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN;
+ m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN;
m->m_pkthdr.rcvif = ifp;
/*
@@ -3376,14 +2763,10 @@ bge_intr(void *xsc)
struct bge_softc *sc;
struct ifnet *ifp;
u_int32_t statusword;
- u_int32_t intrmask = BGE_PCISTATE_INTR_NOT_ACTIVE;
sc = xsc;
ifp = &sc->arpcom.ac_if;
- if (BGE_IS_5717_PLUS(sc))
- intrmask = 0;
-
/* It is possible for the interrupt to arrive before
* the status block is updated prior to the interrupt.
* Reading the PCI State register will confirm whether the
@@ -3391,15 +2774,10 @@ bge_intr(void *xsc)
*/
/* read status word from status block */
- bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map,
- offsetof(struct bge_ring_data, bge_status_block),
- sizeof (struct bge_status_block),
- BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
-
statusword = sc->bge_rdata->bge_status_block.bge_status;
if ((statusword & BGE_STATFLAG_UPDATED) ||
- (~CSR_READ_4(sc, BGE_PCI_PCISTATE) & intrmask)) {
+ (!(CSR_READ_4(sc, BGE_PCI_PCISTATE) & BGE_PCISTATE_INTR_NOT_ACTIVE))) {
/* Ack interrupt and stop others from occurring. */
bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
@@ -3407,11 +2785,6 @@ bge_intr(void *xsc)
/* clear status word */
sc->bge_rdata->bge_status_block.bge_status = 0;
- bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map,
- offsetof(struct bge_ring_data, bge_status_block),
- sizeof (struct bge_status_block),
- BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
-
if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 ||
statusword & BGE_STATFLAG_LINKSTATE_CHANGED ||
BGE_STS_BIT(sc, BGE_STS_LINK_EVT))
@@ -3465,7 +2838,7 @@ bge_tick(void *xsc)
*/
if (!BGE_STS_BIT(sc, BGE_STS_LINK))
mii_tick(mii);
- }
+ }
timeout_add_sec(&sc->bge_timeout, 1);
@@ -3480,12 +2853,11 @@ bge_stats_update_regs(struct bge_softc *sc)
ifp->if_collisions += CSR_READ_4(sc, BGE_MAC_STATS +
offsetof(struct bge_mac_stats_regs, etherStatsCollisions));
- sc->bge_rx_discards += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS);
- sc->bge_rx_inerrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS);
- sc->bge_rx_overruns += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS);
+ ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS);
+
+ ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS);
- ifp->if_ierrors = sc->bge_rx_discards + sc->bge_rx_inerrors +
- sc->bge_rx_overruns;
+ ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS);
}
void
@@ -3835,7 +3207,7 @@ bge_init(void *xsc)
struct bge_softc *sc = xsc;
struct ifnet *ifp;
u_int16_t *m;
- u_int32_t mode;
+ u_int32_t rxmode;
int s;
s = splnet();
@@ -3844,11 +3216,7 @@ bge_init(void *xsc)
/* Cancel pending I/O and flush buffers. */
bge_stop(sc);
- bge_sig_pre_reset(sc, BGE_RESET_START);
bge_reset(sc);
- bge_sig_legacy(sc, BGE_RESET_START);
- bge_sig_post_reset(sc, BGE_RESET_START);
-
bge_chipinit(sc);
/*
@@ -3920,28 +3288,16 @@ bge_init(void *xsc)
/* Init TX ring. */
bge_init_tx_ring(sc);
- /* Enable TX MAC state machine lockup fix. */
- mode = CSR_READ_4(sc, BGE_TX_MODE);
- if (BGE_IS_5755_PLUS(sc) ||
- BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906)
- mode |= BGE_TXMODE_MBUF_LOCKUP_FIX;
- if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) {
- mode &= ~(BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE);
- mode |= CSR_READ_4(sc, BGE_TX_MODE) &
- (BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE);
- }
-
/* Turn on transmitter */
- CSR_WRITE_4(sc, BGE_TX_MODE, mode | BGE_TXMODE_ENABLE);
- DELAY(100);
+ BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE);
+
+ rxmode = BGE_RXMODE_ENABLE;
- mode = CSR_READ_4(sc, BGE_RX_MODE);
if (BGE_IS_5755_PLUS(sc))
- mode |= BGE_RXMODE_IPV6_ENABLE;
+ rxmode |= BGE_RXMODE_RX_IPV6_CSUM_ENABLE;
/* Turn on receiver */
- CSR_WRITE_4(sc, BGE_RX_MODE, mode | BGE_RXMODE_ENABLE);
- DELAY(10);
+ BGE_SETBIT(sc, BGE_RX_MODE, rxmode);
CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 2);
@@ -3999,7 +3355,6 @@ bge_ifmedia_upd(struct ifnet *ifp)
CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig);
}
}
- DELAY(40);
break;
case IFM_1000_SX:
if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
@@ -4204,13 +3559,6 @@ bge_stop(struct bge_softc *sc)
ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
/*
- * Tell firmware we're shutting down.
- */
- /* bge_stop_fw(sc); */
- bge_sig_pre_reset(sc, BGE_RESET_SHUTDOWN);
-
-
- /*
* Disable all of the receiver blocks
*/
bge_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
@@ -4246,14 +3594,14 @@ bge_stop(struct bge_softc *sc)
CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
- if (!BGE_IS_5705_PLUS(sc)) {
+ if (BGE_IS_5700_FAMILY(sc)) {
bge_stop_block(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE);
bge_stop_block(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
}
- bge_reset(sc);
- bge_sig_legacy(sc, BGE_RESET_SHUTDOWN);
- bge_sig_post_reset(sc, BGE_RESET_SHUTDOWN);
+ /* Disable host interrupts. */
+ BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
+ bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
/*
* Tell firmware we're shutting down.
@@ -4339,7 +3687,7 @@ bge_link_upd(struct bge_softc *sc)
BRGPHY_MII_IMR, BRGPHY_INTRS);
}
return;
- }
+ }
if (sc->bge_flags & BGE_PHY_FIBER_TBI) {
status = CSR_READ_4(sc, BGE_MAC_STS);
@@ -4364,13 +3712,13 @@ bge_link_upd(struct bge_softc *sc)
if_link_state_change(ifp);
ifp->if_baudrate = 0;
}
- /*
+ /*
* Discard link events for MII/GMII cards if MI auto-polling disabled.
* This should not happen since mii callouts are locked now, but
* we keep this check for debug.
*/
} else if (BGE_STS_BIT(sc, BGE_STS_AUTOPOLL)) {
- /*
+ /*
* Some broken BCM chips have BGE_STATFLAG_LINKSTATE_CHANGED bit
* in status word always set. Workaround this bug by reading
* PHY link status directly.
diff --git a/sys/dev/pci/if_bgereg.h b/sys/dev/pci/if_bgereg.h
index cba2fed83f7..33df0cb9676 100644
--- a/sys/dev/pci/if_bgereg.h
+++ b/sys/dev/pci/if_bgereg.h
@@ -1,4 +1,4 @@
-/* $OpenBSD: if_bgereg.h,v 1.110 2013/01/29 00:41:02 dlg Exp $ */
+/* $OpenBSD: if_bgereg.h,v 1.111 2013/01/30 11:15:06 dlg Exp $ */
/*
* Copyright (c) 2001 Wind River Systems
@@ -156,7 +156,6 @@
#define BGE_PCI_BIST 0x0F
#define BGE_PCI_BAR0 0x10
#define BGE_PCI_BAR1 0x14
-#define BGE_PCI_BAR2 0x18
#define BGE_PCI_SUBSYS 0x2C
#define BGE_PCI_SUBVID 0x2E
#define BGE_PCI_ROMBASE 0x30
@@ -407,14 +406,11 @@
#define BGE_PCISTATE_PCI_BUSMODE 0x00000004 /* 1 = PCI, 0 = PCI-X */
#define BGE_PCISTATE_PCI_BUSSPEED 0x00000008 /* 1 = 66/133, 0 = 33/66 */
#define BGE_PCISTATE_32BIT_BUS 0x00000010 /* 1 = 32bit, 0 = 64bit */
-#define BGE_PCISTATE_ROM_ENABLE 0x00000020
-#define BGE_PCISTATE_ROM_RETRY_ENABLE 0x00000040
+#define BGE_PCISTATE_WANT_EXPROM 0x00000020
+#define BGE_PCISTATE_EXPROM_RETRY 0x00000040
#define BGE_PCISTATE_FLATVIEW_MODE 0x00000100
-#define BGE_PCISTATE_PCI_TGT_RETRY_MAX 0x00000E00
#define BGE_PCISTATE_RETRY_SAME_DMA 0x00002000
-#define BGE_PCISTATE_ALLOW_APE_CTLSPC_WR 0x00010000
-#define BGE_PCISTATE_ALLOW_APE_SHMEM_WR 0x00020000
-#define BGE_PCISTATE_ALLOW_APE_PSPACE_WR 0x00040000
+#define BGE_PCISTATE_PCI_TGT_RETRY_MAX 0x00000E00
/*
* The following bits in PCI state register are reserved.
@@ -679,8 +675,6 @@
#define BGE_MACMODE_TXDMA_ENB 0x00200000
#define BGE_MACMODE_RXDMA_ENB 0x00400000
#define BGE_MACMODE_FRMHDR_DMA_ENB 0x00800000
-#define BGE_MACMODE_APE_RX_EN 0x08000000
-#define BGE_MACMODE_APE_TX_EN 0x10000000
#define BGE_PORTMODE_NONE 0x00000000
#define BGE_PORTMODE_MII 0x00000004
@@ -768,7 +762,7 @@
#define BGE_RXMODE_RX_PROMISC 0x00000100
#define BGE_RXMODE_RX_NO_CRC_CHECK 0x00000200
#define BGE_RXMODE_RX_KEEP_VLAN_DIAG 0x00000400
-#define BGE_RXMODE_IPV6_ENABLE 0x01000000
+#define BGE_RXMODE_RX_IPV6_CSUM_ENABLE 0x01000000
/* Receive MAC status register */
#define BGE_RXSTAT_REMOTE_XOFFED 0x00000001
@@ -2135,112 +2129,6 @@
#define BGE_MEMWIN_START 0x00008000
#define BGE_MEMWIN_END 0x0000FFFF
-/* BAR1 (APE) Register Definitions */
-
-#define BGE_APE_GPIO_MSG 0x0008
-#define BGE_APE_EVENT 0x000C
-#define BGE_APE_LOCK_REQ 0x002C
-#define BGE_APE_LOCK_GRANT 0x004C
-
-#define BGE_APE_GPIO_MSG_SHIFT 4
-
-#define BGE_APE_EVENT_1 0x00000001
-
-#define BGE_APE_LOCK_REQ_DRIVER0 0x00001000
-
-#define BGE_APE_LOCK_GRANT_DRIVER0 0x00001000
-
-/* APE Shared Memory block (writable by APE only) */
-#define BGE_APE_SEG_SIG 0x4000
-#define BGE_APE_FW_STATUS 0x400C
-#define BGE_APE_FW_FEATURES 0x4010
-#define BGE_APE_FW_BEHAVIOR 0x4014
-#define BGE_APE_FW_VERSION 0x4018
-#define BGE_APE_FW_HEARTBEAT_INTERVAL 0x4024
-#define BGE_APE_FW_HEARTBEAT 0x4028
-#define BGE_APE_FW_ERROR_FLAGS 0x4074
-
-#define BGE_APE_SEG_SIG_MAGIC 0x41504521
-
-#define BGE_APE_FW_STATUS_READY 0x00000100
-
-#define BGE_APE_FW_FEATURE_DASH 0x00000001
-#define BGE_APE_FW_FEATURE_NCSI 0x00000002
-
-#define BGE_APE_FW_VERSION_MAJMSK 0xFF000000
-#define BGE_APE_FW_VERSION_MAJSFT 24
-#define BGE_APE_FW_VERSION_MINMSK 0x00FF0000
-#define BGE_APE_FW_VERSION_MINSFT 16
-#define BGE_APE_FW_VERSION_REVMSK 0x0000FF00
-#define BGE_APE_FW_VERSION_REVSFT 8
-#define BGE_APE_FW_VERSION_BLDMSK 0x000000FF
-
-/* Host Shared Memory block (writable by host only) */
-#define BGE_APE_HOST_SEG_SIG 0x4200
-#define BGE_APE_HOST_SEG_LEN 0x4204
-#define BGE_APE_HOST_INIT_COUNT 0x4208
-#define BGE_APE_HOST_DRIVER_ID 0x420C
-#define BGE_APE_HOST_BEHAVIOR 0x4210
-#define BGE_APE_HOST_HEARTBEAT_INT_MS 0x4214
-#define BGE_APE_HOST_HEARTBEAT_COUNT 0x4218
-#define BGE_APE_HOST_DRVR_STATE 0x421C
-#define BGE_APE_HOST_WOL_SPEED 0x4224
-
-#define BGE_APE_HOST_SEG_SIG_MAGIC 0x484F5354
-
-#define BGE_APE_HOST_SEG_LEN_MAGIC 0x00000020
-
-#define BGE_APE_HOST_DRIVER_ID_FBSD 0xF6000000
-#define BGE_APE_HOST_DRIVER_ID_MAGIC(maj, min) \
- (BGE_APE_HOST_DRIVER_ID_FBSD | \
- ((maj) & 0xffd) << 16 | ((min) & 0xff) << 8)
-
-#define BGE_APE_HOST_BEHAV_NO_PHYLOCK 0x00000001
-
-#define BGE_APE_HOST_HEARTBEAT_INT_DISABLE 0
-#define BGE_APE_HOST_HEARTBEAT_INT_5SEC 5000
-
-#define BGE_APE_HOST_DRVR_STATE_START 0x00000001
-#define BGE_APE_HOST_DRVR_STATE_UNLOAD 0x00000002
-#define BGE_APE_HOST_DRVR_STATE_WOL 0x00000003
-#define BGE_APE_HOST_DRVR_STATE_SUSPEND 0x00000004
-
-#define BGE_APE_HOST_WOL_SPEED_AUTO 0x00008000
-
-#define BGE_APE_EVENT_STATUS 0x4300
-
-#define BGE_APE_EVENT_STATUS_DRIVER_EVNT 0x00000010
-#define BGE_APE_EVENT_STATUS_STATE_CHNGE 0x00000500
-#define BGE_APE_EVENT_STATUS_STATE_START 0x00010000
-#define BGE_APE_EVENT_STATUS_STATE_UNLOAD 0x00020000
-#define BGE_APE_EVENT_STATUS_STATE_WOL 0x00030000
-#define BGE_APE_EVENT_STATUS_STATE_SUSPEND 0x00040000
-#define BGE_APE_EVENT_STATUS_EVENT_PENDING 0x80000000
-
-#define BGE_APE_DEBUG_LOG 0x4E00
-#define BGE_APE_DEBUG_LOG_LEN 0x0100
-
-#define BGE_APE_PER_LOCK_REQ 0x8400
-#define BGE_APE_PER_LOCK_GRANT 0x8420
-
-#define BGE_APE_LOCK_PER_REQ_DRIVER0 0x00001000
-#define BGE_APE_LOCK_PER_REQ_DRIVER1 0x00000002
-#define BGE_APE_LOCK_PER_REQ_DRIVER2 0x00000004
-#define BGE_APE_LOCK_PER_REQ_DRIVER3 0x00000008
-
-#define BGE_APE_PER_LOCK_GRANT_DRIVER0 0x00001000
-#define BGE_APE_PER_LOCK_GRANT_DRIVER1 0x00000002
-#define BGE_APE_PER_LOCK_GRANT_DRIVER2 0x00000004
-#define BGE_APE_PER_LOCK_GRANT_DRIVER3 0x00000008
-
-/* APE Mutex Resources */
-#define BGE_APE_LOCK_PHY0 0
-#define BGE_APE_LOCK_GRC 1
-#define BGE_APE_LOCK_PHY1 2
-#define BGE_APE_LOCK_PHY2 3
-#define BGE_APE_LOCK_MEM 4
-#define BGE_APE_LOCK_PHY3 5
-#define BGE_APE_LOCK_GPIO 7
#define BGE_MEMWIN_READ(pc, tag, x, val) \
do { \
@@ -2382,7 +2270,6 @@ struct bge_ext_rx_bd {
#define BGE_RXBDFLAG_IP_CSUM 0x1000
#define BGE_RXBDFLAG_TCP_UDP_CSUM 0x2000
#define BGE_RXBDFLAG_TCP_UDP_IS_TCP 0x4000
-#define BGE_RXBDFLAG_IPV6 0x8000
#define BGE_RXERRFLAG_BAD_CRC 0x0001
#define BGE_RXERRFLAG_COLL_DETECT 0x0002
@@ -2392,7 +2279,6 @@ struct bge_ext_rx_bd {
#define BGE_RXERRFLAG_RUNT 0x0020
#define BGE_RXERRFLAG_TRUNC_NO_RSRCS 0x0040
#define BGE_RXERRFLAG_GIANT 0x0080
-#define BGE_RXERRFLAG_IP_CSUM_NOK 0x1000 /* 5717 */
struct bge_sts_idx {
#if BYTE_ORDER == LITTLE_ENDIAN
@@ -2699,18 +2585,6 @@ struct bge_gib {
#define BGE_CLRBIT(sc, reg, x) \
CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) & ~(x)))
-/* BAR2 APE register access macros. */
-#define APE_WRITE_4(sc, reg, val) \
- bus_space_write_4(sc->bge_apetag, sc->bge_apehandle, reg, val)
-
-#define APE_READ_4(sc, reg) \
- bus_space_read_4(sc->bge_apetag, sc->bge_apehandle, reg)
-
-#define APE_SETBIT(sc, reg, x) \
- APE_WRITE_4(sc, reg, (APE_READ_4(sc, reg) | (x)))
-#define APE_CLRBIT(sc, reg, x) \
- APE_WRITE_4(sc, reg, (APE_READ_4(sc, reg) & ~(x)))
-
#define PCI_SETBIT(pc, tag, reg, x) \
pci_conf_write(pc, tag, reg, (pci_conf_read(pc, tag, reg) | (x)))
#define PCI_CLRBIT(pc, tag, reg, x) \
@@ -2764,10 +2638,6 @@ struct bge_ring_data {
#define BGE_NTXSEG 31
#endif
-#define BGE_STATUS_BLK_SZ sizeof (struct bge_status_block)
-
-#define BGE_STATS_SZ sizeof (struct bge_stats)
-
/*
* Mbuf pointers. We need these to keep track of the virtual addresses
* of our mbuf chains since we can only convert from physical to virtual,
@@ -2806,8 +2676,6 @@ struct bge_softc {
struct arpcom arpcom; /* interface info */
bus_space_handle_t bge_bhandle;
bus_space_tag_t bge_btag;
- bus_space_handle_t bge_apehandle;
- bus_space_tag_t bge_apetag;
void *bge_intrhand;
struct pci_attach_args bge_pa;
struct mii_data bge_mii;
@@ -2839,18 +2707,8 @@ struct bge_softc {
#define BGE_5755_PLUS 0x00800000
#define BGE_5714_FAMILY 0x01000000
#define BGE_5700_FAMILY 0x02000000
-#define BGE_5717_PLUS 0x04000000
-#define BGE_CPMU_PRESENT 0x08000000
-#define BGE_APE 0x10000000
-#define BGE_575X_PLUS 0x20000000
bus_dma_tag_t bge_dmatag;
- u_int32_t bge_mfw_flags; /* Management F/W flags */
-#define BGE_MFW_ON_RXCPU 0x00000001
-#define BGE_MFW_ON_APE 0x00000002
-#define BGE_MFW_TYPE_NCSI 0x00000004
-#define BGE_MFW_TYPE_DASH 0x00000008
- int bge_phy_ape_lock;
int bge_phy_addr;
u_int32_t bge_chipid;
struct bge_ring_data *bge_rdata; /* rings */
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-02 03:35:55 +0000