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authorTheo de Raadt <deraadt@cvs.openbsd.org>1997-07-03 07:22:55 +0000
committerTheo de Raadt <deraadt@cvs.openbsd.org>1997-07-03 07:22:55 +0000
commit7356e39dca6317808ddf2835743d1bab6f7606e7 (patch)
treec5b9a8f44c54eee6124c462cb488121c6d8e6840 /sys
parent01966f4ac3366c4d42c79898f742450d06bc6164 (diff)
Intel EtherExpress Pro/100B driver, still needs a fix or two
Diffstat (limited to 'sys')
-rw-r--r--sys/dev/pci/files.pci7
-rw-r--r--sys/dev/pci/if_fxp.c1576
-rw-r--r--sys/dev/pci/if_fxpreg.h321
-rw-r--r--sys/dev/pci/if_fxpvar.h116
4 files changed, 2019 insertions, 1 deletions
diff --git a/sys/dev/pci/files.pci b/sys/dev/pci/files.pci
index 6341a2dec23..cd7478d2c7e 100644
--- a/sys/dev/pci/files.pci
+++ b/sys/dev/pci/files.pci
@@ -1,4 +1,4 @@
-# $OpenBSD: files.pci,v 1.10 1996/11/28 23:28:03 niklas Exp $
+# $OpenBSD: files.pci,v 1.11 1997/07/03 07:22:54 deraadt Exp $
# $NetBSD: files.pci,v 1.20 1996/09/24 17:47:15 christos Exp $
#
# Config.new file and device description for machine-independent PCI code.
@@ -60,3 +60,8 @@ file dev/pci/ppb.c ppb
# Cyclades Cyclom-8/16/32
attach cy at pci with cy_pci
file dev/pci/cy_pci.c cy_pci
+
+# Intel EtherExpress PRO 10/100B
+device fxp: ether, ifnet
+attach fxp at pci
+file dev/pci/if_fxp.c fxp
diff --git a/sys/dev/pci/if_fxp.c b/sys/dev/pci/if_fxp.c
new file mode 100644
index 00000000000..76d24aa5e85
--- /dev/null
+++ b/sys/dev/pci/if_fxp.c
@@ -0,0 +1,1576 @@
+/* $NetBSD: if_fxp.c,v 1.2 1997/06/05 02:01:55 thorpej Exp $ */
+
+/*
+ * Copyright (c) 1995, David Greenman
+ * All rights reserved.
+ *
+ * Modifications to support NetBSD:
+ * Copyright (c) 1997 Jason R. Thorpe. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice unmodified, this list of conditions, and the following
+ * disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * Id: if_fxp.c,v 1.34 1997/04/23 01:44:30 davidg Exp
+ */
+
+/*
+ * Intel EtherExpress Pro/100B PCI Fast Ethernet driver
+ */
+
+#include "bpfilter.h"
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/mbuf.h>
+#include <sys/malloc.h>
+#include <sys/kernel.h>
+#include <sys/socket.h>
+#include <sys/syslog.h>
+
+#include <net/if.h>
+#include <net/if_dl.h>
+#include <net/if_types.h>
+
+#ifdef INET
+#include <netinet/in.h>
+#include <netinet/in_systm.h>
+#include <netinet/in_var.h>
+#include <netinet/ip.h>
+#endif
+
+#ifdef IPX
+#include <netipx/ipx.h>
+#include <netipx/ipx_if.h>
+#endif
+
+#ifdef NS
+#include <netns/ns.h>
+#include <netns/ns_if.h>
+#endif
+
+#if NBPFILTER > 0
+#include <net/bpf.h>
+#include <net/bpfdesc.h>
+#endif
+
+#if defined(__NetBSD__) || defined(__OpenBSD__)
+
+#include <sys/ioctl.h>
+#include <sys/errno.h>
+#include <sys/device.h>
+
+#if defined(__NetBSD__)
+#include <net/if_ether.h>
+#include <netinet/if_inarp.h>
+#endif
+
+#if defined(__OpenBSD__)
+#include <netinet/if_ether.h>
+#endif
+
+#include <vm/vm.h>
+
+#include <machine/cpu.h>
+#include <machine/bus.h>
+#include <machine/intr.h>
+
+#include <dev/pci/if_fxpreg.h>
+#include <dev/pci/if_fxpvar.h>
+
+#include <dev/pci/pcivar.h>
+#include <dev/pci/pcireg.h>
+#include <dev/pci/pcidevs.h>
+
+#ifdef __alpha__ /* XXX */
+/* XXX XXX NEED REAL DMA MAPPING SUPPORT XXX XXX */
+#undef vtophys
+#define vtophys(va) alpha_XXX_dmamap((vm_offset_t)(va))
+#endif /* __alpha__ */
+
+#else /* __FreeBSD__ */
+
+#include <sys/sockio.h>
+
+#include <netinet/if_ether.h>
+
+#include <vm/vm.h> /* for vtophys */
+#include <vm/vm_param.h> /* for vtophys */
+#include <vm/pmap.h> /* for vtophys */
+#include <machine/clock.h> /* for DELAY */
+
+#include <pci/pcivar.h>
+#include <pci/if_fxpreg.h>
+#include <pci/if_fxpvar.h>
+
+#endif /* __NetBSD__ || __OpenBSD__ */
+
+/*
+ * NOTE! On the Alpha, we have an alignment constraint. The
+ * card DMAs the packet immediately following the RFA. However,
+ * the first thing in the packet is a 14-byte Ethernet header.
+ * This means that the packet is misaligned. To compensate,
+ * we actually offset the RFA 2 bytes into the cluster. This
+ * alignes the packet after the Ethernet header at a 32-bit
+ * boundary. HOWEVER! This means that the RFA is misaligned!
+ */
+#define RFA_ALIGNMENT_FUDGE 2
+
+/*
+ * Inline function to copy a 16-bit aligned 32-bit quantity.
+ */
+static __inline void fxp_lwcopy __P((volatile u_int32_t *,
+ volatile u_int32_t *));
+static __inline void
+fxp_lwcopy(src, dst)
+ volatile u_int32_t *src, *dst;
+{
+ volatile u_int16_t *a = (u_int16_t *)src;
+ volatile u_int16_t *b = (u_int16_t *)dst;
+
+ b[0] = a[0];
+ b[1] = a[1];
+}
+
+/*
+ * Template for default configuration parameters.
+ * See struct fxp_cb_config for the bit definitions.
+ */
+static u_char fxp_cb_config_template[] = {
+ 0x0, 0x0, /* cb_status */
+ 0x80, 0x2, /* cb_command */
+ 0xff, 0xff, 0xff, 0xff, /* link_addr */
+ 0x16, /* 0 */
+ 0x8, /* 1 */
+ 0x0, /* 2 */
+ 0x0, /* 3 */
+ 0x0, /* 4 */
+ 0x80, /* 5 */
+ 0xb2, /* 6 */
+ 0x3, /* 7 */
+ 0x1, /* 8 */
+ 0x0, /* 9 */
+ 0x26, /* 10 */
+ 0x0, /* 11 */
+ 0x60, /* 12 */
+ 0x0, /* 13 */
+ 0xf2, /* 14 */
+ 0x48, /* 15 */
+ 0x0, /* 16 */
+ 0x40, /* 17 */
+ 0xf3, /* 18 */
+ 0x0, /* 19 */
+ 0x3f, /* 20 */
+ 0x5, /* 21 */
+ 0x0, 0x0
+};
+
+static inline void fxp_scb_wait __P((struct fxp_softc *));
+static FXP_INTR_TYPE fxp_intr __P((void *));
+static void fxp_start __P((struct ifnet *));
+static int fxp_ioctl __P((struct ifnet *,
+ FXP_IOCTLCMD_TYPE, caddr_t));
+static void fxp_init __P((void *));
+static void fxp_stop __P((struct fxp_softc *));
+static void fxp_watchdog __P((struct ifnet *));
+static int fxp_add_rfabuf __P((struct fxp_softc *, struct mbuf *));
+static int fxp_mdi_read __P((struct fxp_softc *, int, int));
+static void fxp_mdi_write __P((struct fxp_softc *, int, int, int));
+static void fxp_read_eeprom __P((struct fxp_softc *, u_int16_t *,
+ int, int));
+static int fxp_attach_common __P((struct fxp_softc *, u_int8_t *));
+
+void fxp_stats_update __P((void *));
+
+/*
+ * Set initial transmit threshold at 64 (512 bytes). This is
+ * increased by 64 (512 bytes) at a time, to maximum of 192
+ * (1536 bytes), if an underrun occurs.
+ */
+static int tx_threshold = 64;
+
+/*
+ * Number of transmit control blocks. This determines the number
+ * of transmit buffers that can be chained in the CB list.
+ * This must be a power of two.
+ */
+#define FXP_NTXCB 128
+
+/*
+ * TxCB list index mask. This is used to do list wrap-around.
+ */
+#define FXP_TXCB_MASK (FXP_NTXCB - 1)
+
+/*
+ * Number of DMA segments in a TxCB. Note that this is carefully
+ * chosen to make the total struct size an even power of two. It's
+ * critical that no TxCB be split across a page boundry since
+ * no attempt is made to allocate physically contiguous memory.
+ *
+ * XXX - don't forget to change the hard-coded constant in the
+ * fxp_cb_tx struct (defined in if_fxpreg.h), too!
+ */
+#define FXP_NTXSEG 29
+
+/*
+ * Number of receive frame area buffers. These are large so chose
+ * wisely.
+ */
+#define FXP_NRFABUFS 32
+
+/*
+ * Wait for the previous command to be accepted (but not necessarily
+ * completed).
+ */
+static inline void
+fxp_scb_wait(sc)
+ struct fxp_softc *sc;
+{
+ int i = 10000;
+
+ while ((CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) & FXP_SCB_COMMAND_MASK)
+ && --i);
+}
+
+/*************************************************************
+ * Operating system-specific autoconfiguration glue
+ *************************************************************/
+
+#if defined(__NetBSD__) || defined(__OpenBSD__)
+
+#if defined(__BROKEN_INDIRECT_CONFIG) || defined(__OpenBSD__)
+static int fxp_match __P((struct device *, void *, void *));
+#else
+static int fxp_match __P((struct device *, struct cfdata *, void *));
+#endif
+static void fxp_attach __P((struct device *, struct device *, void *));
+
+static void fxp_shutdown __P((void *));
+
+/* Compensate for lack of a generic ether_ioctl() */
+static int fxp_ether_ioctl __P((struct ifnet *,
+ FXP_IOCTLCMD_TYPE, caddr_t));
+#define ether_ioctl fxp_ether_ioctl
+
+struct cfattach fxp_ca = {
+ sizeof(struct fxp_softc), fxp_match, fxp_attach
+};
+
+struct cfdriver fxp_cd = {
+ NULL, "fxp", DV_IFNET
+};
+
+/*
+ * Check if a device is an 82557.
+ */
+static int
+fxp_match(parent, match, aux)
+ struct device *parent;
+#if defined(__BROKEN_INDIRECT_CONFIG) || defined(__OpenBSD__)
+ void *match;
+#else
+ struct cfdata *match;
+#endif
+ void *aux;
+{
+ struct pci_attach_args *pa = aux;
+
+ if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_INTEL)
+ return (0);
+
+ switch (PCI_PRODUCT(pa->pa_id)) {
+ case PCI_PRODUCT_INTEL_82557:
+ return (1);
+ }
+
+ return (0);
+}
+
+static void
+fxp_attach(parent, self, aux)
+ struct device *parent, *self;
+ void *aux;
+{
+ struct fxp_softc *sc = (struct fxp_softc *)self;
+ struct pci_attach_args *pa = aux;
+ pci_chipset_tag_t pc = pa->pa_pc;
+ pci_intr_handle_t ih;
+ const char *intrstr = NULL;
+ u_int8_t enaddr[6];
+ struct ifnet *ifp;
+#ifdef __OpenBSD__
+ bus_space_tag_t iot = pa->pa_iot;
+ bus_addr_t iobase;
+ bus_size_t iosize;
+#endif
+
+#ifndef __OpenBSD__
+ /*
+ * Map control/status registers.
+ */
+ if (pci_mapreg_map(pa, FXP_PCI_MMBA, PCI_MAPREG_TYPE_MEM, 0,
+ &sc->sc_st, &sc->sc_sh, NULL, NULL)) {
+ printf(": can't map registers\n");
+ return;
+ }
+#else
+ if (pci_io_find(pc, pa->pa_tag, PCI_MAPREG_TYPE_MEM,
+ &iobase, &iosize)) {
+ printf(": can't find i/o space\n");
+ return;
+ }
+
+ if (bus_space_map(iot, iobase, iosize, 0, &sc->sc_sh)) {
+ printf(": can't map i/o space\n");
+ return;
+ }
+ sc->sc_st = iot;
+#endif
+
+ printf(": Intel EtherExpress Pro 10/100B Ethernet\n");
+
+ /*
+ * Allocate our interrupt.
+ */
+ if (pci_intr_map(pc, pa->pa_intrtag, pa->pa_intrpin,
+ pa->pa_intrline, &ih)) {
+ printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname);
+ return;
+ }
+ intrstr = pci_intr_string(pc, ih);
+ sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, fxp_intr, sc
+#ifdef __OpenBSD__
+ , self->dv_xname
+#endif
+ );
+ if (sc->sc_ih == NULL) {
+ printf("%s: couldn't establish interrupt",
+ sc->sc_dev.dv_xname);
+ if (intrstr != NULL)
+ printf(" at %s", intrstr);
+ printf("\n");
+ return;
+ }
+ printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr);
+
+ /* Do generic parts of attach. */
+ if (fxp_attach_common(sc, enaddr)) {
+ /* Failed! */
+ return;
+ }
+
+ printf("%s: Ethernet address %s%s\n", sc->sc_dev.dv_xname,
+ ether_sprintf(enaddr), sc->phy_10Mbps_only ? ", 10Mbps" : "");
+
+#ifdef __OpenBSD__
+ ifp = &sc->arpcom.ac_if;
+#else
+ ifp = &sc->sc_ethercom.ec_if;
+#endif
+ bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ);
+ ifp->if_softc = sc;
+ ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
+ ifp->if_ioctl = fxp_ioctl;
+ ifp->if_start = fxp_start;
+ ifp->if_watchdog = fxp_watchdog;
+
+ /*
+ * Attach the interface.
+ */
+ if_attach(ifp);
+#ifdef __NetBSD__
+ ether_ifattach(ifp, enaddr);
+#else
+ ether_ifattach(ifp);
+#endif
+#if NBPFILTER > 0
+#ifdef __OpenBSD__
+ bpfattach(&sc->arpcom.ac_if.if_bpf, ifp, DLT_EN10MB,
+ sizeof(struct ether_header));
+#else
+ bpfattach(&sc->sc_ethercom.ec_if.if_bpf, ifp, DLT_EN10MB,
+ sizeof(struct ether_header));
+#endif
+#endif
+
+ /*
+ * Add shutdown hook so that DMA is disabled prior to reboot. Not
+ * doing do could allow DMA to corrupt kernel memory during the
+ * reboot before the driver initializes.
+ */
+ shutdownhook_establish(fxp_shutdown, sc);
+}
+
+/*
+ * Device shutdown routine. Called at system shutdown after sync. The
+ * main purpose of this routine is to shut off receiver DMA so that
+ * kernel memory doesn't get clobbered during warmboot.
+ */
+static void
+fxp_shutdown(sc)
+ void *sc;
+{
+ fxp_stop((struct fxp_softc *) sc);
+}
+
+static int
+fxp_ether_ioctl(ifp, cmd, data)
+ struct ifnet *ifp;
+ FXP_IOCTLCMD_TYPE cmd;
+ caddr_t data;
+{
+ struct ifaddr *ifa = (struct ifaddr *) data;
+ struct fxp_softc *sc = ifp->if_softc;
+
+ switch (cmd) {
+ case SIOCSIFADDR:
+ ifp->if_flags |= IFF_UP;
+
+ switch (ifa->ifa_addr->sa_family) {
+#ifdef INET
+ case AF_INET:
+ fxp_init(sc);
+#ifdef __OpenBSD__
+ arp_ifinit(&sc->arpcom, ifa);
+#else
+ arp_ifinit(ifp, ifa);
+#endif
+ break;
+#endif
+#ifdef NS
+ case AF_NS:
+ {
+ register struct ns_addr *ina = &IA_SNS(ifa)->sns_addr;
+
+ if (ns_nullhost(*ina))
+ ina->x_host = *(union ns_host *)
+ LLADDR(ifp->if_sadl);
+ else
+ bcopy(ina->x_host.c_host, LLADDR(ifp->if_sadl),
+ ifp->if_addrlen);
+ /* Set new address. */
+ fxp_init(sc);
+ break;
+ }
+#endif
+ default:
+ fxp_init(sc);
+ break;
+ }
+ break;
+
+ default:
+ return (EINVAL);
+ }
+
+ return (0);
+}
+
+#else /* __FreeBSD__ */
+
+static u_long fxp_count;
+static char *fxp_probe __P((pcici_t, pcidi_t));
+static void fxp_attach __P((pcici_t, int));
+
+static void fxp_shutdown __P((int, void *));
+
+static struct pci_device fxp_device = {
+ "fxp",
+ fxp_probe,
+ fxp_attach,
+ &fxp_count,
+ NULL
+};
+DATA_SET(pcidevice_set, fxp_device);
+
+/*
+ * Return identification string if this is device is ours.
+ */
+static char *
+fxp_probe(config_id, device_id)
+ pcici_t config_id;
+ pcidi_t device_id;
+{
+ if (((device_id & 0xffff) == FXP_VENDORID_INTEL) &&
+ ((device_id >> 16) & 0xffff) == FXP_DEVICEID_i82557)
+ return ("Intel EtherExpress Pro 10/100B Ethernet");
+
+ return NULL;
+}
+
+static void
+fxp_attach(config_id, unit)
+ pcici_t config_id;
+ int unit;
+{
+ struct fxp_softc *sc;
+ vm_offset_t pbase;
+ struct ifnet *ifp;
+ int s;
+
+ sc = malloc(sizeof(struct fxp_softc), M_DEVBUF, M_NOWAIT);
+ if (sc == NULL)
+ return;
+ bzero(sc, sizeof(struct fxp_softc));
+
+ s = splimp();
+
+ /*
+ * Map control/status registers.
+ */
+ if (!pci_map_mem(config_id, FXP_PCI_MMBA,
+ (vm_offset_t *)&sc->csr, &pbase)) {
+ printf("fxp%d: couldn't map memory\n", unit);
+ goto fail;
+ }
+
+ /*
+ * Allocate our interrupt.
+ */
+ if (!pci_map_int(config_id, fxp_intr, sc, &net_imask)) {
+ printf("fxp%d: couldn't map interrupt\n", unit);
+ goto fail;
+ }
+
+ /* Do generic parts of attach. */
+ if (fxp_attach_common(sc, sc->arpcom.ac_enaddr)) {
+ /* Failed! */
+ (void) pci_unmap_int(config_id);
+ goto fail;
+ }
+
+ printf("fxp%d: Ethernet address %6D%s\n", unit,
+ sc->arpcom.ac_enaddr, ":", sc->phy_10Mbps_only ? ", 10Mbps" : "");
+
+ ifp = &sc->arpcom.ac_if;
+ ifp->if_unit = unit;
+ ifp->if_name = "fxp";
+ ifp->if_output = ether_output;
+ ifp->if_baudrate = 100000000;
+ ifp->if_init = fxp_init;
+ ifp->if_softc = sc;
+ ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
+ ifp->if_ioctl = fxp_ioctl;
+ ifp->if_start = fxp_start;
+ ifp->if_watchdog = fxp_watchdog;
+
+ /*
+ * Attach the interface.
+ */
+ if_attach(ifp);
+ ether_ifattach(ifp);
+#if NBPFILTER > 0
+ bpfattach(ifp, DLT_EN10MB, sizeof(struct ether_header));
+#endif
+
+ /*
+ * Add shutdown hook so that DMA is disabled prior to reboot. Not
+ * doing do could allow DMA to corrupt kernel memory during the
+ * reboot before the driver initializes.
+ */
+ at_shutdown(fxp_shutdown, sc, SHUTDOWN_POST_SYNC);
+
+ splx(s);
+ return;
+
+ fail:
+ free(sc, M_DEVBUF);
+ splx(s);
+}
+
+/*
+ * Device shutdown routine. Called at system shutdown after sync. The
+ * main purpose of this routine is to shut off receiver DMA so that
+ * kernel memory doesn't get clobbered during warmboot.
+ */
+static void
+fxp_shutdown(howto, sc)
+ int howto;
+ void *sc;
+{
+ fxp_stop((struct fxp_softc *) sc);
+}
+
+#endif /* __NetBSD__ || __OpenBSD__ */
+
+/*************************************************************
+ * End of operating system-specific autoconfiguration glue
+ *************************************************************/
+
+/*
+ * Do generic parts of attach.
+ */
+static int
+fxp_attach_common(sc, enaddr)
+ struct fxp_softc *sc;
+ u_int8_t *enaddr;
+{
+ u_int16_t data;
+ int i;
+
+ /*
+ * Reset to a stable state.
+ */
+ CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET);
+ DELAY(10);
+
+ sc->cbl_base = malloc(sizeof(struct fxp_cb_tx) * FXP_NTXCB,
+ M_DEVBUF, M_NOWAIT);
+ if (sc->cbl_base == NULL)
+ goto fail;
+
+ sc->fxp_stats = malloc(sizeof(struct fxp_stats), M_DEVBUF, M_NOWAIT);
+ if (sc->fxp_stats == NULL)
+ goto fail;
+ bzero(sc->fxp_stats, sizeof(struct fxp_stats));
+
+ /*
+ * Pre-allocate our receive buffers.
+ */
+ for (i = 0; i < FXP_NRFABUFS; i++) {
+ if (fxp_add_rfabuf(sc, NULL) != 0) {
+ goto fail;
+ }
+ }
+
+ /*
+ * Get info about the primary PHY
+ */
+ fxp_read_eeprom(sc, (u_int16_t *)&data, 6, 1);
+ sc->phy_primary_addr = data & 0xff;
+ sc->phy_primary_device = (data >> 8) & 0x3f;
+ sc->phy_10Mbps_only = data >> 15;
+
+ /*
+ * Read MAC address.
+ */
+ fxp_read_eeprom(sc, (u_int16_t *)enaddr, 0, 3);
+ return (0);
+
+ fail:
+ printf(FXP_FORMAT ": Failed to malloc memory\n", FXP_ARGS(sc));
+ if (sc->cbl_base)
+ free(sc->cbl_base, M_DEVBUF);
+ if (sc->fxp_stats)
+ free(sc->fxp_stats, M_DEVBUF);
+ /* frees entire chain */
+ if (sc->rfa_headm)
+ m_freem(sc->rfa_headm);
+
+ return (ENOMEM);
+}
+
+/*
+ * Read from the serial EEPROM. Basically, you manually shift in
+ * the read opcode (one bit at a time) and then shift in the address,
+ * and then you shift out the data (all of this one bit at a time).
+ * The word size is 16 bits, so you have to provide the address for
+ * every 16 bits of data.
+ */
+static void
+fxp_read_eeprom(sc, data, offset, words)
+ struct fxp_softc *sc;
+ u_short *data;
+ int offset;
+ int words;
+{
+ u_int16_t reg;
+ int i, x;
+
+ for (i = 0; i < words; i++) {
+ CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
+ /*
+ * Shift in read opcode.
+ */
+ for (x = 3; x > 0; x--) {
+ if (FXP_EEPROM_OPC_READ & (1 << (x - 1))) {
+ reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI;
+ } else {
+ reg = FXP_EEPROM_EECS;
+ }
+ CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
+ CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL,
+ reg | FXP_EEPROM_EESK);
+ DELAY(1);
+ CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
+ DELAY(1);
+ }
+ /*
+ * Shift in address.
+ */
+ for (x = 6; x > 0; x--) {
+ if ((i + offset) & (1 << (x - 1))) {
+ reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI;
+ } else {
+ reg = FXP_EEPROM_EECS;
+ }
+ CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
+ CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL,
+ reg | FXP_EEPROM_EESK);
+ DELAY(1);
+ CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
+ DELAY(1);
+ }
+ reg = FXP_EEPROM_EECS;
+ data[i] = 0;
+ /*
+ * Shift out data.
+ */
+ for (x = 16; x > 0; x--) {
+ CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL,
+ reg | FXP_EEPROM_EESK);
+ DELAY(1);
+ if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) &
+ FXP_EEPROM_EEDO)
+ data[i] |= (1 << (x - 1));
+ CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
+ DELAY(1);
+ }
+ CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
+ DELAY(1);
+ }
+}
+
+/*
+ * Start packet transmission on the interface.
+ */
+static void
+fxp_start(ifp)
+ struct ifnet *ifp;
+{
+ struct fxp_softc *sc = ifp->if_softc;
+ struct fxp_cb_tx *txp;
+ struct mbuf *m, *mb_head;
+ int segment, first = 1;
+
+txloop:
+ /*
+ * See if we're all filled up with buffers to transmit.
+ */
+ if (sc->tx_queued >= FXP_NTXCB)
+ return;
+
+ /*
+ * Grab a packet to transmit.
+ */
+ IF_DEQUEUE(&ifp->if_snd, mb_head);
+ if (mb_head == NULL) {
+ /*
+ * No more packets to send.
+ */
+ return;
+ }
+
+ /*
+ * Get pointer to next available (unused) descriptor.
+ */
+ txp = sc->cbl_last->next;
+
+ /*
+ * Go through each of the mbufs in the chain and initialize
+ * the transmit buffers descriptors with the physical address
+ * and size of the mbuf.
+ */
+tbdinit:
+ for (m = mb_head, segment = 0; m != NULL; m = m->m_next) {
+ if (m->m_len != 0) {
+ if (segment == FXP_NTXSEG)
+ break;
+ txp->tbd[segment].tb_addr =
+ vtophys(mtod(m, vm_offset_t));
+ txp->tbd[segment].tb_size = m->m_len;
+ segment++;
+ }
+ }
+ if (m != NULL) {
+ struct mbuf *mn;
+
+ /*
+ * We ran out of segments. We have to recopy this mbuf
+ * chain first.
+ */
+ MGETHDR(mn, M_DONTWAIT, MT_DATA);
+ if (mn == NULL) {
+ m_freem(mb_head);
+ return;
+ }
+ if (mb_head->m_pkthdr.len > MHLEN) {
+ MCLGET(mn, M_DONTWAIT);
+ if ((mn->m_flags & M_EXT) == 0) {
+ m_freem(mn);
+ m_freem(mb_head);
+ return;
+ }
+ }
+ m_copydata(mb_head, 0, mb_head->m_pkthdr.len,
+ mtod(mn, caddr_t));
+ mn->m_pkthdr.len = mn->m_len = mb_head->m_pkthdr.len;
+ m_freem(mb_head);
+ mb_head = mn;
+ goto tbdinit;
+ }
+
+ txp->tbd_number = segment;
+ txp->mb_head = mb_head;
+
+ /*
+ * Finish the initialization of this TxCB.
+ */
+ txp->cb_status = 0;
+ txp->cb_command =
+ FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF | FXP_CB_COMMAND_S;
+ txp->tx_threshold = tx_threshold;
+
+ /*
+ * Advance the end-of-list forward.
+ */
+ sc->cbl_last->cb_command &= ~FXP_CB_COMMAND_S;
+ sc->cbl_last = txp;
+
+ /*
+ * Advance the beginning of the list forward if there are
+ * no other packets queued (when nothing is queued, cbl_first
+ * sits on the last TxCB that was sent out)..
+ */
+ if (sc->tx_queued == 0)
+ sc->cbl_first = txp;
+
+ sc->tx_queued++;
+
+ /*
+ * Only need to wait prior to the first resume command.
+ */
+ if (first) {
+ first--;
+ fxp_scb_wait(sc);
+ }
+
+ /*
+ * Resume transmission if suspended.
+ */
+ CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_RESUME);
+
+#if NBPFILTER > 0
+ /*
+ * Pass packet to bpf if there is a listener.
+ */
+ if (ifp->if_bpf)
+ bpf_mtap(FXP_BPFTAP_ARG(ifp), mb_head);
+#endif
+ /*
+ * Set a 5 second timer just in case we don't hear from the
+ * card again.
+ */
+ ifp->if_timer = 5;
+
+ goto txloop;
+}
+
+/*
+ * Process interface interrupts.
+ */
+static FXP_INTR_TYPE
+fxp_intr(arg)
+ void *arg;
+{
+ struct fxp_softc *sc = arg;
+ struct ifnet *ifp = &sc->sc_if;
+ u_int8_t statack;
+#if defined(__NetBSD__) || defined(__OpenBSD__)
+ int claimed = 0;
+#endif
+
+ while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) {
+#if defined(__NetBSD__) || defined(__OpenBSD__)
+ claimed = 1;
+#endif
+ /*
+ * First ACK all the interrupts in this pass.
+ */
+ CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack);
+
+ /*
+ * Free any finished transmit mbuf chains.
+ */
+ if (statack & FXP_SCB_STATACK_CNA) {
+ struct fxp_cb_tx *txp;
+
+ for (txp = sc->cbl_first;
+ (txp->cb_status & FXP_CB_STATUS_C) != 0;
+ txp = txp->next) {
+ if (txp->mb_head != NULL) {
+ m_freem(txp->mb_head);
+ txp->mb_head = NULL;
+ sc->tx_queued--;
+ }
+ if (txp->cb_command & FXP_CB_COMMAND_S)
+ break;
+ }
+ sc->cbl_first = txp;
+ /*
+ * Clear watchdog timer. It may or may not be set
+ * again in fxp_start().
+ */
+ ifp->if_timer = 0;
+ if (ifp->if_snd.ifq_head != NULL)
+ fxp_start(ifp);
+ }
+ /*
+ * Process receiver interrupts. If a no-resource (RNR)
+ * condition exists, get whatever packets we can and
+ * re-start the receiver.
+ */
+ if (statack & (FXP_SCB_STATACK_FR | FXP_SCB_STATACK_RNR)) {
+ struct mbuf *m;
+ struct fxp_rfa *rfa;
+rcvloop:
+ m = sc->rfa_headm;
+ rfa = (struct fxp_rfa *)(m->m_ext.ext_buf +
+ RFA_ALIGNMENT_FUDGE);
+
+ if (rfa->rfa_status & FXP_RFA_STATUS_C) {
+ /*
+ * Remove first packet from the chain.
+ */
+ sc->rfa_headm = m->m_next;
+ m->m_next = NULL;
+
+ /*
+ * Add a new buffer to the receive chain.
+ * If this fails, the old buffer is recycled
+ * instead.
+ */
+ if (fxp_add_rfabuf(sc, m) == 0) {
+ struct ether_header *eh;
+ u_int16_t total_len;
+
+ total_len = rfa->actual_size &
+ (MCLBYTES - 1);
+ if (total_len <
+ sizeof(struct ether_header)) {
+ m_freem(m);
+ goto rcvloop;
+ }
+ m->m_pkthdr.rcvif = ifp;
+ m->m_pkthdr.len = m->m_len =
+ total_len -
+ sizeof(struct ether_header);
+ eh = mtod(m, struct ether_header *);
+#if NBPFILTER > 0
+ if (ifp->if_bpf) {
+ bpf_tap(FXP_BPFTAP_ARG(ifp),
+ mtod(m, caddr_t),
+ total_len);
+ /*
+ * Only pass this packet up
+ * if it is for us.
+ */
+ if ((ifp->if_flags &
+ IFF_PROMISC) &&
+ (rfa->rfa_status &
+ FXP_RFA_STATUS_IAMATCH) &&
+ (eh->ether_dhost[0] & 1)
+ == 0) {
+ m_freem(m);
+ goto rcvloop;
+ }
+ }
+#endif /* NBPFILTER > 0 */
+ m->m_data +=
+ sizeof(struct ether_header);
+ ether_input(ifp, eh, m);
+ }
+ goto rcvloop;
+ }
+ if (statack & FXP_SCB_STATACK_RNR) {
+ fxp_scb_wait(sc);
+ CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL,
+ vtophys(sc->rfa_headm->m_ext.ext_buf) +
+ RFA_ALIGNMENT_FUDGE);
+ CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND,
+ FXP_SCB_COMMAND_RU_START);
+ }
+ }
+ }
+#if defined(__NetBSD__) || defined(__OpenBSD__)
+ return (claimed);
+#endif
+}
+
+/*
+ * Update packet in/out/collision statistics. The i82557 doesn't
+ * allow you to access these counters without doing a fairly
+ * expensive DMA to get _all_ of the statistics it maintains, so
+ * we do this operation here only once per second. The statistics
+ * counters in the kernel are updated from the previous dump-stats
+ * DMA and then a new dump-stats DMA is started. The on-chip
+ * counters are zeroed when the DMA completes. If we can't start
+ * the DMA immediately, we don't wait - we just prepare to read
+ * them again next time.
+ */
+void
+fxp_stats_update(arg)
+ void *arg;
+{
+ struct fxp_softc *sc = arg;
+ struct ifnet *ifp = &sc->sc_if;
+ struct fxp_stats *sp = sc->fxp_stats;
+
+ ifp->if_opackets += sp->tx_good;
+ ifp->if_collisions += sp->tx_total_collisions;
+ ifp->if_ipackets += sp->rx_good;
+ ifp->if_ierrors +=
+ sp->rx_crc_errors +
+ sp->rx_alignment_errors +
+ sp->rx_rnr_errors +
+ sp->rx_overrun_errors;
+ /*
+ * If any transmit underruns occured, bump up the transmit
+ * threshold by another 512 bytes (64 * 8).
+ */
+ if (sp->tx_underruns) {
+ ifp->if_oerrors += sp->tx_underruns;
+ if (tx_threshold < 192)
+ tx_threshold += 64;
+ }
+ /*
+ * If there is no pending command, start another stats
+ * dump. Otherwise punt for now.
+ */
+ if ((CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) &
+ FXP_SCB_COMMAND_MASK) == 0) {
+ /*
+ * Start another stats dump. By waiting for it to be
+ * accepted, we avoid having to do splhigh locking when
+ * writing scb_command in other parts of the driver.
+ */
+ CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND,
+ FXP_SCB_COMMAND_CU_DUMPRESET);
+ fxp_scb_wait(sc);
+ } else {
+ /*
+ * A previous command is still waiting to be accepted.
+ * Just zero our copy of the stats and wait for the
+ * next timer event to update them.
+ */
+ sp->tx_good = 0;
+ sp->tx_underruns = 0;
+ sp->tx_total_collisions = 0;
+
+ sp->rx_good = 0;
+ sp->rx_crc_errors = 0;
+ sp->rx_alignment_errors = 0;
+ sp->rx_rnr_errors = 0;
+ sp->rx_overrun_errors = 0;
+ }
+ /*
+ * Schedule another timeout one second from now.
+ */
+ timeout(fxp_stats_update, sc, hz);
+}
+
+/*
+ * Stop the interface. Cancels the statistics updater and resets
+ * the interface.
+ */
+static void
+fxp_stop(sc)
+ struct fxp_softc *sc;
+{
+ struct ifnet *ifp = &sc->sc_if;
+ struct fxp_cb_tx *txp;
+ int i;
+
+ /*
+ * Cancel stats updater.
+ */
+ untimeout(fxp_stats_update, sc);
+
+ /*
+ * Issue software reset
+ */
+ CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET);
+ DELAY(10);
+
+ /*
+ * Release any xmit buffers.
+ */
+ for (txp = sc->cbl_first; txp != NULL && txp->mb_head != NULL;
+ txp = txp->next) {
+ m_freem(txp->mb_head);
+ txp->mb_head = NULL;
+ }
+ sc->tx_queued = 0;
+
+ /*
+ * Free all the receive buffers then reallocate/reinitialize
+ */
+ if (sc->rfa_headm != NULL)
+ m_freem(sc->rfa_headm);
+ sc->rfa_headm = NULL;
+ sc->rfa_tailm = NULL;
+ for (i = 0; i < FXP_NRFABUFS; i++) {
+ if (fxp_add_rfabuf(sc, NULL) != 0) {
+ /*
+ * This "can't happen" - we're at splimp()
+ * and we just freed all the buffers we need
+ * above.
+ */
+ panic("fxp_stop: no buffers!");
+ }
+ }
+
+ ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
+ ifp->if_timer = 0;
+}
+
+/*
+ * Watchdog/transmission transmit timeout handler. Called when a
+ * transmission is started on the interface, but no interrupt is
+ * received before the timeout. This usually indicates that the
+ * card has wedged for some reason.
+ */
+static void
+fxp_watchdog(ifp)
+ struct ifnet *ifp;
+{
+ struct fxp_softc *sc = ifp->if_softc;
+
+ log(LOG_ERR, FXP_FORMAT ": device timeout\n", FXP_ARGS(sc));
+ ifp->if_oerrors++;
+
+ fxp_init(sc);
+}
+
+static void
+fxp_init(xsc)
+ void *xsc;
+{
+ struct fxp_softc *sc = xsc;
+ struct ifnet *ifp = &sc->sc_if;
+ struct fxp_cb_config *cbp;
+ struct fxp_cb_ias *cb_ias;
+ struct fxp_cb_tx *txp;
+ int i, s, mcast, prm;
+
+ s = splimp();
+ /*
+ * Cancel any pending I/O
+ */
+ fxp_stop(sc);
+
+ prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0;
+ sc->promisc_mode = prm;
+ /*
+ * Sleeze out here and enable reception of all multicasts if
+ * multicasts are enabled. Ideally, we'd program the multicast
+ * address filter to only accept specific multicasts.
+ */
+ mcast = (ifp->if_flags & (IFF_MULTICAST|IFF_ALLMULTI)) ? 1 : 0;
+
+ /*
+ * Initialize base of CBL and RFA memory. Loading with zero
+ * sets it up for regular linear addressing.
+ */
+ CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0);
+ CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_BASE);
+
+ fxp_scb_wait(sc);
+ CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_RU_BASE);
+
+ /*
+ * Initialize base of dump-stats buffer.
+ */
+ fxp_scb_wait(sc);
+ CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(sc->fxp_stats));
+ CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_DUMP_ADR);
+
+ /*
+ * We temporarily use memory that contains the TxCB list to
+ * construct the config CB. The TxCB list memory is rebuilt
+ * later.
+ */
+ cbp = (struct fxp_cb_config *) sc->cbl_base;
+
+ /*
+ * This bcopy is kind of disgusting, but there are a bunch of must be
+ * zero and must be one bits in this structure and this is the easiest
+ * way to initialize them all to proper values.
+ */
+ bcopy(fxp_cb_config_template, cbp, sizeof(struct fxp_cb_config));
+
+ cbp->cb_status = 0;
+ cbp->cb_command = FXP_CB_COMMAND_CONFIG | FXP_CB_COMMAND_EL;
+ cbp->link_addr = -1; /* (no) next command */
+ cbp->byte_count = 22; /* (22) bytes to config */
+ cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */
+ cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */
+ cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */
+ cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */
+ cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */
+ cbp->dma_bce = 0; /* (disable) dma max counters */
+ cbp->late_scb = 0; /* (don't) defer SCB update */
+ cbp->tno_int = 0; /* (disable) tx not okay interrupt */
+ cbp->ci_int = 0; /* interrupt on CU not active */
+ cbp->save_bf = prm; /* save bad frames */
+ cbp->disc_short_rx = !prm; /* discard short packets */
+ cbp->underrun_retry = 1; /* retry mode (1) on DMA underrun */
+ cbp->mediatype = !sc->phy_10Mbps_only; /* interface mode */
+ cbp->nsai = 1; /* (don't) disable source addr insert */
+ cbp->preamble_length = 2; /* (7 byte) preamble */
+ cbp->loopback = 0; /* (don't) loopback */
+ cbp->linear_priority = 0; /* (normal CSMA/CD operation) */
+ cbp->linear_pri_mode = 0; /* (wait after xmit only) */
+ cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */
+ cbp->promiscuous = prm; /* promiscuous mode */
+ cbp->bcast_disable = 0; /* (don't) disable broadcasts */
+ cbp->crscdt = 0; /* (CRS only) */
+ cbp->stripping = !prm; /* truncate rx packet to byte count */
+ cbp->padding = 1; /* (do) pad short tx packets */
+ cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */
+ cbp->force_fdx = 0; /* (don't) force full duplex */
+ cbp->fdx_pin_en = 1; /* (enable) FDX# pin */
+ cbp->multi_ia = 0; /* (don't) accept multiple IAs */
+ cbp->mc_all = mcast; /* accept all multicasts */
+
+ /*
+ * Start the config command/DMA.
+ */
+ fxp_scb_wait(sc);
+ CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(cbp));
+ CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_START);
+ /* ...and wait for it to complete. */
+ while (!(cbp->cb_status & FXP_CB_STATUS_C));
+
+ /*
+ * Now initialize the station address. Temporarily use the TxCB
+ * memory area like we did above for the config CB.
+ */
+ cb_ias = (struct fxp_cb_ias *) sc->cbl_base;
+ cb_ias->cb_status = 0;
+ cb_ias->cb_command = FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL;
+ cb_ias->link_addr = -1;
+#if defined(__NetBSD__)
+ bcopy(LLADDR(ifp->if_sadl), (void *)cb_ias->macaddr, 6);
+#else
+ bcopy(sc->arpcom.ac_enaddr, (void *)cb_ias->macaddr,
+ sizeof(sc->arpcom.ac_enaddr));
+#endif /* __NetBSD__ */
+
+ /*
+ * Start the IAS (Individual Address Setup) command/DMA.
+ */
+ fxp_scb_wait(sc);
+ CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_START);
+ /* ...and wait for it to complete. */
+ while (!(cb_ias->cb_status & FXP_CB_STATUS_C));
+
+ /*
+ * Initialize transmit control block (TxCB) list.
+ */
+
+ txp = sc->cbl_base;
+ bzero(txp, sizeof(struct fxp_cb_tx) * FXP_NTXCB);
+ for (i = 0; i < FXP_NTXCB; i++) {
+ txp[i].cb_status = FXP_CB_STATUS_C | FXP_CB_STATUS_OK;
+ txp[i].cb_command = FXP_CB_COMMAND_NOP;
+ txp[i].link_addr = vtophys(&txp[(i + 1) & FXP_TXCB_MASK]);
+ txp[i].tbd_array_addr = vtophys(&txp[i].tbd[0]);
+ txp[i].next = &txp[(i + 1) & FXP_TXCB_MASK];
+ }
+ /*
+ * Set the stop flag on the first TxCB and start the control
+ * unit. It will execute the NOP and then suspend.
+ */
+ txp->cb_command = FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S;
+ sc->cbl_first = sc->cbl_last = txp;
+ sc->tx_queued = 0;
+
+ fxp_scb_wait(sc);
+ CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_START);
+
+ /*
+ * Initialize receiver buffer area - RFA.
+ */
+ fxp_scb_wait(sc);
+ CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL,
+ vtophys(sc->rfa_headm->m_ext.ext_buf) + RFA_ALIGNMENT_FUDGE);
+ CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_RU_START);
+
+ /*
+ * Toggle a few bits in the DP83840 PHY.
+ */
+ if (sc->phy_primary_device == FXP_PHY_DP83840 ||
+ sc->phy_primary_device == FXP_PHY_DP83840A) {
+ fxp_mdi_write(sc, sc->phy_primary_addr, FXP_DP83840_PCR,
+ fxp_mdi_read(sc, sc->phy_primary_addr, FXP_DP83840_PCR) |
+ FXP_DP83840_PCR_LED4_MODE | /* LED4 always indicates duplex */
+ FXP_DP83840_PCR_F_CONNECT | /* force link disconnect bypass */
+ FXP_DP83840_PCR_BIT10); /* XXX I have no idea */
+ /*
+ * If link0 is set, disable auto-negotiation and then:
+ * If link1 is unset = 10Mbps
+ * If link1 is set = 100Mbps
+ * If link2 is unset = half duplex
+ * If link2 is set = full duplex
+ * XXX THIS IS BEGGING FOR IF_MEDIA!
+ */
+ if (ifp->if_flags & IFF_LINK0) {
+ int flags;
+
+ flags = (ifp->if_flags & IFF_LINK1) ?
+ FXP_DP83840_BMCR_SPEED_100M : 0;
+ flags |= (ifp->if_flags & IFF_LINK2) ?
+ FXP_DP83840_BMCR_FULLDUPLEX : 0;
+ fxp_mdi_write(sc, sc->phy_primary_addr,
+ FXP_DP83840_BMCR,
+ (fxp_mdi_read(sc, sc->phy_primary_addr,
+ FXP_DP83840_BMCR) &
+ ~(FXP_DP83840_BMCR_AUTOEN |
+ FXP_DP83840_BMCR_SPEED_100M |
+ FXP_DP83840_BMCR_FULLDUPLEX)) | flags);
+ } else {
+ fxp_mdi_write(sc, sc->phy_primary_addr,
+ FXP_DP83840_BMCR,
+ (fxp_mdi_read(sc, sc->phy_primary_addr,
+ FXP_DP83840_BMCR) |
+ FXP_DP83840_BMCR_AUTOEN));
+ }
+ } else {
+ printf(FXP_FORMAT
+ ": warning: unsupported PHY, type = %d, addr = %d\n",
+ FXP_ARGS(sc), sc->phy_primary_device,
+ sc->phy_primary_addr);
+ }
+
+ ifp->if_flags |= IFF_RUNNING;
+ ifp->if_flags &= ~IFF_OACTIVE;
+ splx(s);
+
+ /*
+ * Start stats updater.
+ */
+ timeout(fxp_stats_update, sc, hz);
+}
+
+/*
+ * Add a buffer to the end of the RFA buffer list.
+ * Return 0 if successful, 1 for failure. A failure results in
+ * adding the 'oldm' (if non-NULL) on to the end of the list -
+ * tossing out it's old contents and recycling it.
+ * The RFA struct is stuck at the beginning of mbuf cluster and the
+ * data pointer is fixed up to point just past it.
+ */
+static int
+fxp_add_rfabuf(sc, oldm)
+ struct fxp_softc *sc;
+ struct mbuf *oldm;
+{
+ u_int32_t v;
+ struct mbuf *m;
+ struct fxp_rfa *rfa, *p_rfa;
+
+ MGETHDR(m, M_DONTWAIT, MT_DATA);
+ if (m != NULL) {
+ MCLGET(m, M_DONTWAIT);
+ if ((m->m_flags & M_EXT) == 0) {
+ m_freem(m);
+ if (oldm == NULL)
+ return 1;
+ m = oldm;
+ m->m_data = m->m_ext.ext_buf;
+ }
+ } else {
+ if (oldm == NULL)
+ return 1;
+ m = oldm;
+ m->m_data = m->m_ext.ext_buf;
+ }
+
+ /*
+ * Move the data pointer up so that the incoming data packet
+ * will be 32-bit aligned.
+ */
+ m->m_data += RFA_ALIGNMENT_FUDGE;
+
+ /*
+ * Get a pointer to the base of the mbuf cluster and move
+ * data start past it.
+ */
+ rfa = mtod(m, struct fxp_rfa *);
+ m->m_data += sizeof(struct fxp_rfa);
+ rfa->size = MCLBYTES - sizeof(struct fxp_rfa) - RFA_ALIGNMENT_FUDGE;
+
+ /*
+ * Initialize the rest of the RFA. Note that since the RFA
+ * is misaligned, we cannot store values directly. Instead,
+ * we use an optimized, inline copy.
+ */
+ rfa->rfa_status = 0;
+ rfa->rfa_control = FXP_RFA_CONTROL_EL;
+ rfa->actual_size = 0;
+
+ v = -1;
+ fxp_lwcopy(&v, &rfa->link_addr);
+ fxp_lwcopy(&v, &rfa->rbd_addr);
+
+ /*
+ * If there are other buffers already on the list, attach this
+ * one to the end by fixing up the tail to point to this one.
+ */
+ if (sc->rfa_headm != NULL) {
+ p_rfa = (struct fxp_rfa *) (sc->rfa_tailm->m_ext.ext_buf +
+ RFA_ALIGNMENT_FUDGE);
+ sc->rfa_tailm->m_next = m;
+ v = vtophys(rfa);
+ fxp_lwcopy(&v, &p_rfa->link_addr);
+ p_rfa->rfa_control &= ~FXP_RFA_CONTROL_EL;
+ } else {
+ sc->rfa_headm = m;
+ }
+ sc->rfa_tailm = m;
+
+ return (m == oldm);
+}
+
+static volatile int
+fxp_mdi_read(sc, phy, reg)
+ struct fxp_softc *sc;
+ int phy;
+ int reg;
+{
+ int count = 10000;
+ int value;
+
+ CSR_WRITE_4(sc, FXP_CSR_MDICONTROL,
+ (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21));
+
+ while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0
+ && count--)
+ DELAY(10);
+
+ if (count <= 0)
+ printf(FXP_FORMAT ": fxp_mdi_read: timed out\n",
+ FXP_ARGS(sc));
+
+ return (value & 0xffff);
+}
+
+static void
+fxp_mdi_write(sc, phy, reg, value)
+ struct fxp_softc *sc;
+ int phy;
+ int reg;
+ int value;
+{
+ int count = 10000;
+
+ CSR_WRITE_4(sc, FXP_CSR_MDICONTROL,
+ (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) |
+ (value & 0xffff));
+
+ while((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 &&
+ count--)
+ DELAY(10);
+
+ if (count <= 0)
+ printf(FXP_FORMAT ": fxp_mdi_write: timed out\n",
+ FXP_ARGS(sc));
+}
+
+static int
+fxp_ioctl(ifp, command, data)
+ struct ifnet *ifp;
+ FXP_IOCTLCMD_TYPE command;
+ caddr_t data;
+{
+ struct fxp_softc *sc = ifp->if_softc;
+ int s, error = 0;
+
+ s = splimp();
+
+ switch (command) {
+
+ case SIOCSIFADDR:
+#if !(defined(__NetBSD__) || defined(__OpenBSD__))
+ case SIOCGIFADDR:
+ case SIOCSIFMTU:
+#endif
+ error = ether_ioctl(ifp, command, data);
+ break;
+
+ case SIOCSIFFLAGS:
+
+ /*
+ * If interface is marked up and not running, then start it.
+ * If it is marked down and running, stop it.
+ * XXX If it's up then re-initialize it. This is so flags
+ * such as IFF_PROMISC are handled.
+ */
+ if (ifp->if_flags & IFF_UP) {
+ fxp_init(sc);
+ } else {
+ if (ifp->if_flags & IFF_RUNNING)
+ fxp_stop(sc);
+ }
+ break;
+
+ case SIOCADDMULTI:
+ case SIOCDELMULTI:
+#if defined(__NetBSD__) || defined(__OpenBSD__)
+ {
+ struct ifreq *ifr = (struct ifreq *) data;
+
+#if defined(__OpenBSD__)
+ error = (command == SIOCADDMULTI) ?
+ ether_addmulti(ifr, &sc->arpcom) :
+ ether_delmulti(ifr, &sc->arpcom);
+#else
+ error = (command == SIOCADDMULTI) ?
+ ether_addmulti(ifr, &sc->sc_ethercom) :
+ ether_delmulti(ifr, &sc->sc_ethercom);
+#endif
+
+ if (error == ENETRESET) {
+ /*
+ * Multicast list has changed; set the hardware
+ * filter accordingly.
+ */
+ fxp_init(sc);
+ error = 0;
+ }
+ }
+#else /* __FreeBSD__ */
+ /*
+ * Multicast list has changed; set the hardware filter
+ * accordingly.
+ */
+ fxp_init(sc);
+ error = 0;
+#endif /* __NetBSD__ || __OpenBSD__ */
+ break;
+
+ default:
+ error = EINVAL;
+ }
+ (void) splx(s);
+ return (error);
+}
diff --git a/sys/dev/pci/if_fxpreg.h b/sys/dev/pci/if_fxpreg.h
new file mode 100644
index 00000000000..0cc1d0afe06
--- /dev/null
+++ b/sys/dev/pci/if_fxpreg.h
@@ -0,0 +1,321 @@
+/* $NetBSD: if_fxpreg.h,v 1.2 1997/06/05 02:01:57 thorpej Exp $ */
+
+/*
+ * Copyright (c) 1995, David Greenman
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice unmodified, this list of conditions, and the following
+ * disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * Id: if_fxpreg.h,v 1.8 1997/03/21 08:00:13 davidg Exp
+ */
+
+#define FXP_VENDORID_INTEL 0x8086
+#define FXP_DEVICEID_i82557 0x1229
+
+#define FXP_PCI_MMBA 0x10
+#define FXP_PCI_IOBA 0x14
+
+/*
+ * Control/status registers.
+ */
+#define FXP_CSR_SCB_RUSCUS 0 /* scb_rus/scb_cus (1 byte) */
+#define FXP_CSR_SCB_STATACK 1 /* scb_statack (1 byte) */
+#define FXP_CSR_SCB_COMMAND 2 /* scb_command (1 byte) */
+#define FXP_CSR_SCB_INTRCNTL 3 /* scb_intrcntl (1 byte) */
+#define FXP_CSR_SCB_GENERAL 4 /* scb_general (4 bytes) */
+#define FXP_CSR_PORT 8 /* port (4 bytes) */
+#define FXP_CSR_FLASHCONTROL 12 /* flash control (2 bytes) */
+#define FXP_CSR_EEPROMCONTROL 14 /* eeprom control (2 bytes) */
+#define FXP_CSR_MDICONTROL 16 /* mdi control (4 bytes) */
+
+/*
+ * FOR REFERENCE ONLY, the old definition of FXP_CSR_SCB_RUSCUS:
+ *
+ * volatile u_int8_t :2,
+ * scb_rus:4,
+ * scb_cus:2;
+ */
+
+#define FXP_PORT_SOFTWARE_RESET 0
+#define FXP_PORT_SELFTEST 1
+#define FXP_PORT_SELECTIVE_RESET 2
+#define FXP_PORT_DUMP 3
+
+#define FXP_SCB_RUS_IDLE 0
+#define FXP_SCB_RUS_SUSPENDED 1
+#define FXP_SCB_RUS_NORESOURCES 2
+#define FXP_SCB_RUS_READY 4
+#define FXP_SCB_RUS_SUSP_NORBDS 9
+#define FXP_SCB_RUS_NORES_NORBDS 10
+#define FXP_SCB_RUS_READY_NORBDS 12
+
+#define FXP_SCB_CUS_IDLE 0
+#define FXP_SCB_CUS_SUSPENDED 1
+#define FXP_SCB_CUS_ACTIVE 2
+
+#define FXP_SCB_STATACK_SWI 0x04
+#define FXP_SCB_STATACK_MDI 0x08
+#define FXP_SCB_STATACK_RNR 0x10
+#define FXP_SCB_STATACK_CNA 0x20
+#define FXP_SCB_STATACK_FR 0x40
+#define FXP_SCB_STATACK_CXTNO 0x80
+
+#define FXP_SCB_COMMAND_MASK 0xff
+#define FXP_SCB_COMMAND_CU_NOP 0x00
+#define FXP_SCB_COMMAND_CU_START 0x10
+#define FXP_SCB_COMMAND_CU_RESUME 0x20
+#define FXP_SCB_COMMAND_CU_DUMP_ADR 0x40
+#define FXP_SCB_COMMAND_CU_DUMP 0x50
+#define FXP_SCB_COMMAND_CU_BASE 0x60
+#define FXP_SCB_COMMAND_CU_DUMPRESET 0x70
+
+#define FXP_SCB_COMMAND_RU_NOP 0
+#define FXP_SCB_COMMAND_RU_START 1
+#define FXP_SCB_COMMAND_RU_RESUME 2
+#define FXP_SCB_COMMAND_RU_ABORT 4
+#define FXP_SCB_COMMAND_RU_LOADHDS 5
+#define FXP_SCB_COMMAND_RU_BASE 6
+#define FXP_SCB_COMMAND_RU_RBDRESUME 7
+
+/*
+ * Command block definitions
+ */
+struct fxp_cb_nop {
+ volatile u_int16_t cb_status;
+ volatile u_int16_t cb_command;
+ volatile u_int32_t link_addr;
+};
+struct fxp_cb_ias {
+ volatile u_int16_t cb_status;
+ volatile u_int16_t cb_command;
+ volatile u_int32_t link_addr;
+ volatile u_int8_t macaddr[6];
+};
+/* I hate bit-fields :-( */
+struct fxp_cb_config {
+ volatile u_int16_t cb_status;
+ volatile u_int16_t cb_command;
+ volatile u_int32_t link_addr;
+ volatile u_int8_t byte_count:6,
+ :2;
+ volatile u_int8_t rx_fifo_limit:4,
+ tx_fifo_limit:3,
+ :1;
+ volatile u_int8_t adaptive_ifs;
+ volatile u_int8_t :8;
+ volatile u_int8_t rx_dma_bytecount:7,
+ :1;
+ volatile u_int8_t tx_dma_bytecount:7,
+ dma_bce:1;
+ volatile u_int8_t late_scb:1,
+ :1,
+ tno_int:1,
+ ci_int:1,
+ :3,
+ save_bf:1;
+ volatile u_int8_t disc_short_rx:1,
+ underrun_retry:2,
+ :5;
+ volatile u_int8_t mediatype:1,
+ :7;
+ volatile u_int8_t :8;
+ volatile u_int8_t :3,
+ nsai:1,
+ preamble_length:2,
+ loopback:2;
+ volatile u_int8_t linear_priority:3,
+ :5;
+ volatile u_int8_t linear_pri_mode:1,
+ :3,
+ interfrm_spacing:4;
+ volatile u_int8_t :8;
+ volatile u_int8_t :8;
+ volatile u_int8_t promiscuous:1,
+ bcast_disable:1,
+ :5,
+ crscdt:1;
+ volatile u_int8_t :8;
+ volatile u_int8_t :8;
+ volatile u_int8_t stripping:1,
+ padding:1,
+ rcv_crc_xfer:1,
+ :5;
+ volatile u_int8_t :6,
+ force_fdx:1,
+ fdx_pin_en:1;
+ volatile u_int8_t :6,
+ multi_ia:1,
+ :1;
+ volatile u_int8_t :3,
+ mc_all:1,
+ :4;
+};
+struct fxp_tbd {
+ volatile u_int32_t tb_addr;
+ volatile u_int32_t tb_size;
+};
+
+struct fxp_cb_tx {
+ volatile u_int16_t cb_status;
+ volatile u_int16_t cb_command;
+ volatile u_int32_t link_addr;
+ volatile u_int32_t tbd_array_addr;
+ volatile u_int16_t byte_count;
+ volatile u_int8_t tx_threshold;
+ volatile u_int8_t tbd_number;
+ /*
+ * The following isn't actually part of the TxCB.
+ */
+ volatile struct fxp_tbd tbd[29];
+ struct mbuf *mb_head;
+ struct fxp_cb_tx *next;
+};
+
+/*
+ * Control Block (CB) definitions
+ */
+
+/* status */
+#define FXP_CB_STATUS_OK 0x2000
+#define FXP_CB_STATUS_C 0x8000
+/* commands */
+#define FXP_CB_COMMAND_NOP 0x0
+#define FXP_CB_COMMAND_IAS 0x1
+#define FXP_CB_COMMAND_CONFIG 0x2
+#define FXP_CB_COMMAND_MAS 0x3
+#define FXP_CB_COMMAND_XMIT 0x4
+#define FXP_CB_COMMAND_RESRV 0x5
+#define FXP_CB_COMMAND_DUMP 0x6
+#define FXP_CB_COMMAND_DIAG 0x7
+/* command flags */
+#define FXP_CB_COMMAND_SF 0x0008 /* simple/flexible mode */
+#define FXP_CB_COMMAND_I 0x2000 /* generate interrupt on completion */
+#define FXP_CB_COMMAND_S 0x4000 /* suspend on completion */
+#define FXP_CB_COMMAND_EL 0x8000 /* end of list */
+
+/*
+ * RFA definitions
+ */
+
+struct fxp_rfa {
+ volatile u_int16_t rfa_status;
+ volatile u_int16_t rfa_control;
+ volatile u_int32_t link_addr;
+ volatile u_int32_t rbd_addr;
+ volatile u_int16_t actual_size;
+ volatile u_int16_t size;
+};
+#define FXP_RFA_STATUS_RCOL 0x0001 /* receive collision */
+#define FXP_RFA_STATUS_IAMATCH 0x0002 /* 0 = matches station address */
+#define FXP_RFA_STATUS_S4 0x0010 /* receive error from PHY */
+#define FXP_RFA_STATUS_TL 0x0020 /* type/length */
+#define FXP_RFA_STATUS_FTS 0x0080 /* frame too short */
+#define FXP_RFA_STATUS_OVERRUN 0x0100 /* DMA overrun */
+#define FXP_RFA_STATUS_RNR 0x0200 /* no resources */
+#define FXP_RFA_STATUS_ALIGN 0x0400 /* alignment error */
+#define FXP_RFA_STATUS_CRC 0x0800 /* CRC error */
+#define FXP_RFA_STATUS_OK 0x2000 /* packet received okay */
+#define FXP_RFA_STATUS_C 0x8000 /* packet reception complete */
+#define FXP_RFA_CONTROL_SF 0x08 /* simple/flexible memory mode */
+#define FXP_RFA_CONTROL_H 0x10 /* header RFD */
+#define FXP_RFA_CONTROL_S 0x4000 /* suspend after reception */
+#define FXP_RFA_CONTROL_EL 0x8000 /* end of list */
+
+/*
+ * Statistics dump area definitions
+ */
+struct fxp_stats {
+ volatile u_int32_t tx_good;
+ volatile u_int32_t tx_maxcols;
+ volatile u_int32_t tx_latecols;
+ volatile u_int32_t tx_underruns;
+ volatile u_int32_t tx_lostcrs;
+ volatile u_int32_t tx_deffered;
+ volatile u_int32_t tx_single_collisions;
+ volatile u_int32_t tx_multiple_collisions;
+ volatile u_int32_t tx_total_collisions;
+ volatile u_int32_t rx_good;
+ volatile u_int32_t rx_crc_errors;
+ volatile u_int32_t rx_alignment_errors;
+ volatile u_int32_t rx_rnr_errors;
+ volatile u_int32_t rx_overrun_errors;
+ volatile u_int32_t rx_cdt_errors;
+ volatile u_int32_t rx_shortframes;
+ volatile u_int32_t completion_status;
+};
+#define FXP_STATS_DUMP_COMPLETE 0xa005
+#define FXP_STATS_DR_COMPLETE 0xa007
+
+/*
+ * Serial EEPROM control register bits
+ */
+/* shift clock */
+#define FXP_EEPROM_EESK 0x01
+/* chip select */
+#define FXP_EEPROM_EECS 0x02
+/* data in */
+#define FXP_EEPROM_EEDI 0x04
+/* data out */
+#define FXP_EEPROM_EEDO 0x08
+
+/*
+ * Serial EEPROM opcodes, including start bit
+ */
+#define FXP_EEPROM_OPC_ERASE 0x4
+#define FXP_EEPROM_OPC_WRITE 0x5
+#define FXP_EEPROM_OPC_READ 0x6
+
+/*
+ * Management Data Interface opcodes
+ */
+#define FXP_MDI_WRITE 0x1
+#define FXP_MDI_READ 0x2
+
+/*
+ * PHY device types
+ */
+#define FXP_PHY_NONE 0
+#define FXP_PHY_82553A 1
+#define FXP_PHY_82553C 2
+#define FXP_PHY_82503 3
+#define FXP_PHY_DP83840 4
+#define FXP_PHY_80C240 5
+#define FXP_PHY_80C24 6
+#define FXP_PHY_DP83840A 10
+
+/*
+ * DP84830 PHY, BMCR Basic Mode Control Register
+ */
+#define FXP_DP83840_BMCR 0x0
+#define FXP_DP83840_BMCR_FULLDUPLEX 0x0100
+#define FXP_DP83840_BMCR_AUTOEN 0x1000
+#define FXP_DP83840_BMCR_SPEED_100M 0x2000
+
+/*
+ * DP84830 PHY, PCS Configuration Register
+ */
+#define FXP_DP83840_PCR 0x17
+#define FXP_DP83840_PCR_LED4_MODE 0x0002 /* 1 = LED4 always indicates full duplex */
+#define FXP_DP83840_PCR_F_CONNECT 0x0020 /* 1 = force link disconnect function bypass */
+#define FXP_DP83840_PCR_BIT8 0x0100
+#define FXP_DP83840_PCR_BIT10 0x0400
diff --git a/sys/dev/pci/if_fxpvar.h b/sys/dev/pci/if_fxpvar.h
new file mode 100644
index 00000000000..d3a2723ff22
--- /dev/null
+++ b/sys/dev/pci/if_fxpvar.h
@@ -0,0 +1,116 @@
+/* $NetBSD: if_fxpvar.h,v 1.1 1997/06/05 02:01:58 thorpej Exp $ */
+
+/*
+ * Copyright (c) 1995, David Greenman
+ * All rights reserved.
+ *
+ * Modifications to support NetBSD:
+ * Copyright (c) 1997 Jason R. Thorpe. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice unmodified, this list of conditions, and the following
+ * disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * Id: if_fxp.c,v 1.34 1997/04/23 01:44:30 davidg Exp
+ */
+
+/*
+ * Misc. defintions for the Intel EtherExpress Pro/100B PCI Fast
+ * Ethernet driver
+ */
+
+struct fxp_softc {
+#if defined(__NetBSD__) || defined(__OpenBSD__)
+ struct device sc_dev; /* generic device structures */
+ void *sc_ih; /* interrupt handler cookie */
+ bus_space_tag_t sc_st; /* bus space tag */
+ bus_space_handle_t sc_sh; /* bus space handle */
+#else
+ struct caddr_t csr; /* control/status registers */
+#endif /* __NetBSD__ || __OpenBSD__ */
+#if defined(__OpenBSD__) || defined(__FreeBSD__)
+ struct arpcom arpcom; /* per-interface network data */
+#endif
+#if defined(__NetBSD__)
+ struct ethercom sc_ethercom; /* ethernet common part */
+#endif
+ struct fxp_cb_tx *cbl_base; /* base of TxCB list */
+ struct fxp_cb_tx *cbl_first; /* first active TxCB in list */
+ struct fxp_cb_tx *cbl_last; /* last active TxCB in list */
+ struct mbuf *rfa_headm; /* first mbuf in receive frame area */
+ struct mbuf *rfa_tailm; /* last mbuf in receive frame area */
+ struct fxp_stats *fxp_stats; /* Pointer to interface stats */
+ int tx_queued; /* # of active TxCB's */
+ int promisc_mode; /* promiscuous mode enabled */
+ int phy_primary_addr; /* address of primary PHY */
+ int phy_primary_device; /* device type of primary PHY */
+ int phy_10Mbps_only; /* PHY is 10Mbps-only device */
+};
+
+/* Macros to ease CSR access. */
+#if defined(__NetBSD__) || defined(__OpenBSD__)
+#define CSR_READ_1(sc, reg) \
+ bus_space_read_1((sc)->sc_st, (sc)->sc_sh, (reg))
+#define CSR_READ_2(sc, reg) \
+ bus_space_read_2((sc)->sc_st, (sc)->sc_sh, (reg))
+#define CSR_READ_4(sc, reg) \
+ bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))
+#define CSR_WRITE_1(sc, reg, val) \
+ bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val))
+#define CSR_WRITE_2(sc, reg, val) \
+ bus_space_write_2((sc)->sc_st, (sc)->sc_sh, (reg), (val))
+#define CSR_WRITE_4(sc, reg, val) \
+ bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))
+#else
+#define CSR_READ_1(sc, reg) \
+ (*((u_int8_t *)((sc)->csr + (reg))))
+#define CSR_READ_2(sc, reg) \
+ (*((u_int16_t *)((sc)->csr + (reg))))
+#define CSR_READ_4(sc, reg) \
+ (*((u_int32_t *)((sc)->csr + (reg))))
+#define CSR_WRITE_1(sc, reg, val) \
+ (*((u_int8_t *)((sc)->csr + (reg)))) = (val)
+#define CSR_WRITE_2(sc, reg, val) \
+ (*((u_int16_t *)((sc)->csr + (reg)))) = (val)
+#define CSR_WRITE_4(sc, reg, val) \
+ (*((u_int32_t *)((sc)->csr + (reg)))) = (val)
+#endif /* __NetBSD__ || __OpenBSD__ */
+
+/* Deal with slight differences in software interfaces. */
+#if defined(__NetBSD__) || defined(__OpenBSD__)
+#if defined(__OpenBSD__)
+#define sc_if arpcom.ac_if
+#else
+#define sc_if sc_ethercom.ec_if
+#endif
+#define FXP_FORMAT "%s"
+#define FXP_ARGS(sc) (sc)->sc_dev.dv_xname
+#define FXP_INTR_TYPE int
+#define FXP_IOCTLCMD_TYPE u_long
+#define FXP_BPFTAP_ARG(ifp) (ifp)->if_bpf
+#else /* __FreeBSD__ */
+#define sc_if arpcom.ac_if
+#define FXP_FORMAT "fxp%d"
+#define FXP_ARGS(sc) (sc)->arpcom.ac_if.if_unit
+#define FXP_INTR_TYPE void
+#define FXP_IOCTLCMD_TYPE int
+#define FXP_BPFTAP_ARG(ifp) ifp
+#endif /* __NetBSD__ || __OpenBSD__ */