Rework the cache handling routines again. We now try to operate on the exact

address range we've been given, rounded to cache line boundaries, instead
of being lazy and operating on pages as soon as the range was large enough.

Also, since the ranges we'll be invoked for are reasonably small, it does
not make sense to check for segment sizes - we're always smaller, really.

While there, hardcode the size in cmmu_flush_data_cache(), which becomes
cmmu_flush_data_page(), since it was always invoked for complete pages.

6 files changed, 156 insertions, 179 deletions

diff --git a/sys/arch/m88k/include/cmmu.h b/sys/arch/m88k/include/cmmu.h
index 4a09689093a..f0bf7c31982 100644
--- a/sys/arch/m88k/include/cmmu.h
+++ b/sys/arch/m88k/include/cmmu.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: cmmu.h,v 1.16 2005/12/11 21:45:28 miod Exp $ */
+/*	$OpenBSD: cmmu.h,v 1.17 2007/02/11 12:49:35 miod Exp $ */
 /*
  * Mach Operating System
  * Copyright (c) 1993-1992 Carnegie Mellon University
@@ -64,9 +64,9 @@ struct cmmu_p {
 	void (*flush_tlb)(cpuid_t, u_int, vaddr_t, u_int);
 	void (*flush_cache)(cpuid_t, paddr_t, psize_t);
 	void (*flush_inst_cache)(cpuid_t, paddr_t, psize_t);
-	void (*flush_data_cache)(cpuid_t, paddr_t, psize_t);
-	int (*dma_cachectl)(pmap_t, vaddr_t, vsize_t, int);
-	int (*dma_cachectl_pa)(paddr_t, psize_t, int);
+	void (*flush_data_page)(cpuid_t, paddr_t);
+	void (*dma_cachectl)(pmap_t, vaddr_t, vsize_t, int);
+	void (*dma_cachectl_pa)(paddr_t, psize_t, int);
 #ifdef MULTIPROCESSOR
 	void (*initialize_cpu)(cpuid_t);
 #endif
@@ -84,7 +84,7 @@ extern struct cmmu_p *cmmu;
 #define	cmmu_flush_tlb(a, b, c, d) 	(cmmu->flush_tlb)(a, b, c, d)
 #define	cmmu_flush_cache(a, b, c)	(cmmu->flush_cache)(a, b, c)
 #define	cmmu_flush_inst_cache(a, b, c)	(cmmu->flush_inst_cache)(a, b, c)
-#define	cmmu_flush_data_cache(a, b, c)	(cmmu->flush_data_cache)(a, b, c)
+#define	cmmu_flush_data_page(a, b)	(cmmu->flush_data_page)(a, b)
 #define	dma_cachectl(a, b, c, d)	(cmmu->dma_cachectl)(a, b, c, d)
 #define	dma_cachectl_pa(a, b, c)	(cmmu->dma_cachectl_pa)(a, b, c)
 #define	cmmu_initialize_cpu(a)		(cmmu->initialize_cpu)(a)
diff --git a/sys/arch/m88k/m88k/m8820x_machdep.c b/sys/arch/m88k/m88k/m8820x_machdep.c
index 7a662f1686d..a469093c359 100644
--- a/sys/arch/m88k/m88k/m8820x_machdep.c
+++ b/sys/arch/m88k/m88k/m8820x_machdep.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: m8820x_machdep.c,v 1.23 2006/05/08 14:36:09 miod Exp $	*/
+/*	$OpenBSD: m8820x_machdep.c,v 1.24 2007/02/11 12:49:37 miod Exp $	*/
 /*
  * Copyright (c) 2004, Miodrag Vallat.
  *
@@ -101,9 +101,9 @@ void	m8820x_set_uapr(apr_t);
 void	m8820x_flush_tlb(cpuid_t, u_int, vaddr_t, u_int);
 void	m8820x_flush_cache(cpuid_t, paddr_t, psize_t);
 void	m8820x_flush_inst_cache(cpuid_t, paddr_t, psize_t);
-void	m8820x_flush_data_cache(cpuid_t, paddr_t, psize_t);
-int	m8820x_dma_cachectl(pmap_t, vaddr_t, vsize_t, int);
-int	m8820x_dma_cachectl_pa(paddr_t, psize_t, int);
+void	m8820x_flush_data_page(cpuid_t, paddr_t);
+void	m8820x_dma_cachectl(pmap_t, vaddr_t, vsize_t, int);
+void	m8820x_dma_cachectl_pa(paddr_t, psize_t, int);
 void	m8820x_initialize_cpu(cpuid_t);
 
 /* This is the function table for the MC8820x CMMUs */
@@ -118,7 +118,7 @@ struct cmmu_p cmmu8820x = {
 	m8820x_flush_tlb,
 	m8820x_flush_cache,
 	m8820x_flush_inst_cache,
-	m8820x_flush_data_cache,
+	m8820x_flush_data_page,
 	m8820x_dma_cachectl,
 	m8820x_dma_cachectl_pa,
 #ifdef MULTIPROCESSOR
@@ -155,9 +155,9 @@ u_int cmmu_shift;
 void	m8820x_cmmu_set_reg(int, u_int, int, int, int);
 void	m8820x_cmmu_set_cmd(u_int, int, int, int, vaddr_t);
 void	m8820x_cmmu_wait(int);
-int	m8820x_cmmu_sync_cache(paddr_t, psize_t);
-int	m8820x_cmmu_sync_inval_cache(paddr_t, psize_t);
-int	m8820x_cmmu_inval_cache(paddr_t, psize_t);
+void	m8820x_cmmu_sync_cache(paddr_t, psize_t);
+void	m8820x_cmmu_sync_inval_cache(paddr_t, psize_t);
+void	m8820x_cmmu_inval_cache(paddr_t, psize_t);
 
 /* Flags passed to m8820x_cmmu_set() */
 #define MODE_VAL		0x01
@@ -561,27 +561,33 @@ m8820x_flush_tlb(cpuid_t cpu, unsigned kernel, vaddr_t vaddr, u_int count)
  * address split - this does not work...
  */
 
+#define	trunc_cache_line(a)	((a) & ~(MC88200_CACHE_LINE - 1))
+#define	round_cache_line(a)	trunc_cache_line((a) + MC88200_CACHE_LINE - 1)
+
 /*
  *	flush both Instruction and Data caches
  */
 void
-m8820x_flush_cache(cpuid_t cpu, paddr_t physaddr, psize_t size)
+m8820x_flush_cache(cpuid_t cpu, paddr_t pa, psize_t size)
 {
 	int s = splhigh();
 	CMMU_LOCK;
 
+	size = round_cache_line(pa + size) - trunc_cache_line(pa);
+	pa = trunc_cache_line(pa);
+
 	if (size > NBSG) {
 		m8820x_cmmu_set_reg(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_ALL, 0,
 		    cpu, 0);
 	} else if (size <= MC88200_CACHE_LINE) {
 		m8820x_cmmu_set_cmd(CMMU_FLUSH_CACHE_CBI_LINE, 0 /* ADDR_VAL */,
-		    cpu, 0, physaddr);
+		    cpu, 0, pa);
 	} else if (size <= PAGE_SIZE) {
 		m8820x_cmmu_set_cmd(CMMU_FLUSH_CACHE_CBI_PAGE, 0 /* ADDR_VAL */,
-		    cpu, 0, physaddr);
+		    cpu, 0, pa);
 	} else {
 		m8820x_cmmu_set_cmd(CMMU_FLUSH_CACHE_CBI_SEGMENT, 0,
-		    cpu, 0, physaddr);
+		    cpu, 0, pa);
 	}
 
 	m8820x_cmmu_wait(cpu);
@@ -594,23 +600,26 @@ m8820x_flush_cache(cpuid_t cpu, paddr_t physaddr, psize_t size)
  *	flush Instruction caches
  */
 void
-m8820x_flush_inst_cache(cpuid_t cpu, paddr_t physaddr, psize_t size)
+m8820x_flush_inst_cache(cpuid_t cpu, paddr_t pa, psize_t size)
 {
 	int s = splhigh();
 	CMMU_LOCK;
 
+	size = round_cache_line(pa + size) - trunc_cache_line(pa);
+	pa = trunc_cache_line(pa);
+
 	if (size > NBSG) {
 		m8820x_cmmu_set_reg(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_ALL,
 		    MODE_VAL, cpu, INST_CMMU);
 	} else if (size <= MC88200_CACHE_LINE) {
 		m8820x_cmmu_set_cmd(CMMU_FLUSH_CACHE_CBI_LINE,
-		    MODE_VAL /* | ADDR_VAL */, cpu, INST_CMMU, physaddr);
+		    MODE_VAL /* | ADDR_VAL */, cpu, INST_CMMU, pa);
 	} else if (size <= PAGE_SIZE) {
 		m8820x_cmmu_set_cmd(CMMU_FLUSH_CACHE_CBI_PAGE,
-		    MODE_VAL /* | ADDR_VAL */, cpu, INST_CMMU, physaddr);
+		    MODE_VAL /* | ADDR_VAL */, cpu, INST_CMMU, pa);
 	} else {
 		m8820x_cmmu_set_cmd(CMMU_FLUSH_CACHE_CBI_SEGMENT,
-		    MODE_VAL, cpu, INST_CMMU, physaddr);
+		    MODE_VAL, cpu, INST_CMMU, pa);
 	}
 
 	m8820x_cmmu_wait(cpu);
@@ -620,25 +629,13 @@ m8820x_flush_inst_cache(cpuid_t cpu, paddr_t physaddr, psize_t size)
 }
 
 void
-m8820x_flush_data_cache(cpuid_t cpu, paddr_t physaddr, psize_t size)
+m8820x_flush_data_page(cpuid_t cpu, paddr_t pa)
 {
 	int s = splhigh();
 	CMMU_LOCK;
 
-	if (size > NBSG) {
-		m8820x_cmmu_set_reg(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_ALL,
-		    MODE_VAL, cpu, DATA_CMMU);
-	} else if (size <= MC88200_CACHE_LINE) {
-		m8820x_cmmu_set_cmd(CMMU_FLUSH_CACHE_CBI_LINE,
-		    MODE_VAL /* | ADDR_VAL */, cpu, DATA_CMMU, physaddr);
-	} else if (size <= PAGE_SIZE) {
-		m8820x_cmmu_set_cmd(CMMU_FLUSH_CACHE_CBI_PAGE,
-		    MODE_VAL /* | ADDR_VAL */, cpu, DATA_CMMU, physaddr);
-	} else {
-		m8820x_cmmu_set_cmd(CMMU_FLUSH_CACHE_CBI_SEGMENT,
-		    MODE_VAL, cpu, DATA_CMMU, physaddr);
-	}
-
+	m8820x_cmmu_set_cmd(CMMU_FLUSH_CACHE_CBI_PAGE,
+	    MODE_VAL /* | ADDR_VAL */, cpu, DATA_CMMU, pa);
 	m8820x_cmmu_wait(cpu);
 
 	CMMU_UNLOCK;
@@ -648,175 +645,138 @@ m8820x_flush_data_cache(cpuid_t cpu, paddr_t physaddr, psize_t size)
 /*
  * sync dcache - icache is never dirty but needs to be invalidated as well.
  */
-int
-m8820x_cmmu_sync_cache(paddr_t physaddr, psize_t size)
+void
+m8820x_cmmu_sync_cache(paddr_t pa, psize_t size)
 {
 	int s = splhigh();
 	int cpu = cpu_number();
-	int rc;
 
 	CMMU_LOCK;
 
-	if (size > NBSG) {
-		m8820x_cmmu_set_reg(CMMU_SCR, CMMU_FLUSH_CACHE_CB_ALL,
-		    MODE_VAL, cpu, DATA_CMMU);
-		rc = 1;
-	} else if (size <= MC88200_CACHE_LINE) {
+	if (size <= MC88200_CACHE_LINE) {
 		m8820x_cmmu_set_cmd(CMMU_FLUSH_CACHE_CB_LINE,
-		    MODE_VAL /* | ADDR_VAL */, cpu, DATA_CMMU, physaddr);
-		rc = 0;
-	} else if (size <= PAGE_SIZE) {
-		m8820x_cmmu_set_cmd(CMMU_FLUSH_CACHE_CB_PAGE,
-		    MODE_VAL /* | ADDR_VAL */, cpu, DATA_CMMU, physaddr);
-		rc = 0;
+		    MODE_VAL /* | ADDR_VAL */, cpu, DATA_CMMU, pa);
 	} else {
-		m8820x_cmmu_set_cmd(CMMU_FLUSH_CACHE_CB_SEGMENT,
-		    MODE_VAL, cpu, DATA_CMMU, physaddr);
-		rc = 0;
+		m8820x_cmmu_set_cmd(CMMU_FLUSH_CACHE_CB_PAGE,
+		    MODE_VAL /* | ADDR_VAL */, cpu, DATA_CMMU, pa);
 	}
 
 	m8820x_cmmu_wait(cpu);
 
 	CMMU_UNLOCK;
 	splx(s);
-	return (rc);
 }
 
-int
-m8820x_cmmu_sync_inval_cache(paddr_t physaddr, psize_t size)
+void
+m8820x_cmmu_sync_inval_cache(paddr_t pa, psize_t size)
 {
 	int s = splhigh();
 	int cpu = cpu_number();
-	int rc;
 
 	CMMU_LOCK;
 
-	if (size > NBSG) {
-		m8820x_cmmu_set_reg(CMMU_SCR, CMMU_FLUSH_CACHE_INV_ALL,
-		    MODE_VAL, cpu, INST_CMMU);
-		m8820x_cmmu_set_reg(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_ALL,
-		    MODE_VAL, cpu, DATA_CMMU);
-		rc = 1;
-	} else if (size <= MC88200_CACHE_LINE) {
+	if (size <= MC88200_CACHE_LINE) {
 		m8820x_cmmu_set_cmd(CMMU_FLUSH_CACHE_INV_LINE,
-		    MODE_VAL /* | ADDR_VAL */, cpu, INST_CMMU, physaddr);
+		    MODE_VAL /* | ADDR_VAL */, cpu, INST_CMMU, pa);
 		m8820x_cmmu_set_cmd(CMMU_FLUSH_CACHE_CBI_LINE,
-		    MODE_VAL /* | ADDR_VAL */, cpu, DATA_CMMU, physaddr);
-		rc = 0;
-	} else if (size <= PAGE_SIZE) {
+		    MODE_VAL /* | ADDR_VAL */, cpu, DATA_CMMU, pa);
+	} else {
 		m8820x_cmmu_set_cmd(CMMU_FLUSH_CACHE_INV_PAGE,
-		    MODE_VAL /* | ADDR_VAL */, cpu, INST_CMMU, physaddr);
+		    MODE_VAL /* | ADDR_VAL */, cpu, INST_CMMU, pa);
 		m8820x_cmmu_set_cmd(CMMU_FLUSH_CACHE_CBI_PAGE,
-		    MODE_VAL /* | ADDR_VAL */, cpu, DATA_CMMU, physaddr);
-		rc = 0;
-	} else {
-		m8820x_cmmu_set_cmd(CMMU_FLUSH_CACHE_INV_SEGMENT,
-		    MODE_VAL, cpu, INST_CMMU, physaddr);
-		m8820x_cmmu_set_cmd(CMMU_FLUSH_CACHE_CBI_SEGMENT,
-		    MODE_VAL, cpu, DATA_CMMU, physaddr);
-		rc = 0;
+		    MODE_VAL /* | ADDR_VAL */, cpu, DATA_CMMU, pa);
 	}
 
 	m8820x_cmmu_wait(cpu);
 
 	CMMU_UNLOCK;
 	splx(s);
-	return (rc);
 }
 
-int
-m8820x_cmmu_inval_cache(paddr_t physaddr, psize_t size)
+void
+m8820x_cmmu_inval_cache(paddr_t pa, psize_t size)
 {
 	int s = splhigh();
 	int cpu = cpu_number();
-	int rc;
 
 	CMMU_LOCK;
 
-	if (size > NBSG) {
-		m8820x_cmmu_set_reg(CMMU_SCR, CMMU_FLUSH_CACHE_INV_ALL, 0,
-		    cpu, 0);
-		rc = 1;
-	} else if (size <= MC88200_CACHE_LINE) {
+	if (size <= MC88200_CACHE_LINE) {
 		m8820x_cmmu_set_cmd(CMMU_FLUSH_CACHE_INV_LINE,
-		    0 /* ADDR_VAL */, cpu, 0, physaddr);
-		rc = 0;
-	} else if (size <= PAGE_SIZE) {
-		m8820x_cmmu_set_cmd(CMMU_FLUSH_CACHE_INV_PAGE,
-		    0 /* ADDR_VAL */, cpu, 0, physaddr);
-		rc = 0;
+		    0 /* ADDR_VAL */, cpu, 0, pa);
 	} else {
-		m8820x_cmmu_set_cmd(CMMU_FLUSH_CACHE_INV_SEGMENT,
-		    0, cpu, 0, physaddr);
-		rc = 0;
+		m8820x_cmmu_set_cmd(CMMU_FLUSH_CACHE_INV_PAGE,
+		    0 /* ADDR_VAL */, cpu, 0, pa);
 	}
 
 	m8820x_cmmu_wait(cpu);
 
 	CMMU_UNLOCK;
 	splx(s);
-	return (rc);
 }
 
-int
+void
 m8820x_dma_cachectl(pmap_t pmap, vaddr_t va, vsize_t size, int op)
 {
 	paddr_t pa;
 	psize_t count;
-	int rc = 0;
+	void (*flusher)(paddr_t, psize_t);
 
-	size = round_page(va + size) - trunc_page(va);
-	va = trunc_page(va);
+	size = round_cache_line(va + size) - trunc_cache_line(va);
+	va = trunc_cache_line(va);
 
-	while (size != 0 && rc == 0) {
-		count = min(size, PAGE_SIZE);
+	switch (op) {
+	case DMA_CACHE_SYNC:
+		flusher = m8820x_cmmu_sync_cache;
+		break;
+	case DMA_CACHE_SYNC_INVAL:
+		flusher = m8820x_cmmu_sync_inval_cache;
+		break;
+	default:
+		flusher = m8820x_cmmu_inval_cache;
+		break;
+	}
 
-		if (pmap_extract(pmap, va, &pa) != FALSE) {
-			switch (op) {
-			case DMA_CACHE_SYNC:
-				rc |= m8820x_cmmu_sync_cache(pa, count);
-				break;
-			case DMA_CACHE_SYNC_INVAL:
-				rc |= m8820x_cmmu_sync_inval_cache(pa, count);
-				break;
-			default:
-				rc |= m8820x_cmmu_inval_cache(pa, count);
-				break;
-			}
-		}
+	while (size != 0) {
+		count = (va & PAGE_MASK) == 0 && size >= PAGE_SIZE ?
+		    PAGE_SIZE : MC88200_CACHE_LINE;
+
+		if (pmap_extract(pmap, va, &pa) != FALSE)
+			(*flusher)(pa, count);
 
 		va += count;
 		size -= count;
 	}
-	return (rc);
 }
 
-int
+void
 m8820x_dma_cachectl_pa(paddr_t pa, psize_t size, int op)
 {
 	psize_t count;
-	int rc = 0;
-
-	size = round_page(pa + size) - trunc_page(pa);
-	pa = trunc_page(pa);
-
-	while (size != 0 && rc == 0) {
-		count = min(size, PAGE_SIZE);
-
-		switch (op) {
-		case DMA_CACHE_SYNC:
-			rc |= m8820x_cmmu_sync_cache(pa, count);
-			break;
-		case DMA_CACHE_SYNC_INVAL:
-			rc |= m8820x_cmmu_sync_inval_cache(pa, count);
-			break;
-		default:
-			rc |= m8820x_cmmu_inval_cache(pa, count);
-			break;
-		}
+	void (*flusher)(paddr_t, psize_t);
+
+	size = round_cache_line(pa + size) - trunc_cache_line(pa);
+	pa = trunc_cache_line(pa);
+
+	switch (op) {
+	case DMA_CACHE_SYNC:
+		flusher = m8820x_cmmu_sync_cache;
+		break;
+	case DMA_CACHE_SYNC_INVAL:
+		flusher = m8820x_cmmu_sync_inval_cache;
+		break;
+	default:
+		flusher = m8820x_cmmu_inval_cache;
+		break;
+	}
+
+	while (size != 0) {
+		count = (pa & PAGE_MASK) == 0 && size >= PAGE_SIZE ?
+		    PAGE_SIZE : MC88200_CACHE_LINE;
+
+		(*flusher)(pa, count);
 
 		pa += count;
 		size -= count;
 	}
-	return (rc);
 }
diff --git a/sys/arch/m88k/m88k/pmap.c b/sys/arch/m88k/m88k/pmap.c
index 2aca2c050de..9b3db4eb826 100644
--- a/sys/arch/m88k/m88k/pmap.c
+++ b/sys/arch/m88k/m88k/pmap.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: pmap.c,v 1.28 2006/06/01 06:28:11 miod Exp $	*/
+/*	$OpenBSD: pmap.c,v 1.29 2007/02/11 12:49:37 miod Exp $	*/
 /*
  * Copyright (c) 2001-2004, Miodrag Vallat
  * Copyright (c) 1998-2001 Steve Murphree, Jr.
@@ -842,7 +842,7 @@ pmap_zero_page(struct vm_page *pg)
 	 * So be sure to have the pa flushed after the filling.
 	 */
 	bzero((void *)va, PAGE_SIZE);
-	cmmu_flush_data_cache(cpu, pa, PAGE_SIZE);
+	cmmu_flush_data_page(cpu, pa);
 
 	splx(spl);
 }
@@ -2115,9 +2115,9 @@ pmap_copy_page(struct vm_page *srcpg, struct vm_page *dstpg)
 	 * So be sure to have the source pa flushed before the copy is
 	 * attempted, and the destination pa flushed afterwards.
 	 */
-	cmmu_flush_data_cache(cpu, src, PAGE_SIZE);
+	cmmu_flush_data_page(cpu, src);
 	bcopy((const void *)srcva, (void *)dstva, PAGE_SIZE);
-	cmmu_flush_data_cache(cpu, dst, PAGE_SIZE);
+	cmmu_flush_data_page(cpu, dst);
 
 	splx(spl);
 }
@@ -2563,22 +2563,21 @@ void
 pmap_proc_iflush(struct proc *p, vaddr_t va, vsize_t len)
 {
 	pmap_t pmap = vm_map_pmap(&p->p_vmspace->vm_map);
-	vaddr_t eva;
 	paddr_t pa;
+	vsize_t count;
 	u_int32_t users;
 	int cpu;
 
-	eva = round_page(va + len);
-	va = trunc_page(va);
-
-	while (va != eva) {
+	while (len != 0) {
+		count = min(len, PAGE_SIZE - (va & PAGE_MASK));
 		if (pmap_extract(pmap, va, &pa)) {
 			users = pmap->pm_cpus;
 			while ((cpu = ff1(users)) != 32) {
-				cmmu_flush_inst_cache(cpu, pa, PAGE_SIZE);
+				cmmu_flush_inst_cache(cpu, pa, count);
 				users &= ~(1 << cpu);
 			}
 		}
-		va += PAGE_SIZE;
+		va += count;
+		len -= count;
 	}
 }
diff --git a/sys/arch/m88k/m88k/trap.c b/sys/arch/m88k/m88k/trap.c
index df8a7c94d2e..df5f44870af 100644
--- a/sys/arch/m88k/m88k/trap.c
+++ b/sys/arch/m88k/m88k/trap.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: trap.c,v 1.37 2006/12/24 20:30:35 miod Exp $	*/
+/*	$OpenBSD: trap.c,v 1.38 2007/02/11 12:49:37 miod Exp $	*/
 /*
  * Copyright (c) 2004, Miodrag Vallat.
  * Copyright (c) 1998 Steve Murphree, Jr.
@@ -1767,6 +1767,9 @@ cache_flush(struct trapframe *tf)
 {
 	struct proc *p;
 	struct pmap *pmap;
+	paddr_t pa;
+	vaddr_t va;
+	vsize_t len, count;
 
 	if ((p = curproc) == NULL)
 		p = &proc0;
@@ -1774,10 +1777,31 @@ cache_flush(struct trapframe *tf)
 	p->p_md.md_tf = tf;
 
 	pmap = vm_map_pmap(&p->p_vmspace->vm_map);
-	dma_cachectl(pmap, tf->tf_r[2], tf->tf_r[3], DMA_CACHE_SYNC);
+	va = tf->tf_r[2];
+	len = tf->tf_r[3];
+
+	if (/* va < VM_MIN_ADDRESS || */ va >= VM_MAXUSER_ADDRESS ||
+	    va + len <= va || va + len >= VM_MAXUSER_ADDRESS)
+		len = 0;
+
+	while (len != 0) {
+		count = min(len, PAGE_SIZE - (va & PAGE_MASK));
+		if (pmap_extract(pmap, va, &pa) != FALSE)	
+			dma_cachectl_pa(pa, count, DMA_CACHE_SYNC);
+		va += count;
+		len -= count;
+	}
 
-	tf->tf_snip = tf->tf_snip & ~NIP_E;
-	tf->tf_sfip = tf->tf_sfip & ~FIP_E;
+	if (CPU_IS88100) {
+		tf->tf_snip = tf->tf_snip & ~NIP_E;
+		tf->tf_sfip = tf->tf_sfip & ~FIP_E;
+	} else {
+		/* skip instruction */
+		if (tf->tf_exip & 1)
+			tf->tf_exip = tf->tf_enip;
+		else
+			tf->tf_exip += 4;
+	}
 
 	userret(p);
 }
diff --git a/sys/arch/mvme88k/mvme88k/bus_dma.c b/sys/arch/mvme88k/mvme88k/bus_dma.c
index e92cb8c0398..7419b19d495 100644
--- a/sys/arch/mvme88k/mvme88k/bus_dma.c
+++ b/sys/arch/mvme88k/mvme88k/bus_dma.c
@@ -1,4 +1,4 @@
-/*      $OpenBSD: bus_dma.c,v 1.4 2005/11/25 22:18:18 miod Exp $	*/
+/*      $OpenBSD: bus_dma.c,v 1.5 2007/02/11 12:49:38 miod Exp $	*/
 /*      $NetBSD: bus_dma.c,v 1.2 2001/06/10 02:31:25 briggs Exp $        */
 
 /*-
@@ -433,17 +433,14 @@ bus_dmamap_sync(t, map, offset, len, op)
 	u_int nsegs;
 	bus_dma_segment_t *seg;
 
-	switch (op) {
-	case BUS_DMASYNC_PREWRITE:
-		op = DMA_CACHE_SYNC;
-		break;
-	case BUS_DMASYNC_PREREAD:
-	case BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE:
+	if (op & BUS_DMASYNC_PREREAD)
 		op = DMA_CACHE_SYNC_INVAL;
-		break;
-	default:
+	else if (op & BUS_DMASYNC_PREWRITE)
+		op = DMA_CACHE_SYNC;
+	else if (op & BUS_DMASYNC_POSTREAD)
+		op = DMA_CACHE_INV;
+	else
 		return;
-	}
 
 	nsegs = map->dm_nsegs;
 	seg = map->dm_segs;
@@ -459,8 +456,7 @@ bus_dmamap_sync(t, map, offset, len, op)
 			if (sublen > len)
 				sublen = len;
 
-			if (dma_cachectl_pa(addr, sublen, op) != 0)
-				break;
+			dma_cachectl_pa(addr, sublen, op);
 
 			offset = 0;
 			len -= sublen;
diff --git a/sys/arch/mvme88k/mvme88k/m88110.c b/sys/arch/mvme88k/mvme88k/m88110.c
index 19ee8bfbcd9..cd41cb49e7d 100644
--- a/sys/arch/mvme88k/mvme88k/m88110.c
+++ b/sys/arch/mvme88k/mvme88k/m88110.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: m88110.c,v 1.37 2006/05/08 14:36:10 miod Exp $	*/
+/*	$OpenBSD: m88110.c,v 1.38 2007/02/11 12:49:38 miod Exp $	*/
 /*
  * Copyright (c) 1998 Steve Murphree, Jr.
  * All rights reserved.
@@ -82,9 +82,9 @@ void	m88110_set_uapr(apr_t);
 void	m88110_flush_tlb(cpuid_t, unsigned, vaddr_t, u_int);
 void	m88110_flush_cache(cpuid_t, paddr_t, psize_t);
 void	m88110_flush_inst_cache(cpuid_t, paddr_t, psize_t);
-void	m88110_flush_data_cache(cpuid_t, paddr_t, psize_t);
-int	m88110_dma_cachectl(pmap_t, vaddr_t, vsize_t, int);
-int	m88110_dma_cachectl_pa(paddr_t, psize_t, int);
+void	m88110_flush_data_page(cpuid_t, paddr_t);
+void	m88110_dma_cachectl(pmap_t, vaddr_t, vsize_t, int);
+void	m88110_dma_cachectl_pa(paddr_t, psize_t, int);
 void	m88110_initialize_cpu(cpuid_t);
 
 /* This is the function table for the MC88110 built-in CMMUs */
@@ -99,7 +99,7 @@ struct cmmu_p cmmu88110 = {
 	m88110_flush_tlb,
 	m88110_flush_cache,
 	m88110_flush_inst_cache,
-	m88110_flush_data_cache,
+	m88110_flush_data_page,
 	m88110_dma_cachectl,
 	m88110_dma_cachectl_pa,
 #ifdef MULTIPROCESSOR
@@ -346,7 +346,7 @@ m88110_flush_tlb(cpuid_t cpu, unsigned kernel, vaddr_t vaddr, u_int count)
  *	flush both Instruction and Data caches
  */
 void
-m88110_flush_cache(cpuid_t cpu, paddr_t physaddr, psize_t size)
+m88110_flush_cache(cpuid_t cpu, paddr_t pa, psize_t size)
 {
 	u_int32_t psr;
 
@@ -363,7 +363,7 @@ m88110_flush_cache(cpuid_t cpu, paddr_t physaddr, psize_t size)
  *	flush Instruction caches
  */
 void
-m88110_flush_inst_cache(cpuid_t cpu, paddr_t physaddr, psize_t size)
+m88110_flush_inst_cache(cpuid_t cpu, paddr_t pa, psize_t size)
 {
 	u_int32_t psr;
 
@@ -377,7 +377,7 @@ m88110_flush_inst_cache(cpuid_t cpu, paddr_t physaddr, psize_t size)
  * flush data cache
  */
 void
-m88110_flush_data_cache(cpuid_t cpu, paddr_t physaddr, psize_t size)
+m88110_flush_data_page(cpuid_t cpu, paddr_t pa)
 {
 	u_int32_t psr;
 
@@ -393,7 +393,7 @@ m88110_flush_data_cache(cpuid_t cpu, paddr_t physaddr, psize_t size)
  * sync dcache (and icache too)
  */
 void
-m88110_cmmu_sync_cache(paddr_t physaddr, psize_t size)
+m88110_cmmu_sync_cache(paddr_t pa, psize_t size)
 {
 	u_int32_t psr;
 
@@ -407,7 +407,7 @@ m88110_cmmu_sync_cache(paddr_t physaddr, psize_t size)
 }
 
 void
-m88110_cmmu_sync_inval_cache(paddr_t physaddr, psize_t size)
+m88110_cmmu_sync_inval_cache(paddr_t pa, psize_t size)
 {
 	u_int32_t psr;
 
@@ -420,7 +420,7 @@ m88110_cmmu_sync_inval_cache(paddr_t physaddr, psize_t size)
 }
 
 void
-m88110_cmmu_inval_cache(paddr_t physaddr, psize_t size)
+m88110_cmmu_inval_cache(paddr_t pa, psize_t size)
 {
 	u_int32_t psr;
 
@@ -433,7 +433,7 @@ m88110_cmmu_inval_cache(paddr_t physaddr, psize_t size)
 	set_psr(psr);
 }
 
-int
+void
 m88110_dma_cachectl(pmap_t pmap, vaddr_t va, vsize_t size, int op)
 {
 	paddr_t pa;
@@ -457,10 +457,9 @@ m88110_dma_cachectl(pmap_t pmap, vaddr_t va, vsize_t size, int op)
 		m88110_cmmu_inval_cache(pa, size);
 		break;
 	}
-	return (1);
 }
 
-int
+void
 m88110_dma_cachectl_pa(paddr_t pa, psize_t size, int op)
 {
 	switch (op) {
@@ -474,5 +473,4 @@ m88110_dma_cachectl_pa(paddr_t pa, psize_t size, int op)
 		m88110_cmmu_inval_cache(pa, size);
 		break;
 	}
-	return (1);
 }