sbus pcmcia bridge driver (nell); from NetBSD.

2 files changed, 1348 insertions, 0 deletions

diff --git a/sys/dev/sbus/stp4020.c b/sys/dev/sbus/stp4020.c
new file mode 100644
index 00000000000..93e979b0722
--- /dev/null
+++ b/sys/dev/sbus/stp4020.c
@@ -0,0 +1,1014 @@
+/*	$OpenBSD: stp4020.c,v 1.1 2002/06/19 19:14:21 fgsch Exp $	*/
+/*	$NetBSD: stp4020.c,v 1.23 2002/06/01 23:51:03 lukem Exp $ */
+
+/*-
+ * Copyright (c) 1998 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Paul Kranenburg.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *        This product includes software developed by the NetBSD
+ *        Foundation, Inc. and its contributors.
+ * 4. Neither the name of The NetBSD Foundation nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * STP4020: SBus/PCMCIA bridge supporting two Type-3 PCMCIA cards.
+ */
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/errno.h>
+#include <sys/malloc.h>
+#include <sys/extent.h>
+#include <sys/proc.h>
+#include <sys/kernel.h>
+#include <sys/kthread.h>
+#include <sys/device.h>
+
+#include <dev/pcmcia/pcmciareg.h>
+#include <dev/pcmcia/pcmciavar.h>
+#include <dev/pcmcia/pcmciachip.h>
+
+#include <machine/bus.h>
+#include <machine/intr.h>
+
+#include <dev/sbus/sbusvar.h>
+#include <dev/sbus/stp4020reg.h>
+
+/*
+ * We use the three available windows per socket in a simple, fixed
+ * arrangement. Each window maps (at full 1 MB size) one of the pcmcia
+ * spaces into sbus space.
+ */
+#define STP_WIN_ATTR	0	/* index of the attribute memory space window */
+#define	STP_WIN_MEM	1	/* index of the common memory space window */
+#define	STP_WIN_IO	2	/* index of the io space window */
+
+
+#if defined(STP4020_DEBUG)
+int stp4020_debug = 0;
+#define DPRINTF(x)	do { if (stp4020_debug) printf x; } while(0)
+#else
+#define DPRINTF(x)
+#endif
+
+/*
+ * Event queue; events detected in an interrupt context go here
+ * awaiting attention from our event handling thread.
+ */
+struct stp4020_event {
+	SIMPLEQ_ENTRY(stp4020_event) se_q;
+	int	se_type;
+	int	se_sock;
+};
+
+/* Defined event types */
+#define STP4020_EVENT_INSERTION	0
+#define STP4020_EVENT_REMOVAL	1
+
+/*
+ * Per socket data.
+ */
+struct stp4020_socket {
+	struct stp4020_softc	*sc;	/* Back link */
+	int		flags;
+#define STP4020_SOCKET_BUSY	0x0001
+#define STP4020_SOCKET_SHUTDOWN	0x0002
+	int		sock;		/* Socket number (0 or 1) */
+	bus_space_tag_t	tag;		/* socket control space */
+	bus_space_handle_t	regs;	/* 			*/
+	struct device	*pcmcia;	/* Associated PCMCIA device */
+	int		(*intrhandler)	/* Card driver interrupt handler */
+			    (void *);
+	void		*intrarg;	/* Card interrupt handler argument */
+	int		ipl;		/* Interrupt level suggested by card */
+	struct {
+		bus_space_handle_t	winaddr;/* this window's address */
+	} windows[STP4020_NWIN];
+
+};
+
+struct stp4020_softc {
+	struct device	sc_dev;		/* Base device */
+	struct sbusdev	sc_sd;		/* SBus device */
+	bus_space_tag_t	sc_bustag;
+	bus_dma_tag_t	sc_dmatag;
+	pcmcia_chipset_tag_t	sc_pct;	/* Chipset methods */
+
+	struct proc	*event_thread;		/* event handling thread */
+	SIMPLEQ_HEAD(, stp4020_event)	events;	/* Pending events for thread */
+
+	struct stp4020_socket sc_socks[STP4020_NSOCK];
+};
+
+
+int	stp4020print(void *, const char *);
+int	stp4020match(struct device *, void *, void *);
+void	stp4020attach(struct device *, struct device *, void *);
+int	stp4020_iointr(void *);
+int	stp4020_statintr(void *);
+void	stp4020_map_window(struct stp4020_socket *, int, int);
+void	stp4020_calc_speed(int, int, int *, int *);
+
+struct cfattach nell_ca = {
+	sizeof(struct stp4020_softc), stp4020match, stp4020attach
+};
+
+struct cfdriver nell_cd = {
+	NULL, "nell", DV_DULL
+};
+
+#ifdef STP4020_DEBUG
+static void	stp4020_dump_regs(struct stp4020_socket *);
+#endif
+
+static int	stp4020_rd_sockctl(struct stp4020_socket *, int);
+static void	stp4020_wr_sockctl(struct stp4020_socket *, int, int);
+static int	stp4020_rd_winctl(struct stp4020_socket *, int, int);
+static void	stp4020_wr_winctl(struct stp4020_socket *, int, int, int);
+
+void	stp4020_delay(unsigned int);
+void	stp4020_attach_socket(struct stp4020_socket *, int);
+void	stp4020_create_event_thread(void *);
+void	stp4020_event_thread(void *);
+void	stp4020_queue_event(struct stp4020_softc *, int, int);
+
+int	stp4020_chip_mem_alloc(pcmcia_chipset_handle_t, bus_size_t,
+	    struct pcmcia_mem_handle *);
+void	stp4020_chip_mem_free(pcmcia_chipset_handle_t,
+	    struct pcmcia_mem_handle *);
+int	stp4020_chip_mem_map(pcmcia_chipset_handle_t, int, bus_addr_t,
+	    bus_size_t, struct pcmcia_mem_handle *, bus_addr_t *, int *);
+void	stp4020_chip_mem_unmap(pcmcia_chipset_handle_t, int);
+
+int	stp4020_chip_io_alloc(pcmcia_chipset_handle_t,
+	    bus_addr_t, bus_size_t, bus_size_t, struct pcmcia_io_handle *);
+void	stp4020_chip_io_free(pcmcia_chipset_handle_t,
+	    struct pcmcia_io_handle *);
+int	stp4020_chip_io_map(pcmcia_chipset_handle_t, int, bus_addr_t,
+	    bus_size_t, struct pcmcia_io_handle *, int *);
+void	stp4020_chip_io_unmap(pcmcia_chipset_handle_t, int);
+
+void	stp4020_chip_socket_enable(pcmcia_chipset_handle_t);
+void	stp4020_chip_socket_disable(pcmcia_chipset_handle_t);
+void	*stp4020_chip_intr_establish(pcmcia_chipset_handle_t,
+	    struct pcmcia_function *, int, int (*) (void *), void *, char *);
+void	stp4020_chip_intr_disestablish(pcmcia_chipset_handle_t, void *);
+
+/* Our PCMCIA chipset methods */
+static struct pcmcia_chip_functions stp4020_functions = {
+	stp4020_chip_mem_alloc,
+	stp4020_chip_mem_free,
+	stp4020_chip_mem_map,
+	stp4020_chip_mem_unmap,
+
+	stp4020_chip_io_alloc,
+	stp4020_chip_io_free,
+	stp4020_chip_io_map,
+	stp4020_chip_io_unmap,
+
+	stp4020_chip_intr_establish,
+	stp4020_chip_intr_disestablish,
+
+	stp4020_chip_socket_enable,
+	stp4020_chip_socket_disable
+};
+
+
+static __inline__ int
+stp4020_rd_sockctl(h, idx)
+	struct stp4020_socket *h;
+	int idx;
+{
+	int o = ((STP4020_SOCKREGS_SIZE * (h->sock)) + idx);
+	return (bus_space_read_2(h->tag, h->regs, o));
+}
+
+static __inline__ void
+stp4020_wr_sockctl(h, idx, v)
+	struct stp4020_socket *h;
+	int idx;
+	int v;
+{
+	int o = (STP4020_SOCKREGS_SIZE * (h->sock)) + idx;
+	bus_space_write_2(h->tag, h->regs, o, v);
+}
+
+static __inline__ int
+stp4020_rd_winctl(h, win, idx)
+	struct stp4020_socket *h;
+	int win;
+	int idx;
+{
+	int o = (STP4020_SOCKREGS_SIZE * (h->sock)) +
+	    (STP4020_WINREGS_SIZE * win) + idx;
+	return (bus_space_read_2(h->tag, h->regs, o));
+}
+
+static __inline__ void
+stp4020_wr_winctl(h, win, idx, v)
+	struct stp4020_socket *h;
+	int win;
+	int idx;
+	int v;
+{
+	int o = (STP4020_SOCKREGS_SIZE * (h->sock)) +
+	    (STP4020_WINREGS_SIZE * win) + idx;
+	bus_space_write_2(h->tag, h->regs, o, v);
+}
+
+
+int
+stp4020print(aux, busname)
+	void *aux;
+	const char *busname;
+{
+	struct pcmciabus_attach_args *paa = aux;
+	struct stp4020_socket *h = paa->pch;
+
+	printf(" socket %d", h->sock);
+	return (UNCONF);
+}
+
+int
+stp4020match(parent, match, aux)
+	struct device *parent;
+	void *match;
+	void *aux;
+{
+	struct sbus_attach_args *sa = aux;
+
+	return (strcmp("SUNW,pcmcia", sa->sa_name) == 0);
+}
+
+/*
+ * Attach all the sub-devices we can find
+ */
+void
+stp4020attach(parent, self, aux)
+	struct device *parent, *self;
+	void *aux;
+{
+	struct sbus_attach_args *sa = aux;
+	struct stp4020_softc *sc = (void *)self;
+	int node, rev;
+	int i;
+	bus_space_handle_t bh;
+
+	node = sa->sa_node;
+
+	/* Transfer bus tags */
+	sc->sc_bustag = sa->sa_bustag;
+	sc->sc_dmatag = sa->sa_dmatag;
+
+	/* Set up per-socket static initialization */
+	sc->sc_socks[0].sc = sc->sc_socks[1].sc = sc;
+	sc->sc_socks[0].tag = sc->sc_socks[1].tag = sa->sa_bustag;
+
+	if (sa->sa_nreg < 8) {
+		printf(": only %d register sets\n", sa->sa_nreg);
+		return;
+	}
+
+	if (sa->sa_nintr != 2) {
+		printf(": expect 2 interrupt Sbus levels; got %d\n",
+		    sa->sa_nintr);
+		return;
+	}
+
+#define STP4020_BANK_PROM	0
+#define STP4020_BANK_CTRL	4
+	for (i = 0; i < 8; i++) {
+
+		/*
+		 * STP4020 Register address map:
+		 *	bank  0:   Forth PROM
+		 *	banks 1-3: socket 0, windows 0-2
+		 *	bank  4:   control registers
+		 *	banks 5-7: socket 1, windows 0-2
+		 */
+
+		if (i == STP4020_BANK_PROM)
+			/* Skip the PROM */
+			continue;
+
+		if (sbus_bus_map(sa->sa_bustag, sa->sa_reg[i].sbr_slot,
+		    sa->sa_reg[i].sbr_offset, sa->sa_reg[i].sbr_size,
+		    BUS_SPACE_MAP_LINEAR, 0, &bh) != 0) {
+			printf(": attach: cannot map registers\n");
+			return;
+		}
+
+		if (i == STP4020_BANK_CTRL) {
+			/*
+			 * Copy tag and handle to both socket structures
+			 * for easy access in control/status IO functions.
+			 */
+			sc->sc_socks[0].regs = sc->sc_socks[1].regs = bh;
+		} else if (i < STP4020_BANK_CTRL) {
+			/* banks 1-3 */
+			sc->sc_socks[0].windows[i-1].winaddr = bh;
+		} else {
+			/* banks 5-7 */
+			sc->sc_socks[1].windows[i-5].winaddr = bh;
+		}
+	}
+
+	sbus_establish(&sc->sc_sd, &sc->sc_dev);
+
+	/*
+	 * We get to use two SBus interrupt levels.
+	 * The higher level we use for status change interrupts;
+	 * the lower level for PC card I/O.
+	 */
+	if (sa->sa_nintr != 0) {
+		bus_intr_establish(sa->sa_bustag, sa->sa_intr[1].sbi_pri,
+		    IPL_NONE, 0, stp4020_statintr, sc);
+
+		bus_intr_establish(sa->sa_bustag, sa->sa_intr[0].sbi_pri,
+		    IPL_NONE, 0, stp4020_iointr, sc);
+	}
+
+	rev = stp4020_rd_sockctl(&sc->sc_socks[0], STP4020_ISR1_IDX) &
+	    STP4020_ISR1_REV_M;
+	printf(": rev %x\n", rev);
+
+	sc->sc_pct = (pcmcia_chipset_tag_t)&stp4020_functions;
+
+	/*
+	 * Arrange that a kernel thread be created to handle
+	 * insert/removal events.
+	 */
+	SIMPLEQ_INIT(&sc->events);
+	kthread_create_deferred(stp4020_create_event_thread, sc);
+
+	for (i = 0; i < STP4020_NSOCK; i++) {
+		struct stp4020_socket *h = &sc->sc_socks[i];
+		h->sock = i;
+		h->sc = sc;
+#ifdef STP4020_DEBUG
+		if (stp4020_debug)
+			stp4020_dump_regs(h);
+#endif
+		stp4020_attach_socket(h, sa->sa_frequency);
+	}
+}
+
+void
+stp4020_attach_socket(h, speed)
+	struct stp4020_socket *h;
+	int speed;
+{
+	struct pcmciabus_attach_args paa;
+	int v;
+
+	/* Map all three windows */
+	stp4020_map_window(h, STP_WIN_ATTR, speed);
+	stp4020_map_window(h, STP_WIN_MEM, speed);
+	stp4020_map_window(h, STP_WIN_IO, speed);
+
+	/* Configure one pcmcia device per socket */
+	paa.paa_busname = "pcmcia";
+	paa.pct = (pcmcia_chipset_tag_t)h->sc->sc_pct;
+	paa.pch = (pcmcia_chipset_handle_t)h;
+	paa.iobase = 0;
+	paa.iosize = STP4020_WINDOW_SIZE;
+
+	h->pcmcia = config_found(&h->sc->sc_dev, &paa, stp4020print);
+
+	if (h->pcmcia == NULL)
+		return;
+
+	/*
+	 * There's actually a pcmcia bus attached; initialize the slot.
+	 */
+
+	/*
+	 * Clear things up before we enable status change interrupts.
+	 * This seems to not be fully initialized by the PROM.
+	 */
+	stp4020_wr_sockctl(h, STP4020_ICR1_IDX, 0);
+	stp4020_wr_sockctl(h, STP4020_ICR0_IDX, 0);
+	stp4020_wr_sockctl(h, STP4020_ISR1_IDX, 0x3fff);
+	stp4020_wr_sockctl(h, STP4020_ISR0_IDX, 0x3fff);
+
+	/*
+	 * Enable socket status change interrupts.
+	 * We use SB_INT[1] for status change interrupts.
+	 */
+	v = STP4020_ICR0_ALL_STATUS_IE | STP4020_ICR0_SCILVL_SB1;
+	stp4020_wr_sockctl(h, STP4020_ICR0_IDX, v);
+
+	/* Get live status bits from ISR0 */
+	v = stp4020_rd_sockctl(h, STP4020_ISR0_IDX);
+	if ((v & (STP4020_ISR0_CD1ST | STP4020_ISR0_CD2ST)) == 0)
+		return;
+
+	pcmcia_card_attach(h->pcmcia);
+	h->flags |= STP4020_SOCKET_BUSY;
+}
+
+
+/*
+ * Deferred thread creation callback.
+ */
+void
+stp4020_create_event_thread(arg)
+	void *arg;
+{
+	struct stp4020_softc *sc = arg;
+	const char *name = sc->sc_dev.dv_xname;
+
+	if (kthread_create(stp4020_event_thread, sc, &sc->event_thread,
+	    "%s", name)) {
+		panic("%s: unable to create event thread", name);
+	}
+}
+
+/*
+ * The actual event handling thread.
+ */
+void
+stp4020_event_thread(arg)
+	void *arg;
+{
+	struct stp4020_softc *sc = arg;
+	struct stp4020_event *e;
+	int s;
+
+	while (1) {
+		struct stp4020_socket *h;
+		int n;
+
+		s = splhigh();
+		if ((e = SIMPLEQ_FIRST(&sc->events)) == NULL) {
+			splx(s);
+			(void)tsleep(&sc->events, PWAIT, "pcicev", 0);
+			continue;
+		}
+		SIMPLEQ_REMOVE_HEAD(&sc->events, e, se_q);
+		splx(s);
+
+		n = e->se_sock;
+		if (n < 0 || n >= STP4020_NSOCK)
+			panic("stp4020_event_thread: wayward socket number %d",
+			    n);
+
+		h = &sc->sc_socks[n];
+		switch (e->se_type) {
+		case STP4020_EVENT_INSERTION:
+			pcmcia_card_attach(h->pcmcia);
+			break;
+		case STP4020_EVENT_REMOVAL:
+			pcmcia_card_detach(h->pcmcia, DETACH_FORCE);
+			break;
+		default:
+			panic("stp4020_event_thread: unknown event type %d",
+			    e->se_type);
+		}
+		free(e, M_TEMP);
+	}
+}
+
+void
+stp4020_queue_event(sc, sock, event)
+	struct stp4020_softc *sc;
+	int sock, event;
+{
+	struct stp4020_event *e;
+	int s;
+
+	e = malloc(sizeof(*e), M_TEMP, M_NOWAIT);
+	if (e == NULL)
+		panic("stp4020_queue_event: can't allocate event");
+
+	e->se_type = event;
+	e->se_sock = sock;
+	s = splhigh();
+	SIMPLEQ_INSERT_TAIL(&sc->events, e, se_q);
+	splx(s);
+	wakeup(&sc->events);
+}
+
+int
+stp4020_statintr(arg)
+	void *arg;
+{
+	struct stp4020_softc *sc = arg;
+	int i, r = 0;
+
+	/*
+	 * Check each socket for pending requests.
+	 */
+	for (i = 0 ; i < STP4020_NSOCK; i++) {
+		struct stp4020_socket *h;
+		int v, cd_change = 0;
+
+		h = &sc->sc_socks[i];
+
+		/* Read socket's ISR0 for the interrupt status bits */
+		v = stp4020_rd_sockctl(h, STP4020_ISR0_IDX);
+
+#ifdef STP4020_DEBUG
+		if (stp4020_debug != 0) {
+			char bits[64];
+			bitmask_snprintf(v, STP4020_ISR0_IOBITS,
+			    bits, sizeof(bits));
+			printf("stp4020_statintr: ISR0=%s\n", bits);
+		}
+#endif
+
+		/* Ack all interrupts at once */
+		stp4020_wr_sockctl(h, STP4020_ISR0_IDX,
+		    STP4020_ISR0_ALL_STATUS_IRQ);
+
+		if ((v & STP4020_ISR0_CDCHG) != 0) {
+			/*
+			 * Card status change detect
+			 */
+			cd_change = 1;
+			r = 1;
+			if ((v & (STP4020_ISR0_CD1ST|STP4020_ISR0_CD2ST)) ==
+			    (STP4020_ISR0_CD1ST|STP4020_ISR0_CD2ST)) {
+				if ((h->flags & STP4020_SOCKET_BUSY) == 0) {
+					stp4020_queue_event(sc, i,
+					    STP4020_EVENT_INSERTION);
+					h->flags |= STP4020_SOCKET_BUSY;
+				}
+			}
+			if ((v & (STP4020_ISR0_CD1ST|STP4020_ISR0_CD2ST)) ==
+			    0) {
+				if ((h->flags & STP4020_SOCKET_BUSY) != 0) {
+					stp4020_queue_event(sc, i,
+					    STP4020_EVENT_REMOVAL);
+					h->flags &= ~STP4020_SOCKET_BUSY;
+				}
+			}
+		}
+
+		/* informational messages */
+		if ((v & STP4020_ISR0_BVD1CHG) != 0) {
+			/* ignore if this is caused by insert or removal */
+			if (!cd_change)
+				printf("stp4020[%d]: Battery change 1\n",
+				    h->sock);
+			r = 1;
+		}
+
+		if ((v & STP4020_ISR0_BVD2CHG) != 0) {
+			/* ignore if this is caused by insert or removal */
+			if (!cd_change)
+				printf("stp4020[%d]: Battery change 2\n",
+				    h->sock);
+			r = 1;
+		}
+
+		if ((v & STP4020_ISR0_RDYCHG) != 0) {
+			DPRINTF(("stp4020[%d]: Ready/Busy change\n",
+			    h->sock));
+			r = 1;
+		}
+
+		if ((v & STP4020_ISR0_WPCHG) != 0) {
+			DPRINTF(("stp4020[%d]: Write protect change\n",
+			    h->sock));
+			r = 1;
+		}
+
+		if ((v & STP4020_ISR0_PCTO) != 0) {
+			DPRINTF(("stp4020[%d]: Card access timeout\n",
+			    h->sock));
+			r = 1;
+		}
+	}
+
+	return (r);
+}
+
+int
+stp4020_iointr(arg)
+	void *arg;
+{
+	struct stp4020_softc *sc = arg;
+	int i, r = 0;
+
+	/*
+	 * Check each socket for pending requests.
+	 */
+	for (i = 0 ; i < STP4020_NSOCK; i++) {
+		struct stp4020_socket *h;
+		int v;
+
+		h = &sc->sc_socks[i];
+		v = stp4020_rd_sockctl(h, STP4020_ISR0_IDX);
+
+		if ((v & STP4020_ISR0_IOINT) != 0) {
+			/* we can not deny this is ours, no matter what the
+			   card driver says. */
+			r = 1;
+
+			/* ack interrupt */
+			stp4020_wr_sockctl(h, STP4020_ISR0_IDX, v);
+
+			/* It's a card interrupt */
+			if ((h->flags & STP4020_SOCKET_BUSY) == 0) {
+				printf("stp4020[%d]: spurious interrupt?\n",
+				    h->sock);
+				continue;
+			}
+			/* Call card handler, if any */
+			if (h->intrhandler != NULL) {
+				/*
+				 * Called without handling of it's requested
+				 * protection level (h->ipl), since we have
+				 * no general queuing mechanism available
+				 * right now and we know for sure we are
+				 * running at a higher protection level
+				 * right now.
+				 */
+				(*h->intrhandler)(h->intrarg);
+			}
+		}
+	}
+
+	return (r);
+}
+
+/*
+ * The function gets the sbus speed and a access time and calculates
+ * values for the CMDLNG and CMDDLAY registers.
+ */
+void
+stp4020_calc_speed(int bus_speed, int ns, int *length, int *delay)
+{
+	int result;
+
+	if (ns < STP4020_MEM_SPEED_MIN)
+		ns = STP4020_MEM_SPEED_MIN;
+	else if (ns > STP4020_MEM_SPEED_MAX)
+		ns = STP4020_MEM_SPEED_MAX;
+	result = ns * (bus_speed / 1000);
+	if (result % 1000000)
+		result = result / 1000000 + 1;
+	else
+		result /= 1000000;
+	*length = result;
+
+	/* the sbus frequency range is limited, so we can keep this simple */
+	*delay = ns <= STP4020_MEM_SPEED_MIN ? 1 : 2;
+}
+
+void
+stp4020_map_window(struct stp4020_socket *h, int win, int speed)
+{
+	int v, length, delay;
+
+	/*
+	 * According to the PC Card standard 300ns access timing should be
+	 * used for attribute memory access. Our pcmcia framework does not
+	 * seem to propagate timing information, so we use that
+	 * everywhere.
+	 */
+	stp4020_calc_speed(speed, 300, &length, &delay);
+
+	/*
+	 * Fill in the Address Space Select and Base Address
+	 * fields of this windows control register 0.
+	 */
+	v = ((delay << STP4020_WCR0_CMDDLY_S)&STP4020_WCR0_CMDDLY_M) |
+	    ((length << STP4020_WCR0_CMDLNG_S)&STP4020_WCR0_CMDLNG_M);
+	switch (win) {
+	case STP_WIN_ATTR:
+		v |= STP4020_WCR0_ASPSEL_AM;
+		break;
+	case STP_WIN_MEM:
+		v |= STP4020_WCR0_ASPSEL_CM;
+		break;
+	case STP_WIN_IO:
+		v |= STP4020_WCR0_ASPSEL_IO;
+		break;
+	}
+	v |= (STP4020_ADDR2PAGE(0) & STP4020_WCR0_BASE_M);
+	stp4020_wr_winctl(h, win, STP4020_WCR0_IDX, v);
+	stp4020_wr_winctl(h, win, STP4020_WCR1_IDX,
+	    1 << STP4020_WCR1_WAITREQ_S);
+}
+
+int
+stp4020_chip_mem_alloc(pch, size, pcmhp)
+	pcmcia_chipset_handle_t pch;
+	bus_size_t size;
+	struct pcmcia_mem_handle *pcmhp;
+{
+	struct stp4020_socket *h = (struct stp4020_socket *)pch;
+
+	/* we can not do much here, defere work to _mem_map */
+	pcmhp->memt = h->tag;
+	pcmhp->size = size;
+	pcmhp->addr = 0;
+	pcmhp->mhandle = 0;
+	pcmhp->realsize = size;
+
+	return (0);
+}
+
+void
+stp4020_chip_mem_free(pch, pcmhp)
+	pcmcia_chipset_handle_t pch;
+	struct pcmcia_mem_handle *pcmhp;
+{
+}
+
+int
+stp4020_chip_mem_map(pch, kind, card_addr, size, pcmhp, offsetp, windowp)
+	pcmcia_chipset_handle_t pch;
+	int kind;
+	bus_addr_t card_addr;
+	bus_size_t size;
+	struct pcmcia_mem_handle *pcmhp;
+	bus_addr_t *offsetp;
+	int *windowp;
+{
+	struct stp4020_socket *h = (struct stp4020_socket *)pch;
+	int win = (kind & PCMCIA_MEM_ATTR) ? STP_WIN_ATTR : STP_WIN_MEM;
+
+	pcmhp->memt = h->tag;
+	bus_space_subregion(h->tag, h->windows[win].winaddr,
+	    card_addr, size, &pcmhp->memh);
+	pcmhp->size = size;
+	pcmhp->realsize = STP4020_WINDOW_SIZE - card_addr;
+	*offsetp = 0;
+	*windowp = 0;
+
+	return (0);
+}
+
+void
+stp4020_chip_mem_unmap(pch, win)
+	pcmcia_chipset_handle_t pch;
+	int win;
+{
+}
+
+int
+stp4020_chip_io_alloc(pch, start, size, align, pcihp)
+	pcmcia_chipset_handle_t pch;
+	bus_addr_t start;
+	bus_size_t size;
+	bus_size_t align;
+	struct pcmcia_io_handle *pcihp;
+{
+	struct stp4020_socket *h = (struct stp4020_socket *)pch;
+
+	pcihp->iot = h->tag;
+	pcihp->ioh = h->windows[STP_WIN_IO].winaddr;
+	return (0);
+}
+
+void
+stp4020_chip_io_free(pch, pcihp)
+	pcmcia_chipset_handle_t pch;
+	struct pcmcia_io_handle *pcihp;
+{
+}
+
+int
+stp4020_chip_io_map(pch, width, offset, size, pcihp, windowp)
+	pcmcia_chipset_handle_t pch;
+	int width;
+	bus_addr_t offset;
+	bus_size_t size;
+	struct pcmcia_io_handle *pcihp;
+	int *windowp;
+{
+	struct stp4020_socket *h = (struct stp4020_socket *)pch;
+
+	pcihp->iot = h->tag;
+	bus_space_subregion(h->tag, h->windows[STP_WIN_IO].winaddr,
+	    offset, size, &pcihp->ioh);
+	*windowp = 0;
+	return (0);
+}
+
+void
+stp4020_chip_io_unmap(pch, win)
+	pcmcia_chipset_handle_t pch;
+	int win;
+{
+}
+
+void
+stp4020_chip_socket_enable(pch)
+	pcmcia_chipset_handle_t pch;
+{
+	struct stp4020_socket *h = (struct stp4020_socket *)pch;
+	int i, v;
+
+	/* this bit is mostly stolen from pcic_attach_card */
+
+	/* Power down the socket to reset it, clear the card reset pin */
+	stp4020_wr_sockctl(h, STP4020_ICR1_IDX, 0);
+
+	/*
+	 * wait 300ms until power fails (Tpf).  Then, wait 100ms since
+	 * we are changing Vcc (Toff).
+	 */
+	stp4020_delay((300 + 100) * 1000);
+
+	/* Power up the socket */
+	v = STP4020_ICR1_MSTPWR;
+	stp4020_wr_sockctl(h, STP4020_ICR1_IDX, v);
+
+	/*
+	 * wait 100ms until power raise (Tpr) and 20ms to become
+	 * stable (Tsu(Vcc)).
+	 */
+	stp4020_delay((100 + 20) * 1000);
+
+	v |= STP4020_ICR1_PCIFOE|STP4020_ICR1_VPP1_VCC;
+	stp4020_wr_sockctl(h, STP4020_ICR1_IDX, v);
+
+	/*
+	 * hold RESET at least 10us.
+	 */
+	delay(10);
+
+	/* Clear reset flag */
+	v = stp4020_rd_sockctl(h, STP4020_ICR0_IDX);
+	v &= ~STP4020_ICR0_RESET;
+	stp4020_wr_sockctl(h, STP4020_ICR0_IDX, v);
+
+	/* wait 20ms as per pc card standard (r2.01) section 4.3.6 */
+	stp4020_delay(20000);
+
+	/* Wait for the chip to finish initializing (5 seconds max) */
+	for (i = 10000; i > 0; i--) {
+		v = stp4020_rd_sockctl(h, STP4020_ISR0_IDX);
+		if ((v & STP4020_ISR0_RDYST) != 0)
+			break;
+		delay(500);
+	}
+	if (i <= 0) {
+#if STP4020_DEBUG
+		char bits[64];
+		bitmask_snprintf(stp4020_rd_sockctl(h, STP4020_ISR0_IDX),
+		    STP4020_ISR0_IOBITS, bits, sizeof(bits));
+		printf("stp4020_chip_socket_enable: not ready: status %s\n",
+		    bits);
+#endif
+		return;
+	}
+
+	v = stp4020_rd_sockctl(h, STP4020_ICR0_IDX);
+
+	/*
+	 * Check the card type.
+	 * Enable socket I/O interrupts for IO cards.
+	 * We use level SB_INT[0] for I/O interrupts.
+	 */
+	if (pcmcia_card_gettype(h->pcmcia) == PCMCIA_IFTYPE_IO) {
+		v &= ~(STP4020_ICR0_IOILVL | STP4020_ICR0_IFTYPE);
+		v |= STP4020_ICR0_IFTYPE_IO | STP4020_ICR0_IOIE |
+		    STP4020_ICR0_IOILVL_SB0 | STP4020_ICR0_SPKREN;
+		DPRINTF(("%s: configuring card for IO usage\n",
+		    h->sc->sc_dev.dv_xname));
+	} else {
+		v &= ~(STP4020_ICR0_IOILVL | STP4020_ICR0_IFTYPE |
+		    STP4020_ICR0_SPKREN | STP4020_ICR0_IOILVL_SB0 |
+		    STP4020_ICR0_IOILVL_SB1 | STP4020_ICR0_SPKREN);
+		v |= STP4020_ICR0_IFTYPE_MEM;
+		DPRINTF(("%s: configuring card for MEM ONLY usage\n",
+		    h->sc->sc_dev.dv_xname));
+	}
+	stp4020_wr_sockctl(h, STP4020_ICR0_IDX, v);
+}
+
+void
+stp4020_chip_socket_disable(pch)
+	pcmcia_chipset_handle_t pch;
+{
+	struct stp4020_socket *h = (struct stp4020_socket *)pch;
+	int v;
+
+	/*
+	 * Disable socket I/O interrupts.
+	 */
+	v = stp4020_rd_sockctl(h, STP4020_ICR0_IDX);
+	v &= ~(STP4020_ICR0_IOIE | STP4020_ICR0_IOILVL);
+	stp4020_wr_sockctl(h, STP4020_ICR0_IDX, v);
+
+	/* Power down the socket */
+	stp4020_wr_sockctl(h, STP4020_ICR1_IDX, 0);
+
+	/*
+	 * wait 300ms until power fails (Tpf).
+	 */
+	stp4020_delay(300 * 1000);
+}
+
+void *
+stp4020_chip_intr_establish(pch, pf, ipl, handler, arg, xname)
+	pcmcia_chipset_handle_t pch;
+	struct pcmcia_function *pf;
+	int ipl;
+	int (*handler) (void *);
+	void *arg;
+	char *xname;
+{
+	struct stp4020_socket *h = (struct stp4020_socket *)pch;
+
+	h->intrhandler = handler;
+	h->intrarg = arg;
+	h->ipl = ipl;
+	return (h);
+}
+
+void
+stp4020_chip_intr_disestablish(pch, ih)
+	pcmcia_chipset_handle_t pch;
+	void *ih;
+{
+	struct stp4020_socket *h = (struct stp4020_socket *)pch;
+
+	h->intrhandler = NULL;
+	h->intrarg = NULL;
+}
+
+/*
+ * Delay and possibly yield CPU.
+ * XXX - assumes a context
+ */
+void
+stp4020_delay(ms)
+	unsigned int ms;
+{
+	unsigned int ticks;
+
+	/* Convert to ticks */
+	ticks = (ms * hz ) / 1000000;
+
+	if (cold || ticks == 0) {
+		delay(ms);
+		return;
+	}
+
+#ifdef DIAGNOSTIC
+	if (ticks > 60 * hz)
+		panic("stp4020: preposterous delay: %u", ticks);
+#endif
+	tsleep(&ticks, 0, "stp4020_delay", ticks);
+}
+
+#ifdef STP4020_DEBUG
+void
+stp4020_dump_regs(h)
+	struct stp4020_socket *h;
+{
+	char bits[64];
+	/*
+	 * Dump control and status registers.
+	 */
+	printf("socket[%d] registers:\n", h->sock);
+	bitmask_snprintf(stp4020_rd_sockctl(h, STP4020_ICR0_IDX),
+	    STP4020_ICR0_BITS, bits, sizeof(bits));
+	printf("\tICR0=%s\n", bits);
+
+	bitmask_snprintf(stp4020_rd_sockctl(h, STP4020_ICR1_IDX),
+	    STP4020_ICR1_BITS, bits, sizeof(bits));
+	printf("\tICR1=%s\n", bits);
+
+	bitmask_snprintf(stp4020_rd_sockctl(h, STP4020_ISR0_IDX),
+	    STP4020_ISR0_IOBITS, bits, sizeof(bits));
+	printf("\tISR0=%s\n", bits);
+
+	bitmask_snprintf(stp4020_rd_sockctl(h, STP4020_ISR1_IDX),
+	    STP4020_ISR1_BITS, bits, sizeof(bits));
+	printf("\tISR1=%s\n", bits);
+}
+#endif /* STP4020_DEBUG */
diff --git a/sys/dev/sbus/stp4020reg.h b/sys/dev/sbus/stp4020reg.h
new file mode 100644
index 00000000000..be02bc7c3ae
--- /dev/null
+++ b/sys/dev/sbus/stp4020reg.h
@@ -0,0 +1,334 @@
+/*	$OpenBSD: stp4020reg.h,v 1.1 2002/06/19 19:14:21 fgsch Exp $	*/
+/*	$NetBSD: stp4020reg.h,v 1.1 1998/11/22 22:14:35 pk Exp $ */
+
+/*-
+ * Copyright (c) 1998 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Paul Kranenburg.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *        This product includes software developed by the NetBSD
+ *        Foundation, Inc. and its contributors.
+ * 4. Neither the name of The NetBSD Foundation nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+#ifndef _STP4020_REG_H
+#define	_STP4020_REG_H
+
+/*
+ * STP4020: SBus/PCMCIA bridge supporting two Type-3 PCMCIA cards.
+ * Programming information source:
+ *	- http://www.sun.com/microelectronics/datasheets/stp4020/
+ *	- SunOS 5.5 header file
+ */
+
+/*
+ * General chip attibutes.
+ */
+#define	STP4020_NSOCK	2	/* number of PCCARD sockets per STP4020 */
+#define	STP4020_NWIN	3	/* number of windows per socket */
+
+/*
+ * Socket control registers.
+ *
+ * Each PCMCIA socket has two interface control registers and two interface
+ * status registers associated with it.
+ */
+
+/*
+ * Socket Interface Control register 0
+ */
+#define	STP4020_ICR0_rsvd1	0xc000	/* reserved bits */
+#define	STP4020_ICR0_PROMEN	0x2000	/* FCode PROM enable */
+/* Status change interrupts can be routed to one of two SBus interrupt levels:*/
+#define	STP4020_ICR0_SCILVL	0x1000	/* card status change interrupt level */
+#define	 STP4020_ICR0_SCILVL_SB0	0x0000	/* interrupt on *SB_INT[0] */
+#define	 STP4020_ICR0_SCILVL_SB1	0x1000	/* interrupt on *SB_INT[1] */
+/* Interrupt enable bits: */
+#define	STP4020_ICR0_CDIE	0x0800	/* card detect interrupt enable */
+#define	STP4020_ICR0_BVD2IE	0x0400	/* battery voltage detect 2 int en. */
+#define	STP4020_ICR0_BVD1IE	0x0200	/* battery voltage detect 1 int en. */
+#define	STP4020_ICR0_RDYIE	0x0100	/* ready/busy interrupt enable */
+#define	STP4020_ICR0_WPIE	0x0080	/* write protect interrupt enable */
+#define	STP4020_ICR0_CTOIE	0x0040	/* PC card timeout interrupt enable */
+#define	STP4020_ICR0_rsvd2	0x0020	/* */
+#define	STP4020_ICR0_IOIE	0x0010	/* I/O (*IRQ) interrupt enable */
+/* PC card I/O interrupts can also be routed to one of two SBus intr levels: */
+#define	STP4020_ICR0_IOILVL	0x0008	/* I/O (*IRQ) interrupt level (SBus) */
+#define	 STP4020_ICR0_IOILVL_SB0	0x0000	/* interrupt on *SB_INT[0] */
+#define	 STP4020_ICR0_IOILVL_SB1	0x0008	/* interrupt on *SB_INT[1] */
+
+#define	STP4020_ICR0_SPKREN	0x0004	/* *SPKR_OUT enable */
+#define	STP4020_ICR0_RESET	0x0002	/* PC card reset */
+#define	STP4020_ICR0_IFTYPE	0x0001	/* PC card interface type */
+#define	 STP4020_ICR0_IFTYPE_MEM	0x0000	/* MEMORY only */
+#define	 STP4020_ICR0_IFTYPE_IO		0x0001	/* MEMORY and I/O */
+#define STP4020_ICR0_BITS	"\177\010"				\
+				"b\0IFTYPE\0b\1RESET\0b\2SPKREN\0"	\
+				"b\3IOILVL\0b\4IOIE\0b\6CTOIE\0"	\
+				"b\7WPIE\0b\10RDYIE\0b\11BVD1IE\0b\12BVD2IE\0"\
+				"b\13CDIE\0b\14SCILV\0b\15PROMEN\0\0"
+
+/* Shorthand for all status change interrupts enables */
+#define	STP4020_ICR0_ALL_STATUS_IE (	\
+	STP4020_ICR0_CDIE |		\
+	STP4020_ICR0_BVD2IE |		\
+	STP4020_ICR0_BVD1IE |		\
+	STP4020_ICR0_RDYIE |		\
+	STP4020_ICR0_WPIE |		\
+	STP4020_ICR0_CTOIE		\
+)
+
+/*
+ * Socket Interface Control register 1
+ */
+#define	STP4020_ICR1_LPBKEN	0x8000	/* PC card data loopback enable */
+#define	STP4020_ICR1_CD1DB	0x4000	/* card detect 1 diagnostic bit */
+#define	STP4020_ICR1_BVD2DB	0x2000	/* battery voltage detect 2 diag bit */
+#define	STP4020_ICR1_BVD1DB	0x1000	/* battery voltage detect 1 diag bit */
+#define	STP4020_ICR1_RDYDB	0x0800	/* ready/busy diagnostic bit */
+#define	STP4020_ICR1_WPDB	0x0400	/* write protect diagnostic bit */
+#define	STP4020_ICR1_WAITDB	0x0200	/* *WAIT diagnostic bit */
+#define	STP4020_ICR1_DIAGEN	0x0100	/* diagnostic enable bit */
+#define	STP4020_ICR1_rsvd1	0x0080	/* reserved */
+#define	STP4020_ICR1_APWREN	0x0040	/* PC card auto power switch enable */
+
+/*
+ * The Vpp controls are two-bit fields which specify which voltage
+ * should be switched onto Vpp for this socket.
+ *
+ * Both of the "no connect" states are equal.
+ */
+#define	STP4020_ICR1_VPP2EN	0x0030	/* Vpp2 power enable */
+#define	 STP4020_ICR1_VPP2_OFF	0x0000	/* no connect */
+#define	 STP4020_ICR1_VPP2_VCC	0x0010	/* Vcc switched onto Vpp2 */
+#define	 STP4020_ICR1_VPP2_VPP	0x0020	/* Vpp switched onto Vpp2 */
+#define	 STP4020_ICR1_VPP2_ZIP	0x0030	/* no connect */
+
+#define	STP4020_ICR1_VPP1EN	0x000c	/* Vpp1 power enable */
+#define	 STP4020_ICR1_VPP1_OFF	0x0000	/* no connect */
+#define	 STP4020_ICR1_VPP1_VCC	0x0004	/* Vcc switched onto Vpp1 */
+#define	 STP4020_ICR1_VPP1_VPP	0x0008	/* Vpp switched onto Vpp1 */
+#define	 STP4020_ICR1_VPP1_ZIP	0x000c	/* no connect */
+
+#define	STP4020_ICR1_MSTPWR	0x0002	/* PC card master power enable */
+#define	STP4020_ICR1_PCIFOE	0x0001	/* PC card interface output enable */
+
+#define STP4020_ICR1_BITS	"\177\010"				     \
+				"b\0PCIFOE\0b\1MSTPWR\0f\2\2VPP1EN\0"	     \
+				"f\4\2VPP2EN\0b\6APWREN\0b\10DIAGEN\0"	     \
+				"b\11WAITDB\0b\12WPDB\0b\13RDYDB\0"	     \
+				"b\14BVD1D\0b\15BVD2D\0\16CD1DB\0b\17LPBKEN\0"
+
+/*
+ * Socket Interface Status register 0
+ *
+ * Some signals in this register change meaning depending on whether
+ * the socket is configured as MEMORY-ONLY or MEMORY & I/O:
+ *	mo: valid only if the socket is in memory-only mode
+ *	io: valid only if the socket is in memory and I/O mode.
+ *
+ * Pending interrupts are cleared by writing the corresponding status
+ * bit set in the upper half of this register.
+ */
+#define	STP4020_ISR0_ZERO	0x8000	/* always reads back as zero (mo) */
+#define	STP4020_ISR0_IOINT	0x8000	/* PC card I/O intr (*IRQ) posted (io)*/
+#define	STP4020_ISR0_SCINT	0x4000	/* status change interrupt posted */
+#define	STP4020_ISR0_CDCHG	0x2000	/* card detect status change */
+#define	STP4020_ISR0_BVD2CHG	0x1000	/* battery voltage detect 2 status change */
+#define	STP4020_ISR0_BVD1CHG	0x0800	/* battery voltage detect 1 status change */
+#define	STP4020_ISR0_RDYCHG	0x0400	/* ready/busy status change */
+#define	STP4020_ISR0_WPCHG	0x0200	/* write protect status change */
+#define	STP4020_ISR0_PCTO	0x0100	/* PC card access timeout */
+#define STP4020_ISR0_ALL_STATUS_IRQ	0x7f00
+
+#define	STP4020_ISR0_LIVE	0x00ff	/* live status bit mask */
+#define	STP4020_ISR0_CD2ST	0x0080	/* card detect 2 live status */
+#define	STP4020_ISR0_CD1ST	0x0040	/* card detect 1 live status */
+#define	STP4020_ISR0_BVD2ST	0x0020	/* battery voltage detect 2 live status (mo) */
+#define	STP4020_ISR0_SPKR	0x0020	/* SPKR signal live status (io)*/
+#define	STP4020_ISR0_BVD1ST	0x0010	/* battery voltage detect 1 live status (mo) */
+#define	STP4020_ISR0_STSCHG	0x0010	/* I/O *STSCHG signal live status (io)*/
+#define	STP4020_ISR0_RDYST	0x0008	/* ready/busy live status (mo) */
+#define	STP4020_ISR0_IOREQ	0x0008	/* I/O *REQ signal live status (io) */
+#define	STP4020_ISR0_WPST	0x0004	/* write protect live status (mo) */
+#define	STP4020_ISR0_IOIS16	0x0004	/* IOIS16 signal live status (io) */
+#define	STP4020_ISR0_WAITST	0x0002	/* wait signal live status */
+#define	STP4020_ISR0_PWRON	0x0001	/* PC card power status */
+
+#define STP4020_ISR0_IOBITS	"\177\010"				     \
+				"b\0PWRON\0b\1WAITST\0b\2IOIS16\0b\3IOREQ\0" \
+				"b\4STSCHG\0b\5SPKR\0b\6CD1ST\0b\7CD2ST\0"   \
+				"b\10PCTO\0b\11WPCHG\0b\12RDYCHG\0"	     \
+				"b\13BVD1CHG\0b\14BVD2CHG\0b\15CDCHG\0"	     \
+				"b\16SCINT\0b\17IOINT\0\0"
+#define STP4020_ISR0_MOBITS	"\177\010"				     \
+				"b\0PWRON\0b\1WAITST\0b\2WPST\0b\3RDYST\0"   \
+				"b\4BVD1ST\0b\5BVD2ST\0b\6CD1ST\0b\7CD2ST\0" \
+				"b\10PCTO\0b\11WPCHG\0b\12RDYCHG\0"	     \
+				"b\13BVD1CHG\0b\14BVD2CHG\0b\15CDCHG\0"	     \
+				"b\16SCINT\0\0"
+
+/*
+ * Socket Interface Status register 1
+ */
+#define	STP4020_ISR1_rsvd	0xffc0	/* reserved */
+#define	STP4020_ISR1_PCTYPE_M	0x0030	/* PC card type(s) supported bit mask */
+#define	STP4020_ISR1_PCTYPE_S	4	/* PC card type(s) supported bit shift */
+#define	STP4020_ISR1_REV_M	0x000f	/* ASIC revision level bit mask */
+#define	STP4020_ISR1_REV_S	0	/* ASIC revision level bit shift */
+#define STP4020_ISR1_BITS	"\177\010"		    \
+				"f\0\4REV\0f\4\2PCTYPE\0\0" \
+
+
+/*
+ * Socket window control/status register definitions.
+ *
+ * According to SunOS 5.5:
+ *	"Each PCMCIA socket has three windows associated with it; each of
+ *	these windows can be programmed to map in either the AM, CM or IO
+ *	space on the PC card.  Each window can also be programmed with a
+ *	starting or base address relative to the PC card's address zero.
+ *	Each window is a fixed 1Mb in size.
+ *
+ *	Each window has two window control registers associated with it to
+ *	control the window's PCMCIA bus timing parameters, PC card address
+ *	space that that window maps, and the base address in the
+ *	selected PC card's address space."
+ */
+#define	STP4020_WINDOW_SIZE		(1024*1024) /* 1MB */
+#define	STP4020_WINDOW_SHIFT	20	/* for 1MB */
+
+/*
+ * PC card Window Control register 0
+ */
+#define	STP4020_WCR0_rsvd	0x8000	/* reserved */
+#define	STP4020_WCR0_CMDLNG_M	0x7c00	/* command strobe length bit mask */
+#define	STP4020_WCR0_CMDLNG_S	10	/* command strobe length bit shift */
+#define	STP4020_WCR0_CMDDLY_M	0x0300	/* command strobe delay bit mask */
+#define	STP4020_WCR0_CMDDLY_S	8	/* command strobe delay bit shift */
+#define	STP4020_MEM_SPEED_MIN	100
+#define	STP4020_MEM_SPEED_MAX	1370
+/*
+ * The ASPSEL (Address Space Select) bits control which of the three PC card
+ * address spaces this window maps in.
+ */
+#define	STP4020_WCR0_ASPSEL_M	0x00c0	/* address space select bit mask */
+#define	 STP4020_WCR0_ASPSEL_AM	0x0000	/* attribute memory */
+#define	 STP4020_WCR0_ASPSEL_CM	0x0040	/* common memory */
+#define	 STP4020_WCR0_ASPSEL_IO	0x0080	/* I/O */
+/*
+ * The base address controls which 1MB range in the 64MB card address space
+ * this window maps to.
+ */
+#define	STP4020_WCR0_BASE_M	0x0003f	/* base address bit mask */
+#define	STP4020_WCR0_BASE_S	0	/* base address bit shift */
+
+#define	STP4020_ADDR2PAGE(x)	((x) >> 20)
+
+/*
+ * PC card Window Control register 1
+ */
+#define	STP4020_WCR1_rsvd	0xffe0	/* reserved */
+#define	STP4020_WCR1_RECDLY_M	0x0018	/* recovery delay bit mask */
+#define	STP4020_WCR1_RECDLY_S	3	/* recovery delay bit shift */
+#define	STP4020_WCR1_WAITDLY_M	0x0006	/* *WAIT signal delay bit mask */
+#define	STP4020_WCR1_WAITDLY_S	1	/* *WAIT signal delay bit shift */
+#define	STP4020_WCR1_WAITREQ_M	0x0001	/* *WAIT signal is required bit mask */
+#define	STP4020_WCR1_WAITREQ_S	0	/* *WAIT signal is required bit shift */
+
+#if for_reference_only
+/*
+ * STP4020 CSR structures
+ *
+ * There is one stp4020_regs_t structure per instance, and it refers to
+ *	the complete Stp4020 register set.
+ *
+ * For each socket, there is one stp4020_socket_csr_t structure, which
+ *	refers to all the registers for that socket.  That structure is
+ *	made up of the window register structures as well as the registers
+ *	that control overall socket operation.
+ *
+ * For each window, there is one stp4020_window_ctl_t structure, which
+ *	refers to all the registers for that window.
+ */
+
+/*
+ * per-window CSR structure
+ */
+typedef struct stp4020_window_ctl_t {
+    volatile	ushort_t	ctl0;		/* window control register 0 */
+    volatile	ushort_t	ctl1;		/* window control register 1 */
+} stp4020_window_ctl_t;
+
+/*
+ * per-socket CSR structure
+ */
+typedef struct stp4020_socket_csr_t {
+    volatile	struct stp4020_window_ctl_t	window[STP4020_NWIN];
+    volatile	ushort_t	ctl0;		/* socket control register 0 */
+    volatile	ushort_t	ctl1;		/* socket control register 1 */
+    volatile	ushort_t	stat0;		/* socket status register 0 */
+    volatile	ushort_t	stat1;		/* socket status register 1 */
+    volatile	uchar_t	filler[12];	/* filler space */
+} stp4020_socket_csr_t;
+
+/*
+ * per-instance CSR structure
+ */
+typedef struct stp4020_regs_t {
+    struct stp4020_socket_csr_t	socket[STP4020_NSOCK];	/* socket CSRs */
+} stp4020_regs_t;
+#endif /* reference */
+
+/* Size of control and status register banks */
+#define STP4020_SOCKREGS_SIZE	32
+#define STP4020_WINREGS_SIZE	 4
+
+/* Relative socket control & status register offsets */
+#define STP4020_ICR0_IDX	12
+#define STP4020_ICR1_IDX	14
+#define STP4020_ISR0_IDX	16
+#define STP4020_ISR1_IDX	18
+
+/* Relative Window control register offsets */
+#define STP4020_WCR0_IDX	 0
+#define STP4020_WCR1_IDX	 2
+
+/* Socket control and status register offsets */
+#define STP4020_ICR0_REG(s)	((32 * (s)) + STP4020_ICR0_IDX)
+#define STP4020_ICR1_REG(s)	((32 * (s)) + STP4020_ICR1_IDX)
+#define STP4020_ISR0_REG(s)	((32 * (s)) + STP4020_ISR0_IDX)
+#define STP4020_ISR1_REG(s)	((32 * (s)) + STP4020_ISR1_IDX)
+
+/* Window control and status registers; one set per socket */
+#define STP4020_WCR0_REG(s,w)	((32 * (s)) + (4 * (w)) + STP4020_WCR0_IDX)
+#define STP4020_WCR1_REG(s,w)	((32 * (s)) + (4 * (w)) + STP4020_WCR1_IDX)
+
+#endif	/* _STP4020_REG_H */