fix all the _BITS and their use

2 files changed, 24 insertions, 55 deletions

diff --git a/sys/dev/sbus/stp4020.c b/sys/dev/sbus/stp4020.c
index afd8993789c..bee112abf2c 100644
--- a/sys/dev/sbus/stp4020.c
+++ b/sys/dev/sbus/stp4020.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: stp4020.c,v 1.6 2003/06/25 17:36:49 miod Exp $	*/
+/*	$OpenBSD: stp4020.c,v 1.7 2003/06/25 21:20:54 mickey Exp $	*/
 /*	$NetBSD: stp4020.c,v 1.23 2002/06/01 23:51:03 lukem Exp $	*/
 
 /*-
@@ -400,12 +400,9 @@ stp4020_statintr(arg)
 		v = stp4020_rd_sockctl(h, STP4020_ISR0_IDX);
 
 #ifdef STP4020_DEBUG
-		if (stp4020_debug != 0) {
-			char bits[64];
-			bitmask_snprintf(v, STP4020_ISR0_IOBITS,
-			    bits, sizeof(bits));
-			printf("stp4020_statintr: ISR0=%s\n", bits);
-		}
+		if (stp4020_debug != 0)
+			printf("stp4020_statintr: ISR0=%b\n",
+			    v, STP4020_ISR0_IOBITS);
 #endif
 
 		/* Ack all interrupts at once */
@@ -736,12 +733,9 @@ stp4020_chip_socket_enable(pch)
 		delay(500);
 	}
 	if (i <= 0) {
-#if STP4020_DEBUG
-		char bits[64];
-		bitmask_snprintf(stp4020_rd_sockctl(h, STP4020_ISR0_IDX),
-		    STP4020_ISR0_IOBITS, bits, sizeof(bits));
-		printf("stp4020_chip_socket_enable: not ready: status %s\n",
-		    bits);
+#ifdef STP4020_DEBUG
+		printf("stp4020_chip_socket_enable: not ready: status %b\n",
+		    v, STP4020_ISR0_IOBITS);
 #endif
 		return;
 	}
@@ -851,25 +845,14 @@ void
 stp4020_dump_regs(h)
 	struct stp4020_socket *h;
 {
-	char bits[64];
 	/*
 	 * Dump control and status registers.
 	 */
-	printf("socket[%d] registers:\n", h->sock);
-	bitmask_snprintf(stp4020_rd_sockctl(h, STP4020_ICR0_IDX),
-	    STP4020_ICR0_BITS, bits, sizeof(bits));
-	printf("\tICR0=%s\n", bits);
-
-	bitmask_snprintf(stp4020_rd_sockctl(h, STP4020_ICR1_IDX),
-	    STP4020_ICR1_BITS, bits, sizeof(bits));
-	printf("\tICR1=%s\n", bits);
-
-	bitmask_snprintf(stp4020_rd_sockctl(h, STP4020_ISR0_IDX),
-	    STP4020_ISR0_IOBITS, bits, sizeof(bits));
-	printf("\tISR0=%s\n", bits);
-
-	bitmask_snprintf(stp4020_rd_sockctl(h, STP4020_ISR1_IDX),
-	    STP4020_ISR1_BITS, bits, sizeof(bits));
-	printf("\tISR1=%s\n", bits);
+	printf("socket[%d] registers:\n"
+	    "\tICR0=%b\n\tICR1=%b\n\tISR0=%b\n\tISR1=%x\n", h->sock,
+	    stp4020_rd_sockctl(h, STP4020_ICR0_IDX), STP4020_ICR0_BITS,
+	    stp4020_rd_sockctl(h, STP4020_ICR1_IDX), STP4020_ICR1_BITS,
+	    stp4020_rd_sockctl(h, STP4020_ISR0_IDX), STP4020_ISR0_IOBITS,
+	    stp4020_rd_sockctl(h, STP4020_ISR1_IDX));
 }
 #endif /* STP4020_DEBUG */
diff --git a/sys/dev/sbus/stp4020reg.h b/sys/dev/sbus/stp4020reg.h
index 85672d92e46..03a8676a247 100644
--- a/sys/dev/sbus/stp4020reg.h
+++ b/sys/dev/sbus/stp4020reg.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: stp4020reg.h,v 1.2 2002/06/21 07:49:31 fgsch Exp $	*/
+/*	$OpenBSD: stp4020reg.h,v 1.3 2003/06/25 21:20:54 mickey Exp $	*/
 /*	$NetBSD: stp4020reg.h,v 1.1 1998/11/22 22:14:35 pk Exp $	*/
 
 /*-
@@ -89,11 +89,8 @@
 #define	STP4020_ICR0_IFTYPE	0x0001	/* PC card interface type */
 #define	 STP4020_ICR0_IFTYPE_MEM	0x0000	/* MEMORY only */
 #define	 STP4020_ICR0_IFTYPE_IO		0x0001	/* MEMORY and I/O */
-#define STP4020_ICR0_BITS	"\177\010"				\
-				"b\0IFTYPE\0b\1RESET\0b\2SPKREN\0"	\
-				"b\3IOILVL\0b\4IOIE\0b\6CTOIE\0"	\
-				"b\7WPIE\0b\10RDYIE\0b\11BVD1IE\0b\12BVD2IE\0"\
-				"b\13CDIE\0b\14SCILV\0b\15PROMEN\0\0"
+#define STP4020_ICR0_BITS	"\010\1IFTYPE\2RESET\3SPKREN\4IOILVL\5IOIE" \
+    "\7CTOIE\10WPIE\11RDYIE\12BVD1IE\13BVD2IE\14CDIE\15SCILV\16PROMEN"
 
 /* Shorthand for all status change interrupts enables */
 #define	STP4020_ICR0_ALL_STATUS_IE (	\
@@ -140,11 +137,8 @@
 #define	STP4020_ICR1_MSTPWR	0x0002	/* PC card master power enable */
 #define	STP4020_ICR1_PCIFOE	0x0001	/* PC card interface output enable */
 
-#define STP4020_ICR1_BITS	"\177\010"				     \
-				"b\0PCIFOE\0b\1MSTPWR\0f\2\2VPP1EN\0"	     \
-				"f\4\2VPP2EN\0b\6APWREN\0b\10DIAGEN\0"	     \
-				"b\11WAITDB\0b\12WPDB\0b\13RDYDB\0"	     \
-				"b\14BVD1D\0b\15BVD2D\0\16CD1DB\0b\17LPBKEN\0"
+#define STP4020_ICR1_BITS	"\010\1PCIFOE\2MSTPWR\7APWREN\11DIAGEN" \
+    "\12WAITDB\13WPDB\14RDYDB\15BVD1D\16BVD2D\17CD1DB\18LPBKEN"
 
 /*
  * Socket Interface Status register 0
@@ -182,18 +176,12 @@
 #define	STP4020_ISR0_WAITST	0x0002	/* wait signal live status */
 #define	STP4020_ISR0_PWRON	0x0001	/* PC card power status */
 
-#define STP4020_ISR0_IOBITS	"\177\010"				     \
-				"b\0PWRON\0b\1WAITST\0b\2IOIS16\0b\3IOREQ\0" \
-				"b\4STSCHG\0b\5SPKR\0b\6CD1ST\0b\7CD2ST\0"   \
-				"b\10PCTO\0b\11WPCHG\0b\12RDYCHG\0"	     \
-				"b\13BVD1CHG\0b\14BVD2CHG\0b\15CDCHG\0"	     \
-				"b\16SCINT\0b\17IOINT\0\0"
-#define STP4020_ISR0_MOBITS	"\177\010"				     \
-				"b\0PWRON\0b\1WAITST\0b\2WPST\0b\3RDYST\0"   \
-				"b\4BVD1ST\0b\5BVD2ST\0b\6CD1ST\0b\7CD2ST\0" \
-				"b\10PCTO\0b\11WPCHG\0b\12RDYCHG\0"	     \
-				"b\13BVD1CHG\0b\14BVD2CHG\0b\15CDCHG\0"	     \
-				"b\16SCINT\0\0"
+#define STP4020_ISR0_IOBITS	"\010\1PWRON\2WAITST\3IOIS16\4IOREQ" \
+    "\5STSCHG\6SPKR\7CD1ST\10CD2ST\11PCTO\12WPCHG\13RDYCHG\14BVD1CHG" \
+    "\15BVD2CHG\16CDCHG\17SCINT\20IOINT"
+#define STP4020_ISR0_MOBITS	"\010\1PWRON\2WAITST\3WPST\4RDYST" \
+    "\5BVD1ST\6BVD2ST\7CD1ST\10CD2ST\11PCTO\12WPCHG\13RDYCHG\14BVD1CHG" \
+    "\15BVD2CHG\16CDCHG\17SCINT"
 
 /*
  * Socket Interface Status register 1
@@ -203,8 +191,6 @@
 #define	STP4020_ISR1_PCTYPE_S	4	/* PC card type(s) supported bit shift */
 #define	STP4020_ISR1_REV_M	0x000f	/* ASIC revision level bit mask */
 #define	STP4020_ISR1_REV_S	0	/* ASIC revision level bit shift */
-#define STP4020_ISR1_BITS	"\177\010"		    \
-				"f\0\4REV\0f\4\2PCTYPE\0\0" \
 
 
 /*