cleanup, more register definitions

2 files changed, 276 insertions, 240 deletions

diff --git a/sys/dev/pci/if_txp.c b/sys/dev/pci/if_txp.c
index 55a1b5b90fd..b454e5ffcff 100644
--- a/sys/dev/pci/if_txp.c
+++ b/sys/dev/pci/if_txp.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: if_txp.c,v 1.1 2001/04/08 02:16:52 jason Exp $	*/
+/*	$OpenBSD: if_txp.c,v 1.2 2001/04/08 05:28:49 jason Exp $	*/
 
 /*
  * Copyright (c) 2001
@@ -15,7 +15,8 @@
  *    documentation and/or other materials provided with the distribution.
  * 3. All advertising materials mentioning features or use of this software
  *    must display the following acknowledgement:
- *	This product includes software developed by Jason L. Wright.
+ *	This product includes software developed by Jason L. Wright and
+ *	Aaron Campbell.
  * 4. Neither the name of the author nor the names of any co-contributors
  *    may be used to endorse or promote products derived from this software
  *    without specific prior written permission.
@@ -82,38 +83,6 @@
 #include <dev/pci/if_txpreg.h>
 #include <dev/pci/typhoon_image.h>
 
-/* XXX not here */
-struct txp_softc {
-	struct device		sc_dev;
-	void *			sc_ih;
-	bus_space_handle_t	sc_bh;
-	bus_space_tag_t		sc_bt;
-	bus_dma_tag_t		sc_dmat;
-	struct arpcom		sc_arpcom;
-	struct timeout		sc_tick_tmo;
-};
-
-struct txp_fw_file_header {
-	u_int8_t       	magicid[8];
-	u_int32_t	version;
-	u_int32_t	nsections;
-	u_int32_t	addr;
-};
-
-struct txp_fw_section_header {
-	u_int32_t	nbytes;
-	u_int16_t	cksum;
-	u_int16_t	reserved;
-	u_int32_t	addr;
-};
-
-#define TXP_PCI_LOMEM                   0x14
-#define WRITE_REG(sc,reg,val) \
-    bus_space_write_4((sc)->sc_bt, (sc)->sc_bh, reg, val)
-#define READ_REG(sc,reg) \
-    bus_space_read_4((sc)->sc_bt, (sc)->sc_bh, reg)
-/* end XXX not here */
-
 int txp_probe	__P((struct device *, void *, void *));
 void txp_attach	__P((struct device *, struct device *, void *));
 int txp_intr	__P((void *));
@@ -240,21 +209,35 @@ txp_chip_init(sc)
 	struct txp_softc *sc;
 {
 	/* disable interrupts */
-	WRITE_REG(sc, TXP_INT_ENABLE_REGISTER, 0);
-	WRITE_REG(sc, TXP_INT_MASK_REGISTER, 0x0000ffff);
+	WRITE_REG(sc, TXP_IER, 0);
+	WRITE_REG(sc, TXP_IMR,
+	    TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT |
+	    TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 |
+	    TXP_INT_LATCH);
 
 	/* ack all interrupts */
-	WRITE_REG(sc, TXP_INT_STATUS_REGISTER, 0xffffffff);
+	WRITE_REG(sc, TXP_ISR, TXP_INT_RESERVED | TXP_INT_LATCH |
+	    TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 |
+	    TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT |
+	    TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 |
+	    TXP_INT_A2H_3 | TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0);
 
 	if (txp_reset_adapter(sc))
 		return (-1);
 
 	/* disable interrupts */
-	WRITE_REG(sc, TXP_INT_ENABLE_REGISTER, 0);
-	WRITE_REG(sc, TXP_INT_MASK_REGISTER, 0x0000ffff);
+	WRITE_REG(sc, TXP_IER, 0);
+	WRITE_REG(sc, TXP_IMR,
+	    TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT |
+	    TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 |
+	    TXP_INT_LATCH);
 
 	/* ack all interrupts */
-	WRITE_REG(sc, TXP_INT_STATUS_REGISTER, 0xffffffff);
+	WRITE_REG(sc, TXP_ISR, TXP_INT_RESERVED | TXP_INT_LATCH |
+	    TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 |
+	    TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT |
+	    TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 |
+	    TXP_INT_A2H_3 | TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0);
 
 	return (0);
 }
@@ -266,19 +249,19 @@ txp_reset_adapter(sc)
 	u_int32_t r;
 	int i;
 
-	WRITE_REG(sc, TXP_SOFT_RESET_REGISTER, 0x7f);
+	WRITE_REG(sc, TXP_SRR, 0x7f);
 	DELAY(1000);
-	WRITE_REG(sc, TXP_SOFT_RESET_REGISTER, 0);
+	WRITE_REG(sc, TXP_SRR, 0);
 
 	/* Should wait max 6 seconds */
 	for (i = 0; i < 6000; i++) {
-		r = READ_REG(sc, TXP_ARM2HOST_COMM_0_REGISTER);
-		if (r == TYPHOON_WAITING_FOR_HOST_REQUEST)
+		r = READ_REG(sc, TXP_A2H_0);
+		if (r == STAT_WAITING_FOR_HOST_REQUEST)
 			break;
 		DELAY(1000);
 	}
 
-	if (r != TYPHOON_WAITING_FOR_HOST_REQUEST) {
+	if (r != STAT_WAITING_FOR_HOST_REQUEST) {
 		printf(": reset hung\n");
 		return (-1);
 	}
@@ -295,31 +278,29 @@ txp_download_fw(sc)
 	int sect;
 	u_int32_t r, i, ier, imr;
 
-	ier = READ_REG(sc, TXP_INT_ENABLE_REGISTER);
-	WRITE_REG(sc, TXP_INT_ENABLE_REGISTER,
-	    ier | TYPHOON_INT_ARM2HOST_COMM_0);
+	ier = READ_REG(sc, TXP_IER);
+	WRITE_REG(sc, TXP_IER, ier | TXP_INT_A2H_0);
 
-	imr = READ_REG(sc, TXP_INT_MASK_REGISTER);
-	WRITE_REG(sc, TXP_INT_MASK_REGISTER,
-	    imr | TYPHOON_INT_ARM2HOST_COMM_0);
+	imr = READ_REG(sc, TXP_IMR);
+	WRITE_REG(sc, TXP_IMR, imr | TXP_INT_A2H_0);
 
 	for (i = 0; i < 10000; i++) {
-		r = READ_REG(sc, TXP_ARM2HOST_COMM_0_REGISTER);
-		if (r == TYPHOON_WAITING_FOR_HOST_REQUEST)
+		r = READ_REG(sc, TXP_A2H_0);
+		if (r == STAT_WAITING_FOR_HOST_REQUEST)
 			break;
 		DELAY(50);
 	}
-	if (r != TYPHOON_WAITING_FOR_HOST_REQUEST) {
+	if (r != STAT_WAITING_FOR_HOST_REQUEST) {
 		printf(": not waiting for host request\n");
 		return (-1);
 	}
 
 	/* Ack the status */
-	WRITE_REG(sc, TXP_INT_STATUS_REGISTER, TYPHOON_INT_ARM2HOST_COMM_0);
+	WRITE_REG(sc, TXP_ISR, TXP_INT_A2H_0);
 
 	/* Tell boot firmware to get ready for image */
-	WRITE_REG(sc, TXP_HOST2ARM_COMM_1_REGISTER, fileheader->addr);
-	WRITE_REG(sc, TXP_HOST2ARM_COMM_0_REGISTER, TYPHOON_BOOTCOMMAND_RUNTIME_IMAGE);
+	WRITE_REG(sc, TXP_H2A_1, fileheader->addr);
+	WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_RUNTIME_IMAGE);
 
 	fileheader = (struct txp_fw_file_header *)TyphoonImage;
 	if (strncmp("TYPHOON", fileheader->magicid, sizeof(fileheader->magicid))) {
@@ -342,22 +323,21 @@ txp_download_fw(sc)
 		    (((u_int8_t *)secthead) + secthead->nbytes + sizeof(*secthead));
 	}
 
-	WRITE_REG(sc, TXP_HOST2ARM_COMM_0_REGISTER,
-	    TYPHOON_BOOTCOMMAND_DOWNLOAD_COMPLETE);
+	WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_DOWNLOAD_COMPLETE);
 
 	for (i = 0; i < 10000; i++) {
-		r = READ_REG(sc, TXP_ARM2HOST_COMM_0_REGISTER);
-		if (r == TYPHOON_WAITING_FOR_BOOT)
+		r = READ_REG(sc, TXP_A2H_0);
+		if (r == STAT_WAITING_FOR_BOOT)
 			break;
 		DELAY(50);
 	}
-	if (r != TYPHOON_WAITING_FOR_BOOT) {
+	if (r != STAT_WAITING_FOR_BOOT) {
 		printf(": not waiting for boot\n");
 		return (-1);
 	}
 
-	WRITE_REG(sc, TXP_INT_ENABLE_REGISTER, ier);
-	WRITE_REG(sc, TXP_INT_MASK_REGISTER, imr);
+	WRITE_REG(sc, TXP_IER, ier);
+	WRITE_REG(sc, TXP_IMR, imr);
 
 	return (0);
 }
@@ -369,21 +349,21 @@ txp_download_fw_wait(sc)
 	u_int32_t i, r;
 
 	for (i = 0; i < 10000; i++) {
-		r = READ_REG(sc, TXP_INT_STATUS_REGISTER);
-		if (r & TYPHOON_INT_ARM2HOST_COMM_0)
+		r = READ_REG(sc, TXP_ISR);
+		if (r & TXP_INT_A2H_0)
 			break;
 		DELAY(50);
 	}
 
-	if (!(r & TYPHOON_INT_ARM2HOST_COMM_0)) {
+	if (!(r & TXP_INT_A2H_0)) {
 		printf(": fw wait failed comm0\n", sc->sc_dev.dv_xname);
 		return (-1);
 	}
 
-	WRITE_REG(sc, TXP_INT_STATUS_REGISTER, TYPHOON_INT_ARM2HOST_COMM_0);
+	WRITE_REG(sc, TXP_ISR, TXP_INT_A2H_0);
 
-	r = READ_REG(sc, TXP_ARM2HOST_COMM_0_REGISTER);
-	if (r != TYPHOON_WAITING_FOR_SEGMENT) {
+	r = READ_REG(sc, TXP_A2H_0);
+	if (r != STAT_WAITING_FOR_SEGMENT) {
 		printf(": fw not waiting for segment\n", sc->sc_dev.dv_xname);
 		return (-1);
 	}
@@ -431,30 +411,29 @@ txp_download_fw_section(sc, sect, sectnum)
 		err = -1;
 		goto bail_destroy;
 	}
+
 	bcopy(((u_int8_t *)sect) + sizeof(*sect), kva, sect->nbytes);
+
 	bus_dmamap_sync(dmat, dmamap,
 	    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
 
 	pa = dmamap->dm_segs[0].ds_addr;
 
-	WRITE_REG(sc, TXP_HOST2ARM_COMM_1_REGISTER, sect->nbytes);
-	WRITE_REG(sc, TXP_HOST2ARM_COMM_2_REGISTER, sect->cksum);
-	WRITE_REG(sc, TXP_HOST2ARM_COMM_3_REGISTER, sect->addr);
-	WRITE_REG(sc, TXP_HOST2ARM_COMM_4_REGISTER, pa >> 32);
-	WRITE_REG(sc, TXP_HOST2ARM_COMM_5_REGISTER, pa & 0xffffffff);
-	WRITE_REG(sc, TXP_HOST2ARM_COMM_0_REGISTER,
-	    TYPHOON_BOOTCOMMAND_SEGMENT_AVAILABLE);
+	WRITE_REG(sc, TXP_H2A_1, sect->nbytes);
+	WRITE_REG(sc, TXP_H2A_2, sect->cksum);
+	WRITE_REG(sc, TXP_H2A_3, sect->addr);
+	WRITE_REG(sc, TXP_H2A_4, pa >> 32);
+	WRITE_REG(sc, TXP_H2A_5, pa & 0xffffffff);
+	WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_SEGMENT_AVAILABLE);
 
 	if (txp_download_fw_wait(sc)) {
 		printf(": fw wait failed, section %d\n", sectnum);
 		err = -1;
-		goto bail;
 	}
 
+
 	bus_dmamap_sync(dmat, dmamap,
 	    BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
-
-bail:
 	bus_dmamap_unload(dmat, dmamap);
 bail_destroy:
 	bus_dmamap_destroy(dmat, dmamap);
diff --git a/sys/dev/pci/if_txpreg.h b/sys/dev/pci/if_txpreg.h
index 9e5573b773c..b2daf771c39 100644
--- a/sys/dev/pci/if_txpreg.h
+++ b/sys/dev/pci/if_txpreg.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: if_txpreg.h,v 1.1 2001/04/08 02:16:52 jason Exp $ */
+/*	$OpenBSD: if_txpreg.h,v 1.2 2001/04/08 05:28:50 jason Exp $ */
 
 /*
  * Copyright (c) 2001 Aaron Campbell <aaron@monkey.org>.
@@ -31,158 +31,191 @@
  * THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-#define TXP_INTR	TXP_INT_STATUS_REGISTER
+#define	TXP_INTR	TXP_INT_STATUS_REGISTER
+
+#define	TXP_PCI_LOMEM			0x14	/* pci conf, memory map BAR */
+#define	TXP_PCI_LOIO			0x10	/* pci conf, IO map BAR */
 
 /*
  * Typhoon registers.
  */
-#define TXP_SOFT_RESET_REGISTER		0x00
-#define TXP_INT_STATUS_REGISTER		0x04
-#define TXP_INT_ENABLE_REGISTER		0x08
-#define TXP_INT_MASK_REGISTER		0x0C
-#define TXP_SELF_INT_REGISTER		0x10
-#define TXP_HOST2ARM_COMM_7_REGISTER	0x14
-#define TXP_HOST2ARM_COMM_6_REGISTER	0x18
-#define TXP_HOST2ARM_COMM_5_REGISTER	0x1C
-#define TXP_HOST2ARM_COMM_4_REGISTER	0x20
-#define TXP_HOST2ARM_COMM_3_REGISTER	0x24
-#define TXP_HOST2ARM_COMM_2_REGISTER	0x28
-#define TXP_HOST2ARM_COMM_1_REGISTER	0x2C
-#define TXP_HOST2ARM_COMM_0_REGISTER	0x30
-#define TXP_ARM2HOST_COMM_3_REGISTER	0x34
-#define TXP_ARM2HOST_COMM_2_REGISTER	0x38
-#define TXP_ARM2HOST_COMM_1_REGISTER	0x3C
-#define TXP_ARM2HOST_COMM_0_REGISTER	0x40
+#define	TXP_SRR				0x00	/* soft reset register */
+#define	TXP_ISR				0x04	/* interrupt status register */
+#define	TXP_IER				0x08	/* interrupt enable register */
+#define	TXP_IMR				0x0c	/* interrupt mask register */
+#define	TXP_SIR				0x10	/* self interrupt register */
+#define	TXP_H2A_7			0x14	/* host->arm comm 7 */
+#define	TXP_H2A_6			0x18	/* host->arm comm 6 */
+#define	TXP_H2A_5			0x1c	/* host->arm comm 5 */
+#define	TXP_H2A_4			0x20	/* host->arm comm 4 */
+#define	TXP_H2A_3			0x24	/* host->arm comm 3 */
+#define	TXP_H2A_2			0x28	/* host->arm comm 2 */
+#define	TXP_H2A_1			0x2c	/* host->arm comm 1 */
+#define	TXP_H2A_0			0x30	/* host->arm comm 0 */
+#define	TXP_A2H_3			0x34	/* arm->host comm 3 */
+#define	TXP_A2H_2			0x38	/* arm->host comm 2 */
+#define	TXP_A2H_1			0x3c	/* arm->host comm 1 */
+#define	TXP_A2H_0			0x40	/* arm->host comm 0 */
+
+/*
+ * interrupt bits (IMR, ISR, IER)
+ */
+#define	TXP_INT_RESERVED	0xffff0000
+#define	TXP_INT_A2H_7		0x00008000	/* arm->host comm 7 */
+#define	TXP_INT_A2H_6		0x00004000	/* arm->host comm 6 */
+#define	TXP_INT_A2H_5		0x00002000	/* arm->host comm 5 */
+#define	TXP_INT_A2H_4		0x00001000	/* arm->host comm 4 */
+#define	TXP_INT_SELF		0x00000800	/* self interrupt */
+#define	TXP_INT_PCI_TABORT	0x00000400	/* pci target abort */
+#define	TXP_INT_PCI_MABORT	0x00000200	/* pci master abort */
+#define	TXP_INT_DMA3		0x00000100	/* dma3 done */
+#define	TXP_INT_DMA2		0x00000080	/* dma2 done */
+#define	TXP_INT_DMA1		0x00000040	/* dma1 done */
+#define	TXP_INT_DMA0		0x00000020	/* dma0 done */
+#define	TXP_INT_A2H_3		0x00000010	/* arm->host comm 3 */
+#define	TXP_INT_A2H_2		0x00000008	/* arm->host comm 2 */
+#define	TXP_INT_A2H_1		0x00000004	/* arm->host comm 1 */
+#define	TXP_INT_A2H_0		0x00000002	/* arm->host comm 0 */
+#define	TXP_INT_LATCH		0x00000001	/* interrupt latch */
+
+/*
+ * Typhoon boot commands.
+ */
+#define	TXP_BOOTCMD_NULL			0x00
+#define	TXP_BOOTCMD_DOWNLOAD_COMPLETE		0xfb
+#define	TXP_BOOTCMD_SEGMENT_AVAILABLE		0xfc
+#define	TXP_BOOTCMD_RUNTIME_IMAGE		0xfd
+#define	TXP_BOOTCMD_REGISTER_BOOT_RECORD	0xff
 
 /*
- * Typhoon commands.
+ * Typhoon runtime commands.
  */
-#define TXP_CMD_GLOBAL_RESET			0x00
-#define TXP_CMD_TX_ENABLE			0x01
-#define TXP_CMD_TX_DISABLE			0x02
-#define TXP_CMD_RX_ENABLE			0x03
-#define TXP_CMD_RX_DISABLE			0x04
-#define TXP_CMD_RX_FILTER_WRITE			0x05
-#define TXP_CMD_RX_FILTER_READ			0x06
-#define TXP_CMD_READ_STATISTICS			0x07
-#define TXP_CMD_CYCLE_STATISTICS		0x08
-#define TXP_CMD_ERROR_READ			0x09
-#define TXP_CMD_MEMORY_READ			0x0a
-#define TXP_CMD_MEMORY_WRITE_SINGLE		0x0b
-#define TXP_CMD_VARIABLE_SECTION_READ		0x0c
-#define TXP_CMD_VARIABLE_SECTION_WRITE		0x0d
-#define TXP_CMD_STATIC_SECTION_READ		0x0e
-#define TXP_CMD_STATIC_SECTION_WRITE		0x0f
-#define TXP_CMD_IMAGE_SECTION_PROGRAM		0x10
-#define TXP_CMD_NVRAM_PAGE_READ			0x11
-#define TXP_CMD_NVRAM_PAGE_WRITE		0x12
-#define TXP_CMD_XCVR_SELECT			0x13
-#define TXP_CMD_TEST_MUX			0x14
-#define TXP_CMD_PHYLOOPBACK_ENABLE		0x15
-#define TXP_CMD_PHYLOOPBACK_DISABLE		0x16
-#define TXP_CMD_MAC_CONTROL_READ		0x17
-#define TXP_CMD_MAC_CONTROL_WRITE		0x18
-#define TXP_CMD_MAX_PKT_SIZE_READ		0x19
-#define TXP_CMD_MAX_PKT_SIZE_WRITE		0x1a
-#define TXP_CMD_MEDIA_STATUS_READ		0x1b
-#define TXP_CMD_MEDIA_STATUS_WRITE		0x1c
-#define TXP_CMD_NETWORK_DIAGS_READ		0x1d
-#define TXP_CMD_NETWORK_DIAGS_WRITE		0x1e
-#define TXP_CMD_POWER_MGMT_EVENT_READ		0x1f
-#define TXP_CMD_POWER_MGMT_EVENT_WRITE		0x20
-#define TXP_CMD_VARIABLE_PARAMETER_READ		0x21
-#define TXP_CMD_VARIABLE_PARAMETER_WRITE	0x22
-#define TXP_CMD_GOTO_SLEEP			0x23
-#define TXP_CMD_FIREWALL_CONTROL		0x24
-#define TXP_CMD_MCAST_HASH_MASK_WRITE		0x25
-#define TXP_CMD_STATION_ADDRESS_WRITE		0x26
-#define TXP_CMD_STATION_ADDRESS_READ		0x27
-#define TXP_CMD_STATION_MASK_WRITE		0x28
-#define TXP_CMD_STATION_MASK_READ		0x29
-#define TXP_CMD_VLAN_ETHER_TYPE_READ		0x2a
-#define TXP_CMD_VLAN_ETHER_TYPE_WRITE		0x2b
-#define TXP_CMD_VLAN_MASK_READ			0x2c
-#define TXP_CMD_VLAN_MASK_WRITE			0x2d
-#define TXP_CMD_BCAST_THROTTLE_WRITE		0x2e
-#define TXP_CMD_BCAST_THROTTLE_READ		0x2f
-#define TXP_CMD_DHCP_PREVENT_WRITE		0x30
-#define TXP_CMD_DHCP_PREVENT_READ		0x31
-#define TXP_CMD_RECV_BUFFER_CONTROL		0x32
-#define TXP_CMD_SOFTWARE_RESET			0x33
-#define TXP_CMD_CREATE_SA			0x34
-#define TXP_CMD_DELETE_SA			0x35
-#define TXP_CMD_ENABLE_RX_IP_OPTION		0x36
-#define TXP_CMD_RANDOM_NUMBER_CONTROL		0x37
-#define TXP_CMD_RANDOM_NUMBER_READ		0x38
-#define TXP_CMD_MATRIX_TABLE_MODE_WRITE		0x39
-#define TXP_CMD_MATRIX_DETAIL_READ		0x3a
-#define TXP_CMD_FILTER_ARRAY_READ		0x3b
-#define TXP_CMD_FILTER_DETAIL_READ		0x3c
-#define TXP_CMD_FILTER_TABLE_MODE_WRITE		0x3d
-#define TXP_CMD_FILTER_TCL_WRITE		0x3e
-#define TXP_CMD_FILTER_TBL_READ			0x3f
-#define TXP_CMD_FILTER_DEFINE			0x45
-#define TXP_CMD_ADD_WAKEUP_PKT			0x46
-#define TXP_CMD_ADD_SLEEP_PKT			0x47
-#define TXP_CMD_ENABLE_SLEEP_EVENTS		0x48
-#define TXP_CMD_ENABLE_WAKEUP_EVENTS		0x49
-#define TXP_CMD_GET_IP_ADDRESS			0x4a
-#define TXP_CMD_READ_PCI_REG			0x4c
-#define TXP_CMD_WRITE_PCI_REG			0x4d
-#define TXP_CMD_OFFLOAD_WRITE			0x4f
-#define TXP_CMD_HELLO_RESPONSE			0x57
-#define TXP_CMD_ENABLE_RX_FILTER		0x58
-#define TXP_CMD_RX_FILTER_CAPABILITY		0x59
-#define TXP_CMD_HALT				0x5d
-#define TXP_CMD_INVALID				0xffff
-
-#define TXP_FRAGMENT		0x0000
-#define TXP_TXFRAME		0x0001
-#define TXP_COMMAND		0x0002
-#define TXP_OPTION		0x0003
-#define TXP_RECEIVE		0x0004
-#define TXP_RESPONSE		0x0005
-
-#define TXP_TYPE_IPSEC		0x0000
-#define TXP_TYPE_TCPSEGMENT	0x0001
-
-#define TXP_PFLAG_NOCRC		0x0000
-#define TXP_PFLAG_IPCKSUM	0x0001
-#define TXP_PFLAG_TCPCKSUM	0x0002
-#define TXP_PFLAG_TCPSEGMENT	0x0004
-#define TXP_PFLAG_INSERTVLAN	0x0008
-#define TXP_PFLAG_IPSEC		0x0010
-#define TXP_PFLAG_PRIORITY	0x0020
-#define TXP_PFLAG_UDPCKSUM	0x0040
-#define TXP_PFLAG_PADFRAME	0x0080
-
-#define TXP_MISC_FIRSTDESC	0x0000
-#define TXP_MISC_LASTDESC	0x0001
-
-#define TXP_ERR_INTERNAL	0x0000
-#define TXP_ERR_FIFOUNDERRUN	0x0001
-#define TXP_ERR_BADSSD		0x0002
-#define TXP_ERR_RUNT		0x0003
-#define TXP_ERR_CRC		0x0004
-#define TXP_ERR_OVERSIZE	0x0005
-#define TXP_ERR_ALIGNMENT	0x0006
-#define TXP_ERR_DRIBBLEBIT	0x0007
-
-#define TXP_PROTO_UNKNOWN	0x0000
-#define TXP_PROTO_IP		0x0001
-#define TXP_PROTO_IPX		0x0002
-#define TXP_PROTO_RESERVED	0x0003
-
-#define TXP_STAT_PROTO		0x0001
-#define TXP_STAT_VLAN		0x0002
-#define TXP_STAT_IPFRAGMENT	0x0004
-#define TXP_STAT_IPSEC		0x0008
-#define TXP_STAT_IPCKSUMBAD	0x0010
-#define TXP_STAT_TCPCKSUMBAD	0x0020
-#define TXP_STAT_UDPCKSUMBAD	0x0040
-#define TXP_STAT_IPCKSUMGOOD	0x0080
-#define TXP_STAT_TCPCKSUMGOOD	0x0100
-#define TXP_STAT_UDPCKSUMGOOD	0x0200
+#define	TXP_CMD_GLOBAL_RESET			0x00
+#define	TXP_CMD_TX_ENABLE			0x01
+#define	TXP_CMD_TX_DISABLE			0x02
+#define	TXP_CMD_RX_ENABLE			0x03
+#define	TXP_CMD_RX_DISABLE			0x04
+#define	TXP_CMD_RX_FILTER_WRITE			0x05
+#define	TXP_CMD_RX_FILTER_READ			0x06
+#define	TXP_CMD_READ_STATISTICS			0x07
+#define	TXP_CMD_CYCLE_STATISTICS		0x08
+#define	TXP_CMD_ERROR_READ			0x09
+#define	TXP_CMD_MEMORY_READ			0x0a
+#define	TXP_CMD_MEMORY_WRITE_SINGLE		0x0b
+#define	TXP_CMD_VARIABLE_SECTION_READ		0x0c
+#define	TXP_CMD_VARIABLE_SECTION_WRITE		0x0d
+#define	TXP_CMD_STATIC_SECTION_READ		0x0e
+#define	TXP_CMD_STATIC_SECTION_WRITE		0x0f
+#define	TXP_CMD_IMAGE_SECTION_PROGRAM		0x10
+#define	TXP_CMD_NVRAM_PAGE_READ			0x11
+#define	TXP_CMD_NVRAM_PAGE_WRITE		0x12
+#define	TXP_CMD_XCVR_SELECT			0x13
+#define	TXP_CMD_TEST_MUX			0x14
+#define	TXP_CMD_PHYLOOPBACK_ENABLE		0x15
+#define	TXP_CMD_PHYLOOPBACK_DISABLE		0x16
+#define	TXP_CMD_MAC_CONTROL_READ		0x17
+#define	TXP_CMD_MAC_CONTROL_WRITE		0x18
+#define	TXP_CMD_MAX_PKT_SIZE_READ		0x19
+#define	TXP_CMD_MAX_PKT_SIZE_WRITE		0x1a
+#define	TXP_CMD_MEDIA_STATUS_READ		0x1b
+#define	TXP_CMD_MEDIA_STATUS_WRITE		0x1c
+#define	TXP_CMD_NETWORK_DIAGS_READ		0x1d
+#define	TXP_CMD_NETWORK_DIAGS_WRITE		0x1e
+#define	TXP_CMD_POWER_MGMT_EVENT_READ		0x1f
+#define	TXP_CMD_POWER_MGMT_EVENT_WRITE		0x20
+#define	TXP_CMD_VARIABLE_PARAMETER_READ		0x21
+#define	TXP_CMD_VARIABLE_PARAMETER_WRITE	0x22
+#define	TXP_CMD_GOTO_SLEEP			0x23
+#define	TXP_CMD_FIREWALL_CONTROL		0x24
+#define	TXP_CMD_MCAST_HASH_MASK_WRITE		0x25
+#define	TXP_CMD_STATION_ADDRESS_WRITE		0x26
+#define	TXP_CMD_STATION_ADDRESS_READ		0x27
+#define	TXP_CMD_STATION_MASK_WRITE		0x28
+#define	TXP_CMD_STATION_MASK_READ		0x29
+#define	TXP_CMD_VLAN_ETHER_TYPE_READ		0x2a
+#define	TXP_CMD_VLAN_ETHER_TYPE_WRITE		0x2b
+#define	TXP_CMD_VLAN_MASK_READ			0x2c
+#define	TXP_CMD_VLAN_MASK_WRITE			0x2d
+#define	TXP_CMD_BCAST_THROTTLE_WRITE		0x2e
+#define	TXP_CMD_BCAST_THROTTLE_READ		0x2f
+#define	TXP_CMD_DHCP_PREVENT_WRITE		0x30
+#define	TXP_CMD_DHCP_PREVENT_READ		0x31
+#define	TXP_CMD_RECV_BUFFER_CONTROL		0x32
+#define	TXP_CMD_SOFTWARE_RESET			0x33
+#define	TXP_CMD_CREATE_SA			0x34
+#define	TXP_CMD_DELETE_SA			0x35
+#define	TXP_CMD_ENABLE_RX_IP_OPTION		0x36
+#define	TXP_CMD_RANDOM_NUMBER_CONTROL		0x37
+#define	TXP_CMD_RANDOM_NUMBER_READ		0x38
+#define	TXP_CMD_MATRIX_TABLE_MODE_WRITE		0x39
+#define	TXP_CMD_MATRIX_DETAIL_READ		0x3a
+#define	TXP_CMD_FILTER_ARRAY_READ		0x3b
+#define	TXP_CMD_FILTER_DETAIL_READ		0x3c
+#define	TXP_CMD_FILTER_TABLE_MODE_WRITE		0x3d
+#define	TXP_CMD_FILTER_TCL_WRITE		0x3e
+#define	TXP_CMD_FILTER_TBL_READ			0x3f
+#define	TXP_CMD_FILTER_DEFINE			0x45
+#define	TXP_CMD_ADD_WAKEUP_PKT			0x46
+#define	TXP_CMD_ADD_SLEEP_PKT			0x47
+#define	TXP_CMD_ENABLE_SLEEP_EVENTS		0x48
+#define	TXP_CMD_ENABLE_WAKEUP_EVENTS		0x49
+#define	TXP_CMD_GET_IP_ADDRESS			0x4a
+#define	TXP_CMD_READ_PCI_REG			0x4c
+#define	TXP_CMD_WRITE_PCI_REG			0x4d
+#define	TXP_CMD_OFFLOAD_WRITE			0x4f
+#define	TXP_CMD_HELLO_RESPONSE			0x57
+#define	TXP_CMD_ENABLE_RX_FILTER		0x58
+#define	TXP_CMD_RX_FILTER_CAPABILITY		0x59
+#define	TXP_CMD_HALT				0x5d
+#define	TXP_CMD_INVALID				0xffff
+
+#define	TXP_FRAGMENT		0x0000
+#define	TXP_TXFRAME		0x0001
+#define	TXP_COMMAND		0x0002
+#define	TXP_OPTION		0x0003
+#define	TXP_RECEIVE		0x0004
+#define	TXP_RESPONSE		0x0005
+
+#define	TXP_TYPE_IPSEC		0x0000
+#define	TXP_TYPE_TCPSEGMENT	0x0001
+
+#define	TXP_PFLAG_NOCRC		0x0000
+#define	TXP_PFLAG_IPCKSUM	0x0001
+#define	TXP_PFLAG_TCPCKSUM	0x0002
+#define	TXP_PFLAG_TCPSEGMENT	0x0004
+#define	TXP_PFLAG_INSERTVLAN	0x0008
+#define	TXP_PFLAG_IPSEC		0x0010
+#define	TXP_PFLAG_PRIORITY	0x0020
+#define	TXP_PFLAG_UDPCKSUM	0x0040
+#define	TXP_PFLAG_PADFRAME	0x0080
+
+#define	TXP_MISC_FIRSTDESC	0x0000
+#define	TXP_MISC_LASTDESC	0x0001
+
+#define	TXP_ERR_INTERNAL	0x0000
+#define	TXP_ERR_FIFOUNDERRUN	0x0001
+#define	TXP_ERR_BADSSD		0x0002
+#define	TXP_ERR_RUNT		0x0003
+#define	TXP_ERR_CRC		0x0004
+#define	TXP_ERR_OVERSIZE	0x0005
+#define	TXP_ERR_ALIGNMENT	0x0006
+#define	TXP_ERR_DRIBBLEBIT	0x0007
+
+#define	TXP_PROTO_UNKNOWN	0x0000
+#define	TXP_PROTO_IP		0x0001
+#define	TXP_PROTO_IPX		0x0002
+#define	TXP_PROTO_RESERVED	0x0003
+
+#define	TXP_STAT_PROTO		0x0001
+#define	TXP_STAT_VLAN		0x0002
+#define	TXP_STAT_IPFRAGMENT	0x0004
+#define	TXP_STAT_IPSEC		0x0008
+#define	TXP_STAT_IPCKSUMBAD	0x0010
+#define	TXP_STAT_TCPCKSUMBAD	0x0020
+#define	TXP_STAT_UDPCKSUMBAD	0x0040
+#define	TXP_STAT_IPCKSUMGOOD	0x0080
+#define	TXP_STAT_TCPCKSUMGOOD	0x0100
+#define	TXP_STAT_UDPCKSUMGOOD	0x0200
 
 struct txp_tx_desc {
 	u_int8_t		tx_desctype:3,
@@ -298,18 +331,42 @@ struct txp_resp_desc {
 
 
 /*
- * TYPHOON status register state
+ * TYPHOON status register state (in TXP_A2H_0)
  */
-#define	TYPHOON_WAITING_FOR_BOOT		0x00000007
-#define	TYPHOON_RUNNING				0x00000009
-#define	TYPHOON_WAITING_FOR_HOST_REQUEST	0x0000000D
-#define	TYPHOON_WAITING_FOR_SEGMENT		0x00000010
-#define	TYPHOON_SLEEPING			0x00000011
-#define	TYPHOON_HALTED				0x00000014
-
-
-/* Random stuff... */
-#define TYPHOON_INT_ARM2HOST_COMM_0     0x00000002
-#define TYPHOON_BOOTCOMMAND_RUNTIME_IMAGE              0xFD
-#define TYPHOON_BOOTCOMMAND_DOWNLOAD_COMPLETE          0xFB
-#define TYPHOON_BOOTCOMMAND_SEGMENT_AVAILABLE          0xFC
+#define	STAT_ROM_CODE			0x00000001
+#define	STAT_ROM_EEPROM_LOAD		0x00000002
+#define	STAT_WAITING_FOR_BOOT		0x00000007
+#define	STAT_RUNNING			0x00000009
+#define	STAT_WAITING_FOR_HOST_REQUEST	0x0000000D
+#define	STAT_WAITING_FOR_SEGMENT	0x00000010
+#define	STAT_SLEEPING			0x00000011
+#define	STAT_HALTED			0x00000014
+
+struct txp_softc {
+	struct device		sc_dev;
+	void *			sc_ih;
+	bus_space_handle_t	sc_bh;
+	bus_space_tag_t		sc_bt;
+	bus_dma_tag_t		sc_dmat;
+	struct arpcom		sc_arpcom;
+	struct timeout		sc_tick_tmo;
+};
+
+struct txp_fw_file_header {
+	u_int8_t	magicid[8];	/* TYPHOON\0 */
+	u_int32_t	version;
+	u_int32_t	nsections;
+	u_int32_t	addr;
+};
+
+struct txp_fw_section_header {
+	u_int32_t	nbytes;
+	u_int16_t	cksum;
+	u_int16_t	reserved;
+	u_int32_t	addr;
+};
+
+#define	WRITE_REG(sc,reg,val) \
+    bus_space_write_4((sc)->sc_bt, (sc)->sc_bh, reg, val)
+#define	READ_REG(sc,reg) \
+    bus_space_read_4((sc)->sc_bt, (sc)->sc_bh, reg)