First support for 53c1010 chip. This enables support up to U2W for

either or both channels on the 53c1010. U3W/U160 support coming.

The particulars of 53c1010 support was derived from the FreeBSD/Linux
sym-2 driver under development by Gerard ROUDIER (groudier@FreeBSD.org).

This first support ensures that registers and bits now reserved are
not used by the 53c1010. It uses the new DFBC register to obtain
DMA FIFO relics.

A single new feature (SF_CHIP_C10) was added, rather than a new
feature for each change the 53c1010 incorporates.

These changes were sufficient to get the imbedded 53c1010 on a Tyan
S2510U3NG board to support installation of OpenBSD to a Quantum Atlas
10K2 drive, and several subsequent 'make build' and 'make release'
cycles using disks on both channels, with and without
softupdates.

More 53c1010 specific code is yet to be extracted from sym-2,
including the changes necessary to enable U160.

4 files changed, 50 insertions, 25 deletions

diff --git a/sys/dev/ic/siop_common.c b/sys/dev/ic/siop_common.c
index fc569695f60..47e1fd813c9 100644
--- a/sys/dev/ic/siop_common.c
+++ b/sys/dev/ic/siop_common.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: siop_common.c,v 1.4 2001/03/06 16:29:32 krw Exp $ */
+/*	$OpenBSD: siop_common.c,v 1.5 2001/03/10 05:04:06 krw Exp $ */
 /*	$NetBSD: siop_common.c,v 1.12 2001/02/11 18:04:50 bouyer Exp $	*/
 
 /*
@@ -93,7 +93,7 @@ siop_common_reset(sc)
 		stest3 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_STEST3);
 		bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST1,
 		    STEST1_DBLEN);
-		if (sc->features & SF_CHIP_QUAD) {
+		if ((sc->features & (SF_CHIP_QUAD | SF_CHIP_C10)) == SF_CHIP_QUAD) {
 			/* wait for PPL to lock */
 			while ((bus_space_read_1(sc->sc_rt, sc->sc_rh,
 			    SIOP_STEST4) & STEST4_LOCK) == 0)
@@ -297,7 +297,8 @@ siop_sdtr_neg(siop_cmd)
 				/* ok, found it. we now are sync. */
 				sc->targets[target]->id |= scf_period[i].scf
 				    << (24 + SCNTL3_SCF_SHIFT);
-				if (sync < 25) /* Ultra */
+				if ((sync < 25)
+				    && ((sc->features & SF_CHIP_C10) == 0))
 					sc->targets[target]->id |=
 					    SCNTL3_ULTRA << 24;
 				sc->targets[target]->id |=
@@ -335,7 +336,8 @@ reject:
 				/* ok, found it. we now are sync. */
 				sc->targets[target]->id |= scf_period[i].scf
 				    << (24 + SCNTL3_SCF_SHIFT);
-				if (sync < 25) /* Ultra */
+				if ((sync < 25)
+				    && ((sc->features & SF_CHIP_C10) == 0))
 					sc->targets[target]->id |=
 					    SCNTL3_ULTRA << 24;
 				sc->targets[target]->id |=
@@ -432,26 +434,32 @@ siop_sdp(siop_cmd)
 	dbc = bus_space_read_4(sc->sc_rt, sc->sc_rh, SIOP_DBC) & 0x00ffffff;
 	if (siop_cmd->xs->flags & SCSI_DATA_OUT) {
 		/* need to account for stale data in FIFO */
-		int dfifo = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_DFIFO);
-		if (sc->features & SF_CHIP_FIFO) {
-			dfifo |= (bus_space_read_1(sc->sc_rt, sc->sc_rh,
-			    SIOP_CTEST5) & CTEST5_BOMASK) << 8;
-			dbc += (dfifo - (dbc & 0x3ff)) & 0x3ff;
-		} else {
-			dbc += (dfifo - (dbc & 0x7f)) & 0x7f;
+		if (sc->features & SF_CHIP_C10)
+			dbc += bus_space_read_2(sc->sc_rt, sc->sc_rh, SIOP_DFBC);
+		else {
+			int dfifo = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_DFIFO);
+			if (sc->features & SF_CHIP_FIFO) {
+				dfifo |= (bus_space_read_1(sc->sc_rt, sc->sc_rh,
+					      SIOP_CTEST5) & CTEST5_BOMASK) << 8;
+				dbc += (dfifo - (dbc & 0x3ff)) & 0x3ff;
+			} else {
+				dbc += (dfifo - (dbc & 0x7f)) & 0x7f;
+			}
 		}
 		sstat = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SSTAT0);
 		if (sstat & SSTAT0_OLF)
 			dbc++;
-		if (sstat & SSTAT0_ORF)
-			dbc++;
+		if ((sc->features & SF_CHIP_C10) == 0)
+			if (sstat & SSTAT0_ORF)
+				dbc++;
 		if (siop_cmd->siop_target->flags & TARF_ISWIDE) {
 			sstat = bus_space_read_1(sc->sc_rt, sc->sc_rh,
 			    SIOP_SSTAT2);
 			if (sstat & SSTAT2_OLF1)
 				dbc++;
-			if (sstat & SSTAT2_ORF1)
-				dbc++;
+			if ((sc->features & SF_CHIP_C10) == 0)
+				if (sstat & SSTAT2_ORF1)
+					dbc++;
 		}
 		/* clear the FIFO */
 		bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3,
@@ -514,10 +522,16 @@ siop_modechange(sc)
 		stest2 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_STEST2);
 		switch(stest4) {
 		case STEST4_MODE_DIF:
-			printf("%s: switching to differential mode\n",
-			    sc->sc_dev.dv_xname);
-			bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST2,
-			    stest2 | STEST2_DIF);
+			if (sc->features & SF_CHIP_C10) {
+				printf("%s: invalid SCSI mode 0x%x\n",
+				    sc->sc_dev.dv_xname, stest4);
+				return 0;
+			} else {
+				printf("%s: switching to differential mode\n",
+				    sc->sc_dev.dv_xname);
+				bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST2,
+				    stest2 | STEST2_DIF);
+			}
 			break;
 		case STEST4_MODE_SE:
 			printf("%s: switching to single-ended mode\n",
diff --git a/sys/dev/ic/siopreg.h b/sys/dev/ic/siopreg.h
index 739afca27f5..dc02816b7c4 100644
--- a/sys/dev/ic/siopreg.h
+++ b/sys/dev/ic/siopreg.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: siopreg.h,v 1.1 2001/02/15 04:07:58 krw Exp $ */
+/*	$OpenBSD: siopreg.h,v 1.2 2001/03/10 05:04:06 krw Exp $ */
 /*	$NetBSD: siopreg.h,v 1.7 2000/10/06 16:35:13 bouyer Exp $	*/
 
 /*
@@ -375,3 +375,5 @@ static const struct scf_period scf_period[] __attribute__((__unused__)) = {
 #define SIOP_SCRATCHI	0x78 /* Scratch register I, R/W, 875-only */
 
 #define SIOP_SCRATCHJ	0x7c /* Scratch register J, R/W, 875-only */
+
+#define SIOP_DFBC	0xf0 /* DMA FIFO byte count, RO, C10-only */
diff --git a/sys/dev/ic/siopvar.h b/sys/dev/ic/siopvar.h
index e63d7a47ef0..b5ca1393cb1 100644
--- a/sys/dev/ic/siopvar.h
+++ b/sys/dev/ic/siopvar.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: siopvar.h,v 1.2 2001/03/01 17:14:28 krw Exp $ */
+/*	$OpenBSD: siopvar.h,v 1.3 2001/03/10 05:04:06 krw Exp $ */
 /*	$NetBSD: siopvar.h,v 1.13 2000/10/23 23:18:11 bouyer Exp $	*/
 
 /*
@@ -88,6 +88,7 @@ struct siop_softc {
 #define SF_CHIP_RAM	0x00002000 /* on-board RAM */
 #define SF_CHIP_LS	0x00004000 /* load/store instruction */
 #define SF_CHIP_10REGS	0x00008000 /* 10 scratch registers */
+#define SF_CHIP_C10	0x00010000 /* 1010 or variant */
 
 #define SF_PCI_RL	0x01000000 /* PCI read line */
 #define SF_PCI_RM	0x02000000 /* PCI read multiple */
diff --git a/sys/dev/pci/siop_pci_common.c b/sys/dev/pci/siop_pci_common.c
index 2a6ffec49bc..72f34553d5c 100644
--- a/sys/dev/pci/siop_pci_common.c
+++ b/sys/dev/pci/siop_pci_common.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: siop_pci_common.c,v 1.3 2001/03/01 17:14:28 krw Exp $ */
+/*	$OpenBSD: siop_pci_common.c,v 1.4 2001/03/10 05:04:06 krw Exp $ */
 /*	$NetBSD: siop_pci_common.c,v 1.6 2001/01/10 15:50:20 thorpej Exp $	*/
 
 /*
@@ -132,7 +132,7 @@ const struct siop_product_desc siop_products[] = {
 	SF_BUS_ULTRA2 | SF_BUS_WIDE,
 	7, 31, 7, 62, 4096
 	},
-	{ PCI_PRODUCT_SYMBIOS_896,
+	{ PCI_PRODUCT_SYMBIOS_895A,
 	0x00,
 	SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM |
 	SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_QUAD |
@@ -140,7 +140,7 @@ const struct siop_product_desc siop_products[] = {
 	SF_BUS_ULTRA2 | SF_BUS_WIDE,
 	7, 31, 7, 62, 8192
 	},
-	{ PCI_PRODUCT_SYMBIOS_895A,
+	{ PCI_PRODUCT_SYMBIOS_896,
 	0x00,
 	SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM |
 	SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_QUAD |
@@ -148,6 +148,14 @@ const struct siop_product_desc siop_products[] = {
 	SF_BUS_ULTRA2 | SF_BUS_WIDE,
 	7, 31, 7, 62, 8192
 	},
+	{ PCI_PRODUCT_SYMBIOS_1010,
+	0x00,
+	SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM |
+	SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_QUAD |
+	SF_CHIP_LS | SF_CHIP_10REGS | SF_CHIP_C10 |
+	SF_BUS_ULTRA2 | SF_BUS_WIDE,
+	7, 31, 0, 62, 8192
+	},
 	{ PCI_PRODUCT_SYMBIOS_1510D,
 	0x00,
 	SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM |
@@ -317,7 +325,7 @@ siop_pci_reset(sc)
 		ctest5 &= ~CTEST5_BBCK;
 		ctest5 |= (sc->maxburst - 1) & CTEST5_BBCK;
 		bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST5, ctest5);
-	} else {
+	} else if ((sc->features & SF_CHIP_C10) == 0) {
 		bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST4,
 		    bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST4) |
 		    CTEST4_BDIS);