diff options
| author | Jonathan Gray <jsg@cvs.openbsd.org> | 2006-01-05 05:40:36 +0000 |
|---|---|---|
| committer | Jonathan Gray <jsg@cvs.openbsd.org> | 2006-01-05 05:40:36 +0000 |
| commit | ce0e39feed1c1997221d24d6f8d3ca69dd8d41bf (patch) | |
| tree | c90e82602479e471d6832268a0516a7f948612d5 /sys | |
| parent | 275e5a4c78f35d4b0aa9cfd4d9e5346e8fc0c513 (diff) | |
rev 1.59 & 1.60 of rtw.c commited by David Young to NetBSD:
On a transmit FIFO overflow (err, actually an underflow...) reset
both the transmit & receive sections of the MAC.
Fix comments and debug printfs: Tx FIFOs underflow, they don't
overflow.
Diffstat (limited to 'sys')
| -rw-r--r-- | sys/dev/ic/rtw.c | 9 | ||||
| -rw-r--r-- | sys/dev/ic/rtwreg.h | 4 |
2 files changed, 6 insertions, 7 deletions
diff --git a/sys/dev/ic/rtw.c b/sys/dev/ic/rtw.c index 90736291103..232e4c80147 100644 --- a/sys/dev/ic/rtw.c +++ b/sys/dev/ic/rtw.c @@ -1,4 +1,4 @@ -/* $OpenBSD: rtw.c,v 1.51 2006/01/05 05:36:05 jsg Exp $ */ +/* $OpenBSD: rtw.c,v 1.52 2006/01/05 05:40:35 jsg Exp $ */ /* $NetBSD: rtw.c,v 1.29 2004/12/27 19:49:16 dyoung Exp $ */ /*- @@ -1736,14 +1736,13 @@ rtw_intr_ioerror(struct rtw_softc *sc, u_int16_t isr) if ((isr & RTW_INTR_TXFOVW) != 0) { RTW_DPRINTF(RTW_DEBUG_BUGS, ("%s: tx fifo underflow\n", sc->sc_dev.dv_xname)); - xmtr = 1; - cr |= RTW_CR_TE; + rcvr = xmtr = 1; + cr |= RTW_CR_TE | RTW_CR_RE; } if ((isr & (RTW_INTR_RDU|RTW_INTR_RXFOVW)) != 0) { - cr = RTW_CR_RE; + cr |= RTW_CR_RE; rcvr = 1; - return; } RTW_DPRINTF(RTW_DEBUG_BUGS, ("%s: restarting xmit/recv, isr %hx" diff --git a/sys/dev/ic/rtwreg.h b/sys/dev/ic/rtwreg.h index f4efc6b1f1e..7fb9fdfb94d 100644 --- a/sys/dev/ic/rtwreg.h +++ b/sys/dev/ic/rtwreg.h @@ -1,4 +1,4 @@ -/* $OpenBSD: rtwreg.h,v 1.12 2006/01/05 05:36:06 jsg Exp $ */ +/* $OpenBSD: rtwreg.h,v 1.13 2006/01/05 05:40:35 jsg Exp $ */ /* $NetBSD: rtwreg.h,v 1.12 2005/01/16 11:50:43 dyoung Exp $ */ /*- * Copyright (c) 2004, 2005 David Young. All rights reserved. @@ -188,7 +188,7 @@ #define RTW_IMR 0x3c /* Interrupt Mask Register, 16b */ #define RTW_ISR 0x3e /* Interrupt status register, 16b */ -#define RTW_INTR_TXFOVW BIT(15) /* Tx FIFO Overflow */ +#define RTW_INTR_TXFOVW BIT(15) /* Tx FIFO underrflow */ #define RTW_INTR_TIMEOUT BIT(14) /* Time Out: 1 indicates * RTW_TSFTR[0:31] = RTW_TINT */ |