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authorgrr <grr@cvs.openbsd.org>1997-07-01 23:35:58 +0000
committergrr <grr@cvs.openbsd.org>1997-07-01 23:35:58 +0000
commitdca688188bd57dae39774c80974f2ef083a8c742 (patch)
tree252903baa3e95477306ce2d605b55d7da1a91c9d /sys
parent874e4aae8603822e3d4a7115d88aec94f85276cd (diff)
gestures in the direction of TurboSpPARC compatibility
Diffstat (limited to 'sys')
-rw-r--r--sys/arch/sparc/include/trap.h17
-rw-r--r--sys/arch/sparc/sparc/locore.s28
-rw-r--r--sys/arch/sparc/sparc/trap.c25
3 files changed, 52 insertions, 18 deletions
diff --git a/sys/arch/sparc/include/trap.h b/sys/arch/sparc/include/trap.h
index 86c45589f80..b2cde2ecc25 100644
--- a/sys/arch/sparc/include/trap.h
+++ b/sys/arch/sparc/include/trap.h
@@ -52,6 +52,15 @@
#ifndef _MACHINE_TRAP_H
#define _MACHINE_TRAP_H
+/*
+ * vectors 0x00..0x1f are common to all sparc implementations, while
+ * vectors 0x20..0x2f are selectively implemented by some v8 cpu's
+ * either to support new instructions or simplify fault decoding.
+ * For sanity, these defines should match the layout of the trap
+ * table, but some cases may be treated in common. The priorities
+ * listed are correct, but the v8 traps been inserted "between levels".
+ */
+
/* trap vec (pri) description */
#define T_RESET 0x00 /* (1) not actually vectored; jumps to 0 */
#define T_TEXTFAULT 0x01 /* (2) address fault during instr fetch */
@@ -85,14 +94,16 @@
#define T_L13INT 0x1d /* (15) level 13 interrupt */
#define T_L14INT 0x1e /* (14) level 14 interrupt */
#define T_L15INT 0x1f /* (13) level 15 interrupt */
-/* 0x20 unused */
+#define T_RREGERROR 0x20 /* (?) r-register access error (v8?) */
+#define T_TEXTERROR 0x21 /* (<2) error during instruction access (v8) */
+/* 0x22 unused */
/* through 0x23 unused */
#define T_CPDISABLED 0x24 /* (5) coprocessor instr while disabled */
/* 0x25 unused */
/* through 0x27 unused */
#define T_CPEXCEPTION 0x28 /* (9) coprocessor exception */
-/* 0x29 unused */
-/* through 0x2a unused */
+#define T_DATAERROR 0x29 /* (<9) error during data access (v8) */
+#define T_IDIV0 0x2a /* (<11) integer divide by zero (v8) */
#define T_STOREBUFFAULT 0x2b /* SuperSPARC: Store buffer copy-back fault */
/* 0x2c unused */
/* through 0x7f unused */
diff --git a/sys/arch/sparc/sparc/locore.s b/sys/arch/sparc/sparc/locore.s
index e97b49ba460..4826e06aa56 100644
--- a/sys/arch/sparc/sparc/locore.s
+++ b/sys/arch/sparc/sparc/locore.s
@@ -924,18 +924,18 @@ trapbase_sun4m:
HARDINT4M(13) ! 1d = level 13 interrupt
HARDINT4M(14) ! 1e = level 14 interrupt
VTRAP(15, nmi_sun4m) ! 1f = nonmaskable interrupt
- UTRAP(0x20)
- UTRAP(0x21)
+ UTRAP(0x20) ! 20 = r-reg access error ???
+ VTRAP(T_TEXTFAULT, memfault_sun4m) ! 21 = v8 instr. fetch error
UTRAP(0x22)
UTRAP(0x23)
- TRAP(T_CPDISABLED) ! 24 = coprocessor instr, EC bit off in psr
- UTRAP(0x25)
+ TRAP(T_CPDISABLED) ! 24 = coprocessor instr, EC off
+ UTRAP(0x25) ! 25 = unimplemented cache flush
UTRAP(0x26)
UTRAP(0x27)
- TRAP(T_CPEXCEPTION) ! 28 = coprocessor exception
- UTRAP(0x29)
- UTRAP(0x2a)
- VTRAP(T_STOREBUFFAULT, memfault_sun4m) ! 2b = SuperSPARC store buffer fault
+ TRAP(T_CPEXCEPTION) ! 28 = coprocessor exception
+ VTRAP(T_DATAFAULT, memfault_sun4m) ! 29 = v8 data fetch error
+ TRAP(T_DIV0) ! 2a = v8 int divide by zero
+ VTRAP(T_STOREBUFFAULT, memfault_sun4m) ! 2b = SS store buffer fault
UTRAP(0x2c)
UTRAP(0x2d)
UTRAP(0x2e)
@@ -3779,6 +3779,11 @@ _sigcode:
1:
ldd [%fp + 64], %o0 ! sig, code
ld [%fp + 76], %o3 ! arg3
+#ifdef SIG_DEBUG
+ subcc %o0, 32, %g0 ! signals are 1-32
+ bgu _suicide
+ nop
+#endif
call %g1 ! (*sa->sa_handler)(sig,code,scp,arg3)
add %fp, 64 + 16, %o2 ! scp
@@ -3822,6 +3827,13 @@ _sigcode:
! sigreturn does not return unless it fails
mov SYS_exit, %g1 ! exit(errno)
t ST_SYSCALL
+
+#ifdef SIG_DEBUG
+ .globl _suicide
+_suicide:
+ mov 139, %g1 ! obsolete syscall, puke...
+ t ST_SYSCALL
+#endif
_esigcode:
#ifdef COMPAT_SVR4
diff --git a/sys/arch/sparc/sparc/trap.c b/sys/arch/sparc/sparc/trap.c
index d3ebb6efb61..f23f537381e 100644
--- a/sys/arch/sparc/sparc/trap.c
+++ b/sys/arch/sparc/sparc/trap.c
@@ -109,6 +109,11 @@ struct fpstate initfpstate = {
*
* Trap type 0 is taken over as an `Asynchronous System Trap'.
* This is left-over Vax emulation crap that should be fixed.
+ *
+ * Note that some of the Sparc v8 traps are actually handled by
+ * the corresponding v7 routine, but listed here for completeness.
+ * The Fujitsu Turbo-Sparc Guide also alludes to several more
+ * unimplemented trap types, but doesn't give the nominal coding.
*/
static const char T[] = "trap";
const char *trap_type[] = {
@@ -140,14 +145,20 @@ const char *trap_type[] = {
"level 13 int", /* 1d */
"level 14 int", /* 1e */
"level 15 int", /* 1f */
- T, T, T, T, T, T, T, T, /* 20..27 */
- T, T, T, T, T, T, T, T, /* 28..2f */
- T, T, T, T, T, T, /* 30..35 */
- "cp disabled", /* 36 */
- T, /* 37 */
+ "v8 r-reg error", /* 20 */
+ "v8 text error", /* 21 */
+ T, T, /* 22..23 */
+ "v8 cp disabled", /* 24 */
+ "v8 unimp flush", /* 25 */
+ T, T, /* 26..27 */
+ "v8 cp exception", /* 28 */
+ "v8 data error", /* 29 */
+ "v8 idiv by zero", /* 2a */
+ "v8 store error", /* 2b */
+ T, T, T, T, /* 2c..2f */
+ T, T, T, T, T, T, T, T, /* 30..37 */
T, T, T, T, T, T, T, T, /* 38..3f */
- "cp exception", /* 40 */
- T, T, T, T, T, T, T, /* 41..47 */
+ T, T, T, T, T, T, T, T, /* 40..48 */
T, T, T, T, T, T, T, T, /* 48..4f */
T, T, T, T, T, T, T, T, /* 50..57 */
T, T, T, T, T, T, T, T, /* 58..5f */