Print out cache sizes on newer G4 processors. Partially from NetBSD.

1 files changed, 35 insertions, 20 deletions

diff --git a/sys/arch/macppc/macppc/cpu.c b/sys/arch/macppc/macppc/cpu.c
index ba87ca34cc0..a8ef9c5d117 100644
--- a/sys/arch/macppc/macppc/cpu.c
+++ b/sys/arch/macppc/macppc/cpu.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: cpu.c,v 1.4 2002/03/21 17:37:57 drahn Exp $ */
+/*	$OpenBSD: cpu.c,v 1.5 2002/04/29 00:00:02 drahn Exp $ */
 
 /*
  * Copyright (c) 1997 Per Fogelstrom
@@ -76,7 +76,7 @@ struct cfdriver cpu_cd = {
 	NULL, "cpu", DV_DULL, NULL, 0
 };
 
-void config_l2cr(void);
+void config_l2cr(int cpu);
 
 int
 cpumatch(parent, cfdata, aux)
@@ -193,10 +193,9 @@ cpuattach(parent, dev, aux)
 	asm ("mtspr %0,1008" : "=r" (hid0));
 
 	/* if processor is G3 or G4, configure l2 cache */ 
-	if  ( (cpu == MPC750) || (cpu == MPC7400) 
-		|| (cpu == MPC7410))
-	{
-		config_l2cr();
+	if ( (cpu == MPC750) || (cpu == MPC7400)
+	    || (cpu == MPC7410) || (cpu == MPC7450) || (cpu == MPC7455)) {
+		config_l2cr(cpu);
 	}
 	printf("\n");
 
@@ -244,8 +243,12 @@ u_int l2cr_config = L2CR_CONFIG;
 u_int l2cr_config = 0;
 #endif
 
+#define SPR_L3CR                0x3fa   /* .6. L3 Control Register */
+#define   L3CR_L3E                0x80000000 /*  0: L3 enable */
+#define   L3CR_L3SIZ              0x10000000 /*  3: L3 size (0=1MB, 1=2MB) */
+
 void
-config_l2cr()
+config_l2cr(int cpu)
 {
 	u_int l2cr, x;
 
@@ -275,18 +278,31 @@ config_l2cr()
 	}
 
 	if (l2cr & L2CR_L2E) {
-		switch (l2cr & L2CR_L2SIZ) {
-		case L2SIZ_256K:
-			printf(": 256KB");
-			break;
-		case L2SIZ_512K:
-			printf(": 512KB");
-			break;
-		case L2SIZ_1M:  
-			printf(": 1MB");
-			break;
-		default:
-			printf(": unknown size");
+		if (cpu == MPC7450 || cpu == MPC7455) {
+			u_int l3cr;
+
+			printf(": 256KB L2 cache");
+
+			__asm__ volatile("mfspr %0, %1" : "=r"(l3cr) :
+			    "n"(SPR_L3CR) );
+			if (l3cr & L3CR_L3E)
+				printf(", %cMB L3 cache",
+				    l3cr & L3CR_L3SIZ ? '2' : '1');
+		} else {
+			switch (l2cr & L2CR_L2SIZ) {
+			case L2SIZ_256K:
+				printf(": 256KB");
+				break;
+			case L2SIZ_512K:
+				printf(": 512KB");
+				break;
+			case L2SIZ_1M:  
+				printf(": 1MB");
+				break;
+			default:
+				printf(": unknown size");
+			}
+			printf(" backside cache");
 		}
 #if 0
 		switch (l2cr & L2CR_L2RAM) {
@@ -306,7 +322,6 @@ config_l2cr()
 		if (l2cr & L2CR_L2PE)
 			printf(" with parity");  
 #endif
-		printf(" backside cache");
 	} else
 		printf(": L2 cache not enabled");