diff options
| author | Mike Larkin <mlarkin@cvs.openbsd.org> | 2017-08-12 19:53:38 +0000 |
|---|---|---|
| committer | Mike Larkin <mlarkin@cvs.openbsd.org> | 2017-08-12 19:53:38 +0000 |
| commit | 3e618cdd9be541d61738c80e79318c7be022a17b (patch) | |
| tree | 2acd08a13e2aeb27f94089dfc070d33b805512cf /sys | |
| parent | 0988de2a87fa15a2f8b7786566410728fefdbaf8 (diff) | |
add some extra comments that got left out of the previous IA32_MISC_ENABLE
MSR commits
Diffstat (limited to 'sys')
| -rw-r--r-- | sys/arch/amd64/include/specialreg.h | 7 | ||||
| -rw-r--r-- | sys/arch/i386/include/specialreg.h | 7 |
2 files changed, 10 insertions, 4 deletions
diff --git a/sys/arch/amd64/include/specialreg.h b/sys/arch/amd64/include/specialreg.h index 3dca06fe763..40f5d2c7e1e 100644 --- a/sys/arch/amd64/include/specialreg.h +++ b/sys/arch/amd64/include/specialreg.h @@ -1,4 +1,4 @@ -/* $OpenBSD: specialreg.h,v 1.60 2017/08/09 21:23:38 mlarkin Exp $ */ +/* $OpenBSD: specialreg.h,v 1.61 2017/08/12 19:53:37 mlarkin Exp $ */ /* $NetBSD: specialreg.h,v 1.1 2003/04/26 18:39:48 fvdl Exp $ */ /* $NetBSD: x86/specialreg.h,v 1.2 2003/04/25 21:54:30 fvdl Exp $ */ @@ -365,6 +365,9 @@ * Processor event based sampling unavailable: 1 if unsupported (R/O) * Enhanced Intel SpeedStep technology enable: 1 to enable (R/W) * Enable monitor FSM: 1 to enable MONITOR/MWAIT (R/W) + * Limit CPUID maxval: 1 to limit CPUID leaf nodes to 0x2 and lower (R/W) + * Enable xTPR message disable: 1 to disable xTPR messages + * XD bit disable: 1 to disable NX capability (bit 34, or bit 2 of %edx/%rdx) */ #define MISC_ENABLE_FAST_STRINGS (1 << 0) #define MISC_ENABLE_TCC (1 << 3) @@ -375,7 +378,7 @@ #define MISC_ENABLE_ENABLE_MONITOR_FSM (1 << 18) #define MISC_ENABLE_LIMIT_CPUID_MAXVAL (1 << 22) #define MISC_ENABLE_xTPR_MESSAGE_DISABLE (1 << 23) -#define MISC_ENABLE_XD_BIT_DISABLE (1 << 34) +#define MISC_ENABLE_XD_BIT_DISABLE (1 << 2) /* * for Core i Series and newer Xeons, see diff --git a/sys/arch/i386/include/specialreg.h b/sys/arch/i386/include/specialreg.h index 07b312a625e..558abf057ce 100644 --- a/sys/arch/i386/include/specialreg.h +++ b/sys/arch/i386/include/specialreg.h @@ -1,4 +1,4 @@ -/* $OpenBSD: specialreg.h,v 1.63 2017/08/09 21:23:38 mlarkin Exp $ */ +/* $OpenBSD: specialreg.h,v 1.64 2017/08/12 19:53:37 mlarkin Exp $ */ /* $NetBSD: specialreg.h,v 1.7 1994/10/27 04:16:26 cgd Exp $ */ /*- @@ -358,6 +358,9 @@ * Processor event based sampling unavailable: 1 if unsupported (R/O) * Enhanced Intel SpeedStep technology enable: 1 to enable (R/W) * Enable monitor FSM: 1 to enable MONITOR/MWAIT (R/W) + * Limit CPUID maxval: 1 to limit CPUID leaf nodes to 0x2 and lower (R/W) + * Enable xTPR message disable: 1 to disable xTPR messages + * XD bit disable: 1 to disable NX capability (bit 34, or bit 2 of %edx/%rdx) */ #define MISC_ENABLE_FAST_STRINGS (1 << 0) #define MISC_ENABLE_TCC (1 << 3) @@ -368,7 +371,7 @@ #define MISC_ENABLE_ENABLE_MONITOR_FSM (1 << 18) #define MISC_ENABLE_LIMIT_CPUID_MAXVAL (1 << 22) #define MISC_ENABLE_xTPR_MESSAGE_DISABLE (1 << 23) -#define MISC_ENABLE_XD_BIT_DISABLE (1 << 34) +#define MISC_ENABLE_XD_BIT_DISABLE (1 << 2) /* * for Core i Series and newer Xeons, see * http://www.intel.com/content/dam/www/public/us/en/ |