diff options
| author | Miod Vallat <miod@cvs.openbsd.org> | 2009-10-14 21:26:55 +0000 |
|---|---|---|
| committer | Miod Vallat <miod@cvs.openbsd.org> | 2009-10-14 21:26:55 +0000 |
| commit | bd565b860ae1095570a3f9d924ccc6f3c9d8614a (patch) | |
| tree | 9d9cb76f17c8c77e0f9b5f44d0038bfde1c7c7d9 /sys | |
| parent | b6601794a3e3b5f17205ccc2f9bebd7888790ce3 (diff) | |
On coherent systems, all bus_dmamap_sync() needs to do is writebacks, no
invalidation is necessary. Help jsing@
Diffstat (limited to 'sys')
| -rw-r--r-- | sys/arch/sgi/sgi/bus_dma.c | 39 |
1 files changed, 14 insertions, 25 deletions
diff --git a/sys/arch/sgi/sgi/bus_dma.c b/sys/arch/sgi/sgi/bus_dma.c index a9f52aa0194..19c177a3c23 100644 --- a/sys/arch/sgi/sgi/bus_dma.c +++ b/sys/arch/sgi/sgi/bus_dma.c @@ -1,4 +1,4 @@ -/* $OpenBSD: bus_dma.c,v 1.14 2009/07/17 18:06:51 miod Exp $ */ +/* $OpenBSD: bus_dma.c,v 1.15 2009/10/14 21:26:54 miod Exp $ */ /* * Copyright (c) 2003-2004 Opsycon AB (www.opsycon.se / www.opsycon.com) @@ -316,15 +316,6 @@ _dmamap_sync(bus_dma_tag_t t, bus_dmamap_t map, bus_addr_t addr, nsegs = map->dm_nsegs; curseg = 0; -#ifdef DEBUG_BUSDMASYNC - printf("dmasync %p:%p:%p:", map, addr, size); - if (op & BUS_DMASYNC_PREWRITE) printf("PRW "); - if (op & BUS_DMASYNC_PREREAD) printf("PRR "); - if (op & BUS_DMASYNC_POSTWRITE) printf("POW "); - if (op & BUS_DMASYNC_POSTREAD) printf("POR "); - printf("\n"); -#endif - while (size && nsegs) { bus_addr_t vaddr; bus_size_t ssize; @@ -351,29 +342,27 @@ _dmamap_sync(bus_dma_tag_t t, bus_dmamap_t map, bus_addr_t addr, } if (ssize != 0) { -#ifdef DEBUG_BUSDMASYNC_FRAG - printf(" syncing %p:%p ", vaddr, ssize); - if (op & BUS_DMASYNC_PREWRITE) printf("PRW "); - if (op & BUS_DMASYNC_PREREAD) printf("PRR "); - if (op & BUS_DMASYNC_POSTWRITE) printf("POW "); - if (op & BUS_DMASYNC_POSTREAD) printf("POR "); - printf("\n"); -#endif /* - * If only PREWRITE is requested, writeback and - * invalidate. PREWRITE with PREREAD writebacks - * and invalidates *all* cache levels. - * Otherwise, just invalidate. - * POSTREAD and POSTWRITE are no-ops since - * we are not bouncing data. + * If only PREWRITE is requested, writeback. + * PREWRITE with PREREAD writebacks + * and invalidates (if noncoherent) *all* cache levels. + * Otherwise, just invalidate (if noncoherent). */ if (op & BUS_DMASYNC_PREWRITE) { +#ifdef TGT_COHERENT + Mips_IOSyncDCache(vaddr, ssize, SYNC_W); +#else if (op & BUS_DMASYNC_PREREAD) Mips_IOSyncDCache(vaddr, ssize, SYNC_X); else Mips_IOSyncDCache(vaddr, ssize, SYNC_W); - } else if (op & (BUS_DMASYNC_PREREAD|BUS_DMASYNC_POSTREAD)) { +#endif + } else + if (op & (BUS_DMASYNC_PREREAD | BUS_DMASYNC_POSTREAD)) { +#ifdef TGT_COHERENT +#else Mips_IOSyncDCache(vaddr, ssize, SYNC_R); +#endif } size -= ssize; } |