diff options
| author | Patrick Wildt <patrick@cvs.openbsd.org> | 2023-07-08 08:37:40 +0000 |
|---|---|---|
| committer | Patrick Wildt <patrick@cvs.openbsd.org> | 2023-07-08 08:37:40 +0000 |
| commit | e137e1c108ebc89c788dedc9dc5a02455178f421 (patch) | |
| tree | c255abded5a76182052d56866d8604124d679864 /sys | |
| parent | e8aad34d35a3c2078ef6d39ce1a0a22db7a5d6aa (diff) | |
Add some resets for the PCIe controllers on the RK3588.
ok kettenis@
Diffstat (limited to 'sys')
| -rw-r--r-- | sys/dev/fdt/rkclock.c | 38 | ||||
| -rw-r--r-- | sys/dev/fdt/rkclock_clocks.h | 9 |
2 files changed, 46 insertions, 1 deletions
diff --git a/sys/dev/fdt/rkclock.c b/sys/dev/fdt/rkclock.c index cbe3a9c3ee6..d11c1049e99 100644 --- a/sys/dev/fdt/rkclock.c +++ b/sys/dev/fdt/rkclock.c @@ -1,4 +1,4 @@ -/* $OpenBSD: rkclock.c,v 1.80 2023/07/07 16:53:39 patrick Exp $ */ +/* $OpenBSD: rkclock.c,v 1.81 2023/07/08 08:37:39 patrick Exp $ */ /* * Copyright (c) 2017, 2018 Mark Kettenis <kettenis@openbsd.org> * @@ -4388,10 +4388,42 @@ rk3588_reset(void *cookie, uint32_t *cells, int on) uint32_t bit, mask, reg; switch (idx) { + case RK3588_SRST_PCIE0_POWER_UP: + reg = RK3588_CRU_SOFTRST_CON(32); + bit = 13; + break; + case RK3588_SRST_PCIE1_POWER_UP: + reg = RK3588_CRU_SOFTRST_CON(32); + bit = 14; + break; + case RK3588_SRST_PCIE2_POWER_UP: + reg = RK3588_CRU_SOFTRST_CON(32); + bit = 15; + break; + case RK3588_SRST_PCIE3_POWER_UP: + reg = RK3588_CRU_SOFTRST_CON(33); + bit = 0; + break; case RK3588_SRST_PCIE4_POWER_UP: reg = RK3588_CRU_SOFTRST_CON(33); bit = 1; break; + case RK3588_SRST_P_PCIE0: + reg = RK3588_CRU_SOFTRST_CON(33); + bit = 12; + break; + case RK3588_SRST_P_PCIE1: + reg = RK3588_CRU_SOFTRST_CON(33); + bit = 13; + break; + case RK3588_SRST_P_PCIE2: + reg = RK3588_CRU_SOFTRST_CON(33); + bit = 14; + break; + case RK3588_SRST_P_PCIE3: + reg = RK3588_CRU_SOFTRST_CON(33); + bit = 15; + break; case RK3588_SRST_P_PCIE4: reg = RK3588_CRU_SOFTRST_CON(34); bit = 0; @@ -4412,6 +4444,10 @@ rk3588_reset(void *cookie, uint32_t *cells, int on) reg = RK3588_PHPTOPCRU_SOFTRST_CON(0); bit = 5; break; + case RK3588_SRST_PCIE30_PHY: + reg = RK3588_PHPTOPCRU_SOFTRST_CON(0); + bit = 10; + break; default: printf("%s: 0x%08x\n", __func__, idx); return; diff --git a/sys/dev/fdt/rkclock_clocks.h b/sys/dev/fdt/rkclock_clocks.h index f4b77278b74..6ca83f5479d 100644 --- a/sys/dev/fdt/rkclock_clocks.h +++ b/sys/dev/fdt/rkclock_clocks.h @@ -477,9 +477,18 @@ #define RK3588_PLL_SPLL 1022 #define RK3588_XIN24M 1023 +#define RK3588_SRST_PCIE0_POWER_UP 294 +#define RK3588_SRST_PCIE1_POWER_UP 295 +#define RK3588_SRST_PCIE2_POWER_UP 296 +#define RK3588_SRST_PCIE3_POWER_UP 297 #define RK3588_SRST_PCIE4_POWER_UP 298 +#define RK3588_SRST_P_PCIE0 299 +#define RK3588_SRST_P_PCIE1 300 +#define RK3588_SRST_P_PCIE2 301 +#define RK3588_SRST_P_PCIE3 302 #define RK3588_SRST_P_PCIE4 303 #define RK3588_SRST_A_USB3OTG0 338 #define RK3588_SRST_A_USB3OTG1 339 #define RK3588_SRST_REF_PIPE_PHY0 572 #define RK3588_SRST_P_PCIE2_PHY0 579 +#define RK3588_SRST_PCIE30_PHY 584 |