drm/amd/display: Expand kernel doc for DC

From Rodrigo Siqueira
6cd736272165d7a6a7d62fb0a40536ed3741ed02 in linux-6.1.y/6.1.66
1682bd1a6b5fb094e914d9b73b711821fd84dcbd in mainline linux

7 files changed, 82 insertions, 3 deletions

diff --git a/sys/dev/pci/drm/amd/display/dc/dc.h b/sys/dev/pci/drm/amd/display/dc/dc.h
index 0dc4a9d1d26..f50e2873048 100644
--- a/sys/dev/pci/drm/amd/display/dc/dc.h
+++ b/sys/dev/pci/drm/amd/display/dc/dc.h
@@ -499,9 +499,12 @@ enum dcn_zstate_support_state {
 	DCN_ZSTATE_SUPPORT_ALLOW_Z10_ONLY,
 	DCN_ZSTATE_SUPPORT_DISALLOW,
 };
-/*
- * For any clocks that may differ per pipe
- * only the max is stored in this structure
+
+/**
+ * dc_clocks - DC pipe clocks
+ *
+ * For any clocks that may differ per pipe only the max is stored in this
+ * structure
  */
 struct dc_clocks {
 	int dispclk_khz;
@@ -528,6 +531,16 @@ struct dc_clocks {
 	bool prev_p_state_change_support;
 	bool fclk_prev_p_state_change_support;
 	int num_ways;
+
+	/**
+	 * @fw_based_mclk_switching
+	 *
+	 * DC has a mechanism that leverage the variable refresh rate to switch
+	 * memory clock in cases that we have a large latency to achieve the
+	 * memory clock change and a short vblank window. DC has some
+	 * requirements to enable this feature, and this field describes if the
+	 * system support or not such a feature.
+	 */
 	bool fw_based_mclk_switching;
 	bool fw_based_mclk_switching_shut_down;
 	int prev_num_ways;
diff --git a/sys/dev/pci/drm/amd/display/dc/dc_stream.h b/sys/dev/pci/drm/amd/display/dc/dc_stream.h
index cb8d2410af2..03f0a39c6f1 100644
--- a/sys/dev/pci/drm/amd/display/dc/dc_stream.h
+++ b/sys/dev/pci/drm/amd/display/dc/dc_stream.h
@@ -202,7 +202,18 @@ struct dc_stream_state {
 	bool use_vsc_sdp_for_colorimetry;
 	bool ignore_msa_timing_param;
 
+	/**
+	 * @allow_freesync:
+	 *
+	 * It say if Freesync is enabled or not.
+	 */
 	bool allow_freesync;
+
+	/**
+	 * @vrr_active_variable:
+	 *
+	 * It describes if VRR is in use.
+	 */
 	bool vrr_active_variable;
 	bool freesync_on_desktop;
 
diff --git a/sys/dev/pci/drm/amd/display/dc/dml/dc_features.h b/sys/dev/pci/drm/amd/display/dc/dml/dc_features.h
index 74e86732e30..2cbdd75429f 100644
--- a/sys/dev/pci/drm/amd/display/dc/dml/dc_features.h
+++ b/sys/dev/pci/drm/amd/display/dc/dml/dc_features.h
@@ -29,6 +29,13 @@
 #define DC__PRESENT 1
 #define DC__PRESENT__1 1
 #define DC__NUM_DPP 4
+
+/**
+ * @DC__VOLTAGE_STATES:
+ *
+ * Define the maximum amount of states supported by the ASIC. Every ASIC has a
+ * specific number of states; this macro defines the maximum number of states.
+ */
 #define DC__VOLTAGE_STATES 20
 #define DC__NUM_DPP__4 1
 #define DC__NUM_DPP__0_PRESENT 1
diff --git a/sys/dev/pci/drm/amd/display/dc/dml/display_mode_enums.h b/sys/dev/pci/drm/amd/display/dc/dml/display_mode_enums.h
index f394b3f3922..0bffae95f3a 100644
--- a/sys/dev/pci/drm/amd/display/dc/dml/display_mode_enums.h
+++ b/sys/dev/pci/drm/amd/display/dc/dml/display_mode_enums.h
@@ -105,14 +105,39 @@ enum source_macro_tile_size {
 enum cursor_bpp {
 	dm_cur_2bit = 0, dm_cur_32bit = 1, dm_cur_64bit = 2
 };
+
+/**
+ * @enum clock_change_support - It represents possible reasons to change the DRAM clock.
+ *
+ * DC may change the DRAM clock during its execution, and this enum tracks all
+ * the available methods. Note that every ASIC has their specific way to deal
+ * with these clock switch.
+ */
 enum clock_change_support {
+	/**
+	 * @dm_dram_clock_change_uninitialized: If you see this, we might have
+	 * a code initialization issue
+	 */
 	dm_dram_clock_change_uninitialized = 0,
+
+	/**
+	 * @dm_dram_clock_change_vactive: Support DRAM switch in VActive
+	 */
 	dm_dram_clock_change_vactive,
+
+	/**
+	 * @dm_dram_clock_change_vblank: Support DRAM switch in VBlank
+	 */
 	dm_dram_clock_change_vblank,
+
 	dm_dram_clock_change_vactive_w_mall_full_frame,
 	dm_dram_clock_change_vactive_w_mall_sub_vp,
 	dm_dram_clock_change_vblank_w_mall_full_frame,
 	dm_dram_clock_change_vblank_w_mall_sub_vp,
+
+	/**
+	 * @dm_dram_clock_change_unsupported: Do not support DRAM switch
+	 */
 	dm_dram_clock_change_unsupported
 };
 
diff --git a/sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h b/sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
index 2b34b02dbd4..81e53e67cd0 100644
--- a/sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
+++ b/sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
@@ -419,6 +419,15 @@ struct vba_vars_st {
 	double MinPixelChunkSizeBytes;
 	unsigned int DCCMetaBufferSizeBytes;
 	// Pipe/Plane Parameters
+
+	/** @VoltageLevel:
+	 * Every ASIC has a fixed number of DPM states, and some devices might
+	 * have some particular voltage configuration that does not map
+	 * directly to the DPM states. This field tells how many states the
+	 * target device supports; even though this field combines the DPM and
+	 * special SOC voltages, it mostly matches the total number of DPM
+	 * states.
+	 */
 	int VoltageLevel;
 	double FabricClock;
 	double DRAMSpeed;
diff --git a/sys/dev/pci/drm/amd/display/dc/inc/core_types.h b/sys/dev/pci/drm/amd/display/dc/inc/core_types.h
index 4a968de5bfc..dbc7f674a6e 100644
--- a/sys/dev/pci/drm/amd/display/dc/inc/core_types.h
+++ b/sys/dev/pci/drm/amd/display/dc/inc/core_types.h
@@ -115,6 +115,13 @@ struct resource_funcs {
 				int vlevel);
 	void (*update_soc_for_wm_a)(
 				struct dc *dc, struct dc_state *context);
+
+	/**
+	 * @populate_dml_pipes - Populate pipe data struct
+	 *
+	 * Returns:
+	 * Total of pipes available in the specific ASIC.
+	 */
 	int (*populate_dml_pipes)(
 		struct dc *dc,
 		struct dc_state *context,
diff --git a/sys/dev/pci/drm/amd/display/dc/inc/hw/hw_shared.h b/sys/dev/pci/drm/amd/display/dc/inc/hw/hw_shared.h
index cd2be729846..a819f0f97c5 100644
--- a/sys/dev/pci/drm/amd/display/dc/inc/hw/hw_shared.h
+++ b/sys/dev/pci/drm/amd/display/dc/inc/hw/hw_shared.h
@@ -35,6 +35,13 @@
  ******************************************************************************/
 
 #define MAX_AUDIOS 7
+
+/**
+ * @MAX_PIPES:
+ *
+ * Every ASIC support a fixed number of pipes; MAX_PIPES defines a large number
+ * to be used inside loops and for determining array sizes.
+ */
 #define MAX_PIPES 6
 #define MAX_DIG_LINK_ENCODERS 7
 #define MAX_DWB_PIPES	1