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authorPatrick Wildt <patrick@cvs.openbsd.org>2019-02-21 22:44:45 +0000
committerPatrick Wildt <patrick@cvs.openbsd.org>2019-02-21 22:44:45 +0000
commitfb3c4d3acc64391196c131bc90a0ba865dc9b341 (patch)
treedd4416687fce3256a340ed4ae71c379edbcfa6d1 /usr.sbin/ifstated
parent651b95692687f26f68a592a76b9db98af21ec9ed (diff)
Transfers that span multiple TRBs which wrap around the ring and
thus have the Link TRB inbetween must have the Chain Bit set in the Link TRB. Otherwise xHCI controllers might think that the transfer ends at that point. Fixes an issue that was most prominently seen as Invalid CSW error when using umass0 on octeon and i.MX8M. Tested by visa@ ok mpi@
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