Save pointers to up to four CMMU PFSR registers into the cpu_info structure.

This allows the exception handling code to skip the PFSR address computations.

The net result is that the PFSR_SAVE code becomes much simpler and smaller,
and that all processors will now spend time in PFSR_SAVE - previously, cpu0
was favored and other processors took a bit more time.

Note that 8:1 configurations do not use these fields - but then this is a
fixed monoprocessor configuration, for which the existing code was already
doing The Right Thing.

Tested on luna88k (2:1) by aoyama@, and on mvme88k (2:1 and 4:1) by me.

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