diff options
| -rw-r--r-- | sys/arch/mvme88k/Makefile | 58 | ||||
| -rw-r--r-- | sys/arch/mvme88k/include/pcb.h | 4 | ||||
| -rw-r--r-- | sys/arch/mvme88k/mvme88k/eh.S | 41 | ||||
| -rw-r--r-- | sys/arch/mvme88k/mvme88k/m18x_cmmu.c | 3268 | ||||
| -rw-r--r-- | sys/arch/mvme88k/mvme88k/m197_cmmu.c | 696 | ||||
| -rw-r--r-- | sys/arch/mvme88k/mvme88k/machdep.c | 2766 | ||||
| -rw-r--r-- | sys/arch/mvme88k/mvme88k/pmap.c | 5 | ||||
| -rw-r--r-- | sys/arch/mvme88k/mvme88k/vm_machdep.c | 31 | ||||
| -rw-r--r-- | sys/arch/mvme88k/stand/Makefile | 9 | ||||
| -rw-r--r-- | sys/arch/mvme88k/stand/installboot/Makefile | 8 |
10 files changed, 3456 insertions, 3430 deletions
diff --git a/sys/arch/mvme88k/Makefile b/sys/arch/mvme88k/Makefile index a1ff9c5f7b7..b9c798e2c36 100644 --- a/sys/arch/mvme88k/Makefile +++ b/sys/arch/mvme88k/Makefile @@ -1,49 +1,35 @@ -# $OpenBSD: Makefile,v 1.3 2000/03/03 00:54:52 todd Exp $ -# from: @(#)Makefile 7.3 (Berkeley) 6/9/91 +# $OpenBSD: Makefile,v 1.4 2000/12/28 21:21:23 smurph Exp $ -SUBDIR= stand -DIRS= conf dev ddb mvme88k include +# from: @(#)Makefile 8.1 (Berkeley) 6/11/93 +# +# Makefile for mvme88k links, tags file -S=${BSDSRCDIR}/sys -COMM= $S/vm/*.[ch] $S/ufs/*.[ch] $S/sys/*.h $S/compat/sunos/*.[ch] \ - $S/nfs/*.[ch] $S/netns/*.[ch] $S/netiso/*.[ch] \ - $S/netiso/xebec/*.[ch] $S/netinet/*.[ch] $S/netccitt/*.[ch] \ - $S/net/*.[ch] $S/miscfs/*/*.[ch] $S/kern/*.[ch] $S/dev/*.[ch] \ - $S/scsi/*.[ch] $S/lib/libkern/m88k/*.[ch] $S/lib/libkern/*.[ch] +NOPROG= noprog +NOMAN= noman +NOOBJ= noobj -# Makefile for m88k tags file +SYSTAGS= ${.CURDIR}/tags +SUBDIR= stand +DIRS= conf dev include mvme88k -#all: -# @echo "make tags or links only" +links:: + -for i in ${DIRS}; do \ + echo $$i ; \ + cd ${.CURDIR} ; \ + (cd $$i && { rm -f tags; ln -s ${SYSTAGS} tags; }) done -TM88K= $S/arch/mvme88k/tags -SM88K= $S/arch/mvme88k/mvme88k/*.[ch] $S/arch/mvme88k/include/*.h \ - $S/arch/mvme88k/dev/*.[ch] -AM88K= $S/arch/mvme88k/mvme88k/*.s - -# Directories in which to place m88k tags links -DM88K= mvme88k dev include - -TAGS: - -etags -dt ${COMM} ${SM88K} ${AM88K} - egrep "^ENTRY(.*)|^ALTENTRY(.*)" ${AM88K} | \ - sed "s;\([^:]*\):\([^(]*\)(\([^, )]*\)\(.*\);\3 \1 /^\2(\3\4$$/;" \ - >> ${TM88K}/tags +MVME88K=/sys/arch/mvme88k/dev/*.[ch] /sys/arch/mvme88k/include/*.[ch] \ + /sys/arch/mvme88k/mvme88k/*.[ch] +AMVME88K=/sys/arch/mvme88k/mvme88k/*.s tags: - -ctags -dtf ${TM88K} ${COMM} ${SM88K} - egrep "^ENTRY(.*)|^ALTENTRY(.*)" ${AM88K} | \ + -ctags -wdt ${COMM} ${MVME88K} + egrep "^ENTRY(.*)|^ALTENTRY(.*)" ${AMVME88K} | \ sed "s;\([^:]*\):\([^(]*\)(\([^, )]*\)\(.*\);\3 \1 /^\2(\3\4$$/;" \ - >> ${TM88K} - sort -o ${TM88K} ${TM88K} - -links: - -for i in ${DM88K}; do \ - rm -f $$i/tags; rm -f $$i/TAGS ; \ - ln -s ../tags $$i/tags; ln -s ../TAGS $$i/TAGS; done + >> tags + sort -o tags tags obj: _SUBDIRUSE .include <bsd.prog.mk> .include <bsd.subdir.mk> - diff --git a/sys/arch/mvme88k/include/pcb.h b/sys/arch/mvme88k/include/pcb.h index 1765e127383..3823e772504 100644 --- a/sys/arch/mvme88k/include/pcb.h +++ b/sys/arch/mvme88k/include/pcb.h @@ -1,4 +1,4 @@ -/* $OpenBSD: pcb.h,v 1.5 1999/09/27 20:46:19 smurph Exp $ */ +/* $OpenBSD: pcb.h,v 1.6 2000/12/28 21:21:24 smurph Exp $ */ /* * Copyright (c) 1996 Nivas Madhur * Mach Operating System @@ -89,7 +89,7 @@ struct m88100_pcb { struct m88100_saved_state { unsigned r[32]; /* 0 - 31 */ -#define pcb_sp r[31] +#define tf_sp r[31] unsigned epsr; /* 32 */ unsigned fpsr; unsigned fpcr; diff --git a/sys/arch/mvme88k/mvme88k/eh.S b/sys/arch/mvme88k/mvme88k/eh.S index 8315a17a27e..0b357b5438c 100644 --- a/sys/arch/mvme88k/mvme88k/eh.S +++ b/sys/arch/mvme88k/mvme88k/eh.S @@ -1,4 +1,4 @@ -/* $OpenBSD: eh.S,v 1.8 1999/09/27 19:13:21 smurph Exp $ */ +/* $OpenBSD: eh.S,v 1.9 2000/12/28 21:21:24 smurph Exp $ */ /* * Mach Operating System * Copyright (c) 1993-1991 Carnegie Mellon University @@ -1873,27 +1873,28 @@ ENTRY(proc_do_uret) LABEL(return_from_exception_handler) LABEL(_return_from_main) - /* - * Regs r1-r30 are free. R31 is pointing at the word - * on the kernel stack where our pointer to the exception frame - * it stored. Reload it now. - * - * At this point, if EF_DMT0 is not zero, then - * this must have been an interrupt where the fault didn't - * get corrected above. We'll do that now. - * - * We load it into r14 since it is preserved across function - * calls, and we may have to call some routines from within here. - * - * control is transfered here from obvious places in this file - * and thread_bootstrap in luna88k/locore.c. - * - */ + /* + * Regs r1-r30 are free. R31 is pointing at the word + * on the kernel stack where our pointer to the exception frame + * it stored. Reload it now. + * + * At this point, if EF_DMT0 is not zero, then + * this must have been an interrupt where the fault didn't + * get corrected above. We'll do that now. + * + * We load it into r14 since it is preserved across function + * calls, and we may have to call some routines from within here. + * + * control is transfered here from obvious places in this file + * and thread_bootstrap in luna88k/locore.c. + * + */ +#ifdef MVME197 or.u r2, r0, hi16(_cputyp) ld r3, r2, lo16(_cputyp) cmp r2, r3, 0x197 bb1 eq, r2, m197_return_code - +#endif #define FPTR r14 ld FPTR, r31, 0 /* grab exception frame pointer */ ld r3, FPTR, REG_OFF(EF_DMT0) @@ -1956,7 +1957,7 @@ LABEL(oops) st r0 , FPTR, REG_OFF(EF_DMT0) 2: br _check_ast - +#ifdef MVME197 LABEL(m197_return_code) #define FPTR r14 ld FPTR, r31, 0 /* grab exception frame pointer */ @@ -2026,7 +2027,7 @@ LABEL(oops2) * interrupts. * If returning to user land, look for ASTs */ - +#endif /* MVME197 */ LABEL(_check_ast) ld r2, FPTR, REG_OFF(EF_EPSR) /* get pre-exception PSR */ diff --git a/sys/arch/mvme88k/mvme88k/m18x_cmmu.c b/sys/arch/mvme88k/mvme88k/m18x_cmmu.c index ca7c7ce3f06..861946d9acf 100644 --- a/sys/arch/mvme88k/mvme88k/m18x_cmmu.c +++ b/sys/arch/mvme88k/mvme88k/m18x_cmmu.c @@ -1,4 +1,4 @@ -/* $OpenBSD: m18x_cmmu.c,v 1.2 2000/03/03 00:54:53 todd Exp $ */ +/* $OpenBSD: m18x_cmmu.c,v 1.3 2000/12/28 21:21:24 smurph Exp $ */ /* * Copyright (c) 1998 Steve Murphree, Jr. * Copyright (c) 1996 Nivas Madhur @@ -81,8 +81,7 @@ unsigned int debuglevel = 0; #undef SHADOW_BATC /* don't use BATCs for now XXX nivas */ struct cmmu_regs { - /* base + $000 */ - volatile unsigned idr; + /* base + $000 */volatile unsigned idr; /* base + $004 */volatile unsigned scr; /* base + $008 */volatile unsigned ssr; /* base + $00C */volatile unsigned sar; @@ -113,20 +112,20 @@ struct cmmu_regs { }; struct cmmu { - struct cmmu_regs *cmmu_regs; /* CMMU "base" area */ - unsigned char cmmu_cpu; /* cpu number it is attached to */ - unsigned char which; /* either INST_CMMU || DATA_CMMU */ - unsigned char cmmu_access; /* either CMMU_ACS_{SUPER,USER,BOTH} */ - unsigned char cmmu_alive; -#define CMMU_DEAD 0 /* This cmmu not there */ -#define CMMU_AVAILABLE 1 /* It's there, but which cpu's? */ -#define CMMU_ALIVE 1 /* It's there. */ -#define CMMU_MARRIED 2 /* Know which cpu it belongs to. */ - vm_offset_t cmmu_addr; /* address range */ - vm_offset_t cmmu_addr_mask; /* address mask */ - int cmmu_addr_match; /* return value of address comparison */ + struct cmmu_regs *cmmu_regs; /* CMMU "base" area */ + unsigned char cmmu_cpu; /* cpu number it is attached to */ + unsigned char which; /* either INST_CMMU || DATA_CMMU */ + unsigned char cmmu_access; /* either CMMU_ACS_{SUPER,USER,BOTH} */ + unsigned char cmmu_alive; +#define CMMU_DEAD 0 /* This cmmu not there */ +#define CMMU_AVAILABLE 1 /* It's there, but which cpu's? */ +#define CMMU_ALIVE 1 /* It's there. */ +#define CMMU_MARRIED 2 /* Know which cpu it belongs to. */ + vm_offset_t cmmu_addr; /* address range */ + vm_offset_t cmmu_addr_mask; /* address mask */ + int cmmu_addr_match; /* return value of address comparison */ #if SHADOW_BATC - unsigned batc[8]; + unsigned batc[8]; #endif }; /* @@ -168,42 +167,40 @@ void m18x_setup_board_config(void); void m18x_show_apr(unsigned value) { - union apr_template apr_template; - apr_template.bits = value; - - printf("table @ 0x%x000", apr_template.field.st_base); - if (apr_template.field.wt) printf(", writethrough"); - if (apr_template.field.g) printf(", global"); - if (apr_template.field.ci) printf(", cache inhibit"); - if (apr_template.field.te) printf(", valid"); - else printf(", not valid"); - printf("\n"); + union apr_template apr_template; + apr_template.bits = value; + + printf("table @ 0x%x000", apr_template.field.st_base); + if (apr_template.field.wt) printf(", writethrough"); + if (apr_template.field.g) printf(", global"); + if (apr_template.field.ci) printf(", cache inhibit"); + if (apr_template.field.te) printf(", valid"); + else printf(", not valid"); + printf("\n"); } void m18x_show_sctr(unsigned value) { - union { - unsigned bits; - struct { - unsigned :16, - pe: 1, - se: 1, - pr: 1, - :13; - } fields; - } sctr; - sctr.bits = value; - printf("%spe, %sse %spr]\n", - sctr.fields.pe ? "" : "!", - sctr.fields.se ? "" : "!", - sctr.fields.pr ? "" : "!"); + union { + unsigned bits; + struct { + unsigned :16, + pe: 1, + se: 1, + pr: 1, + :13; + } fields; + } sctr; + sctr.bits = value; + printf("%spe, %sse %spr]\n", + sctr.fields.pe ? "" : "!", + sctr.fields.se ? "" : "!", + sctr.fields.pr ? "" : "!"); } #endif -/*----------------------------------------------------------------*/ - -/* +/*---------------------------------------------------------------- * The cmmu.c module was initially designed for the Omron Luna 88K * layout consisting of 4 CPUs with 2 CMMUs each, one for data * and one for instructions. @@ -241,14 +238,14 @@ m18x_show_sctr(unsigned value) * used for data and instruction CMMUs. */ struct cmmu_strategy { - int inst; - int data; + int inst; + int data; } cpu_cmmu_strategy[] = { - /* inst data */ - { CMMU_SPLIT_SPV, CMMU_SPLIT_SPV}, /* CPU 0 */ - { CMMU_SPLIT_SPV, CMMU_SPLIT_SPV}, /* CPU 1 */ - { CMMU_SPLIT_ADDRESS, CMMU_SPLIT_ADDRESS}, /* CPU 2 */ - { CMMU_SPLIT_ADDRESS, CMMU_SPLIT_ADDRESS} /* CPU 3 */ + /* inst data */ + { CMMU_SPLIT_SPV, CMMU_SPLIT_SPV}, /* CPU 0 */ + { CMMU_SPLIT_SPV, CMMU_SPLIT_SPV}, /* CPU 1 */ + { CMMU_SPLIT_ADDRESS, CMMU_SPLIT_ADDRESS}, /* CPU 2 */ + { CMMU_SPLIT_ADDRESS, CMMU_SPLIT_ADDRESS} /* CPU 3 */ }; /* @@ -256,28 +253,28 @@ struct cmmu_strategy { * MVME188 configurations which are supported by this module. */ struct board_config { - int supported; - int ncpus; - int ncmmus; + int supported; + int ncpus; + int ncmmus; } bd_config[] = { - /* sup, CPU MMU */ - { 1, 4, 8}, /* 4P128 - 4P512 */ - { 1, 2, 8}, /* 2P128 - 2P512 */ - { 1, 1, 8}, /* 1P128 - 1P512 */ - { -1, -1, -1}, - { -1, -1, -1}, - { 1, 2, 4}, /* 2P64 - 2P256 */ - { 1, 1, 4}, /* 1P64 - 1P256 */ - { -1, -1, -1}, - { -1, -1, -1}, - { -1, -1, -1}, - { 1, 1, 2}, /* 1P32 - 1P128 */ - { -1, -1, -1}, - { -1, -1, -1}, - { -1, -1, -1}, - { -1, -1, -1}, - { -1, -1, -1} + /* sup, CPU MMU */ + { 1, 4, 8}, /* 4P128 - 4P512 */ + { 1, 2, 8}, /* 2P128 - 2P512 */ + { 1, 1, 8}, /* 1P128 - 1P512 */ + { -1, -1, -1}, + { -1, -1, -1}, + { 1, 2, 4}, /* 2P64 - 2P256 */ + { 1, 1, 4}, /* 1P64 - 1P256 */ + { -1, -1, -1}, + { -1, -1, -1}, + { -1, -1, -1}, + { 1, 1, 2}, /* 1P32 - 1P128 */ + { -1, -1, -1}, + { -1, -1, -1}, + { -1, -1, -1}, + { -1, -1, -1}, + { -1, -1, -1} }; /* @@ -286,83 +283,91 @@ struct board_config { struct cmmu cmmu[MAX_CMMUS] = { - /* addr cpu mode access - alive addr mask */ - {(void *)VME_CMMU_I0, -1, INST_CMMU, CMMU_ACS_BOTH, - CMMU_DEAD, 0, 0}, - {(void *)VME_CMMU_D0, -1, DATA_CMMU, CMMU_ACS_BOTH, - CMMU_DEAD, 0, 0}, - {(void *)VME_CMMU_I1, -1, INST_CMMU, CMMU_ACS_BOTH, - CMMU_DEAD, 0, 0}, - {(void *)VME_CMMU_D1, -1, DATA_CMMU, CMMU_ACS_BOTH, - CMMU_DEAD, 0, 0}, - {(void *)VME_CMMU_I2, -1, INST_CMMU, CMMU_ACS_BOTH, - CMMU_DEAD, 0, 0}, - {(void *)VME_CMMU_D2, -1, DATA_CMMU, CMMU_ACS_BOTH, - CMMU_DEAD, 0, 0}, - {(void *)VME_CMMU_I3, -1, INST_CMMU, CMMU_ACS_BOTH, - CMMU_DEAD, 0, 0}, - {(void *)VME_CMMU_D3, -1, DATA_CMMU, CMMU_ACS_BOTH, - CMMU_DEAD, 0, 0} + /* addr cpu mode access + alive addr mask */ + {(void *)VME_CMMU_I0, -1, INST_CMMU, CMMU_ACS_BOTH, + CMMU_DEAD, 0, 0}, + {(void *)VME_CMMU_D0, -1, DATA_CMMU, CMMU_ACS_BOTH, + CMMU_DEAD, 0, 0}, + {(void *)VME_CMMU_I1, -1, INST_CMMU, CMMU_ACS_BOTH, + CMMU_DEAD, 0, 0}, + {(void *)VME_CMMU_D1, -1, DATA_CMMU, CMMU_ACS_BOTH, + CMMU_DEAD, 0, 0}, + {(void *)VME_CMMU_I2, -1, INST_CMMU, CMMU_ACS_BOTH, + CMMU_DEAD, 0, 0}, + {(void *)VME_CMMU_D2, -1, DATA_CMMU, CMMU_ACS_BOTH, + CMMU_DEAD, 0, 0}, + {(void *)VME_CMMU_I3, -1, INST_CMMU, CMMU_ACS_BOTH, + CMMU_DEAD, 0, 0}, + {(void *)VME_CMMU_D3, -1, DATA_CMMU, CMMU_ACS_BOTH, + CMMU_DEAD, 0, 0} }; struct cpu_cmmu { - struct cmmu *pair[2]; + struct cmmu *pair[2]; } cpu_cmmu[MAX_CPUS]; void m18x_setup_board_config(void) { - volatile unsigned long *whoami; - - master_cpu = 0; /* temp to get things going */ - switch (cputyp) { - case CPU_187: - case CPU_197: - vme188_config = 10; /* There is no WHOAMI reg on MVME1x7 - fake it... */ - cmmu[0].cmmu_regs = (void *)SBC_CMMU_I; - cmmu[0].cmmu_cpu = 0; - cmmu[1].cmmu_regs = (void *)SBC_CMMU_D; - cmmu[1].cmmu_cpu = 0; - cmmu[2].cmmu_regs = (void *)NULL; - cmmu[3].cmmu_regs = (void *)NULL; - cmmu[4].cmmu_regs = (void *)NULL; - cmmu[5].cmmu_regs = (void *)NULL; - cmmu[6].cmmu_regs = (void *)NULL; - cmmu[7].cmmu_regs = (void *)NULL; - max_cpus = 1; - max_cmmus = 2; - break; - case CPU_188: - whoami = (volatile unsigned long *)MVME188_WHOAMI; - vme188_config = (*whoami & 0xf0) >> 4; - dprintf(DB_CMMU,("m18x_setup_board_config: WHOAMI @ 0x%08x holds value 0x%08x\n", - whoami, *whoami)); - max_cpus = bd_config[vme188_config].ncpus; - max_cmmus = bd_config[vme188_config].ncmmus; - break; - default: - panic("m18x_setup_board_config: Unknown CPU type."); - } - cpu_cmmu_ratio = max_cmmus / max_cpus; - switch (bd_config[vme188_config].supported) { - case 0: - printf("MVME%x board configuration #%X: %d CPUs %d CMMUs\n", cputyp, - vme188_config, max_cpus, max_cmmus); - panic("This configuration is not supported - go and get another OS.\n"); - /* NOTREACHED */ - break; - case 1: - printf("MVME%x board configuration #%X: %d CPUs %d CMMUs\n", cputyp, - vme188_config, max_cpus, max_cmmus); - m18x_setup_cmmu_config(); - break; - default: - panic("UNKNOWN MVME%x board configuration: WHOAMI = 0x%02x\n", cputyp, *whoami); - /* NOTREACHED */ - break; - } - return; + volatile unsigned long *whoami; + + master_cpu = 0; /* temp to get things going */ + switch (cputyp) { +#ifdef MVME187 + case CPU_187: +#endif +#ifdef MVME197 + case CPU_197: +#endif +#if defined(MVME187) || defined(MVME197) + vme188_config = 10; /* There is no WHOAMI reg on MVME1x7 - fake it... */ + cmmu[0].cmmu_regs = (void *)SBC_CMMU_I; + cmmu[0].cmmu_cpu = 0; + cmmu[1].cmmu_regs = (void *)SBC_CMMU_D; + cmmu[1].cmmu_cpu = 0; + cmmu[2].cmmu_regs = (void *)NULL; + cmmu[3].cmmu_regs = (void *)NULL; + cmmu[4].cmmu_regs = (void *)NULL; + cmmu[5].cmmu_regs = (void *)NULL; + cmmu[6].cmmu_regs = (void *)NULL; + cmmu[7].cmmu_regs = (void *)NULL; + max_cpus = 1; + max_cmmus = 2; + break; +#endif /* defined(MVME187) || defined(MVME197) */ +#ifdef MVME188 + case CPU_188: + whoami = (volatile unsigned long *)MVME188_WHOAMI; + vme188_config = (*whoami & 0xf0) >> 4; + dprintf(DB_CMMU,("m18x_setup_board_config: WHOAMI @ 0x%08x holds value 0x%08x\n", + whoami, *whoami)); + max_cpus = bd_config[vme188_config].ncpus; + max_cmmus = bd_config[vme188_config].ncmmus; + break; +#endif /* MVME188 */ + default: + panic("m18x_setup_board_config: Unknown CPU type."); + } + cpu_cmmu_ratio = max_cmmus / max_cpus; + switch (bd_config[vme188_config].supported) { + case 0: + printf("MVME%x board configuration #%X: %d CPUs %d CMMUs\n", cputyp, + vme188_config, max_cpus, max_cmmus); + panic("This configuration is not supported - go and get another OS.\n"); + /* NOTREACHED */ + break; + case 1: + printf("MVME%x board configuration #%X: %d CPUs %d CMMUs\n", cputyp, + vme188_config, max_cpus, max_cmmus); + m18x_setup_cmmu_config(); + break; + default: + panic("UNKNOWN MVME%x board configuration: WHOAMI = 0x%02x\n", cputyp, *whoami); + /* NOTREACHED */ + break; + } + return; } /* @@ -372,326 +377,351 @@ m18x_setup_board_config(void) void m18x_setup_cmmu_config(void) { - volatile unsigned long *pcnfa; - volatile unsigned long *pcnfb; - - register int num, cmmu_num, val1, val2; - - dprintf(DB_CMMU,("m18x_setup_cmmu_config: initializing with %d CPU(s) and %d CMMU(s)\n", - max_cpus, max_cmmus)); - - /* - * Probe for available MMUs - */ - for (cmmu_num = 0; cmmu_num < max_cmmus; cmmu_num++) - if (!badwordaddr((vm_offset_t)cmmu[cmmu_num].cmmu_regs)) { - union cpupid id; - - id.cpupid = cmmu[cmmu_num].cmmu_regs->idr; - if (id.m88200.type != M88200 && id.m88200.type != M88204) { - printf("WARNING: non M8820x circuit found at CMMU address 0x%08x\n", - cmmu[cmmu_num].cmmu_regs); - continue; - } - cmmu[cmmu_num].cmmu_alive = CMMU_ALIVE; - dprintf(DB_CMMU,("m18x_setup_cmmu_config: CMMU %d found at 0x%08x\n", - cmmu_num, cmmu[cmmu_num].cmmu_regs)); - } - - /* - * Now that we know which CMMUs are there, let's report on which - * CPU/CMMU sets seem complete (hopefully all) - */ - for (num = 0; num < max_cpus; num++) { - register int i; - union cpupid id; - - for (i = 0; i < cpu_cmmu_ratio; i++) { - dprintf(DB_CMMU,("cmmu_init: testing CMMU %d for CPU %d\n", - num*cpu_cmmu_ratio+i, num)); - if (!m18x_cmmu_alive(num*cpu_cmmu_ratio + i)) { - printf("CMMU %d attached to CPU %d is not working\n"); - panic("m18x_setup_cmmu_config"); - } - } - cpu_sets[num] = 1; /* This cpu installed... */ - id.cpupid = cmmu[num*cpu_cmmu_ratio].cmmu_regs->idr; - - if (id.m88200.type == M88204) - printf("CPU%d is attached with %d MC88204 CMMUs\n", - num, cpu_cmmu_ratio); - else - printf("CPU%d is attached with %d MC88200 CMMUs\n", - num, cpu_cmmu_ratio); - } - - for (num = 0; num < max_cpus; num++) { - cpu_cmmu_strategy[num].inst &= CMMU_SPLIT_MASK; - cpu_cmmu_strategy[num].data &= CMMU_SPLIT_MASK; - dprintf(DB_CMMU,("m18x_setup_cmmu_config: CPU %d inst strat %d data strat %d\n", - num, cpu_cmmu_strategy[num].inst, cpu_cmmu_strategy[num].data)); - } - - switch (vme188_config) { - /* - * These configurations have hardwired CPU/CMMU configurations. - */ - case CONFIG_0: - case CONFIG_5: - case CONFIG_A: - dprintf(DB_CMMU,("m18x_setup_cmmu_config: resetting strategies\n")); - for (num = 0; num < max_cpus; num++) - cpu_cmmu_strategy[num].inst = cpu_cmmu_strategy[num].data = - CMMU_SPLIT_ADDRESS; - break; - /* - * Configure CPU/CMMU strategy into PCNFA and PCNFB board registers. - */ - case CONFIG_1: - pcnfa = (volatile unsigned long *)MVME188_PCNFA; - pcnfb = (volatile unsigned long *)MVME188_PCNFB; - val1 = (cpu_cmmu_strategy[0].inst << 2) | cpu_cmmu_strategy[0].data; - val2 = (cpu_cmmu_strategy[1].inst << 2) | cpu_cmmu_strategy[1].data; - *pcnfa = val1; - *pcnfb = val2; - dprintf(DB_CMMU,("m18x_setup_cmmu_config: 2P128: PCNFA = 0x%x, PCNFB = 0x%x\n", val1, val2)); - break; - case CONFIG_2: - pcnfa = (volatile unsigned long *)MVME188_PCNFA; - pcnfb = (volatile unsigned long *)MVME188_PCNFB; - val1 = (cpu_cmmu_strategy[0].inst << 2) | cpu_cmmu_strategy[0].inst; - val2 = (cpu_cmmu_strategy[0].data << 2) | cpu_cmmu_strategy[0].data; - *pcnfa = val1; - *pcnfb = val2; - dprintf(DB_CMMU,("m18x_setup_cmmu_config: 1P128: PCNFA = 0x%x, PCNFB = 0x%x\n", val1, val2)); - break; - case CONFIG_6: - pcnfa = (volatile unsigned long *)MVME188_PCNFA; - val1 = (cpu_cmmu_strategy[0].inst << 2) | cpu_cmmu_strategy[0].data; - *pcnfa = val1; - dprintf(DB_CMMU,("m18x_setup_cmmu_config: 1P64: PCNFA = 0x%x\n", val1)); - break; - default: - panic("m18x_setup_cmmu_config"); - break; - } - - dprintf(DB_CMMU,("m18x_setup_cmmu_config: PCNFA = 0x%x, PCNFB = 0x%x\n", *pcnfa, *pcnfb)); - - /* - * Calculate the CMMU<->CPU connections - */ - for (cmmu_num = 0; cmmu_num < max_cmmus; cmmu_num++) { - cmmu[cmmu_num].cmmu_cpu = - (int) (((float) cmmu_num) * ((float) max_cpus) / ((float) max_cmmus)); - dprintf(DB_CMMU,("m18x_setup_cmmu_config: CMMU %d connected with CPU %d\n", - cmmu_num, cmmu[cmmu_num].cmmu_cpu)); - } - - /* - * Now set cmmu[].cmmu_access and addr - */ - for (cmmu_num = 0; cmmu_num < max_cmmus; cmmu_num++) { - /* - * We don't set up anything for the hardwired configurations. - */ - if (cpu_cmmu_ratio == 2) { - cmmu[cmmu_num].cmmu_addr = - cmmu[cmmu_num].cmmu_addr_mask = 0; - cmmu[cmmu_num].cmmu_addr_match = 1; - cmmu[cmmu_num].cmmu_access = CMMU_ACS_BOTH; - continue; - } - - /* - * First we set the address/mask pairs for the exact address - * matches. - */ - switch ((cmmu[cmmu_num].which == INST_CMMU) ? - cpu_cmmu_strategy[cmmu[cmmu_num].cmmu_cpu].inst : - cpu_cmmu_strategy[cmmu[cmmu_num].cmmu_cpu].data) { - case CMMU_SPLIT_ADDRESS: - cmmu[cmmu_num].cmmu_addr = ((cmmu_num & 0x2) ^ 0x2) << 11; - cmmu[cmmu_num].cmmu_addr_mask = CMMU_A12_MASK; - cmmu[cmmu_num].cmmu_addr_match = 1; - break; - case CMMU_SPLIT_SPV: - cmmu[cmmu_num].cmmu_addr = - cmmu[cmmu_num].cmmu_addr_mask = 0; - cmmu[cmmu_num].cmmu_addr_match = 1; - break; - case CMMU_SPLIT_SRAM_ALL: - cmmu[cmmu_num].cmmu_addr = CMMU_SRAM; - cmmu[cmmu_num].cmmu_addr_mask = CMMU_SRAM_MASK; - cmmu[cmmu_num].cmmu_addr_match = (cmmu_num & 0x2) ? 1 : 0; - break; - case CMMU_SPLIT_SRAM_SPV: - if (cmmu_num & 0x2) { - cmmu[cmmu_num].cmmu_addr = CMMU_SRAM; - cmmu[cmmu_num].cmmu_addr_mask = CMMU_SRAM_MASK; - } else { - cmmu[cmmu_num].cmmu_addr = - cmmu[cmmu_num].cmmu_addr_mask = 0; - } - cmmu[cmmu_num].cmmu_addr_match = 1; - break; - } - - /* - * For MVME188 single processors, we've got to look at A14. - * This bit splits the CMMUs independent of the enabled strategy. - * - * NOT TESTED!!! - em - */ - if (cpu_cmmu_ratio > 4) { - cmmu[cmmu_num].cmmu_addr |= ((cmmu_num & 0x4) ^ 0x4) << 12; - cmmu[cmmu_num].cmmu_addr_mask |= CMMU_A14_MASK; - } - - /* - * Next we cope with the various access modes. - */ - switch ((cmmu[cmmu_num].which == INST_CMMU) ? - cpu_cmmu_strategy[cmmu[cmmu_num].cmmu_cpu].inst : - cpu_cmmu_strategy[cmmu[cmmu_num].cmmu_cpu].data) { - case CMMU_SPLIT_SPV: - cmmu[cmmu_num].cmmu_access = - (cmmu_num & 0x2 ) ? CMMU_ACS_USER : CMMU_ACS_SUPER; - break; - case CMMU_SPLIT_SRAM_SPV: - cmmu[cmmu_num].cmmu_access = - (cmmu_num & 0x2 ) ? CMMU_ACS_SUPER : CMMU_ACS_BOTH; - break; - default: - cmmu[cmmu_num].cmmu_access = CMMU_ACS_BOTH; - break; - } - } - return; + volatile unsigned long *pcnfa; + volatile unsigned long *pcnfb; + + register int num, cmmu_num, val1, val2; + + dprintf(DB_CMMU,("m18x_setup_cmmu_config: initializing with %d CPU(s) and %d CMMU(s)\n", + max_cpus, max_cmmus)); + + /* + * Probe for available MMUs + */ + for (cmmu_num = 0; cmmu_num < max_cmmus; cmmu_num++) + if (!badwordaddr((vm_offset_t)cmmu[cmmu_num].cmmu_regs)) { + union cpupid id; + + id.cpupid = cmmu[cmmu_num].cmmu_regs->idr; + if (id.m88200.type != M88200 && id.m88200.type != M88204) { + printf("WARNING: non M8820x circuit found at CMMU address 0x%08x\n", + cmmu[cmmu_num].cmmu_regs); + continue; + } + cmmu[cmmu_num].cmmu_alive = CMMU_ALIVE; + dprintf(DB_CMMU,("m18x_setup_cmmu_config: CMMU %d found at 0x%08x\n", + cmmu_num, cmmu[cmmu_num].cmmu_regs)); + } + + /* + * Now that we know which CMMUs are there, let's report on which + * CPU/CMMU sets seem complete (hopefully all) + */ + for (num = 0; num < max_cpus; num++) { + register int i; + union cpupid id; + + for (i = 0; i < cpu_cmmu_ratio; i++) { + dprintf(DB_CMMU,("cmmu_init: testing CMMU %d for CPU %d\n", + num*cpu_cmmu_ratio+i, num)); + if (!m18x_cmmu_alive(num*cpu_cmmu_ratio + i)) { + printf("CMMU %d attached to CPU %d is not working\n"); + panic("m18x_setup_cmmu_config"); + } + } + cpu_sets[num] = 1; /* This cpu installed... */ + id.cpupid = cmmu[num*cpu_cmmu_ratio].cmmu_regs->idr; + + if (id.m88200.type == M88204) + printf("CPU%d is attached with %d MC88204 CMMUs\n", + num, cpu_cmmu_ratio); + else + printf("CPU%d is attached with %d MC88200 CMMUs\n", + num, cpu_cmmu_ratio); + } + + for (num = 0; num < max_cpus; num++) { + cpu_cmmu_strategy[num].inst &= CMMU_SPLIT_MASK; + cpu_cmmu_strategy[num].data &= CMMU_SPLIT_MASK; + dprintf(DB_CMMU,("m18x_setup_cmmu_config: CPU %d inst strat %d data strat %d\n", + num, cpu_cmmu_strategy[num].inst, cpu_cmmu_strategy[num].data)); + } + + switch (vme188_config) { + /* + * These configurations have hardwired CPU/CMMU configurations. + */ + case CONFIG_0: + case CONFIG_5: + case CONFIG_A: + dprintf(DB_CMMU,("m18x_setup_cmmu_config: resetting strategies\n")); + for (num = 0; num < max_cpus; num++) + cpu_cmmu_strategy[num].inst = cpu_cmmu_strategy[num].data = + CMMU_SPLIT_ADDRESS; + break; +#ifdef MVME188 + /* + * Configure CPU/CMMU strategy into PCNFA and PCNFB board registers. + */ + case CONFIG_1: + pcnfa = (volatile unsigned long *)MVME188_PCNFA; + pcnfb = (volatile unsigned long *)MVME188_PCNFB; + val1 = (cpu_cmmu_strategy[0].inst << 2) | cpu_cmmu_strategy[0].data; + val2 = (cpu_cmmu_strategy[1].inst << 2) | cpu_cmmu_strategy[1].data; + *pcnfa = val1; + *pcnfb = val2; + dprintf(DB_CMMU,("m18x_setup_cmmu_config: 2P128: PCNFA = 0x%x, PCNFB = 0x%x\n", val1, val2)); + break; + case CONFIG_2: + pcnfa = (volatile unsigned long *)MVME188_PCNFA; + pcnfb = (volatile unsigned long *)MVME188_PCNFB; + val1 = (cpu_cmmu_strategy[0].inst << 2) | cpu_cmmu_strategy[0].inst; + val2 = (cpu_cmmu_strategy[0].data << 2) | cpu_cmmu_strategy[0].data; + *pcnfa = val1; + *pcnfb = val2; + dprintf(DB_CMMU,("m18x_setup_cmmu_config: 1P128: PCNFA = 0x%x, PCNFB = 0x%x\n", val1, val2)); + break; + case CONFIG_6: + pcnfa = (volatile unsigned long *)MVME188_PCNFA; + val1 = (cpu_cmmu_strategy[0].inst << 2) | cpu_cmmu_strategy[0].data; + *pcnfa = val1; + dprintf(DB_CMMU,("m18x_setup_cmmu_config: 1P64: PCNFA = 0x%x\n", val1)); + break; +#endif /* MVME188 */ + default: + panic("m18x_setup_cmmu_config"); + break; + } + +#ifdef MVME188 + dprintf(DB_CMMU,("m18x_setup_cmmu_config: PCNFA = 0x%x, PCNFB = 0x%x\n", *pcnfa, *pcnfb)); +#endif /* MVME188 */ + + /* + * Calculate the CMMU<->CPU connections + */ + for (cmmu_num = 0; cmmu_num < max_cmmus; cmmu_num++) { + cmmu[cmmu_num].cmmu_cpu = + (int) (((float) cmmu_num) * ((float) max_cpus) / ((float) max_cmmus)); + dprintf(DB_CMMU,("m18x_setup_cmmu_config: CMMU %d connected with CPU %d\n", + cmmu_num, cmmu[cmmu_num].cmmu_cpu)); + } + + /* + * Now set cmmu[].cmmu_access and addr + */ + for (cmmu_num = 0; cmmu_num < max_cmmus; cmmu_num++) { + /* + * We don't set up anything for the hardwired configurations. + */ + if (cpu_cmmu_ratio == 2) { + cmmu[cmmu_num].cmmu_addr = + cmmu[cmmu_num].cmmu_addr_mask = 0; + cmmu[cmmu_num].cmmu_addr_match = 1; + cmmu[cmmu_num].cmmu_access = CMMU_ACS_BOTH; + continue; + } + + /* + * First we set the address/mask pairs for the exact address + * matches. + */ + switch ((cmmu[cmmu_num].which == INST_CMMU) ? + cpu_cmmu_strategy[cmmu[cmmu_num].cmmu_cpu].inst : + cpu_cmmu_strategy[cmmu[cmmu_num].cmmu_cpu].data) { + case CMMU_SPLIT_ADDRESS: + cmmu[cmmu_num].cmmu_addr = ((cmmu_num & 0x2) ^ 0x2) << 11; + cmmu[cmmu_num].cmmu_addr_mask = CMMU_A12_MASK; + cmmu[cmmu_num].cmmu_addr_match = 1; + break; + case CMMU_SPLIT_SPV: + cmmu[cmmu_num].cmmu_addr = + cmmu[cmmu_num].cmmu_addr_mask = 0; + cmmu[cmmu_num].cmmu_addr_match = 1; + break; + case CMMU_SPLIT_SRAM_ALL: + cmmu[cmmu_num].cmmu_addr = CMMU_SRAM; + cmmu[cmmu_num].cmmu_addr_mask = CMMU_SRAM_MASK; + cmmu[cmmu_num].cmmu_addr_match = (cmmu_num & 0x2) ? 1 : 0; + break; + case CMMU_SPLIT_SRAM_SPV: + if (cmmu_num & 0x2) { + cmmu[cmmu_num].cmmu_addr = CMMU_SRAM; + cmmu[cmmu_num].cmmu_addr_mask = CMMU_SRAM_MASK; + } else { + cmmu[cmmu_num].cmmu_addr = + cmmu[cmmu_num].cmmu_addr_mask = 0; + } + cmmu[cmmu_num].cmmu_addr_match = 1; + break; + } + + /* + * For MVME188 single processors, we've got to look at A14. + * This bit splits the CMMUs independent of the enabled strategy. + * + * NOT TESTED!!! - em + */ + if (cpu_cmmu_ratio > 4) { + cmmu[cmmu_num].cmmu_addr |= ((cmmu_num & 0x4) ^ 0x4) << 12; + cmmu[cmmu_num].cmmu_addr_mask |= CMMU_A14_MASK; + } + + /* + * Next we cope with the various access modes. + */ + switch ((cmmu[cmmu_num].which == INST_CMMU) ? + cpu_cmmu_strategy[cmmu[cmmu_num].cmmu_cpu].inst : + cpu_cmmu_strategy[cmmu[cmmu_num].cmmu_cpu].data) { + case CMMU_SPLIT_SPV: + cmmu[cmmu_num].cmmu_access = + (cmmu_num & 0x2 ) ? CMMU_ACS_USER : CMMU_ACS_SUPER; + break; + case CMMU_SPLIT_SRAM_SPV: + cmmu[cmmu_num].cmmu_access = + (cmmu_num & 0x2 ) ? CMMU_ACS_SUPER : CMMU_ACS_BOTH; + break; + default: + cmmu[cmmu_num].cmmu_access = CMMU_ACS_BOTH; + break; + } + } + return; } static char *cmmu_strat_string[] = { - "address split ", - "user/spv split", - "spv SRAM split", - "all SRAM split" + "address split ", + "user/spv split", + "spv SRAM split", + "all SRAM split" }; -void m18x_cmmu_dump_config(void) +void +m18x_cmmu_dump_config(void) { - volatile unsigned long *pcnfa; - volatile unsigned long *pcnfb; - register int cmmu_num; - - if (cputyp != CPU_188) return; - - db_printf("Current CPU/CMMU configuration:\n\n"); - - db_printf("VME188 address decoder: PCNFA = 0x%1x, PCNFB = 0x%1x\n\n", *pcnfa & 0xf, *pcnfb & 0xf); - pcnfa = (volatile unsigned long *)MVME188_PCNFA; - pcnfb = (volatile unsigned long *)MVME188_PCNFB; - for (cmmu_num = 0; cmmu_num < max_cmmus; cmmu_num++) { - db_printf("CMMU #%d: %s CMMU for CPU %d:\n Strategy: %s\n %s access addr 0x%08x mask 0x%08x match %s\n", - cmmu_num, - (cmmu[cmmu_num].which == INST_CMMU) ? "inst" : "data", - cmmu[cmmu_num].cmmu_cpu, - cmmu_strat_string[(cmmu[cmmu_num].which == INST_CMMU) ? - cpu_cmmu_strategy[cmmu[cmmu_num].cmmu_cpu].inst : - cpu_cmmu_strategy[cmmu[cmmu_num].cmmu_cpu].data], - (cmmu[cmmu_num].cmmu_access == CMMU_ACS_BOTH) ? "User and spv" : - ((cmmu[cmmu_num].cmmu_access == CMMU_ACS_USER) ? "User " : - "Supervisor "), - cmmu[cmmu_num].cmmu_addr, - cmmu[cmmu_num].cmmu_addr_mask, - cmmu[cmmu_num].cmmu_addr_match ? "TRUE" : "FALSE"); - } + volatile unsigned long *pcnfa; + volatile unsigned long *pcnfb; + register int cmmu_num; + + if (cputyp != CPU_188) return; + + db_printf("Current CPU/CMMU configuration:\n\n"); + + switch (cputyp) { +#ifdef MVME187 + case CPU_187: +#endif +#ifdef MVME197 + case CPU_197: +#endif +#if defined(MVME187) || defined(MVME197) + db_printf("VME1x7 split mode\n\n"); +#endif /* defined(MVME187) || defined(MVME197) */ +#ifdef MVME188 + case CPU_188: + db_printf("VME188 address decoder: PCNFA = 0x%1x, PCNFB = 0x%1x\n\n", *pcnfa & 0xf, *pcnfb & 0xf); + pcnfa = (volatile unsigned long *)MVME188_PCNFA; + pcnfb = (volatile unsigned long *)MVME188_PCNFB; + for (cmmu_num = 0; cmmu_num < max_cmmus; cmmu_num++) { + db_printf("CMMU #%d: %s CMMU for CPU %d:\n Strategy: %s\n %s access addr 0x%08x mask 0x%08x match %s\n", + cmmu_num, + (cmmu[cmmu_num].which == INST_CMMU) ? "inst" : "data", + cmmu[cmmu_num].cmmu_cpu, + cmmu_strat_string[(cmmu[cmmu_num].which == INST_CMMU) ? + cpu_cmmu_strategy[cmmu[cmmu_num].cmmu_cpu].inst : + cpu_cmmu_strategy[cmmu[cmmu_num].cmmu_cpu].data], + (cmmu[cmmu_num].cmmu_access == CMMU_ACS_BOTH) ? "User and spv" : + ((cmmu[cmmu_num].cmmu_access == CMMU_ACS_USER) ? "User " : + "Supervisor "), + cmmu[cmmu_num].cmmu_addr, + cmmu[cmmu_num].cmmu_addr_mask, + cmmu[cmmu_num].cmmu_addr_match ? "TRUE" : "FALSE"); + } +#endif /* MVME188 */ + default: + db_printf("Unknown CPU\n\n"); + } } /* To be implemented as a macro for speedup - XXX-em */ static void m18x_cmmu_store(int mmu, int reg, unsigned val) { - *(volatile unsigned *)(reg + (char*)(cmmu[mmu].cmmu_regs)) = val; + *(volatile unsigned *)(reg + (char*)(cmmu[mmu].cmmu_regs)) = val; } -int m18x_cmmu_alive(int mmu) +int +m18x_cmmu_alive(int mmu) { - return (cmmu[mmu].cmmu_alive == CMMU_ALIVE); + return (cmmu[mmu].cmmu_alive == CMMU_ALIVE); } -unsigned m18x_cmmu_get(int mmu, int reg) +unsigned +m18x_cmmu_get(int mmu, int reg) { - return *(volatile unsigned *)(reg + (char*)(cmmu[mmu].cmmu_regs)); + return *(volatile unsigned *)(reg + (char*)(cmmu[mmu].cmmu_regs)); } /* * This function is called by the MMU module and pokes values * into the CMMU's registers. */ -void m18x_cmmu_set(int reg, unsigned val, int flags, - int num, int mode, int access, vm_offset_t addr) +void +m18x_cmmu_set(int reg, unsigned val, int flags, + int num, int mode, int access, vm_offset_t addr) { - register int mmu; - - if (flags & NUM_CMMU) { - /* - * Special case: user supplied CMMU number directly as argument. - * Simply store the value away. - */ - /* assert(num < max_cmmus); */ - m18x_cmmu_store(num, reg, val); - return; - } - - /* - * We scan all CMMUs to find the matching ones and store the - * values there. - */ - for (mmu = num*cpu_cmmu_ratio; mmu < (num+1)*cpu_cmmu_ratio; mmu++) { - if (((flags & MODE_VAL)) && - (cmmu[mmu].which != mode)) - continue; - if (((flags & ACCESS_VAL)) && - (cmmu[mmu].cmmu_access != access) && - (cmmu[mmu].cmmu_access != CMMU_ACS_BOTH)) - continue; - if (flags & ADDR_VAL) { - if (((addr & cmmu[mmu].cmmu_addr_mask) == cmmu[mmu].cmmu_addr) - != cmmu[mmu].cmmu_addr_match) { - continue; - } - } - m18x_cmmu_store(mmu, reg, val); - } + register int mmu; + + if (flags & NUM_CMMU) { + /* + * Special case: user supplied CMMU number directly as argument. + * Simply store the value away. + */ + /* assert(num < max_cmmus); */ + m18x_cmmu_store(num, reg, val); + return; + } + + /* + * We scan all CMMUs to find the matching ones and store the + * values there. + */ + for (mmu = num*cpu_cmmu_ratio; mmu < (num+1)*cpu_cmmu_ratio; mmu++) { + if (((flags & MODE_VAL)) && + (cmmu[mmu].which != mode)) + continue; + if (((flags & ACCESS_VAL)) && + (cmmu[mmu].cmmu_access != access) && + (cmmu[mmu].cmmu_access != CMMU_ACS_BOTH)) + continue; + if (flags & ADDR_VAL) { + if (((addr & cmmu[mmu].cmmu_addr_mask) == cmmu[mmu].cmmu_addr) + != cmmu[mmu].cmmu_addr_match) { + continue; + } + } + m18x_cmmu_store(mmu, reg, val); + } } #ifdef DDB /* * Used by DDB for cache probe functions */ -unsigned m18x_cmmu_get_by_mode(int cpu, int mode) +unsigned +m18x_cmmu_get_by_mode(int cpu, int mode) { - register int mmu; - - for (mmu = cpu*cpu_cmmu_ratio; mmu < (cpu+1)*cpu_cmmu_ratio; mmu++) - if (cmmu[mmu].which == mode) - return mmu; - printf("can't figure out first %s CMMU for CPU %d\n", - (mode == DATA_CMMU) ? "data" : "instruction", cpu); - panic("m18x_cmmu_get_by_mode"); + register int mmu; + + for (mmu = cpu*cpu_cmmu_ratio; mmu < (cpu+1)*cpu_cmmu_ratio; mmu++) + if (cmmu[mmu].which == mode) + return mmu; + printf("can't figure out first %s CMMU for CPU %d\n", + (mode == DATA_CMMU) ? "data" : "instruction", cpu); + panic("m18x_cmmu_get_by_mode"); } #endif static char *mmutypes[8] = { - "Unknown (0)", - "Unknown (1)", - "Unknown (2)", - "Unknown (3)", - "Unknown (4)", - "M88200 (16K)", - "M88204 (64K)", - "Unknown (7)" + "Unknown (0)", + "Unknown (1)", + "Unknown (2)", + "Unknown (3)", + "Unknown (4)", + "M88200 (16K)", + "M88204 (64K)", + "Unknown (7)" }; /* @@ -699,50 +729,51 @@ static char *mmutypes[8] = { * number and master/slave status . Should be called first * by the master, before the slaves are started. */ -void m18x_cpu_configuration_print(int master) +void +m18x_cpu_configuration_print(int master) { - int pid = read_processor_identification_register(); - int proctype = (pid & 0xff00) >> 8; - int procvers = (pid & 0xe) >> 1; - int mmu, cpu = cpu_number(); - struct simplelock print_lock; + int pid = read_processor_identification_register(); + int proctype = (pid & 0xff00) >> 8; + int procvers = (pid & 0xe) >> 1; + int mmu, cpu = cpu_number(); + struct simplelock print_lock; - if (master) - simple_lock_init(&print_lock); + if (master) + simple_lock_init(&print_lock); - simple_lock(&print_lock); + simple_lock(&print_lock); - printf("Processor %d: ", cpu); - if (proctype) - printf("Architectural Revision 0x%x UNKNOWN CPU TYPE Version 0x%x\n", - proctype, procvers); - else - printf("M88100 Version 0x%x\n", procvers); + printf("Processor %d: ", cpu); + if (proctype) + printf("Architectural Revision 0x%x UNKNOWN CPU TYPE Version 0x%x\n", + proctype, procvers); + else + printf("M88100 Version 0x%x\n", procvers); #if ERRATA__XXX_USR == 0 - if (procvers < 2) - printf("WARNING: M88100 bug workaround code not enabled!!!\n"); + if (procvers < 2) + printf("WARNING: M88100 bug workaround code not enabled!!!\n"); #endif - for (mmu = cpu*cpu_cmmu_ratio; mmu < (cpu+1)*cpu_cmmu_ratio; mmu++) { - int idr = m18x_cmmu_get(mmu, CMMU_IDR); - int mmuid = (0xe00000 & idr)>>21; - - printf(" %s %s Cache: ", - (cmmu[mmu].cmmu_access == CMMU_ACS_BOTH) ? "Spv and User" : - ((cmmu[mmu].cmmu_access == CMMU_ACS_USER) ? "User " : - "Supervisor "), - (cmmu[mmu].which == INST_CMMU) ? "Instruction" : - "Data "); - if (mmutypes[mmuid][0] == 'U') - printf("Type 0x%x ", mmuid); - else - printf("%s ", mmutypes[mmuid]); - printf("Version 0x%x\n", (idr & 0x1f0000)>>16); - } - printf (" Configured as %s and started\n", master ? "master" : "slave"); - - simple_unlock(&print_lock); + for (mmu = cpu*cpu_cmmu_ratio; mmu < (cpu+1)*cpu_cmmu_ratio; mmu++) { + int idr = m18x_cmmu_get(mmu, CMMU_IDR); + int mmuid = (0xe00000 & idr)>>21; + + printf(" %s %s Cache: ", + (cmmu[mmu].cmmu_access == CMMU_ACS_BOTH) ? "Spv and User" : + ((cmmu[mmu].cmmu_access == CMMU_ACS_USER) ? "User " : + "Supervisor "), + (cmmu[mmu].which == INST_CMMU) ? "Instruction" : + "Data "); + if (mmutypes[mmuid][0] == 'U') + printf("Type 0x%x ", mmuid); + else + printf("%s ", mmutypes[mmuid]); + printf("Version 0x%x\n", (idr & 0x1f0000)>>16); + } + printf (" Configured as %s and started\n", master ? "master" : "slave"); + + simple_unlock(&print_lock); } /* @@ -751,210 +782,211 @@ void m18x_cpu_configuration_print(int master) void m18x_cmmu_init(void) { - unsigned tmp, cmmu_num; - union cpupid id; - int cpu; - - for (cpu = 0; cpu < max_cpus; cpu++) { - cpu_cmmu[cpu].pair[INST_CMMU] = cpu_cmmu[cpu].pair[DATA_CMMU] = 0; - } - - for (cmmu_num = 0; cmmu_num < max_cmmus; cmmu_num++) - if (m18x_cmmu_alive(cmmu_num)) { - id.cpupid = cmmu[cmmu_num].cmmu_regs->idr; - - cpu_cmmu[cmmu[cmmu_num].cmmu_cpu].pair[cmmu[cmmu_num].which] = - &cmmu[cmmu_num]; - /* - * Reset cache data.... - * as per M88200 Manual (2nd Ed.) section 3.11. - */ - for (tmp = 0; tmp < 255; tmp++) { - cmmu[cmmu_num].cmmu_regs->sar = tmp << 4; - cmmu[cmmu_num].cmmu_regs->cssp = 0x3f0ff000; - } - - /* 88204 has additional cache to clear */ - if (id.m88200.type == M88204) { - for (tmp = 0; tmp < 255; tmp++) { - cmmu[cmmu_num].cmmu_regs->sar = tmp<<4; - cmmu[cmmu_num].cmmu_regs->cssp1 = 0x3f0ff000; - } - for (tmp = 0; tmp < 255; tmp++) { - cmmu[cmmu_num].cmmu_regs->sar = tmp<<4; - cmmu[cmmu_num].cmmu_regs->cssp2 = 0x3f0ff000; - } - for (tmp = 0; tmp < 255; tmp++) { - cmmu[cmmu_num].cmmu_regs->sar = tmp<<4; - cmmu[cmmu_num].cmmu_regs->cssp3 = 0x3f0ff000; - } - } - - /* - * Set the SCTR, SAPR, and UAPR to some known state - * (I don't trust the reset to do it). - */ - tmp = - ! CMMU_SCTR_PE | /* not parity enable */ - ! CMMU_SCTR_SE | /* not snoop enable */ - ! CMMU_SCTR_PR ; /* not priority arbitration */ - cmmu[cmmu_num].cmmu_regs->sctr = tmp; - - tmp = - (0x00000 << 12) | /* segment table base address */ - AREA_D_WT | /* write through */ - AREA_D_G | /* global */ - AREA_D_CI | /* cache inhibit */ - ! AREA_D_TE ; /* not translation enable */ - cmmu[cmmu_num].cmmu_regs->sapr = - cmmu[cmmu_num].cmmu_regs->uapr = tmp; + unsigned tmp, cmmu_num; + union cpupid id; + int cpu; + + for (cpu = 0; cpu < max_cpus; cpu++) { + cpu_cmmu[cpu].pair[INST_CMMU] = cpu_cmmu[cpu].pair[DATA_CMMU] = 0; + } + + for (cmmu_num = 0; cmmu_num < max_cmmus; cmmu_num++) + if (m18x_cmmu_alive(cmmu_num)) { + id.cpupid = cmmu[cmmu_num].cmmu_regs->idr; + + cpu_cmmu[cmmu[cmmu_num].cmmu_cpu].pair[cmmu[cmmu_num].which] = + &cmmu[cmmu_num]; + /* + * Reset cache data.... + * as per M88200 Manual (2nd Ed.) section 3.11. + */ + for (tmp = 0; tmp < 255; tmp++) { + cmmu[cmmu_num].cmmu_regs->sar = tmp << 4; + cmmu[cmmu_num].cmmu_regs->cssp = 0x3f0ff000; + } + + /* 88204 has additional cache to clear */ + if (id.m88200.type == M88204) { + for (tmp = 0; tmp < 255; tmp++) { + cmmu[cmmu_num].cmmu_regs->sar = tmp<<4; + cmmu[cmmu_num].cmmu_regs->cssp1 = 0x3f0ff000; + } + for (tmp = 0; tmp < 255; tmp++) { + cmmu[cmmu_num].cmmu_regs->sar = tmp<<4; + cmmu[cmmu_num].cmmu_regs->cssp2 = 0x3f0ff000; + } + for (tmp = 0; tmp < 255; tmp++) { + cmmu[cmmu_num].cmmu_regs->sar = tmp<<4; + cmmu[cmmu_num].cmmu_regs->cssp3 = 0x3f0ff000; + } + } + + /* + * Set the SCTR, SAPR, and UAPR to some known state + * (I don't trust the reset to do it). + */ + tmp = + ! CMMU_SCTR_PE | /* not parity enable */ + ! CMMU_SCTR_SE | /* not snoop enable */ + ! CMMU_SCTR_PR ; /* not priority arbitration */ + cmmu[cmmu_num].cmmu_regs->sctr = tmp; + + tmp = + (0x00000 << 12) | /* segment table base address */ + AREA_D_WT | /* write through */ + AREA_D_G | /* global */ + AREA_D_CI | /* cache inhibit */ + ! AREA_D_TE ; /* not translation enable */ + cmmu[cmmu_num].cmmu_regs->sapr = + cmmu[cmmu_num].cmmu_regs->uapr = tmp; #if SHADOW_BATC - cmmu[cmmu_num].batc[0] = - cmmu[cmmu_num].batc[1] = - cmmu[cmmu_num].batc[2] = - cmmu[cmmu_num].batc[3] = - cmmu[cmmu_num].batc[4] = - cmmu[cmmu_num].batc[5] = - cmmu[cmmu_num].batc[6] = - cmmu[cmmu_num].batc[7] = 0; + cmmu[cmmu_num].batc[0] = + cmmu[cmmu_num].batc[1] = + cmmu[cmmu_num].batc[2] = + cmmu[cmmu_num].batc[3] = + cmmu[cmmu_num].batc[4] = + cmmu[cmmu_num].batc[5] = + cmmu[cmmu_num].batc[6] = + cmmu[cmmu_num].batc[7] = 0; #endif - cmmu[cmmu_num].cmmu_regs->bwp[0] = - cmmu[cmmu_num].cmmu_regs->bwp[1] = - cmmu[cmmu_num].cmmu_regs->bwp[2] = - cmmu[cmmu_num].cmmu_regs->bwp[3] = - cmmu[cmmu_num].cmmu_regs->bwp[4] = - cmmu[cmmu_num].cmmu_regs->bwp[5] = - cmmu[cmmu_num].cmmu_regs->bwp[6] = - cmmu[cmmu_num].cmmu_regs->bwp[7] = 0; - cmmu[cmmu_num].cmmu_regs->scr = CMMU_FLUSH_CACHE_INV_ALL; - cmmu[cmmu_num].cmmu_regs->scr = CMMU_FLUSH_SUPER_ALL; - cmmu[cmmu_num].cmmu_regs->scr = CMMU_FLUSH_USER_ALL; - } - - /* - * Enable snooping... - */ - for (cpu = 0; cpu < max_cpus; cpu++) { - if (!cpu_sets[cpu]) - continue; - - /* - * Enable snooping. - * We enable it for instruction cmmus as well so that we can have - * breakpoints, etc, and modify code. - */ - if (cputyp == CPU_188) { - tmp = - ! CMMU_SCTR_PE | /* not parity enable */ - CMMU_SCTR_SE | /* snoop enable */ - ! CMMU_SCTR_PR ; /* not priority arbitration */ - } else { - tmp = - ! CMMU_SCTR_PE | /* not parity enable */ - ! CMMU_SCTR_PR ; /* not priority arbitration */ - } - m18x_cmmu_set(CMMU_SCTR, tmp, 0, cpu, DATA_CMMU, 0, 0); - m18x_cmmu_set(CMMU_SCTR, tmp, 0, cpu, INST_CMMU, 0, 0); - - m18x_cmmu_set(CMMU_SCR, CMMU_FLUSH_SUPER_ALL, ACCESS_VAL, - cpu, DATA_CMMU, CMMU_ACS_SUPER, 0); - m18x_cmmu_set(CMMU_SCR, CMMU_FLUSH_SUPER_ALL, ACCESS_VAL, - cpu, INST_CMMU, CMMU_ACS_SUPER, 0); - } - - /* - * Turn on some cache. - */ - for (cpu = 0; cpu < max_cpus; cpu++) { - if (!cpu_sets[cpu]) - continue; - /* - * Enable some caching for the instruction stream. - * Can't cache data yet 'cause device addresses can never - * be cached, and we don't have those no-caching zones - * set up yet.... - */ - tmp = - (0x00000 << 12) | /* segment table base address */ - AREA_D_WT | /* write through */ - AREA_D_G | /* global */ - AREA_D_CI | /* cache inhibit */ - ! AREA_D_TE ; /* not translation enable */ - /* - REGS(cpu, INST_CMMU).sapr = tmp; - */ - m18x_cmmu_set(CMMU_SAPR, tmp, MODE_VAL, - cpu, INST_CMMU, 0, 0); - - /* - REGS(cpu, DATA_CMMU).scr = CMMU_FLUSH_SUPER_ALL; - */ - m18x_cmmu_set(CMMU_SCR, CMMU_FLUSH_SUPER_ALL, ACCESS_VAL|MODE_VAL, - cpu, DATA_CMMU, CMMU_ACS_SUPER, 0); - } + cmmu[cmmu_num].cmmu_regs->bwp[0] = + cmmu[cmmu_num].cmmu_regs->bwp[1] = + cmmu[cmmu_num].cmmu_regs->bwp[2] = + cmmu[cmmu_num].cmmu_regs->bwp[3] = + cmmu[cmmu_num].cmmu_regs->bwp[4] = + cmmu[cmmu_num].cmmu_regs->bwp[5] = + cmmu[cmmu_num].cmmu_regs->bwp[6] = + cmmu[cmmu_num].cmmu_regs->bwp[7] = 0; + cmmu[cmmu_num].cmmu_regs->scr = CMMU_FLUSH_CACHE_INV_ALL; + cmmu[cmmu_num].cmmu_regs->scr = CMMU_FLUSH_SUPER_ALL; + cmmu[cmmu_num].cmmu_regs->scr = CMMU_FLUSH_USER_ALL; + } + + /* + * Enable snooping... + */ + for (cpu = 0; cpu < max_cpus; cpu++) { + if (!cpu_sets[cpu]) + continue; + + /* + * Enable snooping. + * We enable it for instruction cmmus as well so that we can have + * breakpoints, etc, and modify code. + */ + if (cputyp == CPU_188) { + tmp = + ! CMMU_SCTR_PE | /* not parity enable */ + CMMU_SCTR_SE | /* snoop enable */ + ! CMMU_SCTR_PR ; /* not priority arbitration */ + } else { + tmp = + ! CMMU_SCTR_PE | /* not parity enable */ + ! CMMU_SCTR_PR ; /* not priority arbitration */ + } + m18x_cmmu_set(CMMU_SCTR, tmp, 0, cpu, DATA_CMMU, 0, 0); + m18x_cmmu_set(CMMU_SCTR, tmp, 0, cpu, INST_CMMU, 0, 0); + + m18x_cmmu_set(CMMU_SCR, CMMU_FLUSH_SUPER_ALL, ACCESS_VAL, + cpu, DATA_CMMU, CMMU_ACS_SUPER, 0); + m18x_cmmu_set(CMMU_SCR, CMMU_FLUSH_SUPER_ALL, ACCESS_VAL, + cpu, INST_CMMU, CMMU_ACS_SUPER, 0); + } + + /* + * Turn on some cache. + */ + for (cpu = 0; cpu < max_cpus; cpu++) { + if (!cpu_sets[cpu]) + continue; + /* + * Enable some caching for the instruction stream. + * Can't cache data yet 'cause device addresses can never + * be cached, and we don't have those no-caching zones + * set up yet.... + */ + tmp = + (0x00000 << 12) | /* segment table base address */ + AREA_D_WT | /* write through */ + AREA_D_G | /* global */ + AREA_D_CI | /* cache inhibit */ + ! AREA_D_TE ; /* not translation enable */ + /* + REGS(cpu, INST_CMMU).sapr = tmp; + */ + m18x_cmmu_set(CMMU_SAPR, tmp, MODE_VAL, + cpu, INST_CMMU, 0, 0); + + /* + REGS(cpu, DATA_CMMU).scr = CMMU_FLUSH_SUPER_ALL; + */ + m18x_cmmu_set(CMMU_SCR, CMMU_FLUSH_SUPER_ALL, ACCESS_VAL|MODE_VAL, + cpu, DATA_CMMU, CMMU_ACS_SUPER, 0); + } } - /* * Just before poweroff or reset.... */ void m18x_cmmu_shutdown_now(void) { - unsigned tmp; - unsigned cmmu_num; - - /* - * Now set some state as we like... - */ - for (cmmu_num = 0; cmmu_num < MAX_CMMUS; cmmu_num++) { - if (cputyp == CPU_188) { - tmp = - ! CMMU_SCTR_PE | /* parity enable */ - ! CMMU_SCTR_SE | /* snoop enable */ - ! CMMU_SCTR_PR ; /* priority arbitration */ - } else { - tmp = - ! CMMU_SCTR_PE | /* parity enable */ - ! CMMU_SCTR_PR ; /* priority arbitration */ - } - - cmmu[cmmu_num].cmmu_regs->sctr = tmp; - - tmp = - (0x00000 << 12) | /* segment table base address */ - ! AREA_D_WT | /* write through */ - ! AREA_D_G | /* global */ - AREA_D_CI | /* cache inhibit */ - ! AREA_D_TE ; /* translation disable */ - - cmmu[cmmu_num].cmmu_regs->sapr = tmp; - cmmu[cmmu_num].cmmu_regs->uapr = tmp; - } + unsigned tmp; + unsigned cmmu_num; + + /* + * Now set some state as we like... + */ + for (cmmu_num = 0; cmmu_num < MAX_CMMUS; cmmu_num++) { + if (cputyp == CPU_188) { + tmp = + ! CMMU_SCTR_PE | /* parity enable */ + ! CMMU_SCTR_SE | /* snoop enable */ + ! CMMU_SCTR_PR ; /* priority arbitration */ + } else { + tmp = + ! CMMU_SCTR_PE | /* parity enable */ + ! CMMU_SCTR_PR ; /* priority arbitration */ + } + + cmmu[cmmu_num].cmmu_regs->sctr = tmp; + + tmp = + (0x00000 << 12) | /* segment table base address */ + ! AREA_D_WT | /* write through */ + ! AREA_D_G | /* global */ + AREA_D_CI | /* cache inhibit */ + ! AREA_D_TE ; /* translation disable */ + + cmmu[cmmu_num].cmmu_regs->sapr = tmp; + cmmu[cmmu_num].cmmu_regs->uapr = tmp; + } } #define PARITY_ENABLE /* * enable parity */ -void m18x_cmmu_parity_enable(void) +void +m18x_cmmu_parity_enable(void) { #ifdef PARITY_ENABLE - register int cmmu_num; - - for (cmmu_num = 0; cmmu_num < max_cmmus; cmmu_num++) { - if (m18x_cmmu_alive(cmmu_num)) { - register unsigned val1 = m18x_cmmu_get(cmmu_num, CMMU_SCTR); - - /* - cmmu[cmmu_num].cmmu_regs->sctr |= CMMU_SCTR_PE; - */ - m18x_cmmu_set(CMMU_SCTR, val1 | CMMU_SCTR_PE, NUM_CMMU, - cmmu_num, 0, 0, 0); - } - } + register int cmmu_num; + + for (cmmu_num = 0; cmmu_num < max_cmmus; cmmu_num++) { + if (m18x_cmmu_alive(cmmu_num)) { + register unsigned val1 = + m18x_cmmu_get(cmmu_num, CMMU_SCTR); + + /* + cmmu[cmmu_num].cmmu_regs->sctr |= CMMU_SCTR_PE; + */ + m18x_cmmu_set(CMMU_SCTR, val1 | CMMU_SCTR_PE, + NUM_CMMU, cmmu_num, 0, 0, 0); + } + } #endif /* PARITY_ENABLE */ } @@ -965,38 +997,39 @@ void m18x_cmmu_parity_enable(void) */ #define ILLADDRESS U(0x0F000000) /* any faulty address */ -unsigned m18x_cmmu_cpu_number(void) +unsigned +m18x_cmmu_cpu_number(void) { - register unsigned cmmu_no; - int i; - - - for (i=0; i < 10; i++) { - /* clear CMMU p-bus status registers */ - for (cmmu_no = 0; cmmu_no < MAX_CMMUS; cmmu_no++) { - if (cmmu[cmmu_no].cmmu_alive == CMMU_AVAILABLE && - cmmu[cmmu_no].which == DATA_CMMU) - cmmu[cmmu_no].cmmu_regs->pfSTATUSr = 0; - } - - /* access faulting address */ - badwordaddr((void *)ILLADDRESS); - - /* check which CMMU reporting the fault */ - for (cmmu_no = 0; cmmu_no < MAX_CMMUS; cmmu_no++) { - if (cmmu[cmmu_no].cmmu_alive == CMMU_AVAILABLE && - cmmu[cmmu_no].which == DATA_CMMU && - cmmu[cmmu_no].cmmu_regs->pfSTATUSr & 0x70000) { - if (cmmu[cmmu_no].cmmu_regs->pfSTATUSr & 0x70000) { - cmmu[cmmu_no].cmmu_regs->pfSTATUSr = 0; /* to be clean */ - cmmu[cmmu_no].cmmu_alive = CMMU_MARRIED; - return cmmu[cmmu_no].cmmu_cpu; - } - } - } - } - panic("m18x_cmmu_cpu_number: could not determine my cpu number"); - return 0; /* to make compiler happy */ + register unsigned cmmu_no; + int i; + + + for (i=0; i < 10; i++) { + /* clear CMMU p-bus status registers */ + for (cmmu_no = 0; cmmu_no < MAX_CMMUS; cmmu_no++) { + if (cmmu[cmmu_no].cmmu_alive == CMMU_AVAILABLE && + cmmu[cmmu_no].which == DATA_CMMU) + cmmu[cmmu_no].cmmu_regs->pfSTATUSr = 0; + } + + /* access faulting address */ + badwordaddr((void *)ILLADDRESS); + + /* check which CMMU reporting the fault */ + for (cmmu_no = 0; cmmu_no < MAX_CMMUS; cmmu_no++) { + if (cmmu[cmmu_no].cmmu_alive == CMMU_AVAILABLE && + cmmu[cmmu_no].which == DATA_CMMU && + cmmu[cmmu_no].cmmu_regs->pfSTATUSr & 0x70000) { + if (cmmu[cmmu_no].cmmu_regs->pfSTATUSr & 0x70000) { + cmmu[cmmu_no].cmmu_regs->pfSTATUSr = 0; /* to be clean */ + cmmu[cmmu_no].cmmu_alive = CMMU_MARRIED; + return cmmu[cmmu_no].cmmu_cpu; + } + } + } + } + panic("m18x_cmmu_cpu_number: could not determine my cpu number"); + return 0; /* to make compiler happy */ } /** @@ -1009,7 +1042,7 @@ static void m18x_cmmu_remote_set(unsigned cpu, unsigned r, unsigned data, unsigned x) { - *(volatile unsigned *)(r + (char*)®S(cpu,data)) = x; + *(volatile unsigned *)(r + (char*)®S(cpu,data)) = x; } /* @@ -1022,61 +1055,61 @@ static unsigned m18x_cmmu_remote_get(unsigned cpu, unsigned r, unsigned data) { - return (*(volatile unsigned *)(r + (char*)®S(cpu,data))); + return (*(volatile unsigned *)(r + (char*)®S(cpu,data))); } /* Needs no locking - read only registers */ unsigned m18x_cmmu_get_idr(unsigned data) { - int cpu; - cpu = cpu_number(); - return REGS(cpu,data).idr; + int cpu; + cpu = cpu_number(); + return REGS(cpu,data).idr; } void m18x_cmmu_set_sapr(unsigned ap) { - int cpu; - cpu = cpu_number(); - - if (cache_policy & CACHE_INH) - ap |= AREA_D_CI; - /* - REGS(cpu, INST_CMMU).sapr = ap; - REGS(cpu, DATA_CMMU).sapr = ap; - */ - m18x_cmmu_set(CMMU_SAPR, ap, ACCESS_VAL, - cpu, 0, CMMU_ACS_SUPER, 0); + int cpu; + cpu = cpu_number(); + + if (cache_policy & CACHE_INH) + ap |= AREA_D_CI; + /* + REGS(cpu, INST_CMMU).sapr = ap; + REGS(cpu, DATA_CMMU).sapr = ap; + */ + m18x_cmmu_set(CMMU_SAPR, ap, ACCESS_VAL, + cpu, 0, CMMU_ACS_SUPER, 0); } void m18x_cmmu_remote_set_sapr(unsigned cpu, unsigned ap) { - if (cache_policy & CACHE_INH) - ap |= AREA_D_CI; - - /* - REGS(cpu, INST_CMMU).sapr = ap; - REGS(cpu, DATA_CMMU).sapr = ap; - */ - m18x_cmmu_set(CMMU_SAPR, ap, ACCESS_VAL, - cpu, 0, CMMU_ACS_SUPER, 0); + if (cache_policy & CACHE_INH) + ap |= AREA_D_CI; + + /* + REGS(cpu, INST_CMMU).sapr = ap; + REGS(cpu, DATA_CMMU).sapr = ap; + */ + m18x_cmmu_set(CMMU_SAPR, ap, ACCESS_VAL, + cpu, 0, CMMU_ACS_SUPER, 0); } void m18x_cmmu_set_uapr(unsigned ap) { - int cpu; - cpu = cpu_number(); - - /* this functionality also mimiced in m18x_cmmu_pmap_activate() */ - /* - REGS(cpu, INST_CMMU).uapr = ap; - REGS(cpu, DATA_CMMU).uapr = ap; - */ - m18x_cmmu_set(CMMU_UAPR, ap, ACCESS_VAL, - cpu, 0, CMMU_ACS_USER, 0); + int cpu; + cpu = cpu_number(); + + /* this functionality also mimiced in m18x_cmmu_pmap_activate() */ + /* + REGS(cpu, INST_CMMU).uapr = ap; + REGS(cpu, DATA_CMMU).uapr = ap; + */ + m18x_cmmu_set(CMMU_UAPR, ap, ACCESS_VAL, + cpu, 0, CMMU_ACS_USER, 0); } /* @@ -1088,23 +1121,22 @@ m18x_cmmu_set_uapr(unsigned ap) * batc values. */ void -m18x_cmmu_set_batc_entry( - unsigned cpu, - unsigned entry_no, - unsigned data, /* 1 = data, 0 = instruction */ - unsigned value) /* the value to stuff into the batc */ +m18x_cmmu_set_batc_entry(unsigned cpu, + unsigned entry_no, + unsigned data, /* 1 = data, 0 = instruction */ + unsigned value) /* the value to stuff into the batc */ { - /* - REGS(cpu,data).bwp[entry_no] = value; - */ - m18x_cmmu_set(CMMU_BWP(entry_no), value, MODE_VAL|ACCESS_VAL, - cpu, data, CMMU_ACS_USER, 0); + /* + REGS(cpu,data).bwp[entry_no] = value; + */ + m18x_cmmu_set(CMMU_BWP(entry_no), value, MODE_VAL|ACCESS_VAL, + cpu, data, CMMU_ACS_USER, 0); #if SHADOW_BATC - CMMU(cpu,data)->batc[entry_no] = value; + CMMU(cpu,data)->batc[entry_no] = value; #endif #if 0 /* was for debugging piece (peace?) of mind */ - REGS(cpu,data).scr = CMMU_FLUSH_SUPER_ALL; - REGS(cpu,data).scr = CMMU_FLUSH_USER_ALL; + REGS(cpu,data).scr = CMMU_FLUSH_SUPER_ALL; + REGS(cpu,data).scr = CMMU_FLUSH_USER_ALL; #endif } @@ -1113,34 +1145,33 @@ m18x_cmmu_set_batc_entry( * the data and instruction cache for the named CPU. */ void -m18x_cmmu_set_pair_batc_entry( - unsigned cpu, - unsigned entry_no, - unsigned value) /* the value to stuff into the batc */ +m18x_cmmu_set_pair_batc_entry(unsigned cpu, + unsigned entry_no, + unsigned value) /* the value to stuff into the batc */ { - /* - REGS(cpu,DATA_CMMU).bwp[entry_no] = value; - */ - m18x_cmmu_set(CMMU_BWP(entry_no), value, MODE_VAL|ACCESS_VAL, - cpu, DATA_CMMU, CMMU_ACS_USER, 0); + /* + REGS(cpu,DATA_CMMU).bwp[entry_no] = value; + */ + m18x_cmmu_set(CMMU_BWP(entry_no), value, MODE_VAL|ACCESS_VAL, + cpu, DATA_CMMU, CMMU_ACS_USER, 0); #if SHADOW_BATC - CMMU(cpu,DATA_CMMU)->batc[entry_no] = value; + CMMU(cpu,DATA_CMMU)->batc[entry_no] = value; #endif - /* - REGS(cpu,INST_CMMU).bwp[entry_no] = value; - */ - m18x_cmmu_set(CMMU_BWP(entry_no), value, MODE_VAL|ACCESS_VAL, - cpu, INST_CMMU, CMMU_ACS_USER, 0); + /* + REGS(cpu,INST_CMMU).bwp[entry_no] = value; + */ + m18x_cmmu_set(CMMU_BWP(entry_no), value, MODE_VAL|ACCESS_VAL, + cpu, INST_CMMU, CMMU_ACS_USER, 0); #if SHADOW_BATC - CMMU(cpu,INST_CMMU)->batc[entry_no] = value; + CMMU(cpu,INST_CMMU)->batc[entry_no] = value; #endif #if 0 /* was for debugging piece (peace?) of mind */ - REGS(cpu,INST_CMMU).scr = CMMU_FLUSH_SUPER_ALL; - REGS(cpu,INST_CMMU).scr = CMMU_FLUSH_USER_ALL; - REGS(cpu,DATA_CMMU).scr = CMMU_FLUSH_SUPER_ALL; - REGS(cpu,DATA_CMMU).scr = CMMU_FLUSH_USER_ALL; + REGS(cpu,INST_CMMU).scr = CMMU_FLUSH_SUPER_ALL; + REGS(cpu,INST_CMMU).scr = CMMU_FLUSH_USER_ALL; + REGS(cpu,DATA_CMMU).scr = CMMU_FLUSH_SUPER_ALL; + REGS(cpu,DATA_CMMU).scr = CMMU_FLUSH_USER_ALL; #endif } @@ -1155,41 +1186,39 @@ m18x_cmmu_set_pair_batc_entry( void m18x_cmmu_flush_remote_tlb(unsigned cpu, unsigned kernel, vm_offset_t vaddr, int size) { - register s = splhigh(); - - if (cpu > max_cpus) { - cpu = cpu_number(); - } - - if ((unsigned)size > M88K_PGBYTES) { - /* - REGS(cpu, INST_CMMU).scr = - REGS(cpu, DATA_CMMU).scr = - kernel ? CMMU_FLUSH_SUPER_ALL : CMMU_FLUSH_USER_ALL; - */ - - m18x_cmmu_set(CMMU_SCR, kernel ? CMMU_FLUSH_SUPER_ALL : CMMU_FLUSH_USER_ALL, ACCESS_VAL, - cpu, 0, kernel ? CMMU_ACS_SUPER : CMMU_ACS_USER, 0); - } else { /* a page or smaller */ - - - /* - REGS(cpu, INST_CMMU).sar = (unsigned)vaddr; - REGS(cpu, DATA_CMMU).sar = (unsigned)vaddr; - */ - m18x_cmmu_set(CMMU_SAR, vaddr, ADDR_VAL|ACCESS_VAL, - cpu, 0, kernel ? CMMU_ACS_SUPER : CMMU_ACS_USER, vaddr); - - /* - REGS(cpu, INST_CMMU).scr = - REGS(cpu, DATA_CMMU).scr = - kernel ? CMMU_FLUSH_SUPER_PAGE : CMMU_FLUSH_USER_PAGE; - */ - m18x_cmmu_set(CMMU_SCR, kernel ? CMMU_FLUSH_SUPER_PAGE : CMMU_FLUSH_USER_PAGE, ADDR_VAL|ACCESS_VAL, - cpu, 0, kernel ? CMMU_ACS_SUPER : CMMU_ACS_USER, vaddr); - } - - splx(s); + register s = splhigh(); + + if (cpu > max_cpus) { + cpu = cpu_number(); + } + + if ((unsigned)size > M88K_PGBYTES) { + /* + REGS(cpu, INST_CMMU).scr = + REGS(cpu, DATA_CMMU).scr = + kernel ? CMMU_FLUSH_SUPER_ALL : CMMU_FLUSH_USER_ALL; + */ + + m18x_cmmu_set(CMMU_SCR, kernel ? CMMU_FLUSH_SUPER_ALL : CMMU_FLUSH_USER_ALL, ACCESS_VAL, + cpu, 0, kernel ? CMMU_ACS_SUPER : CMMU_ACS_USER, 0); + } else { /* a page or smaller */ + /* + REGS(cpu, INST_CMMU).sar = (unsigned)vaddr; + REGS(cpu, DATA_CMMU).sar = (unsigned)vaddr; + */ + m18x_cmmu_set(CMMU_SAR, vaddr, ADDR_VAL|ACCESS_VAL, + cpu, 0, kernel ? CMMU_ACS_SUPER : CMMU_ACS_USER, vaddr); + + /* + REGS(cpu, INST_CMMU).scr = + REGS(cpu, DATA_CMMU).scr = + kernel ? CMMU_FLUSH_SUPER_PAGE : CMMU_FLUSH_USER_PAGE; + */ + m18x_cmmu_set(CMMU_SCR, kernel ? CMMU_FLUSH_SUPER_PAGE : CMMU_FLUSH_USER_PAGE, ADDR_VAL|ACCESS_VAL, + cpu, 0, kernel ? CMMU_ACS_SUPER : CMMU_ACS_USER, vaddr); + } + + splx(s); } /* @@ -1198,9 +1227,9 @@ m18x_cmmu_flush_remote_tlb(unsigned cpu, unsigned kernel, vm_offset_t vaddr, int void m18x_cmmu_flush_tlb(unsigned kernel, vm_offset_t vaddr, int size) { - int cpu; - cpu = cpu_number(); - m18x_cmmu_flush_remote_tlb(cpu, kernel, vaddr, size); + int cpu; + cpu = cpu_number(); + m18x_cmmu_flush_remote_tlb(cpu, kernel, vaddr, size); } /* @@ -1209,50 +1238,49 @@ m18x_cmmu_flush_tlb(unsigned kernel, vm_offset_t vaddr, int size) * Only called from pmap.c's _pmap_activate(). */ void -m18x_cmmu_pmap_activate( - unsigned cpu, - unsigned uapr, - batc_template_t i_batc[BATC_MAX], - batc_template_t d_batc[BATC_MAX]) +m18x_cmmu_pmap_activate(unsigned cpu, + unsigned uapr, + batc_template_t i_batc[BATC_MAX], + batc_template_t d_batc[BATC_MAX]) { - int entry_no; - - - /* the following is from m18x_cmmu_set_uapr */ - /* - REGS(cpu, INST_CMMU).uapr = uapr; - REGS(cpu, DATA_CMMU).uapr = uapr; - */ - m18x_cmmu_set(CMMU_UAPR, uapr, ACCESS_VAL, - cpu, 0, CMMU_ACS_USER, 0); - - for (entry_no = 0; entry_no < BATC_MAX; entry_no++) { - /* - REGS(cpu,INST_CMMU).bwp[entry_no] = i_batc[entry_no].bits; - REGS(cpu,DATA_CMMU).bwp[entry_no] = d_batc[entry_no].bits; - */ - m18x_cmmu_set(CMMU_BWP(entry_no), i_batc[entry_no].bits, MODE_VAL|ACCESS_VAL, - cpu, INST_CMMU, CMMU_ACS_USER, 0); - m18x_cmmu_set(CMMU_BWP(entry_no), d_batc[entry_no].bits, MODE_VAL|ACCESS_VAL, - cpu, DATA_CMMU, CMMU_ACS_USER, 0); + int entry_no; + + + /* the following is from m18x_cmmu_set_uapr */ + /* + REGS(cpu, INST_CMMU).uapr = uapr; + REGS(cpu, DATA_CMMU).uapr = uapr; + */ + m18x_cmmu_set(CMMU_UAPR, uapr, ACCESS_VAL, + cpu, 0, CMMU_ACS_USER, 0); + + for (entry_no = 0; entry_no < BATC_MAX; entry_no++) { + /* + REGS(cpu,INST_CMMU).bwp[entry_no] = i_batc[entry_no].bits; + REGS(cpu,DATA_CMMU).bwp[entry_no] = d_batc[entry_no].bits; + */ + m18x_cmmu_set(CMMU_BWP(entry_no), i_batc[entry_no].bits, MODE_VAL|ACCESS_VAL, + cpu, INST_CMMU, CMMU_ACS_USER, 0); + m18x_cmmu_set(CMMU_BWP(entry_no), d_batc[entry_no].bits, MODE_VAL|ACCESS_VAL, + cpu, DATA_CMMU, CMMU_ACS_USER, 0); #if SHADOW_BATC - CMMU(cpu,INST_CMMU)->batc[entry_no] = i_batc[entry_no].bits; - CMMU(cpu,DATA_CMMU)->batc[entry_no] = d_batc[entry_no].bits; + CMMU(cpu,INST_CMMU)->batc[entry_no] = i_batc[entry_no].bits; + CMMU(cpu,DATA_CMMU)->batc[entry_no] = d_batc[entry_no].bits; #endif - } - - - /* - * Flush the user TLB. - * IF THE KERNEL WILL EVER CARE ABOUT THE BATC ENTRIES, - * THE SUPERVISOR TLBs SHOULB EE FLUSHED AS WELL. - */ - /* - REGS(cpu, INST_CMMU).scr = CMMU_FLUSH_USER_ALL; - REGS(cpu, DATA_CMMU).scr = CMMU_FLUSH_USER_ALL; - */ - m18x_cmmu_set(CMMU_SCR, CMMU_FLUSH_USER_ALL, ACCESS_VAL, - cpu, 0, CMMU_ACS_USER, 0); + } + + + /* + * Flush the user TLB. + * IF THE KERNEL WILL EVER CARE ABOUT THE BATC ENTRIES, + * THE SUPERVISOR TLBs SHOULB EE FLUSHED AS WELL. + */ + /* + REGS(cpu, INST_CMMU).scr = CMMU_FLUSH_USER_ALL; + REGS(cpu, DATA_CMMU).scr = CMMU_FLUSH_USER_ALL; + */ + m18x_cmmu_set(CMMU_SCR, CMMU_FLUSH_USER_ALL, ACCESS_VAL, + cpu, 0, CMMU_ACS_USER, 0); } /** @@ -1274,76 +1302,68 @@ m18x_cmmu_pmap_activate( void m18x_cmmu_flush_remote_cache(int cpu, vm_offset_t physaddr, int size) { - register s = splhigh(); + register s = splhigh(); #if !defined(BROKEN_MMU_MASK) - if (size < 0 || size > NBSG ) { - - - /* - REGS(cpu, INST_CMMU).scr = CMMU_FLUSH_CACHE_CBI_ALL; - REGS(cpu, DATA_CMMU).scr = CMMU_FLUSH_CACHE_CBI_ALL; - */ - m18x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_ALL, 0, - cpu, 0, 0, 0); - } else if (size <= 16) { - - - /* - REGS(cpu, INST_CMMU).sar = (unsigned)physaddr; - REGS(cpu, DATA_CMMU).sar = (unsigned)physaddr; - */ - m18x_cmmu_set(CMMU_SAR, (unsigned)physaddr, ADDR_VAL, - cpu, 0, 0, (unsigned)physaddr); - /* - REGS(cpu, INST_CMMU).scr = CMMU_FLUSH_CACHE_CBI_LINE; - REGS(cpu, DATA_CMMU).scr = CMMU_FLUSH_CACHE_CBI_LINE; - */ - m18x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_LINE , ADDR_VAL, - cpu, 0, 0, (unsigned)physaddr); - } else if (size <= NBPG) { - - - /* - REGS(cpu, INST_CMMU).sar = (unsigned)physaddr; - REGS(cpu, DATA_CMMU).sar = (unsigned)physaddr; - */ - m18x_cmmu_set(CMMU_SAR, (unsigned)physaddr, ADDR_VAL, - cpu, 0, 0, (unsigned)physaddr); - /* - REGS(cpu, INST_CMMU).scr = CMMU_FLUSH_CACHE_CBI_PAGE; - REGS(cpu, DATA_CMMU).scr = CMMU_FLUSH_CACHE_CBI_PAGE; - */ - m18x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_PAGE , ADDR_VAL, - cpu, 0, 0, (unsigned)physaddr); - } else { - /* - REGS(cpu, INST_CMMU).sar = (unsigned)physaddr; - REGS(cpu, DATA_CMMU).sar = (unsigned)physaddr; - */ - m18x_cmmu_set(CMMU_SAR, (unsigned)physaddr, 0, - cpu, 0, 0, 0); - /* - REGS(cpu, INST_CMMU).scr = CMMU_FLUSH_CACHE_CBI_SEGMENT; - REGS(cpu, DATA_CMMU).scr = CMMU_FLUSH_CACHE_CBI_SEGMENT; - */ - m18x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_SEGMENT, 0, - cpu, 0, 0, 0); - } + if (size < 0 || size > NBSG ) { + /* + REGS(cpu, INST_CMMU).scr = CMMU_FLUSH_CACHE_CBI_ALL; + REGS(cpu, DATA_CMMU).scr = CMMU_FLUSH_CACHE_CBI_ALL; + */ + m18x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_ALL, 0, + cpu, 0, 0, 0); + } else if (size <= 16) { + /* + REGS(cpu, INST_CMMU).sar = (unsigned)physaddr; + REGS(cpu, DATA_CMMU).sar = (unsigned)physaddr; + */ + m18x_cmmu_set(CMMU_SAR, (unsigned)physaddr, ADDR_VAL, + cpu, 0, 0, (unsigned)physaddr); + /* + REGS(cpu, INST_CMMU).scr = CMMU_FLUSH_CACHE_CBI_LINE; + REGS(cpu, DATA_CMMU).scr = CMMU_FLUSH_CACHE_CBI_LINE; + */ + m18x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_LINE , ADDR_VAL, + cpu, 0, 0, (unsigned)physaddr); + } else if (size <= NBPG) { + /* + REGS(cpu, INST_CMMU).sar = (unsigned)physaddr; + REGS(cpu, DATA_CMMU).sar = (unsigned)physaddr; + */ + m18x_cmmu_set(CMMU_SAR, (unsigned)physaddr, ADDR_VAL, + cpu, 0, 0, (unsigned)physaddr); + /* + REGS(cpu, INST_CMMU).scr = CMMU_FLUSH_CACHE_CBI_PAGE; + REGS(cpu, DATA_CMMU).scr = CMMU_FLUSH_CACHE_CBI_PAGE; + */ + m18x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_PAGE , ADDR_VAL, + cpu, 0, 0, (unsigned)physaddr); + } else { + /* + REGS(cpu, INST_CMMU).sar = (unsigned)physaddr; + REGS(cpu, DATA_CMMU).sar = (unsigned)physaddr; + */ + m18x_cmmu_set(CMMU_SAR, (unsigned)physaddr, 0, + cpu, 0, 0, 0); + /* + REGS(cpu, INST_CMMU).scr = CMMU_FLUSH_CACHE_CBI_SEGMENT; + REGS(cpu, DATA_CMMU).scr = CMMU_FLUSH_CACHE_CBI_SEGMENT; + */ + m18x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_SEGMENT, 0, + cpu, 0, 0, 0); + } #else - /* - REGS(cpu, INST_CMMU).scr = CMMU_FLUSH_CACHE_CBI_ALL; - REGS(cpu, DATA_CMMU).scr = CMMU_FLUSH_CACHE_CBI_ALL; - */ - m18x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_ALL, 0, - cpu, 0, 0, 0); + /* + REGS(cpu, INST_CMMU).scr = CMMU_FLUSH_CACHE_CBI_ALL; + REGS(cpu, DATA_CMMU).scr = CMMU_FLUSH_CACHE_CBI_ALL; + */ + m18x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_ALL, 0, + cpu, 0, 0, 0); #endif /* !BROKEN_MMU_MASK */ - - - splx(s); + splx(s); } /* @@ -1352,8 +1372,8 @@ m18x_cmmu_flush_remote_cache(int cpu, vm_offset_t physaddr, int size) void m18x_cmmu_flush_cache(vm_offset_t physaddr, int size) { - int cpu = cpu_number(); - m18x_cmmu_flush_remote_cache(cpu, physaddr, size); + int cpu = cpu_number(); + m18x_cmmu_flush_remote_cache(cpu, physaddr, size); } /* @@ -1362,61 +1382,61 @@ m18x_cmmu_flush_cache(vm_offset_t physaddr, int size) void m18x_cmmu_flush_remote_inst_cache(int cpu, vm_offset_t physaddr, int size) { - register s = splhigh(); + register s = splhigh(); #if !defined(BROKEN_MMU_MASK) - if (size < 0 || size > NBSG ) { - /* - REGS(cpu, INST_CMMU).scr = CMMU_FLUSH_CACHE_CBI_ALL; - */ - m18x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_ALL, MODE_VAL, - cpu, INST_CMMU, 0, 0); - } else if (size <= 16) { - - /* - REGS(cpu, INST_CMMU).sar = (unsigned)physaddr; - */ - m18x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL, - cpu, INST_CMMU, 0, (unsigned)physaddr); - /* - REGS(cpu, INST_CMMU).scr = CMMU_FLUSH_CACHE_CBI_LINE; - */ - m18x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_LINE, MODE_VAL|ADDR_VAL, - cpu, INST_CMMU, 0, (unsigned)physaddr); - } else if (size <= NBPG) { - /* - REGS(cpu, INST_CMMU).sar = (unsigned)physaddr; - */ - m18x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL, - cpu, INST_CMMU, 0, (unsigned)physaddr); - /* - REGS(cpu, INST_CMMU).scr = CMMU_FLUSH_CACHE_CBI_PAGE; - */ - m18x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_PAGE, MODE_VAL|ADDR_VAL, - cpu, INST_CMMU, 0, (unsigned)physaddr); - } else { - /* - REGS(cpu, INST_CMMU).sar = (unsigned)physaddr; - */ - m18x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL, - cpu, INST_CMMU, 0, 0); - /* - REGS(cpu, INST_CMMU).scr = CMMU_FLUSH_CACHE_CBI_SEGMENT; - */ - m18x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_SEGMENT, MODE_VAL, - cpu, INST_CMMU, 0, 0); - } + if (size < 0 || size > NBSG ) { + /* + REGS(cpu, INST_CMMU).scr = CMMU_FLUSH_CACHE_CBI_ALL; + */ + m18x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_ALL, MODE_VAL, + cpu, INST_CMMU, 0, 0); + } else if (size <= 16) { + + /* + REGS(cpu, INST_CMMU).sar = (unsigned)physaddr; + */ + m18x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL, + cpu, INST_CMMU, 0, (unsigned)physaddr); + /* + REGS(cpu, INST_CMMU).scr = CMMU_FLUSH_CACHE_CBI_LINE; + */ + m18x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_LINE, MODE_VAL|ADDR_VAL, + cpu, INST_CMMU, 0, (unsigned)physaddr); + } else if (size <= NBPG) { + /* + REGS(cpu, INST_CMMU).sar = (unsigned)physaddr; + */ + m18x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL, + cpu, INST_CMMU, 0, (unsigned)physaddr); + /* + REGS(cpu, INST_CMMU).scr = CMMU_FLUSH_CACHE_CBI_PAGE; + */ + m18x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_PAGE, MODE_VAL|ADDR_VAL, + cpu, INST_CMMU, 0, (unsigned)physaddr); + } else { + /* + REGS(cpu, INST_CMMU).sar = (unsigned)physaddr; + */ + m18x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL, + cpu, INST_CMMU, 0, 0); + /* + REGS(cpu, INST_CMMU).scr = CMMU_FLUSH_CACHE_CBI_SEGMENT; + */ + m18x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_SEGMENT, MODE_VAL, + cpu, INST_CMMU, 0, 0); + } #else - /* - REGS(cpu, INST_CMMU).scr = CMMU_FLUSH_CACHE_CBI_ALL; - */ - m18x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_ALL, MODE_VAL, - cpu, INST_CMMU, 0, 0); + /* + REGS(cpu, INST_CMMU).scr = CMMU_FLUSH_CACHE_CBI_ALL; + */ + m18x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_ALL, MODE_VAL, + cpu, INST_CMMU, 0, 0); #endif /* !BROKEN_MMU_MASK */ - - splx(s); + + splx(s); } /* @@ -1425,66 +1445,61 @@ m18x_cmmu_flush_remote_inst_cache(int cpu, vm_offset_t physaddr, int size) void m18x_cmmu_flush_inst_cache(vm_offset_t physaddr, int size) { - int cpu; - cpu = cpu_number(); - m18x_cmmu_flush_remote_inst_cache(cpu, physaddr, size); + int cpu; + cpu = cpu_number(); + m18x_cmmu_flush_remote_inst_cache(cpu, physaddr, size); } void m18x_cmmu_flush_remote_data_cache(int cpu, vm_offset_t physaddr, int size) { - register s = splhigh(); - - + register s = splhigh(); #if !defined(BROKEN_MMU_MASK) - if (size < 0 || size > NBSG ) { - - /* - REGS(cpu, DATA_CMMU).scr = CMMU_FLUSH_CACHE_CBI_ALL; - */ - m18x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_ALL, MODE_VAL, - cpu, DATA_CMMU, 0, 0); - } else if (size <= 16) { - /* - REGS(cpu, DATA_CMMU).sar = (unsigned)physaddr; - REGS(cpu, DATA_CMMU).scr = CMMU_FLUSH_CACHE_CBI_LINE; - */ - m18x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL, - cpu, DATA_CMMU, 0, (unsigned)physaddr); - m18x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_LINE, MODE_VAL|ADDR_VAL, - cpu, DATA_CMMU, 0, (unsigned)physaddr); - - } else if (size <= NBPG) { - /* - REGS(cpu, DATA_CMMU).sar = (unsigned)physaddr; - REGS(cpu, DATA_CMMU).scr = CMMU_FLUSH_CACHE_CBI_PAGE; - */ - m18x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL, - cpu, DATA_CMMU, 0, (unsigned)physaddr); - m18x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_PAGE, MODE_VAL|ADDR_VAL, - cpu, DATA_CMMU, 0, (unsigned)physaddr); - } else { - /* - REGS(cpu, DATA_CMMU).sar = (unsigned)physaddr; - REGS(cpu, DATA_CMMU).scr = CMMU_FLUSH_CACHE_CBI_SEGMENT; - */ - m18x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL, - cpu, DATA_CMMU, 0, 0); - m18x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_SEGMENT, MODE_VAL, - cpu, DATA_CMMU, 0, 0); - } + if (size < 0 || size > NBSG ) { + + /* + REGS(cpu, DATA_CMMU).scr = CMMU_FLUSH_CACHE_CBI_ALL; + */ + m18x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_ALL, MODE_VAL, + cpu, DATA_CMMU, 0, 0); + } else if (size <= 16) { + /* + REGS(cpu, DATA_CMMU).sar = (unsigned)physaddr; + REGS(cpu, DATA_CMMU).scr = CMMU_FLUSH_CACHE_CBI_LINE; + */ + m18x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL, + cpu, DATA_CMMU, 0, (unsigned)physaddr); + m18x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_LINE, MODE_VAL|ADDR_VAL, + cpu, DATA_CMMU, 0, (unsigned)physaddr); + + } else if (size <= NBPG) { + /* + REGS(cpu, DATA_CMMU).sar = (unsigned)physaddr; + REGS(cpu, DATA_CMMU).scr = CMMU_FLUSH_CACHE_CBI_PAGE; + */ + m18x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL, + cpu, DATA_CMMU, 0, (unsigned)physaddr); + m18x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_PAGE, MODE_VAL|ADDR_VAL, + cpu, DATA_CMMU, 0, (unsigned)physaddr); + } else { + /* + REGS(cpu, DATA_CMMU).sar = (unsigned)physaddr; + REGS(cpu, DATA_CMMU).scr = CMMU_FLUSH_CACHE_CBI_SEGMENT; + */ + m18x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL, + cpu, DATA_CMMU, 0, 0); + m18x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_SEGMENT, MODE_VAL, + cpu, DATA_CMMU, 0, 0); + } #else - /* - REGS(cpu, DATA_CMMU).scr = CMMU_FLUSH_CACHE_CBI_ALL; - */ - m18x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_ALL, MODE_VAL, - cpu, DATA_CMMU, 0, 0); + /* + REGS(cpu, DATA_CMMU).scr = CMMU_FLUSH_CACHE_CBI_ALL; + */ + m18x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_ALL, MODE_VAL, + cpu, DATA_CMMU, 0, 0); #endif /* !BROKEN_MMU_MASK */ - - - - splx(s); + splx(s); } /* @@ -1493,9 +1508,9 @@ m18x_cmmu_flush_remote_data_cache(int cpu, vm_offset_t physaddr, int size) void m18x_cmmu_flush_data_cache(vm_offset_t physaddr, int size) { - int cpu; - cpu = cpu_number(); - m18x_cmmu_flush_remote_data_cache(cpu, physaddr, size); + int cpu; + cpu = cpu_number(); + m18x_cmmu_flush_remote_data_cache(cpu, physaddr, size); } /* @@ -1504,296 +1519,281 @@ m18x_cmmu_flush_data_cache(vm_offset_t physaddr, int size) void m18x_cmmu_sync_cache(vm_offset_t physaddr, int size) { - register s = splhigh(); - int cpu; - cpu = cpu_number(); - - + register s = splhigh(); + int cpu; + cpu = cpu_number(); #if !defined(BROKEN_MMU_MASK) - if (size < 0 || size > NBSG ) { - /* - REGS(cpu, INST_CMMU).scr = CMMU_FLUSH_CACHE_CB_ALL; - REGS(cpu, DATA_CMMU).scr = CMMU_FLUSH_CACHE_CB_ALL; - */ - m18x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CB_ALL, MODE_VAL, - cpu, DATA_CMMU, 0, 0); - m18x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CB_ALL, MODE_VAL, - cpu, INST_CMMU, 0, 0); - } else if (size <= 16) { - /* - REGS(cpu, INST_CMMU).sar = (unsigned)physaddr; - REGS(cpu, INST_CMMU).scr = CMMU_FLUSH_CACHE_CB_LINE; - */ - m18x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL, - cpu, INST_CMMU, 0, (unsigned)physaddr); - m18x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_CB_LINE, MODE_VAL, - cpu, INST_CMMU, 0, 0); - /* - REGS(cpu, DATA_CMMU).sar = (unsigned)physaddr; - REGS(cpu, DATA_CMMU).scr = CMMU_FLUSH_CACHE_CB_LINE; - */ - m18x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL, - cpu, DATA_CMMU, 0, (unsigned)physaddr); - m18x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_CB_LINE, MODE_VAL, - cpu, DATA_CMMU, 0, 0); - } else if (size <= NBPG) { - /* - REGS(cpu, INST_CMMU).sar = (unsigned)physaddr; - REGS(cpu, INST_CMMU).scr = CMMU_FLUSH_CACHE_CB_PAGE; - */ - m18x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL, - cpu, INST_CMMU, 0, (unsigned)physaddr); - m18x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_CB_PAGE, MODE_VAL, - cpu, INST_CMMU, 0, 0); - /* - REGS(cpu, DATA_CMMU).sar = (unsigned)physaddr; - REGS(cpu, DATA_CMMU).scr = CMMU_FLUSH_CACHE_CB_PAGE; - */ - m18x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL, - cpu, DATA_CMMU, 0, (unsigned)physaddr); - m18x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_CB_PAGE, MODE_VAL, - cpu, DATA_CMMU, 0, 0); - } else { - /* - REGS(cpu, INST_CMMU).sar = (unsigned)physaddr; - REGS(cpu, INST_CMMU).scr = CMMU_FLUSH_CACHE_CB_SEGMENT; - */ - m18x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL, - cpu, INST_CMMU, 0, (unsigned)physaddr); - m18x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_CB_SEGMENT, MODE_VAL, - cpu, INST_CMMU, 0, 0); - /* - REGS(cpu, DATA_CMMU).sar = (unsigned)physaddr; - REGS(cpu, DATA_CMMU).scr = CMMU_FLUSH_CACHE_CB_SEGMENT; - */ - m18x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL, - cpu, DATA_CMMU, 0, (unsigned)physaddr); - m18x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_CB_SEGMENT, MODE_VAL, - cpu, DATA_CMMU, 0, 0); - } + if (size < 0 || size > NBSG ) { + /* + REGS(cpu, INST_CMMU).scr = CMMU_FLUSH_CACHE_CB_ALL; + REGS(cpu, DATA_CMMU).scr = CMMU_FLUSH_CACHE_CB_ALL; + */ + m18x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CB_ALL, MODE_VAL, + cpu, DATA_CMMU, 0, 0); + m18x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CB_ALL, MODE_VAL, + cpu, INST_CMMU, 0, 0); + } else if (size <= 16) { + /* + REGS(cpu, INST_CMMU).sar = (unsigned)physaddr; + REGS(cpu, INST_CMMU).scr = CMMU_FLUSH_CACHE_CB_LINE; + */ + m18x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL, + cpu, INST_CMMU, 0, (unsigned)physaddr); + m18x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_CB_LINE, MODE_VAL, + cpu, INST_CMMU, 0, 0); + /* + REGS(cpu, DATA_CMMU).sar = (unsigned)physaddr; + REGS(cpu, DATA_CMMU).scr = CMMU_FLUSH_CACHE_CB_LINE; + */ + m18x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL, + cpu, DATA_CMMU, 0, (unsigned)physaddr); + m18x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_CB_LINE, MODE_VAL, + cpu, DATA_CMMU, 0, 0); + } else if (size <= NBPG) { + /* + REGS(cpu, INST_CMMU).sar = (unsigned)physaddr; + REGS(cpu, INST_CMMU).scr = CMMU_FLUSH_CACHE_CB_PAGE; + */ + m18x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL, + cpu, INST_CMMU, 0, (unsigned)physaddr); + m18x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_CB_PAGE, MODE_VAL, + cpu, INST_CMMU, 0, 0); + /* + REGS(cpu, DATA_CMMU).sar = (unsigned)physaddr; + REGS(cpu, DATA_CMMU).scr = CMMU_FLUSH_CACHE_CB_PAGE; + */ + m18x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL, + cpu, DATA_CMMU, 0, (unsigned)physaddr); + m18x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_CB_PAGE, MODE_VAL, + cpu, DATA_CMMU, 0, 0); + } else { + /* + REGS(cpu, INST_CMMU).sar = (unsigned)physaddr; + REGS(cpu, INST_CMMU).scr = CMMU_FLUSH_CACHE_CB_SEGMENT; + */ + m18x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL, + cpu, INST_CMMU, 0, (unsigned)physaddr); + m18x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_CB_SEGMENT, MODE_VAL, + cpu, INST_CMMU, 0, 0); + /* + REGS(cpu, DATA_CMMU).sar = (unsigned)physaddr; + REGS(cpu, DATA_CMMU).scr = CMMU_FLUSH_CACHE_CB_SEGMENT; + */ + m18x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL, + cpu, DATA_CMMU, 0, (unsigned)physaddr); + m18x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_CB_SEGMENT, MODE_VAL, + cpu, DATA_CMMU, 0, 0); + } #else - /* - REGS(cpu, DATA_CMMU).scr = CMMU_FLUSH_CACHE_CB_ALL; - REGS(cpu, DATA_CMMU).scr = CMMU_FLUSH_CACHE_CB_ALL; - */ - m18x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CB_ALL, MODE_VAL, - cpu, DATA_CMMU, 0, 0); - m18x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CB_ALL, MODE_VAL, - cpu, INST_CMMU, 0, 0); + /* + REGS(cpu, DATA_CMMU).scr = CMMU_FLUSH_CACHE_CB_ALL; + REGS(cpu, DATA_CMMU).scr = CMMU_FLUSH_CACHE_CB_ALL; + */ + m18x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CB_ALL, MODE_VAL, + cpu, DATA_CMMU, 0, 0); + m18x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CB_ALL, MODE_VAL, + cpu, INST_CMMU, 0, 0); #endif /* !BROKEN_MMU_MASK */ - - - - splx(s); + splx(s); } void m18x_cmmu_sync_inval_cache(vm_offset_t physaddr, int size) { - register s = splhigh(); - int cpu; - cpu = cpu_number(); - - + register s = splhigh(); + int cpu; + cpu = cpu_number(); #if !defined(BROKEN_MMU_MASK) - if (size < 0 || size > NBSG ) { - /* - REGS(cpu, DATA_CMMU).scr = CMMU_FLUSH_CACHE_CBI_ALL; - REGS(cpu, INST_CMMU).scr = CMMU_FLUSH_CACHE_CBI_ALL; - */ - m18x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_ALL, MODE_VAL, - cpu, DATA_CMMU, 0, 0); - m18x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_ALL, MODE_VAL, - cpu, INST_CMMU, 0, 0); - } else if (size <= 16) { - /* - REGS(cpu, DATA_CMMU).sar = (unsigned)physaddr; - REGS(cpu, DATA_CMMU).scr = CMMU_FLUSH_CACHE_CBI_LINE; - */ - m18x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL, - cpu, INST_CMMU, 0, (unsigned)physaddr); - m18x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_CBI_LINE, MODE_VAL, - cpu, INST_CMMU, 0, 0); - /* - REGS(cpu, INST_CMMU).sar = (unsigned)physaddr; - REGS(cpu, INST_CMMU).scr = CMMU_FLUSH_CACHE_CBI_LINE; - */ - m18x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL, - cpu, DATA_CMMU, 0, (unsigned)physaddr); - m18x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_CBI_LINE, MODE_VAL, - cpu, DATA_CMMU, 0, 0); - } else if (size <= NBPG) { - /* - REGS(cpu, DATA_CMMU).sar = (unsigned)physaddr; - REGS(cpu, DATA_CMMU).scr = CMMU_FLUSH_CACHE_CBI_PAGE; - */ - m18x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL, - cpu, INST_CMMU, 0, (unsigned)physaddr); - m18x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_CBI_PAGE, MODE_VAL, - cpu, INST_CMMU, 0, 0); - /* - REGS(cpu, INST_CMMU).sar = (unsigned)physaddr; - REGS(cpu, INST_CMMU).scr = CMMU_FLUSH_CACHE_CBI_PAGE; - */ - m18x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL, - cpu, DATA_CMMU, 0, (unsigned)physaddr); - m18x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_CBI_PAGE, MODE_VAL, - cpu, DATA_CMMU, 0, 0); - } else { - /* - REGS(cpu, DATA_CMMU).sar = (unsigned)physaddr; - REGS(cpu, DATA_CMMU).scr = CMMU_FLUSH_CACHE_CBI_SEGMENT; - */ - m18x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL, - cpu, INST_CMMU, 0, (unsigned)physaddr); - m18x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_CBI_SEGMENT, MODE_VAL, - cpu, INST_CMMU, 0, 0); - /* - REGS(cpu, INST_CMMU).sar = (unsigned)physaddr; - REGS(cpu, INST_CMMU).scr = CMMU_FLUSH_CACHE_CBI_SEGMENT; - */ - m18x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL, - cpu, DATA_CMMU, 0, (unsigned)physaddr); - m18x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_CBI_SEGMENT, MODE_VAL, - cpu, DATA_CMMU, 0, 0); - } + if (size < 0 || size > NBSG ) { + /* + REGS(cpu, DATA_CMMU).scr = CMMU_FLUSH_CACHE_CBI_ALL; + REGS(cpu, INST_CMMU).scr = CMMU_FLUSH_CACHE_CBI_ALL; + */ + m18x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_ALL, MODE_VAL, + cpu, DATA_CMMU, 0, 0); + m18x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_ALL, MODE_VAL, + cpu, INST_CMMU, 0, 0); + } else if (size <= 16) { + /* + REGS(cpu, DATA_CMMU).sar = (unsigned)physaddr; + REGS(cpu, DATA_CMMU).scr = CMMU_FLUSH_CACHE_CBI_LINE; + */ + m18x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL, + cpu, INST_CMMU, 0, (unsigned)physaddr); + m18x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_CBI_LINE, MODE_VAL, + cpu, INST_CMMU, 0, 0); + /* + REGS(cpu, INST_CMMU).sar = (unsigned)physaddr; + REGS(cpu, INST_CMMU).scr = CMMU_FLUSH_CACHE_CBI_LINE; + */ + m18x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL, + cpu, DATA_CMMU, 0, (unsigned)physaddr); + m18x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_CBI_LINE, MODE_VAL, + cpu, DATA_CMMU, 0, 0); + } else if (size <= NBPG) { + /* + REGS(cpu, DATA_CMMU).sar = (unsigned)physaddr; + REGS(cpu, DATA_CMMU).scr = CMMU_FLUSH_CACHE_CBI_PAGE; + */ + m18x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL, + cpu, INST_CMMU, 0, (unsigned)physaddr); + m18x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_CBI_PAGE, MODE_VAL, + cpu, INST_CMMU, 0, 0); + /* + REGS(cpu, INST_CMMU).sar = (unsigned)physaddr; + REGS(cpu, INST_CMMU).scr = CMMU_FLUSH_CACHE_CBI_PAGE; + */ + m18x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL, + cpu, DATA_CMMU, 0, (unsigned)physaddr); + m18x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_CBI_PAGE, MODE_VAL, + cpu, DATA_CMMU, 0, 0); + } else { + /* + REGS(cpu, DATA_CMMU).sar = (unsigned)physaddr; + REGS(cpu, DATA_CMMU).scr = CMMU_FLUSH_CACHE_CBI_SEGMENT; + */ + m18x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL, + cpu, INST_CMMU, 0, (unsigned)physaddr); + m18x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_CBI_SEGMENT, MODE_VAL, + cpu, INST_CMMU, 0, 0); + /* + REGS(cpu, INST_CMMU).sar = (unsigned)physaddr; + REGS(cpu, INST_CMMU).scr = CMMU_FLUSH_CACHE_CBI_SEGMENT; + */ + m18x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL, + cpu, DATA_CMMU, 0, (unsigned)physaddr); + m18x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_CBI_SEGMENT, MODE_VAL, + cpu, DATA_CMMU, 0, 0); + } #else - /* - REGS(cpu, DATA_CMMU).scr = CMMU_FLUSH_CACHE_CBI_ALL; - REGS(cpu, INST_CMMU).scr = CMMU_FLUSH_CACHE_CBI_ALL; - */ - m18x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_ALL, MODE_VAL, - cpu, DATA_CMMU, 0, 0); - m18x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_ALL, MODE_VAL, - cpu, INST_CMMU, 0, 0); + /* + REGS(cpu, DATA_CMMU).scr = CMMU_FLUSH_CACHE_CBI_ALL; + REGS(cpu, INST_CMMU).scr = CMMU_FLUSH_CACHE_CBI_ALL; + */ + m18x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_ALL, MODE_VAL, + cpu, DATA_CMMU, 0, 0); + m18x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_ALL, MODE_VAL, + cpu, INST_CMMU, 0, 0); #endif /* !BROKEN_MMU_MASK */ - - - - splx(s); + splx(s); } void m18x_cmmu_inval_cache(vm_offset_t physaddr, int size) { - register s = splhigh(); - int cpu; - cpu = cpu_number(); - - + register s = splhigh(); + int cpu; + cpu = cpu_number(); #if !defined(BROKEN_MMU_MASK) - if (size < 0 || size > NBSG ) { - /* - REGS(cpu, DATA_CMMU).scr = CMMU_FLUSH_CACHE_INV_ALL; - REGS(cpu, INST_CMMU).scr = CMMU_FLUSH_CACHE_INV_ALL; - */ - m18x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_INV_ALL, MODE_VAL, - cpu, DATA_CMMU, 0, 0); - m18x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_INV_ALL, MODE_VAL, - cpu, INST_CMMU, 0, 0); - } else if (size <= 16) { - /* - REGS(cpu, DATA_CMMU).sar = (unsigned)physaddr; - REGS(cpu, DATA_CMMU).scr = CMMU_FLUSH_CACHE_INV_LINE; - */ - m18x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL, - cpu, INST_CMMU, 0, (unsigned)physaddr); - m18x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_INV_LINE, MODE_VAL, - cpu, INST_CMMU, 0, 0); - /* - REGS(cpu, INST_CMMU).sar = (unsigned)physaddr; - REGS(cpu, INST_CMMU).scr = CMMU_FLUSH_CACHE_INV_LINE; - */ - m18x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL, - cpu, DATA_CMMU, 0, (unsigned)physaddr); - m18x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_INV_LINE, MODE_VAL, - cpu, DATA_CMMU, 0, 0); - } else if (size <= NBPG) { - /* - REGS(cpu, DATA_CMMU).sar = (unsigned)physaddr; - REGS(cpu, DATA_CMMU).scr = CMMU_FLUSH_CACHE_INV_PAGE; - */ - m18x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL, - cpu, INST_CMMU, 0, (unsigned)physaddr); - m18x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_INV_PAGE, MODE_VAL, - cpu, INST_CMMU, 0, 0); - /* - REGS(cpu, INST_CMMU).sar = (unsigned)physaddr; - REGS(cpu, INST_CMMU).scr = CMMU_FLUSH_CACHE_INV_PAGE; - */ - m18x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL, - cpu, DATA_CMMU, 0, (unsigned)physaddr); - m18x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_INV_PAGE, MODE_VAL, - cpu, DATA_CMMU, 0, 0); - } else { - /* - REGS(cpu, DATA_CMMU).sar = (unsigned)physaddr; - REGS(cpu, DATA_CMMU).scr = CMMU_FLUSH_CACHE_INV_SEGMENT; - */ - m18x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL, - cpu, INST_CMMU, 0, (unsigned)physaddr); - m18x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_INV_SEGMENT, MODE_VAL, - cpu, INST_CMMU, 0, 0); - /* - REGS(cpu, INST_CMMU).sar = (unsigned)physaddr; - REGS(cpu, INST_CMMU).scr = CMMU_FLUSH_CACHE_INV_SEGMENT; - */ - m18x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL, - cpu, DATA_CMMU, 0, (unsigned)physaddr); - m18x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_INV_SEGMENT, MODE_VAL, - cpu, DATA_CMMU, 0, 0); - } + if (size < 0 || size > NBSG ) { + /* + REGS(cpu, DATA_CMMU).scr = CMMU_FLUSH_CACHE_INV_ALL; + REGS(cpu, INST_CMMU).scr = CMMU_FLUSH_CACHE_INV_ALL; + */ + m18x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_INV_ALL, MODE_VAL, + cpu, DATA_CMMU, 0, 0); + m18x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_INV_ALL, MODE_VAL, + cpu, INST_CMMU, 0, 0); + } else if (size <= 16) { + /* + REGS(cpu, DATA_CMMU).sar = (unsigned)physaddr; + REGS(cpu, DATA_CMMU).scr = CMMU_FLUSH_CACHE_INV_LINE; + */ + m18x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL, + cpu, INST_CMMU, 0, (unsigned)physaddr); + m18x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_INV_LINE, MODE_VAL, + cpu, INST_CMMU, 0, 0); + /* + REGS(cpu, INST_CMMU).sar = (unsigned)physaddr; + REGS(cpu, INST_CMMU).scr = CMMU_FLUSH_CACHE_INV_LINE; + */ + m18x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL, + cpu, DATA_CMMU, 0, (unsigned)physaddr); + m18x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_INV_LINE, MODE_VAL, + cpu, DATA_CMMU, 0, 0); + } else if (size <= NBPG) { + /* + REGS(cpu, DATA_CMMU).sar = (unsigned)physaddr; + REGS(cpu, DATA_CMMU).scr = CMMU_FLUSH_CACHE_INV_PAGE; + */ + m18x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL, + cpu, INST_CMMU, 0, (unsigned)physaddr); + m18x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_INV_PAGE, MODE_VAL, + cpu, INST_CMMU, 0, 0); + /* + REGS(cpu, INST_CMMU).sar = (unsigned)physaddr; + REGS(cpu, INST_CMMU).scr = CMMU_FLUSH_CACHE_INV_PAGE; + */ + m18x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL, + cpu, DATA_CMMU, 0, (unsigned)physaddr); + m18x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_INV_PAGE, MODE_VAL, + cpu, DATA_CMMU, 0, 0); + } else { + /* + REGS(cpu, DATA_CMMU).sar = (unsigned)physaddr; + REGS(cpu, DATA_CMMU).scr = CMMU_FLUSH_CACHE_INV_SEGMENT; + */ + m18x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL, + cpu, INST_CMMU, 0, (unsigned)physaddr); + m18x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_INV_SEGMENT, MODE_VAL, + cpu, INST_CMMU, 0, 0); + /* + REGS(cpu, INST_CMMU).sar = (unsigned)physaddr; + REGS(cpu, INST_CMMU).scr = CMMU_FLUSH_CACHE_INV_SEGMENT; + */ + m18x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL, + cpu, DATA_CMMU, 0, (unsigned)physaddr); + m18x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_INV_SEGMENT, MODE_VAL, + cpu, DATA_CMMU, 0, 0); + } #else - /* - REGS(cpu, DATA_CMMU).scr = CMMU_FLUSH_CACHE_INV_ALL; - REGS(cpu, INST_CMMU).scr = CMMU_FLUSH_CACHE_INV_ALL; - */ - m18x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_INV_ALL, MODE_VAL, - cpu, DATA_CMMU, 0, 0); - m18x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_INV_ALL, MODE_VAL, - cpu, INST_CMMU, 0, 0); + /* + REGS(cpu, DATA_CMMU).scr = CMMU_FLUSH_CACHE_INV_ALL; + REGS(cpu, INST_CMMU).scr = CMMU_FLUSH_CACHE_INV_ALL; + */ + m18x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_INV_ALL, MODE_VAL, + cpu, DATA_CMMU, 0, 0); + m18x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_INV_ALL, MODE_VAL, + cpu, INST_CMMU, 0, 0); #endif /* !BROKEN_MMU_MASK */ - - - splx(s); + splx(s); } void m18x_dma_cachectl(vm_offset_t va, int size, int op) { - int count; + int count; #if !defined(BROKEN_MMU_MASK) - while (size) { - - count = NBPG - ((int)va & PGOFSET); - - if (size < count) - count = size; - - if (op == DMA_CACHE_SYNC) - m18x_cmmu_sync_cache(kvtop(va), count); - else if (op == DMA_CACHE_SYNC_INVAL) - m18x_cmmu_sync_inval_cache(kvtop(va), count); - else - m18x_cmmu_inval_cache(kvtop(va), count); - - va = (vm_offset_t)((int)va + count); - size -= count; - } + while (size) { + count = NBPG - ((int)va & PGOFSET); + + if (size < count) + count = size; + + if (op == DMA_CACHE_SYNC) + m18x_cmmu_sync_cache(kvtop(va), count); + else if (op == DMA_CACHE_SYNC_INVAL) + m18x_cmmu_sync_inval_cache(kvtop(va), count); + else + m18x_cmmu_inval_cache(kvtop(va), count); + + va = (vm_offset_t)((int)va + count); + size -= count; + } #else - if (op == DMA_CACHE_SYNC) - m18x_cmmu_sync_cache(kvtop(va), size); - else if (op == DMA_CACHE_SYNC_INVAL) - m18x_cmmu_sync_inval_cache(kvtop(va), size); - else - m18x_cmmu_inval_cache(kvtop(va), size); + if (op == DMA_CACHE_SYNC) + m18x_cmmu_sync_cache(kvtop(va), size); + else if (op == DMA_CACHE_SYNC_INVAL) + m18x_cmmu_sync_inval_cache(kvtop(va), size); + else + m18x_cmmu_inval_cache(kvtop(va), size); #endif /* !BROKEN_MMU_MASK */ } @@ -1881,403 +1881,401 @@ m18x_cmmu_show_translation( unsigned verbose_flag, int cmmu_num) { - /* - * A virtual address is split into three fields. Two are used as - * indicies into tables (segment and page), and one is an offset into - * a page of memory. - */ - union { - unsigned bits; - struct { - unsigned segment_table_index:10, - page_table_index:10, - page_offset:12; - } field; - } virtual_address; - unsigned value; - - if (verbose_flag) - db_printf("-------------------------------------------\n"); - - - - /****** ACCESS PROPER CMMU or THREAD ***********/ - #if 0 /* no thread */ - if (thread != 0) { - /* the following tidbit from _pmap_activate in m88k/pmap.c */ - register apr_template_t apr_data; - supervisor_flag = 0; /* thread implies user */ - - if (thread->task == 0) { - db_printf("[thread %x has empty task pointer]\n", thread); - return; - } else if (thread->task->map == 0) { - db_printf("[thread/task %x/%x has empty map pointer]\n", - thread, thread->task); - return; - } else if (thread->task->map->pmap == 0) { - db_printf("[thread/task/map %x/%x/%x has empty pmap pointer]\n", - thread, thread->task, thread->task->map); - return; - } - if (thread->task->map->pmap->lock.lock_data) { - db_printf("[Warning: thread %x's task %x's map %x's " - "pmap %x is locked]\n", thread, thread->task, - thread->task->map, thread->task->map->pmap); - } - apr_data.bits = 0; - apr_data.field.st_base = M88K_BTOP(thread->task->map->pmap->sdt_paddr); - apr_data.field.wt = 0; - apr_data.field.g = 1; - apr_data.field.ci = 0; - apr_data.field.te = 1; - value = apr_data.bits; - if (verbose_flag) { - db_printf("[thread %x task %x map %x pmap %x UAPR is %x]\n", - thread, thread->task, thread->task->map, - thread->task->map->pmap, value); - } - } else - #endif /* 0 */ - { - if (cmmu_num == -1) { - if (cpu_cmmu[0].pair[DATA_CMMU] == 0) { - db_printf("ack! can't figure my own data cmmu number.\n"); - return; - } - cmmu_num = cpu_cmmu[0].pair[DATA_CMMU] - cmmu; - if (verbose_flag) - db_printf("The data cmmu for cpu#%d is cmmu#%d.\n", - 0, cmmu_num); - } else if (cmmu_num < 0 || cmmu_num >= MAX_CMMUS) { - db_printf("invalid cpu number [%d]... must be in range [0..%d]\n", - cmmu_num, MAX_CMMUS - 1); - - return; - } - - if (cmmu[cmmu_num].cmmu_alive == 0) { - db_printf("warning: cmmu %d is not alive.\n", cmmu_num); - #if 0 - - return; - #endif - } - - if (!verbose_flag) { - if (!(cmmu[cmmu_num].cmmu_regs->sctr & CMMU_SCTR_SE)) - db_printf("WARNING: snooping not enabled for CMMU#%d.\n", - cmmu_num); - } else { - int i; - for (i=0; i<MAX_CMMUS; i++) - if ((i == cmmu_num || cmmu[i].cmmu_alive) && - (verbose_flag>1 || !(cmmu[i].cmmu_regs->sctr&CMMU_SCTR_SE))) { - db_printf("CMMU#%d (cpu %d %s) snooping %s\n", i, - cmmu[i].cmmu_cpu, cmmu[i].which ? "data" : "inst", - (cmmu[i].cmmu_regs->sctr & CMMU_SCTR_SE) ? "on":"OFF"); - } - } - - if (supervisor_flag) - value = cmmu[cmmu_num].cmmu_regs->sapr; - else - value = cmmu[cmmu_num].cmmu_regs->uapr; - - } - - /******* LOOK AT THE BATC ** (if not a thread) **************/ - #if 0 - #if SHADOW_BATC - if (thread == 0) { - int i; - union batcu batc; - for (i = 0; i < 8; i++) { - batc.bits = cmmu[cmmu_num].batc[i]; - if (batc.field.v == 0) { - if (verbose_flag>1) - db_printf("cmmu #%d batc[%d] invalid.\n", cmmu_num, i); - } else { - db_printf("cmmu#%d batc[%d] v%08x p%08x", cmmu_num, i, - batc.field.lba << 18, batc.field.pba); - if (batc.field.s) db_printf(", supervisor"); - if (batc.field.wt) db_printf(", wt.th"); - if (batc.field.g) db_printf(", global"); - if (batc.field.ci) db_printf(", cache inhibit"); - if (batc.field.wp) db_printf(", write protect"); - } - } - } - #endif - #endif /* 0 */ - - /******* SEE WHAT A PROBE SAYS (if not a thread) ***********/ - #if 0 - if (thread == 0) - #endif /* 0 */ - { - union ssr ssr; - struct cmmu_regs *cmmu_regs = cmmu[cmmu_num].cmmu_regs; - cmmu_regs->sar = address; - cmmu_regs->scr = supervisor_flag ? CMMU_PROBE_SUPER : CMMU_PROBE_USER; - ssr.bits = cmmu_regs->ssr; - if (verbose_flag > 1) - db_printf("probe of 0x%08x returns ssr=0x%08x\n", - address, ssr.bits); - if (ssr.field.v) - db_printf("PROBE of 0x%08x returns phys=0x%x", - address, cmmu_regs->sar); - else - db_printf("PROBE fault at 0x%x", cmmu_regs->pfADDRr); - if (ssr.field.ce) db_printf(", copyback err"); - if (ssr.field.be) db_printf(", bus err"); - if (ssr.field.wt) db_printf(", writethrough"); - if (ssr.field.sp) db_printf(", sup prot"); - if (ssr.field.g) db_printf(", global"); - if (ssr.field.ci) db_printf(", cache inhibit"); - if (ssr.field.m) db_printf(", modified"); - if (ssr.field.u) db_printf(", used"); - if (ssr.field.wp) db_printf(", write prot"); - if (ssr.field.bh) db_printf(", BATC"); - db_printf(".\n"); - } - - /******* INTERPRET AREA DESCRIPTOR *********/ - { - union apr_template apr_template; - apr_template.bits = value; - if (verbose_flag > 1) { - db_printf("CMMU#%d", cmmu_num); - #if 0 - if (thread == 0) - db_printf("CMMU#%d", cmmu_num); - else - db_printf("THREAD %x", thread); - #endif /* 0 */ - db_printf(" %cAPR is 0x%08x\n", - supervisor_flag ? 'S' : 'U', apr_template.bits); - } - db_printf("CMMU#%d", cmmu_num); - #if 0 - if (thread == 0) - db_printf("CMMU#%d", cmmu_num); - else - db_printf("THREAD %x", thread); - #endif /* 0 */ - db_printf(" %cAPR: SegTbl: 0x%x000p", - supervisor_flag ? 'S' : 'U', apr_template.field.st_base); - if (apr_template.field.wt) db_printf(", WTHRU"); - else db_printf(", !wthru"); - if (apr_template.field.g) db_printf(", GLOBAL"); - else db_printf(", !global"); - if (apr_template.field.ci) db_printf(", $INHIBIT"); - else db_printf(", $ok"); - if (apr_template.field.te) db_printf(", VALID"); - else db_printf(", !valid"); - db_printf(".\n"); - - /* if not valid, done now */ - if (apr_template.field.te == 0) { - db_printf("<would report an error, valid bit not set>\n"); - - return; - } - - value = apr_template.field.st_base << 12; /* now point to seg page */ - } - - /* translate value from physical to virtual */ - if (verbose_flag) - db_printf("[%x physical is %x virtual]\n", value, value + VEQR_ADDR); - value += VEQR_ADDR; - - virtual_address.bits = address; - - /****** ACCESS SEGMENT TABLE AND INTERPRET SEGMENT DESCRIPTOR *******/ - { - union sdt_entry_template std_template; - if (verbose_flag) - db_printf("will follow to entry %d of page at 0x%x...\n", - virtual_address.field.segment_table_index, value); - value |= virtual_address.field.segment_table_index * - sizeof(struct sdt_entry); - - if (badwordaddr(value)) { - db_printf("ERROR: unable to access page at 0x%08x.\n", value); - - return; - } - - std_template.bits = *(unsigned *)value; - if (verbose_flag > 1) - db_printf("SEG DESC @0x%x is 0x%08x\n", value, std_template.bits); - db_printf("SEG DESC @0x%x: PgTbl: 0x%x000", - value, std_template.sdt_desc.table_addr); - if (std_template.sdt_desc.wt) db_printf(", WTHRU"); - else db_printf(", !wthru"); - if (std_template.sdt_desc.sup) db_printf(", S-PROT"); - else db_printf(", UserOk"); - if (std_template.sdt_desc.g) db_printf(", GLOBAL"); - else db_printf(", !global"); - if (std_template.sdt_desc.no_cache) db_printf(", $INHIBIT"); - else db_printf(", $ok"); - if (std_template.sdt_desc.prot) db_printf(", W-PROT"); - else db_printf(", WriteOk"); - if (std_template.sdt_desc.dtype) db_printf(", VALID"); - else db_printf(", !valid"); - db_printf(".\n"); - - /* if not valid, done now */ - if (std_template.sdt_desc.dtype == 0) { - db_printf("<would report an error, STD entry not valid>\n"); - - return; - } - - value = std_template.sdt_desc.table_addr << 12; - } - - /* translate value from physical to virtual */ - if (verbose_flag) - db_printf("[%x physical is %x virtual]\n", value, value + VEQR_ADDR); - value += VEQR_ADDR; - - /******* PAGE TABLE *********/ - { - union pte_template pte_template; - if (verbose_flag) - db_printf("will follow to entry %d of page at 0x%x...\n", - virtual_address.field.page_table_index, value); - value |= virtual_address.field.page_table_index * - sizeof(struct pt_entry); - - if (badwordaddr(value)) { - db_printf("error: unable to access page at 0x%08x.\n", value); - - return; - } - - pte_template.bits = *(unsigned *)value; - if (verbose_flag > 1) - db_printf("PAGE DESC @0x%x is 0x%08x.\n", value, pte_template.bits); - db_printf("PAGE DESC @0x%x: page @%x000", - value, pte_template.pte.pfn); - if (pte_template.pte.wired) db_printf(", WIRE"); - else db_printf(", !wire"); - if (pte_template.pte.wt) db_printf(", WTHRU"); - else db_printf(", !wthru"); - if (pte_template.pte.sup) db_printf(", S-PROT"); - else db_printf(", UserOk"); - if (pte_template.pte.g) db_printf(", GLOBAL"); - else db_printf(", !global"); - if (pte_template.pte.ci) db_printf(", $INHIBIT"); - else db_printf(", $ok"); - if (pte_template.pte.modified) db_printf(", MOD"); - else db_printf(", !mod"); - if (pte_template.pte.pg_used) db_printf(", USED"); - else db_printf(", !used"); - if (pte_template.pte.prot) db_printf(", W-PROT"); - else db_printf(", WriteOk"); - if (pte_template.pte.dtype) db_printf(", VALID"); - else db_printf(", !valid"); - db_printf(".\n"); - - /* if not valid, done now */ - if (pte_template.pte.dtype == 0) { - db_printf("<would report an error, PTE entry not valid>\n"); - - return; - } - - value = pte_template.pte.pfn << 12; - if (verbose_flag) - db_printf("will follow to byte %d of page at 0x%x...\n", - virtual_address.field.page_offset, value); - value |= virtual_address.field.page_offset; - - if (badwordaddr(value)) { - db_printf("error: unable to access page at 0x%08x.\n", value); - - return; - } - } - - /* translate value from physical to virtual */ - if (verbose_flag) - db_printf("[%x physical is %x virtual]\n", value, value + VEQR_ADDR); - value += VEQR_ADDR; - - db_printf("WORD at 0x%x is 0x%08x.\n", value, *(unsigned *)value); - -} + /* + * A virtual address is split into three fields. Two are used as + * indicies into tables (segment and page), and one is an offset into + * a page of memory. + */ + union { + unsigned bits; + struct { + unsigned segment_table_index:10, + page_table_index:10, + page_offset:12; + } field; + } virtual_address; + unsigned value; + + if (verbose_flag) + db_printf("-------------------------------------------\n"); + + + + /****** ACCESS PROPER CMMU or THREAD ***********/ +#if 0 /* no thread */ + if (thread != 0) { + /* the following tidbit from _pmap_activate in m88k/pmap.c */ + register apr_template_t apr_data; + supervisor_flag = 0; /* thread implies user */ + + if (thread->task == 0) { + db_printf("[thread %x has empty task pointer]\n", thread); + return; + } else if (thread->task->map == 0) { + db_printf("[thread/task %x/%x has empty map pointer]\n", + thread, thread->task); + return; + } else if (thread->task->map->pmap == 0) { + db_printf("[thread/task/map %x/%x/%x has empty pmap pointer]\n", + thread, thread->task, thread->task->map); + return; + } + if (thread->task->map->pmap->lock.lock_data) { + db_printf("[Warning: thread %x's task %x's map %x's " + "pmap %x is locked]\n", thread, thread->task, + thread->task->map, thread->task->map->pmap); + } + apr_data.bits = 0; + apr_data.field.st_base = M88K_BTOP(thread->task->map->pmap->sdt_paddr); + apr_data.field.wt = 0; + apr_data.field.g = 1; + apr_data.field.ci = 0; + apr_data.field.te = 1; + value = apr_data.bits; + if (verbose_flag) { + db_printf("[thread %x task %x map %x pmap %x UAPR is %x]\n", + thread, thread->task, thread->task->map, + thread->task->map->pmap, value); + } + } else +#endif /* 0 */ + { + if (cmmu_num == -1) { + if (cpu_cmmu[0].pair[DATA_CMMU] == 0) { + db_printf("ack! can't figure my own data cmmu number.\n"); + return; + } + cmmu_num = cpu_cmmu[0].pair[DATA_CMMU] - cmmu; + if (verbose_flag) + db_printf("The data cmmu for cpu#%d is cmmu#%d.\n", + 0, cmmu_num); + } else if (cmmu_num < 0 || cmmu_num >= MAX_CMMUS) { + db_printf("invalid cpu number [%d]... must be in range [0..%d]\n", + cmmu_num, MAX_CMMUS - 1); + + return; + } + + if (cmmu[cmmu_num].cmmu_alive == 0) { + db_printf("warning: cmmu %d is not alive.\n", cmmu_num); +#if 0 + return; +#endif + } + + if (!verbose_flag) { + if (!(cmmu[cmmu_num].cmmu_regs->sctr & CMMU_SCTR_SE)) + db_printf("WARNING: snooping not enabled for CMMU#%d.\n", + cmmu_num); + } else { + int i; + for (i=0; i<MAX_CMMUS; i++) + if ((i == cmmu_num || cmmu[i].cmmu_alive) && + (verbose_flag>1 || !(cmmu[i].cmmu_regs->sctr&CMMU_SCTR_SE))) { + db_printf("CMMU#%d (cpu %d %s) snooping %s\n", i, + cmmu[i].cmmu_cpu, cmmu[i].which ? "data" : "inst", + (cmmu[i].cmmu_regs->sctr & CMMU_SCTR_SE) ? "on":"OFF"); + } + } + + if (supervisor_flag) + value = cmmu[cmmu_num].cmmu_regs->sapr; + else + value = cmmu[cmmu_num].cmmu_regs->uapr; + + } + + /******* LOOK AT THE BATC ** (if not a thread) **************/ +#if 0 +#if SHADOW_BATC + if (thread == 0) { + int i; + union batcu batc; + for (i = 0; i < 8; i++) { + batc.bits = cmmu[cmmu_num].batc[i]; + if (batc.field.v == 0) { + if (verbose_flag>1) + db_printf("cmmu #%d batc[%d] invalid.\n", cmmu_num, i); + } else { + db_printf("cmmu#%d batc[%d] v%08x p%08x", cmmu_num, i, + batc.field.lba << 18, batc.field.pba); + if (batc.field.s) db_printf(", supervisor"); + if (batc.field.wt) db_printf(", wt.th"); + if (batc.field.g) db_printf(", global"); + if (batc.field.ci) db_printf(", cache inhibit"); + if (batc.field.wp) db_printf(", write protect"); + } + } + } +#endif /* SHADOW_BATC */ +#endif /* 0 */ + + /******* SEE WHAT A PROBE SAYS (if not a thread) ***********/ +#if 0 + if (thread == 0) +#endif /* 0 */ + { + union ssr ssr; + struct cmmu_regs *cmmu_regs = cmmu[cmmu_num].cmmu_regs; + cmmu_regs->sar = address; + cmmu_regs->scr = supervisor_flag ? CMMU_PROBE_SUPER : CMMU_PROBE_USER; + ssr.bits = cmmu_regs->ssr; + if (verbose_flag > 1) + db_printf("probe of 0x%08x returns ssr=0x%08x\n", + address, ssr.bits); + if (ssr.field.v) + db_printf("PROBE of 0x%08x returns phys=0x%x", + address, cmmu_regs->sar); + else + db_printf("PROBE fault at 0x%x", cmmu_regs->pfADDRr); + if (ssr.field.ce) db_printf(", copyback err"); + if (ssr.field.be) db_printf(", bus err"); + if (ssr.field.wt) db_printf(", writethrough"); + if (ssr.field.sp) db_printf(", sup prot"); + if (ssr.field.g) db_printf(", global"); + if (ssr.field.ci) db_printf(", cache inhibit"); + if (ssr.field.m) db_printf(", modified"); + if (ssr.field.u) db_printf(", used"); + if (ssr.field.wp) db_printf(", write prot"); + if (ssr.field.bh) db_printf(", BATC"); + db_printf(".\n"); + } + + /******* INTERPRET AREA DESCRIPTOR *********/ + { + union apr_template apr_template; + apr_template.bits = value; + if (verbose_flag > 1) { + db_printf("CMMU#%d", cmmu_num); +#if 0 + if (thread == 0) + db_printf("CMMU#%d", cmmu_num); + else + db_printf("THREAD %x", thread); +#endif /* 0 */ + db_printf(" %cAPR is 0x%08x\n", + supervisor_flag ? 'S' : 'U', apr_template.bits); + } + db_printf("CMMU#%d", cmmu_num); +#if 0 + if (thread == 0) + db_printf("CMMU#%d", cmmu_num); + else + db_printf("THREAD %x", thread); +#endif /* 0 */ + db_printf(" %cAPR: SegTbl: 0x%x000p", + supervisor_flag ? 'S' : 'U', apr_template.field.st_base); + if (apr_template.field.wt) db_printf(", WTHRU"); + else db_printf(", !wthru"); + if (apr_template.field.g) db_printf(", GLOBAL"); + else db_printf(", !global"); + if (apr_template.field.ci) db_printf(", $INHIBIT"); + else db_printf(", $ok"); + if (apr_template.field.te) db_printf(", VALID"); + else db_printf(", !valid"); + db_printf(".\n"); + + /* if not valid, done now */ + if (apr_template.field.te == 0) { + db_printf("<would report an error, valid bit not set>\n"); + + return; + } + + value = apr_template.field.st_base << 12; /* now point to seg page */ + } + + /* translate value from physical to virtual */ + if (verbose_flag) + db_printf("[%x physical is %x virtual]\n", value, value + VEQR_ADDR); + value += VEQR_ADDR; + + virtual_address.bits = address; + + /****** ACCESS SEGMENT TABLE AND INTERPRET SEGMENT DESCRIPTOR *******/ + { + union sdt_entry_template std_template; + if (verbose_flag) + db_printf("will follow to entry %d of page at 0x%x...\n", + virtual_address.field.segment_table_index, value); + value |= virtual_address.field.segment_table_index * + sizeof(struct sdt_entry); + + if (badwordaddr(value)) { + db_printf("ERROR: unable to access page at 0x%08x.\n", value); + + return; + } + + std_template.bits = *(unsigned *)value; + if (verbose_flag > 1) + db_printf("SEG DESC @0x%x is 0x%08x\n", value, std_template.bits); + db_printf("SEG DESC @0x%x: PgTbl: 0x%x000", + value, std_template.sdt_desc.table_addr); + if (std_template.sdt_desc.wt) db_printf(", WTHRU"); + else db_printf(", !wthru"); + if (std_template.sdt_desc.sup) db_printf(", S-PROT"); + else db_printf(", UserOk"); + if (std_template.sdt_desc.g) db_printf(", GLOBAL"); + else db_printf(", !global"); + if (std_template.sdt_desc.no_cache) db_printf(", $INHIBIT"); + else db_printf(", $ok"); + if (std_template.sdt_desc.prot) db_printf(", W-PROT"); + else db_printf(", WriteOk"); + if (std_template.sdt_desc.dtype) db_printf(", VALID"); + else db_printf(", !valid"); + db_printf(".\n"); + + /* if not valid, done now */ + if (std_template.sdt_desc.dtype == 0) { + db_printf("<would report an error, STD entry not valid>\n"); + + return; + } + + value = std_template.sdt_desc.table_addr << 12; + } + + /* translate value from physical to virtual */ + if (verbose_flag) + db_printf("[%x physical is %x virtual]\n", value, value + VEQR_ADDR); + value += VEQR_ADDR; + + /******* PAGE TABLE *********/ + { + union pte_template pte_template; + if (verbose_flag) + db_printf("will follow to entry %d of page at 0x%x...\n", + virtual_address.field.page_table_index, value); + value |= virtual_address.field.page_table_index * + sizeof(struct pt_entry); + + if (badwordaddr(value)) { + db_printf("error: unable to access page at 0x%08x.\n", value); + + return; + } + + pte_template.bits = *(unsigned *)value; + if (verbose_flag > 1) + db_printf("PAGE DESC @0x%x is 0x%08x.\n", value, pte_template.bits); + db_printf("PAGE DESC @0x%x: page @%x000", + value, pte_template.pte.pfn); + if (pte_template.pte.wired) db_printf(", WIRE"); + else db_printf(", !wire"); + if (pte_template.pte.wt) db_printf(", WTHRU"); + else db_printf(", !wthru"); + if (pte_template.pte.sup) db_printf(", S-PROT"); + else db_printf(", UserOk"); + if (pte_template.pte.g) db_printf(", GLOBAL"); + else db_printf(", !global"); + if (pte_template.pte.ci) db_printf(", $INHIBIT"); + else db_printf(", $ok"); + if (pte_template.pte.modified) db_printf(", MOD"); + else db_printf(", !mod"); + if (pte_template.pte.pg_used) db_printf(", USED"); + else db_printf(", !used"); + if (pte_template.pte.prot) db_printf(", W-PROT"); + else db_printf(", WriteOk"); + if (pte_template.pte.dtype) db_printf(", VALID"); + else db_printf(", !valid"); + db_printf(".\n"); + + /* if not valid, done now */ + if (pte_template.pte.dtype == 0) { + db_printf("<would report an error, PTE entry not valid>\n"); + + return; + } + + value = pte_template.pte.pfn << 12; + if (verbose_flag) + db_printf("will follow to byte %d of page at 0x%x...\n", + virtual_address.field.page_offset, value); + value |= virtual_address.field.page_offset; + + if (badwordaddr(value)) { + db_printf("error: unable to access page at 0x%08x.\n", value); + + return; + } + } + + /* translate value from physical to virtual */ + if (verbose_flag) + db_printf("[%x physical is %x virtual]\n", value, value + VEQR_ADDR); + value += VEQR_ADDR; + + db_printf("WORD at 0x%x is 0x%08x.\n", value, *(unsigned *)value); +} void m18x_cmmu_cache_state(unsigned addr, unsigned supervisor_flag) { - static char *vv_name[4] = - {"exclu-unmod", "exclu-mod", "shared-unmod", "invalid"}; - int cmmu_num; - - for (cmmu_num = 0; cmmu_num < MAX_CMMUS; cmmu_num++) { - union ssr ssr; - union cssp cssp; - struct cmmu_regs *R; - unsigned tag, line; - if (!cmmu[cmmu_num].cmmu_alive) - continue; - R = cmmu[cmmu_num].cmmu_regs; - db_printf("cmmu #%d %s cmmu for cpu %d.\n", cmmu_num, - cmmu[cmmu_num].which ? "data" : "inst", - cmmu[cmmu_num].cmmu_cpu); - R->sar = addr; - R->scr = supervisor_flag ? CMMU_PROBE_SUPER : CMMU_PROBE_USER; - - ssr.bits = R->ssr; - if (!ssr.field.v) { - db_printf("PROBE of 0x%08x faults.\n",addr); - continue; - } - db_printf("PROBE of 0x%08x returns phys=0x%x", addr, R->sar); - - tag = R->sar & ~0xfff; - cssp.bits = R->cssp; - - /* check to see if any of the tags for the set match the address */ - for (line = 0; line < 4; line++) { - if (VV(cssp, line) == VV_INVALID) { - db_printf("line %d invalid.\n", line); - continue; /* line is invalid */ - } - if (D(cssp, line)) { - db_printf("line %d disabled.\n", line); - continue; /* line is disabled */ - } - - if ((R->ctp[line] & ~0xfff) != tag) { - db_printf("line %d address tag is %x.\n", line, - (R->ctp[line] & ~0xfff)); - continue; - } - db_printf("found in line %d as %08x (%s).\n", - line, R->cdp[line], vv_name[VV(cssp, line)]); - } - } - + static char *vv_name[4] = + {"exclu-unmod", "exclu-mod", "shared-unmod", "invalid"}; + int cmmu_num; + + for (cmmu_num = 0; cmmu_num < MAX_CMMUS; cmmu_num++) { + union ssr ssr; + union cssp cssp; + struct cmmu_regs *R; + unsigned tag, line; + if (!cmmu[cmmu_num].cmmu_alive) + continue; + R = cmmu[cmmu_num].cmmu_regs; + db_printf("cmmu #%d %s cmmu for cpu %d.\n", cmmu_num, + cmmu[cmmu_num].which ? "data" : "inst", + cmmu[cmmu_num].cmmu_cpu); + R->sar = addr; + R->scr = supervisor_flag ? CMMU_PROBE_SUPER : CMMU_PROBE_USER; + + ssr.bits = R->ssr; + if (!ssr.field.v) { + db_printf("PROBE of 0x%08x faults.\n",addr); + continue; + } + db_printf("PROBE of 0x%08x returns phys=0x%x", addr, R->sar); + + tag = R->sar & ~0xfff; + cssp.bits = R->cssp; + + /* check to see if any of the tags for the set match the address */ + for (line = 0; line < 4; line++) { + if (VV(cssp, line) == VV_INVALID) { + db_printf("line %d invalid.\n", line); + continue; /* line is invalid */ + } + if (D(cssp, line)) { + db_printf("line %d disabled.\n", line); + continue; /* line is disabled */ + } + + if ((R->ctp[line] & ~0xfff) != tag) { + db_printf("line %d address tag is %x.\n", line, + (R->ctp[line] & ~0xfff)); + continue; + } + db_printf("found in line %d as %08x (%s).\n", + line, R->cdp[line], vv_name[VV(cssp, line)]); + } + } + } void +#endif /* end if DDB */ m18x_show_cmmu_info(unsigned addr) { - int cmmu_num; - m18x_cmmu_cache_state(addr, 1); - - for (cmmu_num = 0; cmmu_num < MAX_CMMUS; cmmu_num++) - if (cmmu[cmmu_num].cmmu_alive) { - db_printf("cmmu #%d %s cmmu for cpu %d: ", cmmu_num, - cmmu[cmmu_num].which ? "data" : "inst", - cmmu[cmmu_num].cmmu_cpu); - m18x_cmmu_show_translation(addr, 1, 0, cmmu_num); - } + int cmmu_num; + m18x_cmmu_cache_state(addr, 1); + + for (cmmu_num = 0; cmmu_num < MAX_CMMUS; cmmu_num++) + if (cmmu[cmmu_num].cmmu_alive) { + db_printf("cmmu #%d %s cmmu for cpu %d: ", cmmu_num, + cmmu[cmmu_num].which ? "data" : "inst", + cmmu[cmmu_num].cmmu_cpu); + m18x_cmmu_show_translation(addr, 1, 0, cmmu_num); + } } -#endif /* end if DDB */ diff --git a/sys/arch/mvme88k/mvme88k/m197_cmmu.c b/sys/arch/mvme88k/mvme88k/m197_cmmu.c index 33aa0a7e44e..bf17ea716b6 100644 --- a/sys/arch/mvme88k/mvme88k/m197_cmmu.c +++ b/sys/arch/mvme88k/mvme88k/m197_cmmu.c @@ -1,4 +1,4 @@ -/* $OpenBSD: m197_cmmu.c,v 1.2 2000/03/03 00:54:53 todd Exp $ */ +/* $OpenBSD: m197_cmmu.c,v 1.3 2000/12/28 21:21:24 smurph Exp $ */ /* * Copyright (c) 1998 Steve Murphree, Jr. * Copyright (c) 1996 Nivas Madhur @@ -109,59 +109,59 @@ void m197_setup_board_config(void); void m197_show_apr(unsigned value) { - union apr_template apr_template; - apr_template.bits = value; + union apr_template apr_template; + apr_template.bits = value; - printf("table @ 0x%x000", apr_template.field.st_base); - if (apr_template.field.wt) printf(", writethrough"); - if (apr_template.field.g) printf(", global"); - if (apr_template.field.ci) printf(", cache inhibit"); - if (apr_template.field.te) printf(", valid"); - else printf(", not valid"); - printf("\n"); + printf("table @ 0x%x000", apr_template.field.st_base); + if (apr_template.field.wt) printf(", writethrough"); + if (apr_template.field.g) printf(", global"); + if (apr_template.field.ci) printf(", cache inhibit"); + if (apr_template.field.te) printf(", valid"); + else printf(", not valid"); + printf("\n"); } void m197_show_sctr(unsigned value) { - union { - unsigned bits; - struct { - unsigned :16, - pe: 1, - se: 1, - pr: 1, - :13; - } fields; - } sctr; - sctr.bits = value; - printf("%spe, %sse %spr]\n", - sctr.fields.pe ? "" : "!", - sctr.fields.se ? "" : "!", - sctr.fields.pr ? "" : "!"); + union { + unsigned bits; + struct { + unsigned :16, + pe: 1, + se: 1, + pr: 1, + :13; + } fields; + } sctr; + sctr.bits = value; + printf("%spe, %sse %spr]\n", + sctr.fields.pe ? "" : "!", + sctr.fields.se ? "" : "!", + sctr.fields.pr ? "" : "!"); } #endif void m197_setup_board_config(void) { - /* dummy routine */ - m197_setup_cmmu_config(); - return; + /* dummy routine */ + m197_setup_cmmu_config(); + return; } void m197_setup_cmmu_config(void) { - /* we can print something here... */ - cpu_sets[0] = 1; /* This cpu installed... */ - return; + /* we can print something here... */ + cpu_sets[0] = 1; /* This cpu installed... */ + return; } void m197_cmmu_dump_config(void) { - /* dummy routine */ - return; + /* dummy routine */ + return; } /* To be implemented as a macro for speedup - XXX-smurph */ @@ -170,12 +170,14 @@ m197_cmmu_store(int mmu, int reg, unsigned val) { } -int m197_cmmu_alive(int mmu) +int +m197_cmmu_alive(int mmu) { return 1; } -unsigned m197_cmmu_get(int mmu, int reg) +unsigned +m197_cmmu_get(int mmu, int reg) { unsigned val; return val; @@ -185,7 +187,8 @@ unsigned m197_cmmu_get(int mmu, int reg) * This function is called by the MMU module and pokes values * into the CMMU's registers. */ -void m197_cmmu_set(int reg, unsigned val, int flags, +void +m197_cmmu_set(int reg, unsigned val, int flags, int num, int mode, int access, vm_offset_t addr) { return; @@ -197,7 +200,7 @@ void m197_cmmu_set(int reg, unsigned val, int flags, */ unsigned m197_cmmu_get_by_mode(int cpu, int mode) { - return 0; + return 0; } #endif @@ -206,28 +209,29 @@ unsigned m197_cmmu_get_by_mode(int cpu, int mode) * number and master/slave status . Should be called first * by the master, before the slaves are started. */ -void m197_cpu_configuration_print(int master) -{ - int pid = read_processor_identification_register(); - int proctype = (pid & 0xff00) >> 8; - int procvers = (pid & 0xe) >> 1; - int mmu, cpu = cpu_number(); - struct simplelock print_lock; - - if (master) - simple_lock_init(&print_lock); - - simple_lock(&print_lock); - - printf("Processor %d: ", cpu); - if (proctype) - printf("Architectural Revision 0x%x UNKNOWN CPU TYPE Version 0x%x\n", - proctype, procvers); - else - printf("M88110 Version 0x%x\n", procvers); - - simple_unlock(&print_lock); - return; +void +m197_cpu_configuration_print(int master) +{ + int pid = read_processor_identification_register(); + int proctype = (pid & 0xff00) >> 8; + int procvers = (pid & 0xe) >> 1; + int mmu, cpu = cpu_number(); + struct simplelock print_lock; + + if (master) + simple_lock_init(&print_lock); + + simple_lock(&print_lock); + + printf("Processor %d: ", cpu); + if (proctype) + printf("Architectural Revision 0x%x UNKNOWN CPU TYPE Version 0x%x\n", + proctype, procvers); + else + printf("M88110 Version 0x%x\n", procvers); + + simple_unlock(&print_lock); + return; } /* @@ -238,72 +242,72 @@ void m197_load_patc(int entry, vm_offset_t vaddr, vm_offset_t paddr, int kernel) void m197_cmmu_init(void) { - int i; - unsigned tmp; - extern void *kernel_sdt; - unsigned lba, pba, value; - init_done = 0; - - /* clear BATCs */ - for (i=0; i<8; i++) { - m197_cmmu_set_pair_batc_entry(0, i, 0); - } - /* clear PATCs */ - for (i=0; i<32; i++) { - m197_load_patc(i, 0, 0, 0); - } - set_ictl(CMMU_ICTL_DID /* Double instruction disable */ - | CMMU_ICTL_MEN - | CMMU_ICTL_HTEN); - - - set_dctl(CMMU_DCTL_MEN - | CMMU_DCTL_HTEN); - - set_icmd(CMMU_ICMD_INV_ITIC); /* clear instruction cache */ - set_dcmd(CMMU_DCMD_INV_ALL); /* clear data cache */ - - tmp = (0x00000 << 12) | /* segment table base address */ - AREA_D_WT | /* write through */ - AREA_D_G | /* global */ - ! AREA_D_TE ; /* not translation enable */ - - set_isap(tmp); - set_dsap(tmp); - - set_isr(0); - set_ilar(0); - set_ipar(0); - set_dsr(0); - set_dlar(0); - set_dpar(0); - - lba = pba = (unsigned)&kernel_sdt; - lba &= ~0x7FFFF; - pba = pba >> 13; - pba &= ~0x3F; - value = lba | pba | 0x20 | 0x01; - - m197_cmmu_set_pair_batc_entry(0, 0, value); - -} + int i; + unsigned tmp; + extern void *kernel_sdt; + unsigned lba, pba, value; + init_done = 0; + + /* clear BATCs */ + for (i=0; i<8; i++) { + m197_cmmu_set_pair_batc_entry(0, i, 0); + } + /* clear PATCs */ + for (i=0; i<32; i++) { + m197_load_patc(i, 0, 0, 0); + } + set_ictl(CMMU_ICTL_DID /* Double instruction disable */ + | CMMU_ICTL_MEN + | CMMU_ICTL_HTEN); + set_dctl(CMMU_DCTL_MEN + | CMMU_DCTL_HTEN); + + set_icmd(CMMU_ICMD_INV_ITIC); /* clear instruction cache */ + set_dcmd(CMMU_DCMD_INV_ALL); /* clear data cache */ + + tmp = (0x00000 << 12) | /* segment table base address */ + AREA_D_WT | /* write through */ + AREA_D_G | /* global */ + ! AREA_D_TE ; /* not translation enable */ + + set_isap(tmp); + set_dsap(tmp); + + set_isr(0); + set_ilar(0); + set_ipar(0); + set_dsr(0); + set_dlar(0); + set_dpar(0); + + lba = pba = (unsigned)&kernel_sdt; + lba &= ~0x7FFFF; + pba = pba >> 13; + pba &= ~0x3F; + value = lba | pba | 0x20 | 0x01; + + m197_cmmu_set_pair_batc_entry(0, 0, value); + +} + /* * Just before poweroff or reset.... */ void m197_cmmu_shutdown_now(void) { - unsigned tmp; - unsigned cmmu_num; + unsigned tmp; + unsigned cmmu_num; } /* * enable parity */ -void m197_cmmu_parity_enable(void) +void +m197_cmmu_parity_enable(void) { #ifdef PARITY_ENABLE #endif /* PARITY_ENABLE */ @@ -316,9 +320,10 @@ void m197_cmmu_parity_enable(void) */ #define ILLADDRESS U(0x0F000000) /* any faulty address */ -unsigned m197_cmmu_cpu_number(void) +unsigned +m197_cmmu_cpu_number(void) { - return 0; /* to make compiler happy */ + return 0; /* to make compiler happy */ } /** @@ -330,7 +335,7 @@ static void m197_cmmu_remote_set(unsigned cpu, unsigned r, unsigned data, unsigned x) { - panic("m197_cmmu_remote_set() called!\n"); + panic("m197_cmmu_remote_set() called!\n"); } /* @@ -343,78 +348,78 @@ static unsigned m197_cmmu_remote_get(unsigned cpu, unsigned r, unsigned data) { - panic("m197_cmmu_remote_get() called!\n"); - return 0; + panic("m197_cmmu_remote_get() called!\n"); + return 0; } /* Needs no locking - read only registers */ unsigned m197_cmmu_get_idr(unsigned data) { - return 0; /* todo */ + return 0; /* todo */ } int probe_mmu(vm_offset_t va, int data) { - unsigned result; - if (data) { - set_dsar((unsigned)va); - set_dcmd(CMMU_DCMD_PRB_SUPR); - result = get_dsr(); - if (result & CMMU_DSR_PH) - return 1; - else - return 0; - } else { - set_isar((unsigned)va); - set_icmd(CMMU_ICMD_PRB_SUPR); - result = get_isr(); - if (result & CMMU_ISR_BH) - return 2; - else if (result & CMMU_ISR_PH) - return 1; - else - return 0; - } - return 0; + unsigned result; + if (data) { + set_dsar((unsigned)va); + set_dcmd(CMMU_DCMD_PRB_SUPR); + result = get_dsr(); + if (result & CMMU_DSR_PH) + return 1; + else + return 0; + } else { + set_isar((unsigned)va); + set_icmd(CMMU_ICMD_PRB_SUPR); + result = get_isr(); + if (result & CMMU_ISR_BH) + return 2; + else if (result & CMMU_ISR_PH) + return 1; + else + return 0; + } + return 0; } void m197_cmmu_set_sapr(unsigned ap) { - int result; - set_icmd(CMMU_ICMD_INV_SATC); - set_dcmd(CMMU_DCMD_INV_SATC); - /* load an entry pointing to seg table into PATC */ - /* Don't forget to set it valid */ - - m197_load_patc(0, (vm_offset_t)ap, (vm_offset_t)(ap | 0x1), 1); - if(!(result = probe_mmu((vm_offset_t) ap, 1))){ - printf("Didn't make it!!!!\n"); - return; - } else { - if (result == 2) - printf("area pointer is in BATC.\n"); - if (result == 1) - printf("area pointer is in PATC.\n"); - } - - set_isap(ap); - set_dsap(ap); + int result; + set_icmd(CMMU_ICMD_INV_SATC); + set_dcmd(CMMU_DCMD_INV_SATC); + /* load an entry pointing to seg table into PATC */ + /* Don't forget to set it valid */ + + m197_load_patc(0, (vm_offset_t)ap, (vm_offset_t)(ap | 0x1), 1); + if (!(result = probe_mmu((vm_offset_t) ap, 1))) { + printf("Didn't make it!!!!\n"); + return; + } else { + if (result == 2) + printf("area pointer is in BATC.\n"); + if (result == 1) + printf("area pointer is in PATC.\n"); + } + + set_isap(ap); + set_dsap(ap); } void m197_cmmu_remote_set_sapr(unsigned cpu, unsigned ap) { - m197_cmmu_set_sapr(ap); + m197_cmmu_set_sapr(ap); } void m197_cmmu_set_uapr(unsigned ap) { - set_iuap(ap); - set_duap(ap); + set_iuap(ap); + set_duap(ap); } /* @@ -427,18 +432,18 @@ m197_cmmu_set_uapr(unsigned ap) */ void m197_cmmu_set_batc_entry( - unsigned cpu, - unsigned entry_no, - unsigned data, /* 1 = data, 0 = instruction */ - unsigned value) /* the value to stuff */ + unsigned cpu, + unsigned entry_no, + unsigned data, /* 1 = data, 0 = instruction */ + unsigned value) /* the value to stuff */ { - if (data) { - set_dir(entry_no); - set_dbp(value); - } else { - set_iir(entry_no); - set_ibp(value); - } + if (data) { + set_dir(entry_no); + set_dbp(value); + } else { + set_iir(entry_no); + set_ibp(value); + } } /* @@ -449,8 +454,8 @@ void m197_cmmu_set_pair_batc_entry(unsigned cpu, unsigned entry_no, unsigned value) /* the value to stuff into the batc */ { - m197_cmmu_set_batc_entry(cpu, entry_no, 1, value); - m197_cmmu_set_batc_entry(cpu, entry_no, 0, value); + m197_cmmu_set_batc_entry(cpu, entry_no, 1, value); + m197_cmmu_set_batc_entry(cpu, entry_no, 0, value); } /** @@ -464,15 +469,15 @@ m197_cmmu_set_pair_batc_entry(unsigned cpu, unsigned entry_no, unsigned value) void m197_cmmu_flush_remote_tlb(unsigned cpu, unsigned kernel, vm_offset_t vaddr, int size) { - register s = splhigh(); - if (kernel) { - set_icmd(CMMU_ICMD_INV_SATC); - set_dcmd(CMMU_DCMD_INV_SATC); - } else { - set_icmd(CMMU_ICMD_INV_UATC); - set_dcmd(CMMU_DCMD_INV_UATC); - } - splx(s); + register s = splhigh(); + if (kernel) { + set_icmd(CMMU_ICMD_INV_SATC); + set_dcmd(CMMU_DCMD_INV_SATC); + } else { + set_icmd(CMMU_ICMD_INV_UATC); + set_dcmd(CMMU_DCMD_INV_UATC); + } + splx(s); } /* @@ -481,9 +486,9 @@ m197_cmmu_flush_remote_tlb(unsigned cpu, unsigned kernel, vm_offset_t vaddr, int void m197_cmmu_flush_tlb(unsigned kernel, vm_offset_t vaddr, int size) { - int cpu; - cpu = cpu_number(); - m197_cmmu_flush_remote_tlb(cpu, kernel, vaddr, size); + int cpu; + cpu = cpu_number(); + m197_cmmu_flush_remote_tlb(cpu, kernel, vaddr, size); } /* @@ -493,28 +498,28 @@ m197_cmmu_flush_tlb(unsigned kernel, vm_offset_t vaddr, int size) */ void m197_cmmu_pmap_activate( - unsigned cpu, - unsigned uapr, - batc_template_t i_batc[BATC_MAX], - batc_template_t d_batc[BATC_MAX]) -{ - int entry_no; - - m197_cmmu_set_uapr(uapr); - - /* - for (entry_no = 0; entry_no < 8; entry_no++) { - m197_cmmu_set_batc_entry(cpu, entry_no, 0, i_batc[entry_no].bits); - m197_cmmu_set_batc_entry(cpu, entry_no, 1, d_batc[entry_no].bits); - } - */ - /* - * Flush the user TLB. - * IF THE KERNEL WILL EVER CARE ABOUT THE BATC ENTRIES, - * THE SUPERVISOR TLBs SHOULB EE FLUSHED AS WELL. - */ - set_icmd(CMMU_ICMD_INV_UATC); - set_dcmd(CMMU_DCMD_INV_UATC); + unsigned cpu, + unsigned uapr, + batc_template_t i_batc[BATC_MAX], + batc_template_t d_batc[BATC_MAX]) +{ + int entry_no; + + m197_cmmu_set_uapr(uapr); + + /* + for (entry_no = 0; entry_no < 8; entry_no++) { + m197_cmmu_set_batc_entry(cpu, entry_no, 0, i_batc[entry_no].bits); + m197_cmmu_set_batc_entry(cpu, entry_no, 1, d_batc[entry_no].bits); + } + */ + /* + * Flush the user TLB. + * IF THE KERNEL WILL EVER CARE ABOUT THE BATC ENTRIES, + * THE SUPERVISOR TLBs SHOULB EE FLUSHED AS WELL. + */ + set_icmd(CMMU_ICMD_INV_UATC); + set_dcmd(CMMU_DCMD_INV_UATC); } /** @@ -536,10 +541,10 @@ m197_cmmu_pmap_activate( void m197_cmmu_flush_remote_cache(int cpu, vm_offset_t physaddr, int size) { - register s = splhigh(); - set_icmd(CMMU_ICMD_INV_ITIC); - set_dcmd(CMMU_DCMD_FLUSH_ALL_INV); - splx(s); + register s = splhigh(); + set_icmd(CMMU_ICMD_INV_ITIC); + set_dcmd(CMMU_DCMD_FLUSH_ALL_INV); + splx(s); } /* @@ -548,8 +553,8 @@ m197_cmmu_flush_remote_cache(int cpu, vm_offset_t physaddr, int size) void m197_cmmu_flush_cache(vm_offset_t physaddr, int size) { - int cpu = cpu_number(); - m197_cmmu_flush_remote_cache(cpu, physaddr, size); + int cpu = cpu_number(); + m197_cmmu_flush_remote_cache(cpu, physaddr, size); } /* @@ -558,11 +563,11 @@ m197_cmmu_flush_cache(vm_offset_t physaddr, int size) void m197_cmmu_flush_remote_inst_cache(int cpu, vm_offset_t physaddr, int size) { - register s = splhigh(); - - set_icmd(CMMU_ICMD_INV_ITIC); + register s = splhigh(); + + set_icmd(CMMU_ICMD_INV_ITIC); - splx(s); + splx(s); } /* @@ -571,9 +576,9 @@ m197_cmmu_flush_remote_inst_cache(int cpu, vm_offset_t physaddr, int size) void m197_cmmu_flush_inst_cache(vm_offset_t physaddr, int size) { - int cpu; - cpu = cpu_number(); - m197_cmmu_flush_remote_inst_cache(cpu, physaddr, size); + int cpu; + cpu = cpu_number(); + m197_cmmu_flush_remote_inst_cache(cpu, physaddr, size); } /* @@ -582,9 +587,9 @@ m197_cmmu_flush_inst_cache(vm_offset_t physaddr, int size) void m197_cmmu_flush_remote_data_cache(int cpu, vm_offset_t physaddr, int size) { - register s = splhigh(); - set_dcmd(CMMU_DCMD_FLUSH_ALL_INV); - splx(s); + register s = splhigh(); + set_dcmd(CMMU_DCMD_FLUSH_ALL_INV); + splx(s); } /* @@ -593,9 +598,9 @@ m197_cmmu_flush_remote_data_cache(int cpu, vm_offset_t physaddr, int size) void m197_cmmu_flush_data_cache(vm_offset_t physaddr, int size) { - int cpu; - cpu = cpu_number(); - m197_cmmu_flush_remote_data_cache(cpu, physaddr, size); + int cpu; + cpu = cpu_number(); + m197_cmmu_flush_remote_data_cache(cpu, physaddr, size); } /* @@ -604,47 +609,47 @@ m197_cmmu_flush_data_cache(vm_offset_t physaddr, int size) void m197_cmmu_sync_cache(vm_offset_t physaddr, int size) { - register s = splhigh(); - int cpu; - cpu = cpu_number(); - /* set_mmureg(CMMU_ICTL, CMMU_ICMD_INV_TIC); */ - set_dcmd(CMMU_DCMD_FLUSH_ALL); + register s = splhigh(); + int cpu; + cpu = cpu_number(); + /* set_mmureg(CMMU_ICTL, CMMU_ICMD_INV_TIC); */ + set_dcmd(CMMU_DCMD_FLUSH_ALL); - splx(s); + splx(s); } void m197_cmmu_sync_inval_cache(vm_offset_t physaddr, int size) { - register s = splhigh(); - int cpu; - cpu = cpu_number(); + register s = splhigh(); + int cpu; + cpu = cpu_number(); - set_dcmd(CMMU_DCMD_FLUSH_ALL_INV); - splx(s); + set_dcmd(CMMU_DCMD_FLUSH_ALL_INV); + splx(s); } void m197_cmmu_inval_cache(vm_offset_t physaddr, int size) { - register s = splhigh(); - int cpu; - cpu = cpu_number(); - set_icmd(CMMU_ICMD_INV_ITIC); - set_dcmd(CMMU_DCMD_INV_ALL); - splx(s); + register s = splhigh(); + int cpu; + cpu = cpu_number(); + set_icmd(CMMU_ICMD_INV_ITIC); + set_dcmd(CMMU_DCMD_INV_ALL); + splx(s); } void m197_dma_cachectl(vm_offset_t va, int size, int op) { - int count; - if (op == DMA_CACHE_SYNC) - m197_cmmu_sync_cache(kvtop(va), size); - else if (op == DMA_CACHE_SYNC_INVAL) - m197_cmmu_sync_inval_cache(kvtop(va), size); - else - m197_cmmu_inval_cache(kvtop(va), size); + int count; + if (op == DMA_CACHE_SYNC) + m197_cmmu_sync_cache(kvtop(va), size); + else if (op == DMA_CACHE_SYNC_INVAL) + m197_cmmu_sync_inval_cache(kvtop(va), size); + else + m197_cmmu_inval_cache(kvtop(va), size); } #ifdef DDB @@ -674,29 +679,28 @@ m197_dma_cachectl(vm_offset_t va, int size, int op) * If cmmu == -1, the data cmmu for the current cpu is used. */ void -m197_cmmu_show_translation( - unsigned address, - unsigned supervisor_flag, - unsigned verbose_flag, - int cmmu_num) +m197_cmmu_show_translation(unsigned address, + unsigned supervisor_flag, + unsigned verbose_flag, + int cmmu_num) { - /* - * A virtual address is split into three fields. Two are used as - * indicies into tables (segment and page), and one is an offset into - * a page of memory. - */ - union { - unsigned bits; - struct { - unsigned segment_table_index:10, - page_table_index:10, - page_offset:12; - } field; - } virtual_address; - unsigned value; + /* + * A virtual address is split into three fields. Two are used as + * indicies into tables (segment and page), and one is an offset into + * a page of memory. + */ + union { + unsigned bits; + struct { + unsigned segment_table_index:10, + page_table_index:10, + page_offset:12; + } field; + } virtual_address; + unsigned value; - if (verbose_flag) - db_printf("-------------------------------------------\n"); + if (verbose_flag) + db_printf("-------------------------------------------\n"); } @@ -704,16 +708,16 @@ m197_cmmu_show_translation( void m197_cmmu_cache_state(unsigned addr, unsigned supervisor_flag) { - static char *vv_name[4] = - {"exclu-unmod", "exclu-mod", "shared-unmod", "invalid"}; - int cmmu_num; + static char *vv_name[4] = + {"exclu-unmod", "exclu-mod", "shared-unmod", "invalid"}; + int cmmu_num; } void m197_show_cmmu_info(unsigned addr) { - int cmmu_num; - m197_cmmu_cache_state(addr, 1); + int cmmu_num; + m197_cmmu_cache_state(addr, 1); } #endif /* end if DDB */ @@ -722,20 +726,20 @@ m197_show_cmmu_info(unsigned addr) void m197_load_patc(int entry, vm_offset_t vaddr, vm_offset_t paddr, int kernel) { - unsigned lpa, pfa, i; - - lpa = (unsigned)vaddr & 0xFFFFF000; - if (kernel) { - lpa |= 0x01; - } - pfa = (unsigned)paddr; - i = entry << 5; - set_iir(i); - set_ippu(lpa); - set_ippl(pfa); - set_dir(i); - set_dppu(lpa); - set_dppl(lpa); + unsigned lpa, pfa, i; + + lpa = (unsigned)vaddr & 0xFFFFF000; + if (kernel) { + lpa |= 0x01; + } + pfa = (unsigned)paddr; + i = entry << 5; + set_iir(i); + set_ippu(lpa); + set_ippl(pfa); + set_dir(i); + set_dppu(lpa); + set_dppl(lpa); } #define SDT_WP(sd_ptr) ((sd_ptr)->prot != 0) @@ -746,62 +750,62 @@ m197_load_patc(int entry, vm_offset_t vaddr, vm_offset_t paddr, int kernel) int m197_table_search(pmap_t map, vm_offset_t virt, int write, int kernel, int data) { - sdt_entry_t *sdt; - pt_entry_t *pte; - unsigned lpa, pfa, i; - static entry_num = 0; - - if (map == (pmap_t)0) - panic("m197_table_search: pmap is NULL"); - - sdt = SDTENT(map, virt); - - /* - * Check whether page table exist or not. - */ - if (!SDT_VALID(sdt)) - return (4); /* seg fault */ - - /* OK, it's valid. Now check permissions. */ - if (!kernel) - if (SDT_SUP(sdt)) - return (6); /* Supervisor Violation */ - if (write) - if (SDT_WP(sdt)) - return (7); /* Write Violation */ - - else - pte = (pt_entry_t *)(((sdt + SDT_ENTRIES)->table_addr)<<PDT_SHIFT) + PDTIDX(virt); - /* - * Check whether page frame exist or not. - */ - if (!PDT_VALID(pte)) - return (5); /* Page Fault */ - - /* OK, it's valid. Now check permissions. */ - if (!kernel) - if (PDT_SUP(sdt)) - return (6); /* Supervisor Violation */ - if (write) - if (PDT_WP(sdt)) - return (7); /* Write Violation */ - /* If we get here, load the PATC. */ - if (entry_num > 32) - entry_num = 0; - lpa = (unsigned)virt & 0xFFFFF000; - if (kernel) - lpa |= 0x01; - i = entry_num << 5; - if (data) { - set_dir(i); /* set PATC index */ - set_dppu(lpa); /* set logical address */ - set_dppl((unsigned)pte); /* set page fram address */ - } else { - set_iir(i); - set_ippu(lpa); - set_ippl((unsigned)pte); - } - return 0; + sdt_entry_t *sdt; + pt_entry_t *pte; + unsigned lpa, pfa, i; + static entry_num = 0; + + if (map == (pmap_t)0) + panic("m197_table_search: pmap is NULL"); + + sdt = SDTENT(map, virt); + + /* + * Check whether page table exist or not. + */ + if (!SDT_VALID(sdt)) + return (4); /* seg fault */ + + /* OK, it's valid. Now check permissions. */ + if (!kernel) + if (SDT_SUP(sdt)) + return (6); /* Supervisor Violation */ + if (write) + if (SDT_WP(sdt)) + return (7); /* Write Violation */ + + else + pte = (pt_entry_t *)(((sdt + SDT_ENTRIES)->table_addr)<<PDT_SHIFT) + PDTIDX(virt); + /* + * Check whether page frame exist or not. + */ + if (!PDT_VALID(pte)) + return (5); /* Page Fault */ + + /* OK, it's valid. Now check permissions. */ + if (!kernel) + if (PDT_SUP(sdt)) + return (6); /* Supervisor Violation */ + if (write) + if (PDT_WP(sdt)) + return (7); /* Write Violation */ + /* If we get here, load the PATC. */ + if (entry_num > 32) + entry_num = 0; + lpa = (unsigned)virt & 0xFFFFF000; + if (kernel) + lpa |= 0x01; + i = entry_num << 5; + if (data) { + set_dir(i); /* set PATC index */ + set_dppu(lpa); /* set logical address */ + set_dppl((unsigned)pte); /* set page fram address */ + } else { + set_iir(i); + set_ippu(lpa); + set_ippl((unsigned)pte); + } + return 0; } #endif /* MVME197 */ diff --git a/sys/arch/mvme88k/mvme88k/machdep.c b/sys/arch/mvme88k/mvme88k/machdep.c index e0b04f9cb5e..88f5822d696 100644 --- a/sys/arch/mvme88k/mvme88k/machdep.c +++ b/sys/arch/mvme88k/mvme88k/machdep.c @@ -1,4 +1,4 @@ -/* $OpenBSD: machdep.c,v 1.20 2000/03/23 09:59:55 art Exp $ */ +/* $OpenBSD: machdep.c,v 1.21 2000/12/28 21:21:24 smurph Exp $ */ /* * Copyright (c) 1998, 1999 Steve Murphree, Jr. * Copyright (c) 1996 Nivas Madhur @@ -119,14 +119,14 @@ void m88110_Xfp_precise(void); void setupiackvectors(void); unsigned char *ivec[] = { - (unsigned char *)0xFFFE0003, /* not used, no such thing as int 0 */ - (unsigned char *)0xFFFE0007, - (unsigned char *)0xFFFE000B, - (unsigned char *)0xFFFE000F, - (unsigned char *)0xFFFE0013, - (unsigned char *)0xFFFE0017, - (unsigned char *)0xFFFE001B, - (unsigned char *)0xFFFE001F, + (unsigned char *)0xFFFE0003, /* not used, no such thing as int 0 */ + (unsigned char *)0xFFFE0007, + (unsigned char *)0xFFFE000B, + (unsigned char *)0xFFFE000F, + (unsigned char *)0xFFFE0013, + (unsigned char *)0xFFFE0017, + (unsigned char *)0xFFFE001B, + (unsigned char *)0xFFFE001F, }; #ifdef MVME188 @@ -135,10 +135,10 @@ unsigned char *ivec[] = { * Points to the hardware interrupt status register for each CPU. */ volatile unsigned int *int_mask_reg[MAX_CPUS] = { - (volatile unsigned int *)IEN0_REG, - (volatile unsigned int *)IEN1_REG, - (volatile unsigned int *)IEN2_REG, - (volatile unsigned int *)IEN3_REG + (volatile unsigned int *)IEN0_REG, + (volatile unsigned int *)IEN1_REG, + (volatile unsigned int *)IEN2_REG, + (volatile unsigned int *)IEN3_REG }; #endif /* MVME188 */ @@ -154,8 +154,8 @@ volatile vm_offset_t sramva; volatile vm_offset_t obiova; volatile vm_offset_t extiova; -int physmem; /* available physical memory, in pages */ -int cold; /* boot process flag */ +int physmem; /* available physical memory, in pages */ +int cold; /* boot process flag */ vm_offset_t avail_end, avail_start, avail_next; int foodebug = 0; /* for size_memory() */ int longformat = 1; /* for regdump() */ @@ -198,22 +198,22 @@ caddr_t allocsys __P((caddr_t)); /* * Info for CTL_HW */ -char machine[] = "mvme88k"; /* cpu "architecture" */ +char machine[] = "mvme88k"; /* cpu "architecture" */ char cpu_model[120]; extern unsigned master_cpu; extern char version[]; struct bugenv bugargs; struct kernel { - void *entry; - void *symtab; - void *esym; - int bflags; - int bdev; - char *kname; - void *smini; - void *emini; - void *end_load; + void *entry; + void *symtab; + void *esym; + int bflags; + int bdev; + char *kname; + void *smini; + void *emini; + void *end_load; }kflags; char *esym; @@ -255,8 +255,8 @@ int bootcngetc __P((dev_t)); extern void nullcnpollc __P((dev_t, int)); #define bootcnpollc nullcnpollc static struct consdev bootcons = { -NULL, NULL, bootcngetc, bootcnputc, - bootcnpollc, makedev(14,0), 1}; + NULL, NULL, bootcngetc, bootcnputc, + bootcnpollc, makedev(14,0), 1}; void cmmu_init(void); /* * Console initialization: called early on from main, @@ -266,18 +266,18 @@ void cmmu_init(void); void consinit() { - extern struct consdev *cn_tab; - /* - * Initialize the console before we print anything out. - */ + extern struct consdev *cn_tab; + /* + * Initialize the console before we print anything out. + */ - cn_tab = NULL; - cninit(); + cn_tab = NULL; + cninit(); #if defined (DDB) - kdb_init(); - if (boothowto & RB_KDB) - Debugger(); + kdb_init(); + if (boothowto & RB_KDB) + Debugger(); #endif } @@ -289,90 +289,90 @@ consinit() vm_offset_t size_memory(void) { - volatile unsigned int *look; - unsigned int *max; - extern char *end; + volatile unsigned int *look; + unsigned int *max; + extern char *end; #define PATTERN 0x5a5a5a5a #define STRIDE (4*1024) /* 4k at a time */ #define Roundup(value, stride) (((unsigned)(value) + (stride) - 1) & ~((stride)-1)) #if 1 - /* - * count it up. - */ - max = (void*)MAXPHYSMEM; - for (look = (void*)Roundup(end, STRIDE); look < max; - look = (int*)((unsigned)look + STRIDE)) { - unsigned save; - - /* if can't access, we've reached the end */ - if (foodebug) printf("%x\n", look); - if (badwordaddr((vm_offset_t)look)) { + /* + * count it up. + */ + max = (void*)MAXPHYSMEM; + for (look = (void*)Roundup(end, STRIDE); look < max; + look = (int*)((unsigned)look + STRIDE)) { + unsigned save; + + /* if can't access, we've reached the end */ + if (foodebug) printf("%x\n", look); + if (badwordaddr((vm_offset_t)look)) { #if defined(DEBUG) - printf("%x\n", look); + printf("%x\n", look); #endif - look = (int *)((int)look - STRIDE); - break; - } - - /* - * If we write a value, we expect to read the same value back. - * We'll do this twice, the 2nd time with the opposite bit - * pattern from the first, to make sure we check all bits. - */ - save = *look; - if (*look = PATTERN, *look != PATTERN) - break; - if (*look = ~PATTERN, *look != ~PATTERN) - break; - *look = save; - } + look = (int *)((int)look - STRIDE); + break; + } + + /* + * If we write a value, we expect to read the same value back. + * We'll do this twice, the 2nd time with the opposite bit + * pattern from the first, to make sure we check all bits. + */ + save = *look; + if (*look = PATTERN, *look != PATTERN) + break; + if (*look = ~PATTERN, *look != ~PATTERN) + break; + *look = save; + } #else - look = (unsigned int *)0x03FFF000; /* temp hack to fake 32Meg on MVME188 */ + look = (unsigned int *)0x03FFF000; /* temp hack to fake 32Meg on MVME188 */ #endif - physmem = btoc(trunc_page((unsigned)look)); /* in pages */ - return (trunc_page((unsigned)look)); + physmem = btoc(trunc_page((unsigned)look)); /* in pages */ + return (trunc_page((unsigned)look)); } int getcpuspeed(void) { - struct bugbrdid brdid; - int speed = 0; - int i, c; - bugbrdid(&brdid); - for (i=0; i<4; i++) { - c=(unsigned char)brdid.speed[i]; - c-= '0'; - speed *=10; - speed +=c; - } - speed = speed / 100; - return (speed); + struct bugbrdid brdid; + int speed = 0; + int i, c; + bugbrdid(&brdid); + for (i=0; i<4; i++) { + c=(unsigned char)brdid.speed[i]; + c-= '0'; + speed *=10; + speed +=c; + } + speed = speed / 100; + return (speed); } int getscsiid(void) { - struct bugbrdid brdid; - int scsiid = 0; - int i, c; - bugbrdid(&brdid); - for (i=0; i<2; i++) { - c=(unsigned char)brdid.scsiid[i]; - scsiid *=10; - c-= '0'; - scsiid +=c; - } - printf("SCSI ID = %d\n", scsiid); - return (7); /* hack! */ + struct bugbrdid brdid; + int scsiid = 0; + int i, c; + bugbrdid(&brdid); + for (i=0; i<2; i++) { + c=(unsigned char)brdid.scsiid[i]; + scsiid *=10; + c-= '0'; + scsiid +=c; + } + printf("SCSI ID = %d\n", scsiid); + return (7); /* hack! */ } void identifycpu() { - cpuspeed = getcpuspeed(); - sprintf(cpu_model, "Motorola MVME%x %dMhz", cputyp, cpuspeed); - printf("\nModel: %s\n", cpu_model); + cpuspeed = getcpuspeed(); + sprintf(cpu_model, "Motorola MVME%x %dMhz", cputyp, cpuspeed); + printf("\nModel: %s\n", cpu_model); } /* The following two functions assume UPAGES == 4 */ @@ -391,25 +391,25 @@ identifycpu() void save_u_area(struct proc *p, vm_offset_t va) { - int i; - for (i=0; i<UPAGES; i++) { - p->p_md.md_upte[i] = kvtopte(va + (i * NBPG))->bits; - } + int i; + for (i=0; i<UPAGES; i++) { + p->p_md.md_upte[i] = kvtopte(va + (i * NBPG))->bits; + } } void load_u_area(struct proc *p) { - pte_template_t *t; - - int i; - for (i=0; i<UPAGES; i++) { - t = kvtopte(UADDR + (i * NBPG)); - t->bits = p->p_md.md_upte[i]; - } - for (i=0; i<UPAGES; i++) { - cmmu_flush_tlb(1, UADDR + (i * NBPG), NBPG); - } + pte_template_t *t; + + int i; + for (i=0; i<UPAGES; i++) { + t = kvtopte(UADDR + (i * NBPG)); + t->bits = p->p_md.md_upte[i]; + } + for (i=0; i<UPAGES; i++) { + cmmu_flush_tlb(1, UADDR + (i * NBPG), NBPG); + } } /* @@ -420,22 +420,22 @@ void cpu_initclocks(void) { #ifdef DEBUG - printf("cpu_initclocks(): "); + printf("cpu_initclocks(): "); #endif - if (mdfp.clock_init_func != NULL){ + if (mdfp.clock_init_func != NULL) { #ifdef DEBUG - printf("[interval clock] "); + printf("[interval clock] "); #endif - (*mdfp.clock_init_func)(); - } - if (mdfp.statclock_init_func != NULL){ + (*mdfp.clock_init_func)(); + } + if (mdfp.statclock_init_func != NULL) { #ifdef DEBUG - printf("[statistics clock]"); + printf("[statistics clock]"); #endif - (*mdfp.statclock_init_func)(); - } + (*mdfp.statclock_init_func)(); + } #ifdef DEBUG - printf("\n"); + printf("\n"); #endif } @@ -449,232 +449,245 @@ setstatclockrate(int newhz) void cpu_startup() { - caddr_t v; - int sz, i; - vm_size_t size; - int base, residual; - vm_offset_t minaddr, maxaddr, uarea_pages; - extern vm_offset_t miniroot; - /* - * Initialize error message buffer (at end of core). - * avail_end was pre-decremented in mvme_bootstrap(). - */ - - for (i = 0; i < btoc(MSGBUFSIZE); i++) - pmap_enter(kernel_pmap, (vm_offset_t)msgbufp, - avail_end + i * NBPG, VM_PROT_READ|VM_PROT_WRITE, - VM_PROT_READ|VM_PROT_WRITE, TRUE); - initmsgbuf((caddr_t)msgbufp, round_page(MSGBUFSIZE)); - - printf("real mem = %d\n", ctob(physmem)); - - /* - * Find out how much space we need, allocate it, - * and then give everything true virtual addresses. - */ - sz = (int)allocsys((caddr_t)0); - if ((v = (caddr_t)kmem_alloc(kernel_map, round_page(sz))) == 0) - panic("startup: no room for tables"); - if (allocsys(v) - v != sz) - panic("startup: table size inconsistency"); - - /* - * Grab UADDR virtual address - */ - - uarea_pages = UADDR; - - vm_map_find(kernel_map, vm_object_allocate(USPACE), 0, - (vm_offset_t *)&uarea_pages, USPACE, TRUE); - - if (uarea_pages != UADDR) { - printf("uarea_pages %x: UADDR not free\n", uarea_pages); - panic("bad UADDR"); - } - - if (cputyp != CPU_188) { /* != CPU_188 */ - - /* - * Grab the BUGROM space that we hardwired in pmap_bootstrap - */ - bugromva = BUGROM_START; - - vm_map_find(kernel_map, vm_object_allocate(BUGROM_SIZE), 0, - (vm_offset_t *)&bugromva, BUGROM_SIZE, TRUE); - - if (bugromva != BUGROM_START) { - printf("bugromva %x: BUGROM not free\n", bugromva); - panic("bad bugromva"); - } - - /* - * Grab the SRAM space that we hardwired in pmap_bootstrap - */ - sramva = SRAM_START; - - vm_map_find(kernel_map, vm_object_allocate(SRAM_SIZE), 0, - (vm_offset_t *)&sramva, SRAM_SIZE, TRUE); - - if (sramva != SRAM_START) { - printf("sramva %x: SRAM not free\n", sramva); - panic("bad sramva"); - } - - /* - * Grab the OBIO space that we hardwired in pmap_bootstrap - */ - obiova = OBIO_START; - - vm_map_find(kernel_map, vm_object_allocate(OBIO_SIZE), 0, - (vm_offset_t *)&obiova, OBIO_SIZE, TRUE); - - if (obiova != OBIO_START) { - printf("obiova %x: OBIO not free\n", obiova); - panic("bad OBIO"); - } - } else { /* cputyp == CPU_188 */ - /* - * Grab the UTIL space that we hardwired in pmap_bootstrap - */ - utilva = MVME188_UTILITY; - - vm_map_find(kernel_map, vm_object_allocate(MVME188_UTILITY_SIZE), 0, - (vm_offset_t *)&utilva, MVME188_UTILITY_SIZE, TRUE); - - if (utilva != MVME188_UTILITY) { - printf("utilva %x: UTILITY area not free\n", utilva); - panic("bad utilva"); - } - } - - /* - * Now allocate buffers proper. They are different than the above - * in that they usually occupy more virtual memory than physical. - */ - - size = MAXBSIZE * nbuf; - buffer_map = kmem_suballoc(kernel_map, (vm_offset_t *)&buffers, - &maxaddr, size, TRUE); - minaddr = (vm_offset_t)buffers; - if (vm_map_find(buffer_map, vm_object_allocate(size), (vm_offset_t)0, - (vm_offset_t *)&minaddr, size, FALSE) != KERN_SUCCESS) { - panic("startup: cannot allocate buffers"); - } - if ((bufpages / nbuf) >= btoc(MAXBSIZE)) { - /* don't want to alloc more physical mem than needed */ - bufpages = btoc(MAXBSIZE) * nbuf; - } - base = bufpages / nbuf; - residual = bufpages % nbuf; - - for (i = 0; i < nbuf; i++) { - vm_size_t curbufsize; - vm_offset_t curbuf; - - /* - * First <residual> buffers get (base+1) physical pages - * allocated for them. The rest get (base) physical pages. - * - * The rest of each buffer occupies virtual space, - * but has no physical memory allocated for it. - */ - curbuf = (vm_offset_t)buffers + i * MAXBSIZE; - curbufsize = CLBYTES * (i < residual ? base+1 : base); - - /* this faults in the required physical pages */ - vm_map_pageable(buffer_map, curbuf, curbuf+curbufsize, FALSE); - - vm_map_simplify(buffer_map, curbuf); - } - - /* - * Allocate a submap for exec arguments. This map effectively - * limits the number of processes exec'ing at any time. - */ - exec_map = kmem_suballoc(kernel_map, &minaddr, &maxaddr, - 16*NCARGS, TRUE); + caddr_t v; + int sz, i; + vm_size_t size; + int base, residual; + vm_offset_t minaddr, maxaddr, uarea_pages; + extern vm_offset_t miniroot; + /* + * Initialize error message buffer (at end of core). + * avail_end was pre-decremented in mvme_bootstrap(). + */ + + for (i = 0; i < btoc(MSGBUFSIZE); i++) + pmap_enter(kernel_pmap, (vm_offset_t)msgbufp, + avail_end + i * NBPG, VM_PROT_READ|VM_PROT_WRITE, + VM_PROT_READ|VM_PROT_WRITE, TRUE); + initmsgbuf((caddr_t)msgbufp, round_page(MSGBUFSIZE)); + + printf("real mem = %d\n", ctob(physmem)); + + /* + * Find out how much space we need, allocate it, + * and then give everything true virtual addresses. + */ + sz = (int)allocsys((caddr_t)0); + if ((v = (caddr_t)kmem_alloc(kernel_map, round_page(sz))) == 0) + panic("startup: no room for tables"); + if (allocsys(v) - v != sz) + panic("startup: table size inconsistency"); + + /* + * Grab UADDR virtual address + */ + + uarea_pages = UADDR; + + vm_map_find(kernel_map, vm_object_allocate(USPACE), 0, + (vm_offset_t *)&uarea_pages, USPACE, TRUE); + + if (uarea_pages != UADDR) { + printf("uarea_pages %x: UADDR not free\n", uarea_pages); + panic("bad UADDR"); + } + + switch (cputyp) { +#ifdef MVME187 + case CPU_187: +#endif +#ifdef MVME197 + case CPU_197: +#endif +#if defined(MVME187) || defined(MVME197) + /* + * Grab the BUGROM space that we hardwired in pmap_bootstrap + */ + bugromva = BUGROM_START; + + vm_map_find(kernel_map, vm_object_allocate(BUGROM_SIZE), 0, + (vm_offset_t *)&bugromva, BUGROM_SIZE, TRUE); + + if (bugromva != BUGROM_START) { + printf("bugromva %x: BUGROM not free\n", bugromva); + panic("bad bugromva"); + } + + /* + * Grab the SRAM space that we hardwired in pmap_bootstrap + */ + sramva = SRAM_START; + + vm_map_find(kernel_map, vm_object_allocate(SRAM_SIZE), 0, + (vm_offset_t *)&sramva, SRAM_SIZE, TRUE); + + if (sramva != SRAM_START) { + printf("sramva %x: SRAM not free\n", sramva); + panic("bad sramva"); + } + + /* + * Grab the OBIO space that we hardwired in pmap_bootstrap + */ + obiova = OBIO_START; + + vm_map_find(kernel_map, vm_object_allocate(OBIO_SIZE), 0, + (vm_offset_t *)&obiova, OBIO_SIZE, TRUE); + + if (obiova != OBIO_START) { + printf("obiova %x: OBIO not free\n", obiova); + panic("bad OBIO"); + } + break; +#endif +#ifdef MVME188 + case CPU_188: + /* + * Grab the UTIL space that we hardwired in pmap_bootstrap + */ + utilva = MVME188_UTILITY; + + vm_map_find(kernel_map, vm_object_allocate(MVME188_UTILITY_SIZE), 0, + (vm_offset_t *)&utilva, MVME188_UTILITY_SIZE, TRUE); + + if (utilva != MVME188_UTILITY) { + printf("utilva %x: UTILITY area not free\n", utilva); + panic("bad utilva"); + } + break; +#endif + default: + panic("startup: unknown cpu type."); + } + + /* + * Now allocate buffers proper. They are different than the above + * in that they usually occupy more virtual memory than physical. + */ + + size = MAXBSIZE * nbuf; + buffer_map = kmem_suballoc(kernel_map, (vm_offset_t *)&buffers, + &maxaddr, size, TRUE); + minaddr = (vm_offset_t)buffers; + if (vm_map_find(buffer_map, vm_object_allocate(size), (vm_offset_t)0, + (vm_offset_t *)&minaddr, size, FALSE) != KERN_SUCCESS) { + panic("startup: cannot allocate buffers"); + } + if ((bufpages / nbuf) >= btoc(MAXBSIZE)) { + /* don't want to alloc more physical mem than needed */ + bufpages = btoc(MAXBSIZE) * nbuf; + } + base = bufpages / nbuf; + residual = bufpages % nbuf; + + for (i = 0; i < nbuf; i++) { + vm_size_t curbufsize; + vm_offset_t curbuf; + + /* + * First <residual> buffers get (base+1) physical pages + * allocated for them. The rest get (base) physical pages. + * + * The rest of each buffer occupies virtual space, + * but has no physical memory allocated for it. + */ + curbuf = (vm_offset_t)buffers + i * MAXBSIZE; + curbufsize = CLBYTES * (i < residual ? base+1 : base); + + /* this faults in the required physical pages */ + vm_map_pageable(buffer_map, curbuf, curbuf+curbufsize, FALSE); + + vm_map_simplify(buffer_map, curbuf); + } + + /* + * Allocate a submap for exec arguments. This map effectively + * limits the number of processes exec'ing at any time. + */ + exec_map = kmem_suballoc(kernel_map, &minaddr, &maxaddr, + 16*NCARGS, TRUE); #ifdef DEBUG - printf("exe_map from 0x%x to 0x%x\n", (unsigned)minaddr, (unsigned)maxaddr); + printf("exe_map from 0x%x to 0x%x\n", (unsigned)minaddr, (unsigned)maxaddr); #endif - /* - * Allocate map for physio. - */ - - phys_map = vm_map_create(kernel_pmap, PHYSIO_MAP_START, - PHYSIO_MAP_START + PHYSIO_MAP_SIZE, TRUE); - if (phys_map == NULL) { - panic("cpu_startup: unable to create phys_map"); - } - - /* - * Allocate map for external I/O XXX new code - smurph - */ - /* - * IOMAP_MAP_START was used for the base address of this map, but - * IOMAP_MAP_START == 0xEF000000, which is larger than a signed - * long (int on 88k). This causes rminit() to break when DIAGNOSTIC is - * defined, as it checks (long)addr < 0. So as a workaround, I use - * 0x10000000 as a base address. XXX smurph - */ - - iomap_map = vm_map_create(kernel_pmap, (u_long)0x10000000, - (u_long)0x10000000 + IOMAP_SIZE, TRUE); - if (iomap_map == NULL) { - panic("cpu_startup: unable to create iomap_map"); - } + /* + * Allocate map for physio. + */ + + phys_map = vm_map_create(kernel_pmap, PHYSIO_MAP_START, + PHYSIO_MAP_START + PHYSIO_MAP_SIZE, TRUE); + if (phys_map == NULL) { + panic("cpu_startup: unable to create phys_map"); + } + + /* + * Allocate map for external I/O XXX new code - smurph + */ + /* + * IOMAP_MAP_START was used for the base address of this map, but + * IOMAP_MAP_START == 0xEF000000, which is larger than a signed + * long (int on 88k). This causes rminit() to break when DIAGNOSTIC is + * defined, as it checks (long)addr < 0. So as a workaround, I use + * 0x10000000 as a base address. XXX smurph + */ + + iomap_map = vm_map_create(kernel_pmap, (u_long)0x10000000, + (u_long)0x10000000 + IOMAP_SIZE, TRUE); + if (iomap_map == NULL) { + panic("cpu_startup: unable to create iomap_map"); + } iomapbase = (void *)kmem_alloc_wait(iomap_map, IOMAP_SIZE); - rminit(iomap, IOMAP_SIZE, (u_long)iomapbase, "iomap", NIOPMAP); - - /* - * Finally, allocate mbuf pool. Since mclrefcnt is an off-size - * we use the more space efficient malloc in place of kmem_alloc. - */ - mclrefcnt = (char *)malloc(NMBCLUSTERS+CLBYTES/MCLBYTES, - M_MBUF, M_NOWAIT); - bzero(mclrefcnt, NMBCLUSTERS+CLBYTES/MCLBYTES); - mb_map = kmem_suballoc(kernel_map, (vm_offset_t *)&mbutl, &maxaddr, - VM_MBUF_SIZE, FALSE); - - /* - * Initialize timeouts - */ - timeout_init(); - - printf("avail mem = %d\n", ptoa(cnt.v_free_count)); - printf("using %d buffers containing %d bytes of memory\n", - nbuf, bufpages * CLBYTES); + rminit(iomap, IOMAP_SIZE, (u_long)iomapbase, "iomap", NIOPMAP); + + /* + * Finally, allocate mbuf pool. Since mclrefcnt is an off-size + * we use the more space efficient malloc in place of kmem_alloc. + */ + mclrefcnt = (char *)malloc(NMBCLUSTERS+CLBYTES/MCLBYTES, + M_MBUF, M_NOWAIT); + bzero(mclrefcnt, NMBCLUSTERS+CLBYTES/MCLBYTES); + mb_map = kmem_suballoc(kernel_map, (vm_offset_t *)&mbutl, &maxaddr, + VM_MBUF_SIZE, FALSE); + + /* + * Initialize timeouts + */ + timeout_init(); + + printf("avail mem = %d\n", ptoa(cnt.v_free_count)); + printf("using %d buffers containing %d bytes of memory\n", + nbuf, bufpages * CLBYTES); #if 0 /* #ifdef MFS */ - /* - * Check to see if a mini-root was loaded into memory. It resides - * at the start of the next page just after the end of BSS. - */ - { - extern void *smini; - - if (miniroot && (boothowto & RB_MINIROOT)) { - boothowto |= RB_DFLTROOT; - mfs_initminiroot(miniroot); - } - } + /* + * Check to see if a mini-root was loaded into memory. It resides + * at the start of the next page just after the end of BSS. + */ + { + extern void *smini; + + if (miniroot && (boothowto & RB_MINIROOT)) { + boothowto |= RB_DFLTROOT; + mfs_initminiroot(miniroot); + } + } #endif - /* - * Set up buffers, so they can be used to read disk labels. - */ - bufinit(); - - /* - * Configure the system. - */ - nofault = NULL; - - /* - * zero out intr_handlers - */ - bzero((void *)intr_handlers, 256 * sizeof(struct intrhand *)); - setupiackvectors(); - configure(); + /* + * Set up buffers, so they can be used to read disk labels. + */ + bufinit(); + + /* + * Configure the system. + */ + nofault = NULL; + + /* + * zero out intr_handlers + */ + bzero((void *)intr_handlers, 256 * sizeof(struct intrhand *)); + setupiackvectors(); + configure(); } /* @@ -695,59 +708,59 @@ register caddr_t v; v = (caddr_t)(((name) = (type *)v) + (num)) #ifdef REAL_CLISTS - valloc(cfree, struct cblock, nclist); + valloc(cfree, struct cblock, nclist); #endif - valloc(timeouts, struct timeout, ntimeout); + valloc(timeouts, struct timeout, ntimeout); #if 0 - valloc(swapmap, struct map, nswapmap = maxproc * 2); + valloc(swapmap, struct map, nswapmap = maxproc * 2); #endif #ifdef SYSVSHM - valloc(shmsegs, struct shmid_ds, shminfo.shmmni); + valloc(shmsegs, struct shmid_ds, shminfo.shmmni); #endif #ifdef SYSVSEM - valloc(sema, struct semid_ds, seminfo.semmni); - valloc(sem, struct sem, seminfo.semmns); - /* This is pretty disgusting! */ - valloc(semu, int, (seminfo.semmnu * seminfo.semusz) / sizeof(int)); + valloc(sema, struct semid_ds, seminfo.semmni); + valloc(sem, struct sem, seminfo.semmns); + /* This is pretty disgusting! */ + valloc(semu, int, (seminfo.semmnu * seminfo.semusz) / sizeof(int)); #endif #ifdef SYSVMSG - valloc(msgpool, char, msginfo.msgmax); - valloc(msgmaps, struct msgmap, msginfo.msgseg); - valloc(msghdrs, struct msg, msginfo.msgtql); - valloc(msqids, struct msqid_ds, msginfo.msgmni); + valloc(msgpool, char, msginfo.msgmax); + valloc(msgmaps, struct msgmap, msginfo.msgseg); + valloc(msghdrs, struct msg, msginfo.msgtql); + valloc(msqids, struct msqid_ds, msginfo.msgmni); #endif - /* - * Determine how many buffers to allocate (enough to - * hold 5% of total physical memory, but at least 16). - * Allocate 1/2 as many swap buffer headers as file i/o buffers. - */ - if (bufpages == 0) - if (physmem < btoc(2 * 1024 * 1024)) - bufpages = (physmem / 10) / CLSIZE; - else - bufpages = (physmem / 20) / CLSIZE; - if (nbuf == 0) { - nbuf = bufpages; - if (nbuf < 16) - nbuf = 16; - } - if (nswbuf == 0) { - nswbuf = (nbuf / 2) &~ 1; /* force even */ - if (nswbuf > 256) - nswbuf = 256; /* sanity */ - } - valloc(swbuf, struct buf, nswbuf); - valloc(buf, struct buf, nbuf); + /* + * Determine how many buffers to allocate (enough to + * hold 5% of total physical memory, but at least 16). + * Allocate 1/2 as many swap buffer headers as file i/o buffers. + */ + if (bufpages == 0) + if (physmem < btoc(2 * 1024 * 1024)) + bufpages = (physmem / 10) / CLSIZE; + else + bufpages = (physmem / 20) / CLSIZE; + if (nbuf == 0) { + nbuf = bufpages; + if (nbuf < 16) + nbuf = 16; + } + if (nswbuf == 0) { + nswbuf = (nbuf / 2) &~ 1; /* force even */ + if (nswbuf > 256) + nswbuf = 256; /* sanity */ + } + valloc(swbuf, struct buf, nswbuf); + valloc(buf, struct buf, nbuf); #if 1 /*XXX_FUTURE*/ - /* - * Arbitrarily limit the number of devices mapping - * the IO space at a given time to NIOPMAP (= 32, default). - */ - valloc(iomap, struct map, niomap = NIOPMAP); + /* + * Arbitrarily limit the number of devices mapping + * the IO space at a given time to NIOPMAP (= 32, default). + */ + valloc(iomap, struct map, niomap = NIOPMAP); #endif - return v; + return v; } /* @@ -764,60 +777,60 @@ struct exec_package *pack; u_long stack; int retval[2]; { - register struct trapframe *tf = USER_REGS(p); + register struct trapframe *tf = USER_REGS(p); /* printf("stack at %x\n", stack); printf("%x - %x\n", USRSTACK - MAXSSIZ, USRSTACK); */ - /* - * The syscall will ``return'' to snip; set it. - * argc, argv, envp are placed on the stack by copyregs. - * Point r2 to the stack. crt0 should extract envp from - * argc & argv before calling user's main. - */ + /* + * The syscall will ``return'' to snip; set it. + * argc, argv, envp are placed on the stack by copyregs. + * Point r2 to the stack. crt0 should extract envp from + * argc & argv before calling user's main. + */ #if 0 - /* - * I don't think I need to mess with fpstate on 88k because - * we make sure the floating point pipeline is drained in - * the trap handlers. Should check on this later. XXX Nivas. - */ - - if ((fs = p->p_md.md_fpstate) != NULL) { - /* - * We hold an FPU state. If we own *the* FPU chip state - * we must get rid of it, and the only way to do that is - * to save it. In any case, get rid of our FPU state. - */ - if (p == fpproc) { - savefpstate(fs); - fpproc = NULL; - } - free((void *)fs, M_SUBPROC); - p->p_md.md_fpstate = NULL; - } + /* + * I don't think I need to mess with fpstate on 88k because + * we make sure the floating point pipeline is drained in + * the trap handlers. Should check on this later. XXX Nivas. + */ + + if ((fs = p->p_md.md_fpstate) != NULL) { + /* + * We hold an FPU state. If we own *the* FPU chip state + * we must get rid of it, and the only way to do that is + * to save it. In any case, get rid of our FPU state. + */ + if (p == fpproc) { + savefpstate(fs); + fpproc = NULL; + } + free((void *)fs, M_SUBPROC); + p->p_md.md_fpstate = NULL; + } #endif /* 0 */ - bzero((caddr_t)tf, sizeof *tf); - tf->epsr = 0x3f0; /* user mode, interrupts enabled, fp enabled */ + bzero((caddr_t)tf, sizeof *tf); + tf->epsr = 0x3f0; /* user mode, interrupts enabled, fp enabled */ /* tf->epsr = 0x3f4;*/ /* user mode, interrupts enabled, fp enabled, MXM Mask */ - /* - * We want to start executing at pack->ep_entry. The way to - * do this is force the processor to fetch from ep_entry. Set - * NIP to something bogus and invalid so that it will be a NOOP. - * And set sfip to ep_entry with valid bit on so that it will be - * fetched. - */ - - tf->snip = pack->ep_entry & ~3; - tf->sfip = (pack->ep_entry & ~3) | FIP_V; - tf->r[2] = stack; - tf->r[31] = stack; - retval[1] = 0; + /* + * We want to start executing at pack->ep_entry. The way to + * do this is force the processor to fetch from ep_entry. Set + * NIP to something bogus and invalid so that it will be a NOOP. + * And set sfip to ep_entry with valid bit on so that it will be + * fetched. + */ + + tf->snip = pack->ep_entry & ~3; + tf->sfip = (pack->ep_entry & ~3) | FIP_V; + tf->r[2] = stack; + tf->r[31] = stack; + retval[1] = 0; } struct sigstate { - int ss_flags; /* which of the following are valid */ - struct trapframe ss_frame; /* original exception frame */ + int ss_flags; /* which of the following are valid */ + struct trapframe ss_frame; /* original exception frame */ }; /* @@ -825,12 +838,12 @@ struct sigstate { * thru sf_handler so... don't screw with them! */ struct sigframe { - int sf_signo; /* signo for handler */ - siginfo_t *sf_sip; - struct sigcontext *sf_scp; /* context ptr for handler */ - sig_t sf_handler; /* handler addr for u_sigc */ - struct sigcontext sf_sc; /* actual context */ - siginfo_t sf_si; + int sf_signo; /* signo for handler */ + siginfo_t *sf_sip; + struct sigcontext *sf_scp; /* context ptr for handler */ + sig_t sf_handler; /* handler addr for u_sigc */ + struct sigcontext sf_sc; /* actual context */ + siginfo_t sf_si; }; #ifdef DEBUG @@ -853,115 +866,115 @@ unsigned long code; int type; union sigval val; { - register struct proc *p = curproc; - register struct trapframe *tf; - register struct sigacts *psp = p->p_sigacts; - struct sigframe *fp; - int oonstack, fsize; - struct sigframe sf; - int addr; - extern char sigcode[], esigcode[]; + register struct proc *p = curproc; + register struct trapframe *tf; + register struct sigacts *psp = p->p_sigacts; + struct sigframe *fp; + int oonstack, fsize; + struct sigframe sf; + int addr; + extern char sigcode[], esigcode[]; #define szsigcode (esigcode - sigcode) - tf = p->p_md.md_tf; - oonstack = psp->ps_sigstk.ss_flags & SA_ONSTACK; - /* - * Allocate and validate space for the signal handler - * context. Note that if the stack is in data space, the - * call to grow() is a nop, and the copyout() - * will fail if the process has not already allocated - * the space with a `brk'. - */ - fsize = sizeof(struct sigframe); - if ((psp->ps_flags & SAS_ALTSTACK) && - (psp->ps_sigstk.ss_flags & SA_ONSTACK) == 0 && - (psp->ps_sigonstack & sigmask(sig))) { - fp = (struct sigframe *)(psp->ps_sigstk.ss_sp + - psp->ps_sigstk.ss_size - fsize); - psp->ps_sigstk.ss_flags |= SA_ONSTACK; - } else - fp = (struct sigframe *)(tf->r[31] - fsize); - if ((unsigned)fp <= USRSTACK - ctob(p->p_vmspace->vm_ssize)) - (void)grow(p, (unsigned)fp); + tf = p->p_md.md_tf; + oonstack = psp->ps_sigstk.ss_flags & SA_ONSTACK; + /* + * Allocate and validate space for the signal handler + * context. Note that if the stack is in data space, the + * call to grow() is a nop, and the copyout() + * will fail if the process has not already allocated + * the space with a `brk'. + */ + fsize = sizeof(struct sigframe); + if ((psp->ps_flags & SAS_ALTSTACK) && + (psp->ps_sigstk.ss_flags & SA_ONSTACK) == 0 && + (psp->ps_sigonstack & sigmask(sig))) { + fp = (struct sigframe *)(psp->ps_sigstk.ss_sp + + psp->ps_sigstk.ss_size - fsize); + psp->ps_sigstk.ss_flags |= SA_ONSTACK; + } else + fp = (struct sigframe *)(tf->r[31] - fsize); + if ((unsigned)fp <= USRSTACK - ctob(p->p_vmspace->vm_ssize)) + (void)grow(p, (unsigned)fp); #ifdef DEBUG - if ((sigdebug & SDB_FOLLOW) || - (sigdebug & SDB_KSTACK) && p->p_pid == sigpid) - printf("sendsig(%d): sig %d ssp %x usp %x scp %x\n", - p->p_pid, sig, &oonstack, fp, &fp->sf_sc); + if ((sigdebug & SDB_FOLLOW) || + (sigdebug & SDB_KSTACK) && p->p_pid == sigpid) + printf("sendsig(%d): sig %d ssp %x usp %x scp %x\n", + p->p_pid, sig, &oonstack, fp, &fp->sf_sc); #endif - /* - * Build the signal context to be used by sigreturn. - */ - sf.sf_signo = sig; - sf.sf_scp = &fp->sf_sc; - sf.sf_handler = catcher; - sf.sf_sc.sc_onstack = oonstack; - sf.sf_sc.sc_mask = mask; - - if (psp->ps_siginfo & sigmask(sig)) { - sf.sf_sip = &fp->sf_si; - initsiginfo(&sf.sf_si, sig, code, type, val); - } - - - /* - * Copy the whole user context into signal context that we - * are building. - */ - bcopy((caddr_t)tf->r, (caddr_t)sf.sf_sc.sc_regs, - sizeof(sf.sf_sc.sc_regs)); - sf.sf_sc.sc_xip = tf->sxip & ~3; - sf.sf_sc.sc_nip = tf->snip & ~3; - sf.sf_sc.sc_fip = tf->sfip & ~3; - sf.sf_sc.sc_ps = tf->epsr; - sf.sf_sc.sc_sp = tf->r[31]; - sf.sf_sc.sc_fpsr = tf->fpsr; - sf.sf_sc.sc_fpcr = tf->fpcr; - sf.sf_sc.sc_ssbr = tf->ssbr; - sf.sf_sc.sc_dmt0 = tf->dmt0; - sf.sf_sc.sc_dmd0 = tf->dmd0; - sf.sf_sc.sc_dma0 = tf->dma0; - sf.sf_sc.sc_dmt1 = tf->dmt1; - sf.sf_sc.sc_dmd1 = tf->dmd1; - sf.sf_sc.sc_dma1 = tf->dma1; - sf.sf_sc.sc_dmt2 = tf->dmt2; - sf.sf_sc.sc_dmd2 = tf->dmd2; - sf.sf_sc.sc_dma2 = tf->dma2; - sf.sf_sc.sc_fpecr = tf->fpecr; - sf.sf_sc.sc_fphs1 = tf->fphs1; - sf.sf_sc.sc_fpls1 = tf->fpls1; - sf.sf_sc.sc_fphs2 = tf->fphs2; - sf.sf_sc.sc_fpls2 = tf->fpls2; - sf.sf_sc.sc_fppt = tf->fppt; - sf.sf_sc.sc_fprh = tf->fprh; - sf.sf_sc.sc_fprl = tf->fprl; - sf.sf_sc.sc_fpit = tf->fpit; - if (copyout((caddr_t)&sf, (caddr_t)fp, sizeof sf)) { - /* - * Process has trashed its stack; give it an illegal - * instruction to halt it in its tracks. - */ - SIGACTION(p, SIGILL) = SIG_DFL; - sig = sigmask(SIGILL); - p->p_sigignore &= ~sig; - p->p_sigcatch &= ~sig; - p->p_sigmask &= ~sig; - psignal(p, SIGILL); - return; - } - /* - * Build the argument list for the signal handler. - * Signal trampoline code is at base of user stack. - */ - addr = (int)PS_STRINGS - szsigcode; - tf->snip = (addr & ~3) | NIP_V; - tf->sfip = (tf->snip + 4) | FIP_V; - tf->r[31] = (unsigned)fp; + /* + * Build the signal context to be used by sigreturn. + */ + sf.sf_signo = sig; + sf.sf_scp = &fp->sf_sc; + sf.sf_handler = catcher; + sf.sf_sc.sc_onstack = oonstack; + sf.sf_sc.sc_mask = mask; + + if (psp->ps_siginfo & sigmask(sig)) { + sf.sf_sip = &fp->sf_si; + initsiginfo(&sf.sf_si, sig, code, type, val); + } + + + /* + * Copy the whole user context into signal context that we + * are building. + */ + bcopy((caddr_t)tf->r, (caddr_t)sf.sf_sc.sc_regs, + sizeof(sf.sf_sc.sc_regs)); + sf.sf_sc.sc_xip = tf->sxip & ~3; + sf.sf_sc.sc_nip = tf->snip & ~3; + sf.sf_sc.sc_fip = tf->sfip & ~3; + sf.sf_sc.sc_ps = tf->epsr; + sf.sf_sc.sc_sp = tf->r[31]; + sf.sf_sc.sc_fpsr = tf->fpsr; + sf.sf_sc.sc_fpcr = tf->fpcr; + sf.sf_sc.sc_ssbr = tf->ssbr; + sf.sf_sc.sc_dmt0 = tf->dmt0; + sf.sf_sc.sc_dmd0 = tf->dmd0; + sf.sf_sc.sc_dma0 = tf->dma0; + sf.sf_sc.sc_dmt1 = tf->dmt1; + sf.sf_sc.sc_dmd1 = tf->dmd1; + sf.sf_sc.sc_dma1 = tf->dma1; + sf.sf_sc.sc_dmt2 = tf->dmt2; + sf.sf_sc.sc_dmd2 = tf->dmd2; + sf.sf_sc.sc_dma2 = tf->dma2; + sf.sf_sc.sc_fpecr = tf->fpecr; + sf.sf_sc.sc_fphs1 = tf->fphs1; + sf.sf_sc.sc_fpls1 = tf->fpls1; + sf.sf_sc.sc_fphs2 = tf->fphs2; + sf.sf_sc.sc_fpls2 = tf->fpls2; + sf.sf_sc.sc_fppt = tf->fppt; + sf.sf_sc.sc_fprh = tf->fprh; + sf.sf_sc.sc_fprl = tf->fprl; + sf.sf_sc.sc_fpit = tf->fpit; + if (copyout((caddr_t)&sf, (caddr_t)fp, sizeof sf)) { + /* + * Process has trashed its stack; give it an illegal + * instruction to halt it in its tracks. + */ + SIGACTION(p, SIGILL) = SIG_DFL; + sig = sigmask(SIGILL); + p->p_sigignore &= ~sig; + p->p_sigcatch &= ~sig; + p->p_sigmask &= ~sig; + psignal(p, SIGILL); + return; + } + /* + * Build the argument list for the signal handler. + * Signal trampoline code is at base of user stack. + */ + addr = (int)PS_STRINGS - szsigcode; + tf->snip = (addr & ~3) | NIP_V; + tf->sfip = (tf->snip + 4) | FIP_V; + tf->r[31] = (unsigned)fp; #ifdef DEBUG - if ((sigdebug & SDB_FOLLOW) || - (sigdebug & SDB_KSTACK) && p->p_pid == sigpid) - printf("sendsig(%d): sig %d returns\n", p->p_pid, sig); + if ((sigdebug & SDB_FOLLOW) || + (sigdebug & SDB_KSTACK) && p->p_pid == sigpid) + printf("sendsig(%d): sig %d returns\n", p->p_pid, sig); #endif } @@ -984,168 +997,168 @@ struct proc *p; void *v; register_t *retval; { - struct sys_sigreturn_args /* { - syscallarg(struct sigcontext *) sigcntxp; - } */ *uap = v; - register struct sigcontext *scp; - register struct trapframe *tf; - struct sigcontext ksc; - int error; - - scp = (struct sigcontext *)SCARG(uap, sigcntxp); + struct sys_sigreturn_args /* { + syscallarg(struct sigcontext *) sigcntxp; + } */ *uap = v; + register struct sigcontext *scp; + register struct trapframe *tf; + struct sigcontext ksc; + int error; + + scp = (struct sigcontext *)SCARG(uap, sigcntxp); #ifdef DEBUG - if (sigdebug & SDB_FOLLOW) - printf("sigreturn: pid %d, scp %x\n", p->p_pid, scp); + if (sigdebug & SDB_FOLLOW) + printf("sigreturn: pid %d, scp %x\n", p->p_pid, scp); #endif - if ((int)scp & 3 || useracc((caddr_t)scp, sizeof *scp, B_WRITE) == 0 || - copyin((caddr_t)scp, (caddr_t)&ksc, sizeof(struct sigcontext))) - return (EINVAL); - - tf = p->p_md.md_tf; - scp = &ksc; - /* - * xip, nip and fip must be multiples of 4. This is all - * that is required; if it holds, just do it. - */ + if ((int)scp & 3 || useracc((caddr_t)scp, sizeof *scp, B_WRITE) == 0 || + copyin((caddr_t)scp, (caddr_t)&ksc, sizeof(struct sigcontext))) + return (EINVAL); + + tf = p->p_md.md_tf; + scp = &ksc; + /* + * xip, nip and fip must be multiples of 4. This is all + * that is required; if it holds, just do it. + */ #if 0 - if (((scp->sc_xip | scp->sc_nip | scp->sc_fip) & 3) != 0) - return (EINVAL); + if (((scp->sc_xip | scp->sc_nip | scp->sc_fip) & 3) != 0) + return (EINVAL); #endif /* 0 */ - if (((scp->sc_xip | scp->sc_nip | scp->sc_fip) & 3) != 0) - printf("xip %x nip %x fip %x\n", - scp->sc_xip, scp->sc_nip, scp->sc_fip); - - /* - * this can be improved by doing - * bcopy(sc_reg to tf, sizeof sigcontext - 2 words) - * XXX nivas - */ - - bcopy((caddr_t)scp->sc_regs, (caddr_t)tf->r, sizeof(scp->sc_regs)); - tf->sxip = (scp->sc_xip) | XIP_V; - tf->snip = (scp->sc_nip) | NIP_V; - tf->sfip = (scp->sc_fip) | FIP_V; - tf->epsr = scp->sc_ps; - tf->r[31] = scp->sc_sp; - tf->fpsr = scp->sc_fpsr; - tf->fpcr = scp->sc_fpcr; - tf->ssbr = scp->sc_ssbr; - tf->dmt0 = scp->sc_dmt0; - tf->dmd0 = scp->sc_dmd0; - tf->dma0 = scp->sc_dma0; - tf->dmt1 = scp->sc_dmt1; - tf->dmd1 = scp->sc_dmd1; - tf->dma1 = scp->sc_dma1; - tf->dmt2 = scp->sc_dmt2; - tf->dmd2 = scp->sc_dmd2; - tf->dma2 = scp->sc_dma2; - tf->fpecr = scp->sc_fpecr; - tf->fphs1 = scp->sc_fphs1; - tf->fpls1 = scp->sc_fpls1; - tf->fphs2 = scp->sc_fphs2; - tf->fpls2 = scp->sc_fpls2; - tf->fppt = scp->sc_fppt; - tf->fprh = scp->sc_fprh; - tf->fprl = scp->sc_fprl; - tf->fpit = scp->sc_fpit; - - tf->epsr = scp->sc_ps; - /* - * Restore the user supplied information - */ - if (scp->sc_onstack & 01) - p->p_sigacts->ps_sigstk.ss_flags |= SA_ONSTACK; - else - p->p_sigacts->ps_sigstk.ss_flags &= ~SA_ONSTACK; - p->p_sigmask = scp->sc_mask & ~sigcantmask; - return (EJUSTRETURN); + if (((scp->sc_xip | scp->sc_nip | scp->sc_fip) & 3) != 0) + printf("xip %x nip %x fip %x\n", + scp->sc_xip, scp->sc_nip, scp->sc_fip); + + /* + * this can be improved by doing + * bcopy(sc_reg to tf, sizeof sigcontext - 2 words) + * XXX nivas + */ + + bcopy((caddr_t)scp->sc_regs, (caddr_t)tf->r, sizeof(scp->sc_regs)); + tf->sxip = (scp->sc_xip) | XIP_V; + tf->snip = (scp->sc_nip) | NIP_V; + tf->sfip = (scp->sc_fip) | FIP_V; + tf->epsr = scp->sc_ps; + tf->r[31] = scp->sc_sp; + tf->fpsr = scp->sc_fpsr; + tf->fpcr = scp->sc_fpcr; + tf->ssbr = scp->sc_ssbr; + tf->dmt0 = scp->sc_dmt0; + tf->dmd0 = scp->sc_dmd0; + tf->dma0 = scp->sc_dma0; + tf->dmt1 = scp->sc_dmt1; + tf->dmd1 = scp->sc_dmd1; + tf->dma1 = scp->sc_dma1; + tf->dmt2 = scp->sc_dmt2; + tf->dmd2 = scp->sc_dmd2; + tf->dma2 = scp->sc_dma2; + tf->fpecr = scp->sc_fpecr; + tf->fphs1 = scp->sc_fphs1; + tf->fpls1 = scp->sc_fpls1; + tf->fphs2 = scp->sc_fphs2; + tf->fpls2 = scp->sc_fpls2; + tf->fppt = scp->sc_fppt; + tf->fprh = scp->sc_fprh; + tf->fprl = scp->sc_fprl; + tf->fpit = scp->sc_fpit; + + tf->epsr = scp->sc_ps; + /* + * Restore the user supplied information + */ + if (scp->sc_onstack & 01) + p->p_sigacts->ps_sigstk.ss_flags |= SA_ONSTACK; + else + p->p_sigacts->ps_sigstk.ss_flags &= ~SA_ONSTACK; + p->p_sigmask = scp->sc_mask & ~sigcantmask; + return (EJUSTRETURN); } _doboot() { - cmmu_shutdown_now(); - bugreturn(); + cmmu_shutdown_now(); + bugreturn(); } void boot(howto) register int howto; { - /* take a snap shot before clobbering any registers */ - if (curproc) - savectx(curproc->p_addr, 0); - - boothowto = howto; - if ((howto & RB_NOSYNC) == 0 && waittime < 0) { - extern struct proc proc0; - - /* protect against curproc->p_stats.foo refs in sync() XXX */ - if (curproc == NULL) - curproc = &proc0; - - waittime = 0; - vfs_shutdown(); - - /* - * If we've been adjusting the clock, the todr - * will be out of synch; adjust it now. - */ - resettodr(); - } - splhigh(); /* extreme priority */ - if (howto & RB_HALT) { - printf("halted\n\n"); - bugreturn(); - } else { - if (howto & RB_DUMP) - dumpsys(); - doboot(); - /*NOTREACHED*/ - } - /*NOTREACHED*/ - while (1); /* to keep compiler happy, and me from going crazy */ + /* take a snap shot before clobbering any registers */ + if (curproc) + savectx(curproc->p_addr->u_pcb); + + boothowto = howto; + if ((howto & RB_NOSYNC) == 0 && waittime < 0) { + extern struct proc proc0; + + /* protect against curproc->p_stats.foo refs in sync() XXX */ + if (curproc == NULL) + curproc = &proc0; + + waittime = 0; + vfs_shutdown(); + + /* + * If we've been adjusting the clock, the todr + * will be out of synch; adjust it now. + */ + resettodr(); + } + splhigh(); /* extreme priority */ + if (howto & RB_HALT) { + printf("halted\n\n"); + bugreturn(); + } else { + if (howto & RB_DUMP) + dumpsys(); + doboot(); + /*NOTREACHED*/ + } + /*NOTREACHED*/ + while (1); /* to keep compiler happy, and me from going crazy */ } #ifdef MVME188 void m188_reset(void) { - volatile int cnt; - - *sys_syscon->ien0 = 0; - *sys_syscon->ien1 = 0; - *sys_syscon->ien2 = 0; - *sys_syscon->ien3 = 0; - *sys_syscon->glbres = 1; /* system reset */ - *sys_syscon->ucsr |= 0x2000; /* clear SYSFAIL* */ - for (cnt = 0; cnt < 5*1024*1024; cnt++) - ; - *sys_syscon->ucsr |= 0x2000; /* clear SYSFAIL* */ + volatile int cnt; + + *sys_syscon->ien0 = 0; + *sys_syscon->ien1 = 0; + *sys_syscon->ien2 = 0; + *sys_syscon->ien3 = 0; + *sys_syscon->glbres = 1; /* system reset */ + *sys_syscon->ucsr |= 0x2000; /* clear SYSFAIL* */ + for (cnt = 0; cnt < 5*1024*1024; cnt++) + ; + *sys_syscon->ucsr |= 0x2000; /* clear SYSFAIL* */ } #endif /* MVME188 */ -unsigned dumpmag = 0x8fca0101; /* magic number for savecore */ -int dumpsize = 0; /* also for savecore */ +unsigned dumpmag = 0x8fca0101; /* magic number for savecore */ +int dumpsize = 0; /* also for savecore */ long dumplo = 0; dumpconf() { - int nblks; - - dumpsize = physmem; - if (dumpdev != NODEV && bdevsw[major(dumpdev)].d_psize) { - nblks = (*bdevsw[major(dumpdev)].d_psize)(dumpdev); - if (dumpsize > btoc(dbtob(nblks - dumplo))) - dumpsize = btoc(dbtob(nblks - dumplo)); - else if (dumplo == 0) - dumplo = nblks - btodb(ctob(physmem)); - } - /* - * Don't dump on the first CLBYTES (why CLBYTES?) - * in case the dump device includes a disk label. - */ - if (dumplo < btodb(CLBYTES)) - dumplo = btodb(CLBYTES); + int nblks; + + dumpsize = physmem; + if (dumpdev != NODEV && bdevsw[major(dumpdev)].d_psize) { + nblks = (*bdevsw[major(dumpdev)].d_psize)(dumpdev); + if (dumpsize > btoc(dbtob(nblks - dumplo))) + dumpsize = btoc(dbtob(nblks - dumplo)); + else if (dumplo == 0) + dumplo = nblks - btodb(ctob(physmem)); + } + /* + * Don't dump on the first CLBYTES (why CLBYTES?) + * in case the dump device includes a disk label. + */ + if (dumplo < btodb(CLBYTES)) + dumplo = btodb(CLBYTES); } /* @@ -1155,43 +1168,39 @@ dumpconf() */ dumpsys() { - extern int msgbufmapped; - - msgbufmapped = 0; - if (dumpdev == NODEV) - return; - /* - * For dumps during autoconfiguration, - * if dump device has already configured... - */ - if (dumpsize == 0) - dumpconf(); - if (dumplo < 0) - return; - printf("\ndumping to dev %x, offset %d\n", dumpdev, dumplo); - printf("dump "); - switch ((*bdevsw[major(dumpdev)].d_dump)(dumpdev)) { - - case ENXIO: - printf("device bad\n"); - break; - - case EFAULT: - printf("device not ready\n"); - break; - - case EINVAL: - printf("area improper\n"); - break; - - case EIO: - printf("i/o error\n"); - break; - - default: - printf("succeeded\n"); - break; - } + extern int msgbufmapped; + + msgbufmapped = 0; + if (dumpdev == NODEV) + return; + /* + * For dumps during autoconfiguration, + * if dump device has already configured... + */ + if (dumpsize == 0) + dumpconf(); + if (dumplo < 0) + return; + printf("\ndumping to dev %x, offset %d\n", dumpdev, dumplo); + printf("dump "); + switch ((*bdevsw[major(dumpdev)].d_dump)(dumpdev)) { + + case ENXIO: + printf("device bad\n"); + break; + case EFAULT: + printf("device not ready\n"); + break; + case EINVAL: + printf("area improper\n"); + break; + case EIO: + printf("i/o error\n"); + break; + default: + printf("succeeded\n"); + break; + } } /* @@ -1200,76 +1209,84 @@ dumpsys() void setupiackvectors() { - register u_char *vaddr; + register u_char *vaddr; #undef MAP_VEC /* Swicthing to new virtual addresses XXX smurph */ #ifdef MAP_VEC - extern vm_offset_t iomap_mapin(vm_offset_t, vm_size_t, boolean_t); + extern vm_offset_t iomap_mapin(vm_offset_t, vm_size_t, boolean_t); #endif - /* - * map a page in for phys address 0xfffe0000 and set the - * addresses for various levels. - */ - switch (cputyp) { - case CPU_187: + /* + * map a page in for phys address 0xfffe0000 and set the + * addresses for various levels. + */ + switch (cputyp) { +#ifdef MVME187 + case CPU_187: #ifdef MAP_VEC /* do for MVME188 too */ - vaddr = (u_char *)iomap_mapin(M187_IACK, NBPG, 1); + vaddr = (u_char *)iomap_mapin(M187_IACK, NBPG, 1); #else - vaddr = (u_char *)M187_IACK; + vaddr = (u_char *)M187_IACK; #endif - break; - case CPU_188: + break; +#endif /* MVME187 */ +#ifdef MVME188 + case CPU_188: #ifdef MAP_VEC /* do for MVME188 too */ - vaddr = (u_char *)iomap_mapin(M188_IACK, NBPG, 1); + vaddr = (u_char *)iomap_mapin(M188_IACK, NBPG, 1); #else - vaddr = (u_char *)M188_IACK; + vaddr = (u_char *)M188_IACK; #endif - break; - case CPU_197: + break; +#endif /* MVME188 */ +#ifdef MVME197 + case CPU_197: #ifdef MAP_VEC /* do for MVME188 too */ - vaddr = (u_char *)iomap_mapin(M197_IACK, NBPG, 1); + vaddr = (u_char *)iomap_mapin(M197_IACK, NBPG, 1); #else - vaddr = (u_char *)M197_IACK; + vaddr = (u_char *)M197_IACK; #endif - break; - } + break; +#endif /* MVME197 */ + defualt: + panic("setupiackvectors: unknow cpu"); + } #ifdef DEBUG - printf("interrupt ACK address mapped at 0x%x\n", vaddr); + printf("interrupt ACK address mapped at 0x%x\n", vaddr); #endif - ivec[0] = vaddr + 0x03; - ivec[1] = vaddr + 0x07; - ivec[2] = vaddr + 0x0b; - ivec[3] = vaddr + 0x0f; - ivec[4] = vaddr + 0x13; - ivec[5] = vaddr + 0x17; - ivec[6] = vaddr + 0x1b; - ivec[7] = vaddr + 0x1f; + ivec[0] = vaddr + 0x03; + ivec[1] = vaddr + 0x07; + ivec[2] = vaddr + 0x0b; + ivec[3] = vaddr + 0x0f; + ivec[4] = vaddr + 0x13; + ivec[5] = vaddr + 0x17; + ivec[6] = vaddr + 0x1b; + ivec[7] = vaddr + 0x1f; } /* gets an interrupt stack for slave processors */ vm_offset_t get_slave_stack(void) { - vm_offset_t addr = 0; + vm_offset_t addr = 0; - addr = (vm_offset_t)kmem_alloc(kernel_map, INTSTACK_SIZE + 4096); + addr = (vm_offset_t)kmem_alloc(kernel_map, INTSTACK_SIZE + 4096); - if (addr == NULL) - panic("Cannot allocate slave stack"); + if (addr == NULL) + panic("Cannot allocate slave stack"); - if (interrupt_stack[0] == 0) - interrupt_stack[0] = (vm_offset_t) intstack; - interrupt_stack[cpu_number()] = addr; - return addr; + if (interrupt_stack[0] == 0) + interrupt_stack[0] = (vm_offset_t) intstack; + interrupt_stack[cpu_number()] = addr; + return addr; } /* dummy main routine for slave processors */ int slave_main(void) { - printf("slave CPU%d started\n", cpu_number()); - while (-1); /* spin forever */ - return 0; + printf("slave CPU%d started\n", cpu_number()); + while (-1); /* spin forever */ + return 0; } /* @@ -1284,15 +1301,15 @@ int intr_findvec(start, end) int start, end; { - register struct intrhand *intr; - int vec; - - if (start < 0 || end > 255 || start > end) - return (-1); - for (vec = end; vec > start; --vec) - if (intr_handlers[vec] == (struct intrhand *)0) - return (vec); - return (-1); + register struct intrhand *intr; + int vec; + + if (start < 0 || end > 255 || start > end) + return (-1); + for (vec = end; vec > start; --vec) + if (intr_handlers[vec] == (struct intrhand *)0) + return (vec); + return (-1); } /* @@ -1303,40 +1320,40 @@ int start, end; int intr_establish(int vec, struct intrhand *ihand) { - register struct intrhand *intr; - - if (vec < 0 || vec > 255) { - #if DIAGNOSTIC - panic("intr_establish: vec (%x) not between 0 and 0xff", - vec); - #endif /* DIAGNOSTIC */ - return (INTR_EST_BADVEC); - } - - if (intr = intr_handlers[vec]) { - if (intr->ih_ipl != ihand->ih_ipl) { - #if DIAGNOSTIC - panic("intr_establish: there are other handlers with vec (%x) at ipl %x, but you want it at %x", - intr->ih_ipl, vec, ihand->ih_ipl); - #endif /* DIAGNOSTIC */ - return (INTR_EST_BADIPL); - } - - /* - * Go to the end of the chain - */ - while (intr->ih_next) - intr = intr->ih_next; - } - - ihand->ih_next = 0; - - if (intr) - intr->ih_next = ihand; - else - intr_handlers[vec] = ihand; - - return (INTR_EST_SUCC); + register struct intrhand *intr; + + if (vec < 0 || vec > 255) { +#if DIAGNOSTIC + panic("intr_establish: vec (%x) not between 0 and 0xff", + vec); +#endif /* DIAGNOSTIC */ + return (INTR_EST_BADVEC); + } + + if (intr = intr_handlers[vec]) { + if (intr->ih_ipl != ihand->ih_ipl) { +#if DIAGNOSTIC + panic("intr_establish: there are other handlers with vec (%x) at ipl %x, but you want it at %x", + intr->ih_ipl, vec, ihand->ih_ipl); +#endif /* DIAGNOSTIC */ + return (INTR_EST_BADIPL); + } + + /* + * Go to the end of the chain + */ + while (intr->ih_next) + intr = intr->ih_next; + } + + ihand->ih_next = 0; + + if (intr) + intr->ih_next = ihand; + else + intr_handlers[vec] = ihand; + + return (INTR_EST_SUCC); } #ifdef MVME188 @@ -1352,168 +1369,168 @@ intr_establish(int vec, struct intrhand *ihand) /* Hard coded vector table for onboard devices. */ unsigned obio_vec[32] = {SYSCV_ABRT,SYSCV_ACF,0,SYSCV_TIMER1,0,0,0,0, - 0,0,SYSCV_TIMER2,SYSCV_SYSF,0,0,SYSCV_SCC,0, - 0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0, + 0,0,SYSCV_TIMER2,SYSCV_SYSF,0,0,SYSCV_SCC,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, }; #define GET_MASK(cpu, val) *int_mask_reg[cpu] & (val) void m188_ext_int(u_int v, struct m88100_saved_state *eframe) { - register int cpu = 0; /*cpu_number();*/ - register unsigned int cur_mask; - register unsigned int level, old_spl; - register struct intrhand *intr; - int ret, intnum; - unsigned vec; - - cur_mask = ISR_GET_CURRENT_MASK(cpu); - old_spl = m188_curspl[cpu]; - eframe->mask = old_spl; - - if (! cur_mask) { - /* - * Spurious interrupts - may be caused by debug output clearing - * DUART interrupts. - */ - flush_pipeline(); - return; - } - - /* We want to service all interrupts marked in the IST register */ - /* They are all valid because the mask would have prevented them */ - /* from being generated otherwise. We will service them in order of */ - /* priority. */ - do { - /* - printf("interrupt: mask = 0x%08x spl = %d imr = 0x%x\n", ISR_GET_CURRENT_MASK(cpu), - old_spl, *int_mask_reg[cpu]); - */ - level = safe_level(cur_mask, old_spl); - - if (old_spl >= level) { - register int i; - - printf("safe level %d <= old level %d\n", level, old_spl); - printf("cur_mask = 0x%b\n", cur_mask, IST_STRING); - for (i = 0; i < 4; i++) - printf("IEN%d = 0x%b ", i, *int_mask_reg[i], IST_STRING); - printf("\nCPU0 spl %d CPU1 spl %d CPU2 spl %d CPU3 spl %d\n", - m188_curspl[0], m188_curspl[1], - m188_curspl[2], m188_curspl[3]); - for (i = 0; i < 8; i++) - printf("int_mask[%d] = 0x%08x\n", i, int_mask_val[i]); - printf("--CPU %d halted--", cpu_number()); - spl7(); - while (1) - ; - } - - setipl((u_char)level); - - if (level > 7 || (char)level < 0) { - panic("int level (%x) is not between 0 and 7", level); - } - - /* generate IACK and get the vector */ - - /* - * This is tricky. If you don't catch all the - * interrupts, you die. Game over. Insert coin... - * XXX smurph - */ - - intnum = ff1(cur_mask); - if (intnum & OBIO_INTERRUPT_MASK) { - vec = obio_vec[intnum]; - if (vec = 0) { - printf("unknown onboard interrupt: mask = 0x%b\n", 1 << intnum, IST_STRING); - panic("m188_ext_int"); - } - } else if (intnum & HW_FAILURE_MASK) { - vec = obio_vec[intnum]; - if (vec = 0) { - printf("unknown hadware failure: mask = 0x%b\n", 1 << intnum, IST_STRING); - panic("m188_ext_int"); - } - } else if (intnum & VME_INTERRUPT_MASK) { - asm volatile("tb1 0, r0, 0"); - if (guarded_access(ivec[level], 1, &vec) == EFAULT) { - printf("Unable to get vector for this vmebus interrupt (level %x)\n", level); - goto out_m188; - } - } else { - printf("unknown interrupt: mask = 0x%b\n", 1 << intnum, IST_STRING); - panic("m188_ext_int"); - } + register int cpu = 0; /*cpu_number();*/ + register unsigned int cur_mask; + register unsigned int level, old_spl; + register struct intrhand *intr; + int ret, intnum; + unsigned vec; + + cur_mask = ISR_GET_CURRENT_MASK(cpu); + old_spl = m188_curspl[cpu]; + eframe->mask = old_spl; + + if (! cur_mask) { + /* + * Spurious interrupts - may be caused by debug output clearing + * DUART interrupts. + */ + flush_pipeline(); + return; + } + + /* We want to service all interrupts marked in the IST register */ + /* They are all valid because the mask would have prevented them */ + /* from being generated otherwise. We will service them in order of */ + /* priority. */ + do { + /* + printf("interrupt: mask = 0x%08x spl = %d imr = 0x%x\n", ISR_GET_CURRENT_MASK(cpu), + old_spl, *int_mask_reg[cpu]); + */ + level = safe_level(cur_mask, old_spl); + + if (old_spl >= level) { + register int i; + + printf("safe level %d <= old level %d\n", level, old_spl); + printf("cur_mask = 0x%b\n", cur_mask, IST_STRING); + for (i = 0; i < 4; i++) + printf("IEN%d = 0x%b ", i, *int_mask_reg[i], IST_STRING); + printf("\nCPU0 spl %d CPU1 spl %d CPU2 spl %d CPU3 spl %d\n", + m188_curspl[0], m188_curspl[1], + m188_curspl[2], m188_curspl[3]); + for (i = 0; i < 8; i++) + printf("int_mask[%d] = 0x%08x\n", i, int_mask_val[i]); + printf("--CPU %d halted--", cpu_number()); + spl7(); + while (1) + ; + } + + setipl((u_char)level); + + if (level > 7 || (char)level < 0) { + panic("int level (%x) is not between 0 and 7", level); + } + + /* generate IACK and get the vector */ + + /* + * This is tricky. If you don't catch all the + * interrupts, you die. Game over. Insert coin... + * XXX smurph + */ + + intnum = ff1(cur_mask); + if (intnum & OBIO_INTERRUPT_MASK) { + vec = obio_vec[intnum]; + if (vec = 0) { + printf("unknown onboard interrupt: mask = 0x%b\n", 1 << intnum, IST_STRING); + panic("m188_ext_int"); + } + } else if (intnum & HW_FAILURE_MASK) { + vec = obio_vec[intnum]; + if (vec = 0) { + printf("unknown hadware failure: mask = 0x%b\n", 1 << intnum, IST_STRING); + panic("m188_ext_int"); + } + } else if (intnum & VME_INTERRUPT_MASK) { + asm volatile("tb1 0, r0, 0"); + if (guarded_access(ivec[level], 1, &vec) == EFAULT) { + printf("Unable to get vector for this vmebus interrupt (level %x)\n", level); + goto out_m188; + } + } else { + printf("unknown interrupt: mask = 0x%b\n", 1 << intnum, IST_STRING); + panic("m188_ext_int"); + } #if 0 - if (cur_mask & ABRT_BIT) { /* abort button interrupt */ - vec = 110; - } else if (cur_mask & DTI_BIT) { /* interval timer interrupt */ - vec = SYSCV_TIMER1; - } else if (cur_mask & CIOI_BIT) { /* statistics timer interrupt */ - vec = SYSCV_TIMER2; - } else if (cur_mask & DI_BIT) { /* duart interrupt */ - vec = SYSCV_SCC; - } else { /* vmebus interrupt */ - asm volatile("tb1 0, r0, 0"); - if (guarded_access(ivec[level], 1, &vec) == EFAULT) { - printf("Unable to get vector for this vmebus interrupt (level %x)\n", level); - goto out_m188; - } - } + if (cur_mask & ABRT_BIT) { /* abort button interrupt */ + vec = 110; + } else if (cur_mask & DTI_BIT) { /* interval timer interrupt */ + vec = SYSCV_TIMER1; + } else if (cur_mask & CIOI_BIT) { /* statistics timer interrupt */ + vec = SYSCV_TIMER2; + } else if (cur_mask & DI_BIT) { /* duart interrupt */ + vec = SYSCV_SCC; + } else { /* vmebus interrupt */ + asm volatile("tb1 0, r0, 0"); + if (guarded_access(ivec[level], 1, &vec) == EFAULT) { + printf("Unable to get vector for this vmebus interrupt (level %x)\n", level); + goto out_m188; + } + } #endif - asm volatile("tb1 0, r0, 0"); - asm volatile("tb1 0, r0, 0"); - asm volatile("tb1 0, r0, 0"); - if (vec > 0xFF) { - panic("interrupt vector %x greater than 255", vec); - } + asm volatile("tb1 0, r0, 0"); + asm volatile("tb1 0, r0, 0"); + asm volatile("tb1 0, r0, 0"); + if (vec > 0xFF) { + panic("interrupt vector %x greater than 255", vec); + } #if 0 - enable_interrupt(); /* should we ?? */ + enable_interrupt(); /* should we ?? */ #endif - if ((intr = intr_handlers[vec]) == 0) - printf("Spurious interrupt (level %x and vec %x)\n", level, vec); - - /* - * Walk through all interrupt handlers in the chain for the - * given vector, calling each handler in turn, till some handler - * returns a value != 0. - */ - for (ret = 0; intr; intr = intr->ih_next) { - if (intr->ih_wantframe) - ret = (*intr->ih_fn)(intr->ih_arg, (void *)eframe); - else - ret = (*intr->ih_fn)(intr->ih_arg); - if (ret) - break; - } - if (ret == 0) - printf("Unclaimed interrupt (level %x and vec %x)\n", level, vec); - } while (cur_mask = ISR_GET_CURRENT_MASK(cpu)); - - - /* - * process any remaining data access exceptions before - * returning to assembler - */ - disable_interrupt(); -out_m188: - if (eframe->dmt0 & DMT_VALID) { - trap(T_DATAFLT, eframe); - data_access_emulation(eframe); - eframe->dmt0 &= ~DMT_VALID; - } - - /* - * Restore the mask level to what it was when the interrupt - * was taken. - */ - setipl((u_char)eframe->mask); - flush_pipeline(); - return; + if ((intr = intr_handlers[vec]) == 0) + printf("Spurious interrupt (level %x and vec %x)\n", level, vec); + + /* + * Walk through all interrupt handlers in the chain for the + * given vector, calling each handler in turn, till some handler + * returns a value != 0. + */ + for (ret = 0; intr; intr = intr->ih_next) { + if (intr->ih_wantframe) + ret = (*intr->ih_fn)(intr->ih_arg, (void *)eframe); + else + ret = (*intr->ih_fn)(intr->ih_arg); + if (ret) + break; + } + if (ret == 0) + printf("Unclaimed interrupt (level %x and vec %x)\n", level, vec); + } while (cur_mask = ISR_GET_CURRENT_MASK(cpu)); + + + /* + * process any remaining data access exceptions before + * returning to assembler + */ + disable_interrupt(); + out_m188: + if (eframe->dmt0 & DMT_VALID) { + trap(T_DATAFLT, eframe); + data_access_emulation(eframe); + eframe->dmt0 &= ~DMT_VALID; + } + + /* + * Restore the mask level to what it was when the interrupt + * was taken. + */ + setipl((u_char)eframe->mask); + flush_pipeline(); + return; } #endif /* MVME188 */ @@ -1531,116 +1548,116 @@ out_m188: void sbc_ext_int(u_int v, struct m88100_saved_state *eframe) { - register u_char mask, level, xxxvec; - register struct intrhand *intr; - int ret; - u_char vec; - - /* get level and mask */ - asm volatile("ld.b %0,%1" : "=r" (mask) : "" (*pcc2intr_mask)); - asm volatile("ld.b %0,%1" : "=r" (level) : "" (*pcc2intr_ipl)); - - /* - * It is really bizarre for the mask and level to the be the same. - * pcc2 for 187 blocks all interrupts at and below the mask value, - * so we should not be getting an interrupt at the level that is - * already blocked. I can't explain this case XXX nivas - */ - - if ((mask == level) && level) { - printf("mask == level, %d\n", level); - goto beatit; - } - - /* - * Interrupting level cannot be 0--0 doesn't produce an interrupt. - * Weird! XXX nivas - */ - - if (level == 0) { - printf("Bogons... level %x and mask %x\n", level, mask); - goto beatit; - } - - /* and block interrupts at level or lower */ - setipl((u_char)level); - /* and stash it away in the trap frame */ - eframe->mask = mask; - - if (level > 7 || (char)level < 0) { - panic("int level (%x) is not between 0 and 7", level); - } - - /* generate IACK and get the vector */ - asm volatile("tb1 0, r0, 0"); - if (guarded_access(ivec[level], 1, &vec) == EFAULT) { - printf("Unable to get vector for this interrupt (level %x)\n", level); - goto out; - } - asm volatile("tb1 0, r0, 0"); - asm volatile("tb1 0, r0, 0"); - asm volatile("tb1 0, r0, 0"); - /*vec = xxxvec;*/ - - if (vec > 0xFF) { - panic("interrupt vector %x greater than 255", vec); - } - - enable_interrupt(); - - if ((intr = intr_handlers[vec]) == 0) { - printf("Spurious interrupt (level %x and vec %x)\n", - level, vec); - } - if (intr && intr->ih_ipl != level) { - panic("Handler ipl %x not the same as level %x. vec = 0x%x", - intr->ih_ipl, level, vec); - } - - /* - * Walk through all interrupt handlers in the chain for the - * given vector, calling each handler in turn, till some handler - * returns a value != 0. - */ - - for (ret = 0; intr; intr = intr->ih_next) { - if (intr->ih_wantframe) - ret = (*intr->ih_fn)(intr->ih_arg, (void *)eframe); - else - ret = (*intr->ih_fn)(intr->ih_arg); - if (ret) - break; - } - - if (ret == 0) { - printf("Unclaimed interrupt (level %x and vec %x)\n", - level, vec); - } - - /* - * process any remaining data access exceptions before - * returning to assembler - */ - disable_interrupt(); - -out: - if (cputyp != CPU_197) { - if (eframe->dmt0 & DMT_VALID) { - trap(T_DATAFLT, eframe); - data_access_emulation(eframe); - eframe->dmt0 &= ~DMT_VALID; - } - } - mask = eframe->mask; - - /* - * Restore the mask level to what it was when the interrupt - * was taken. - */ - setipl((u_char)mask); - -beatit: - return; + register u_char mask, level, xxxvec; + register struct intrhand *intr; + int ret; + u_char vec; + + /* get level and mask */ + asm volatile("ld.b %0,%1" : "=r" (mask) : "" (*pcc2intr_mask)); + asm volatile("ld.b %0,%1" : "=r" (level) : "" (*pcc2intr_ipl)); + + /* + * It is really bizarre for the mask and level to the be the same. + * pcc2 for 187 blocks all interrupts at and below the mask value, + * so we should not be getting an interrupt at the level that is + * already blocked. I can't explain this case XXX nivas + */ + + if ((mask == level) && level) { + printf("mask == level, %d\n", level); + goto beatit; + } + + /* + * Interrupting level cannot be 0--0 doesn't produce an interrupt. + * Weird! XXX nivas + */ + + if (level == 0) { + printf("Bogons... level %x and mask %x\n", level, mask); + goto beatit; + } + + /* and block interrupts at level or lower */ + setipl((u_char)level); + /* and stash it away in the trap frame */ + eframe->mask = mask; + + if (level > 7 || (char)level < 0) { + panic("int level (%x) is not between 0 and 7", level); + } + + /* generate IACK and get the vector */ + asm volatile("tb1 0, r0, 0"); + if (guarded_access(ivec[level], 1, &vec) == EFAULT) { + printf("Unable to get vector for this interrupt (level %x)\n", level); + goto out; + } + asm volatile("tb1 0, r0, 0"); + asm volatile("tb1 0, r0, 0"); + asm volatile("tb1 0, r0, 0"); + /*vec = xxxvec;*/ + + if (vec > 0xFF) { + panic("interrupt vector %x greater than 255", vec); + } + + enable_interrupt(); + + if ((intr = intr_handlers[vec]) == 0) { + printf("Spurious interrupt (level %x and vec %x)\n", + level, vec); + } + if (intr && intr->ih_ipl != level) { + panic("Handler ipl %x not the same as level %x. vec = 0x%x", + intr->ih_ipl, level, vec); + } + + /* + * Walk through all interrupt handlers in the chain for the + * given vector, calling each handler in turn, till some handler + * returns a value != 0. + */ + + for (ret = 0; intr; intr = intr->ih_next) { + if (intr->ih_wantframe) + ret = (*intr->ih_fn)(intr->ih_arg, (void *)eframe); + else + ret = (*intr->ih_fn)(intr->ih_arg); + if (ret) + break; + } + + if (ret == 0) { + printf("Unclaimed interrupt (level %x and vec %x)\n", + level, vec); + } + + /* + * process any remaining data access exceptions before + * returning to assembler + */ + disable_interrupt(); + + out: + if (cputyp != CPU_197) { + if (eframe->dmt0 & DMT_VALID) { + trap(T_DATAFLT, eframe); + data_access_emulation(eframe); + eframe->dmt0 &= ~DMT_VALID; + } + } + mask = eframe->mask; + + /* + * Restore the mask level to what it was when the interrupt + * was taken. + */ + setipl((u_char)mask); + + beatit: + return; } #endif /* defined(MVME187) || defined(MVME197) */ @@ -1648,7 +1665,7 @@ cpu_exec_aout_makecmds(p, epp) struct proc *p; struct exec_package *epp; { - return ENOEXEC; + return ENOEXEC; } sys_sysarch(p, v, retval) @@ -1656,18 +1673,18 @@ struct proc *p; void *v; register_t *retval; { - struct sys_sysarch_args /* { - syscallarg(int) op; - syscallarg(char *) parm; - } */ *uap = v; - int error = 0; - - switch ((int)SCARG(uap, op)) { - default: - error = EINVAL; - break; - } - return (error); + struct sys_sysarch_args /* { + syscallarg(int) op; + syscallarg(char *) parm; + } */ *uap = v; + int error = 0; + + switch ((int)SCARG(uap, op)) { + default: + error = EINVAL; + break; + } + return (error); } /* @@ -1684,15 +1701,15 @@ size_t newlen; struct proc *p; { - /* all sysctl names are this level are terminal */ - if (namelen != 1) - return (ENOTDIR); /* overloaded */ + /* all sysctl names are this level are terminal */ + if (namelen != 1) + return (ENOTDIR); /* overloaded */ - switch (name[0]) { - default: - return (EOPNOTSUPP); - } - /*NOTREACHED*/ + switch (name[0]) { + default: + return (EOPNOTSUPP); + } + /*NOTREACHED*/ } /* @@ -1703,13 +1720,13 @@ void _insque(velement, vhead) void *velement, *vhead; { - register struct prochd *element, *head; - element = velement; - head = vhead; - element->ph_link = head->ph_link; - head->ph_link = (struct proc *)element; - element->ph_rlink = (struct proc *)head; - ((struct prochd *)(element->ph_link))->ph_rlink=(struct proc *)element; + register struct prochd *element, *head; + element = velement; + head = vhead; + element->ph_link = head->ph_link; + head->ph_link = (struct proc *)element; + element->ph_rlink = (struct proc *)head; + ((struct prochd *)(element->ph_link))->ph_rlink=(struct proc *)element; } /* @@ -1720,11 +1737,11 @@ void _remque(velement) void *velement; { - register struct prochd *element; - element = velement; - ((struct prochd *)(element->ph_link))->ph_rlink = element->ph_rlink; - ((struct prochd *)(element->ph_rlink))->ph_link = element->ph_link; - element->ph_rlink = (struct proc *)0; + register struct prochd *element; + element = velement; + ((struct prochd *)(element->ph_link))->ph_rlink = element->ph_rlink; + ((struct prochd *)(element->ph_rlink))->ph_link = element->ph_link; + element->ph_rlink = (struct proc *)0; } int @@ -1734,41 +1751,41 @@ void *toaddr; size_t maxlength; size_t *lencopied; { - u_int tally; + u_int tally; - tally = 0; + tally = 0; - while (maxlength--) { - *(u_char *)toaddr = *(u_char *)fromaddr++; - tally++; - if (*(u_char *)toaddr++ == 0) { - if (lencopied) *lencopied = tally; - return (0); - } - } + while (maxlength--) { + *(u_char *)toaddr = *(u_char *)fromaddr++; + tally++; + if (*(u_char *)toaddr++ == 0) { + if (lencopied) *lencopied = tally; + return (0); + } + } - if (lencopied) - *lencopied = tally; + if (lencopied) + *lencopied = tally; - return (ENAMETOOLONG); + return (ENAMETOOLONG); } void setrunqueue(p) register struct proc *p; { - register struct prochd *q; - register struct proc *oldlast; - register int which = p->p_priority >> 2; - - if (p->p_back != NULL) - panic("setrunqueue %x", p); - q = &qs[which]; - whichqs |= 1 << which; - p->p_forw = (struct proc *)q; - p->p_back = oldlast = q->ph_rlink; - q->ph_rlink = p; - oldlast->p_forw = p; + register struct prochd *q; + register struct proc *oldlast; + register int which = p->p_priority >> 2; + + if (p->p_back != NULL) + panic("setrunqueue %x", p); + q = &qs[which]; + whichqs |= 1 << which; + p->p_forw = (struct proc *)q; + p->p_back = oldlast = q->ph_rlink; + q->ph_rlink = p; + oldlast->p_forw = p; } /* @@ -1779,18 +1796,18 @@ void remrunqueue(vp) struct proc *vp; { - register struct proc *p = vp; - register int which = p->p_priority >> 2; - register struct prochd *q; - - if ((whichqs & (1 << which)) == 0) - panic("remrq %x", p); - p->p_forw->p_back = p->p_back; - p->p_back->p_forw = p->p_forw; - p->p_back = NULL; - q = &qs[which]; - if (q->ph_link == (struct proc *)q) - whichqs &= ~(1 << which); + register struct proc *p = vp; + register int which = p->p_priority >> 2; + register struct prochd *q; + + if ((whichqs & (1 << which)) == 0) + panic("remrq %x", p); + p->p_forw->p_back = p->p_back; + p->p_back->p_forw = p->p_forw; + p->p_back = NULL; + q = &qs[which]; + if (q->ph_link == (struct proc *)q) + whichqs &= ~(1 << which); } /* dummys for now */ @@ -1803,107 +1820,107 @@ void myetheraddr(cp) u_char *cp; { - struct bugniocall niocall; - struct bugbrdid brdid; - bugbrdid(&brdid); - bcopy(&brdid.etheraddr, cp, 6); + struct bugniocall niocall; + struct bugbrdid brdid; + bugbrdid(&brdid); + bcopy(&brdid.etheraddr, cp, 6); } void netintr() { #ifdef INET - if (netisr & (1 << NETISR_ARP)) { - netisr &= ~(1 << NETISR_ARP); - arpintr(); - } - if (netisr & (1 << NETISR_IP)) { - netisr &= ~(1 << NETISR_IP); - ipintr(); - } + if (netisr & (1 << NETISR_ARP)) { + netisr &= ~(1 << NETISR_ARP); + arpintr(); + } + if (netisr & (1 << NETISR_IP)) { + netisr &= ~(1 << NETISR_IP); + ipintr(); + } #endif #ifdef INET6 - if (netisr & (1 << NETISR_IPV6)) { - netisr &= ~(1 << NETISR_IPV6); - ip6intr(); - } + if (netisr & (1 << NETISR_IPV6)) { + netisr &= ~(1 << NETISR_IPV6); + ip6intr(); + } #endif #ifdef NETATALK - if (netisr & (1 << NETISR_ATALK)) { - netisr &= ~(1 << NETISR_ATALK); - atintr(); - } + if (netisr & (1 << NETISR_ATALK)) { + netisr &= ~(1 << NETISR_ATALK); + atintr(); + } #endif #ifdef NS - if (netisr & (1 << NETISR_NS)) { - netisr &= ~(1 << NETISR_NS); - nsintr(); - } + if (netisr & (1 << NETISR_NS)) { + netisr &= ~(1 << NETISR_NS); + nsintr(); + } #endif #ifdef ISO - if (netisr & (1 << NETISR_ISO)) { - netisr &= ~(1 << NETISR_ISO); - clnlintr(); - } + if (netisr & (1 << NETISR_ISO)) { + netisr &= ~(1 << NETISR_ISO); + clnlintr(); + } #endif #ifdef CCITT - if (netisr & (1 << NETISR_CCITT)) { - netisr &= ~(1 << NETISR_CCITT); - ccittintr(); - } + if (netisr & (1 << NETISR_CCITT)) { + netisr &= ~(1 << NETISR_CCITT); + ccittintr(); + } #endif #include "ppp.h" #if NPPP > 0 - if (netisr & (1 << NETISR_PPP)) { - netisr &= ~(1 << NETISR_PPP); - pppintr(); - } + if (netisr & (1 << NETISR_PPP)) { + netisr &= ~(1 << NETISR_PPP); + pppintr(); + } #endif #include "bridge.h" #if NBRIDGE > 0 - if (netisr & (1 << NETISR_BRIDGE)) { - netisr &= ~(1 << NETISR_BRIDGE); - bridgeintr(); - } + if (netisr & (1 << NETISR_BRIDGE)) { + netisr &= ~(1 << NETISR_BRIDGE); + bridgeintr(); + } #endif } void dosoftint() { - if (ssir & SIR_NET) { - siroff(SIR_NET); - cnt.v_soft++; - netintr(); - } - - if (ssir & SIR_CLOCK) { - siroff(SIR_CLOCK); - cnt.v_soft++; - softclock(); - } - - return; + if (ssir & SIR_NET) { + siroff(SIR_NET); + cnt.v_soft++; + netintr(); + } + + if (ssir & SIR_CLOCK) { + siroff(SIR_CLOCK); + cnt.v_soft++; + softclock(); + } + + return; } int spl0() { - int x; - int level = 0; - x = splsoftclock(); + int x; + int level = 0; + x = splsoftclock(); - if (ssir) { - dosoftint(); - } + if (ssir) { + dosoftint(); + } - setipl(0); + setipl(0); - return (x); + return (x); } badwordaddr(void *addr) { - return badaddr((vm_offset_t)addr, 4); + return badaddr((vm_offset_t)addr, 4); } MY_info(f, p, flags, s) @@ -1912,118 +1929,124 @@ caddr_t p; int flags; char *s; { - regdump(f); - printf("proc %x flags %x type %s\n", p, flags, s); + regdump(f); + printf("proc %x flags %x type %s\n", p, flags, s); } MY_info_done(f, flags) struct trapframe *f; int flags; { - regdump(f); + regdump(f); } void nmihand(void *framep) { - struct m88100_saved_state *frame = framep; + struct m88100_saved_state *frame = framep; #if DDB - DEBUG_MSG("Abort Pressed\n"); - Debugger(); + DEBUG_MSG("Abort Pressed\n"); + Debugger(); #else - DEBUG_MSG("Spurious NMI?\n"); + DEBUG_MSG("Spurious NMI?\n"); #endif /* DDB */ } regdump(struct trapframe *f) { #define R(i) f->r[i] - printf("R00-05: 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n", - R(0),R(1),R(2),R(3),R(4),R(5)); - printf("R06-11: 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n", - R(6),R(7),R(8),R(9),R(10),R(11)); - printf("R12-17: 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n", - R(12),R(13),R(14),R(15),R(16),R(17)); - printf("R18-23: 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n", - R(18),R(19),R(20),R(21),R(22),R(23)); - printf("R24-29: 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n", - R(24),R(25),R(26),R(27),R(28),R(29)); - printf("R30-31: 0x%08x 0x%08x\n",R(30),R(31)); - if (cputyp == CPU_197) { - printf("exip %x enip %x\n", f->sxip, f->snip); - } else { - printf("sxip %x snip %x sfip %x\n", f->sxip, f->snip, f->sfip); - } - if (f->vector == 0x3 && cputyp != CPU_197) { - /* print dmt stuff for data access fault */ - printf("dmt0 %x dmd0 %x dma0 %x\n", f->dmt0, f->dmd0, f->dma0); - printf("dmt1 %x dmd1 %x dma1 %x\n", f->dmt1, f->dmd1, f->dma1); - printf("dmt2 %x dmd2 %x dma2 %x\n", f->dmt2, f->dmd2, f->dma2); - printf("fault type %d\n", (f->dpfsr >> 16) & 0x7); - dae_print(f); - } - if (longformat && cputyp != CPU_197) { - printf("fpsr %x ", f->fpsr); - printf("fpcr %x ", f->fpcr); - printf("epsr %x ", f->epsr); - printf("ssbr %x\n", f->ssbr); - printf("fpecr %x ", f->fpecr); - printf("fphs1 %x ", f->fphs1); - printf("fpls1 %x ", f->fpls1); - printf("fphs2 %x ", f->fphs2); - printf("fpls2 %x\n", f->fpls2); - printf("fppt %x ", f->fppt); - printf("fprh %x ", f->fprh); - printf("fprl %x ", f->fprl); - printf("fpit %x\n", f->fpit); - printf("vector %x ", f->vector); - printf("mask %x ", f->mask); - printf("mode %x ", f->mode); - printf("scratch1 %x ", f->scratch1); - printf("pad %x\n", f->pad); - } - if (longformat && cputyp == CPU_197) { - printf("fpsr %x ", f->fpsr); - printf("fpcr %x ", f->fpcr); - printf("fpecr %x ", f->fpecr); - printf("epsr %x\n", f->epsr); - printf("dsap %x ", f->dmt1); - printf("dsr %x ", f->dsr); - printf("dlar %x ", f->dlar); - printf("dpar %x\n", f->dpar); - printf("isap %x ", f->dmt0); - printf("isr %x ", f->isr); - printf("ilar %x ", f->ilar); - printf("ipar %x\n", f->ipar); - printf("vector %x ", f->vector); - printf("mask %x ", f->mask); - printf("mode %x ", f->mode); - printf("scratch1 %x ", f->scratch1); - printf("pad %x\n", f->pad); - } - if (cputyp == CPU_188 ) { - unsigned int istr, cur_mask; - - istr = *(volatile int *)IST_REG; - cur_mask = GET_MASK(0, istr); - printf("emask = 0x%b\n", f->mask, IST_STRING); - printf("istr = 0x%b\n", istr, IST_STRING); - printf("cmask = 0x%b\n", cur_mask, IST_STRING); - } + printf("R00-05: 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n", + R(0),R(1),R(2),R(3),R(4),R(5)); + printf("R06-11: 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n", + R(6),R(7),R(8),R(9),R(10),R(11)); + printf("R12-17: 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n", + R(12),R(13),R(14),R(15),R(16),R(17)); + printf("R18-23: 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n", + R(18),R(19),R(20),R(21),R(22),R(23)); + printf("R24-29: 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n", + R(24),R(25),R(26),R(27),R(28),R(29)); + printf("R30-31: 0x%08x 0x%08x\n",R(30),R(31)); + if (cputyp == CPU_197) { + printf("exip %x enip %x\n", f->sxip, f->snip); + } else { + printf("sxip %x snip %x sfip %x\n", f->sxip, f->snip, f->sfip); + } +#if defined(MVME187) || defined(MVME188) + if (f->vector == 0x3 && cputyp != CPU_197) { + /* print dmt stuff for data access fault */ + printf("dmt0 %x dmd0 %x dma0 %x\n", f->dmt0, f->dmd0, f->dma0); + printf("dmt1 %x dmd1 %x dma1 %x\n", f->dmt1, f->dmd1, f->dma1); + printf("dmt2 %x dmd2 %x dma2 %x\n", f->dmt2, f->dmd2, f->dma2); + printf("fault type %d\n", (f->dpfsr >> 16) & 0x7); + dae_print(f); + } + if (longformat && cputyp != CPU_197) { + printf("fpsr %x ", f->fpsr); + printf("fpcr %x ", f->fpcr); + printf("epsr %x ", f->epsr); + printf("ssbr %x\n", f->ssbr); + printf("fpecr %x ", f->fpecr); + printf("fphs1 %x ", f->fphs1); + printf("fpls1 %x ", f->fpls1); + printf("fphs2 %x ", f->fphs2); + printf("fpls2 %x\n", f->fpls2); + printf("fppt %x ", f->fppt); + printf("fprh %x ", f->fprh); + printf("fprl %x ", f->fprl); + printf("fpit %x\n", f->fpit); + printf("vector %x ", f->vector); + printf("mask %x ", f->mask); + printf("mode %x ", f->mode); + printf("scratch1 %x ", f->scratch1); + printf("pad %x\n", f->pad); + } +#endif +#ifdef MVME197 + if (longformat && cputyp == CPU_197) { + printf("fpsr %x ", f->fpsr); + printf("fpcr %x ", f->fpcr); + printf("fpecr %x ", f->fpecr); + printf("epsr %x\n", f->epsr); + printf("dsap %x ", f->dmt1); + printf("dsr %x ", f->dsr); + printf("dlar %x ", f->dlar); + printf("dpar %x\n", f->dpar); + printf("isap %x ", f->dmt0); + printf("isr %x ", f->isr); + printf("ilar %x ", f->ilar); + printf("ipar %x\n", f->ipar); + printf("vector %x ", f->vector); + printf("mask %x ", f->mask); + printf("mode %x ", f->mode); + printf("scratch1 %x ", f->scratch1); + printf("pad %x\n", f->pad); + } +#endif +#ifdef MVME188 + if (cputyp == CPU_188 ) { + unsigned int istr, cur_mask; + + istr = *(volatile int *)IST_REG; + cur_mask = GET_MASK(0, istr); + printf("emask = 0x%b\n", f->mask, IST_STRING); + printf("istr = 0x%b\n", istr, IST_STRING); + printf("cmask = 0x%b\n", cur_mask, IST_STRING); + } +#endif } #if DDB inline int db_splhigh(void) { - return (db_setipl(IPL_HIGH)); + return (db_setipl(IPL_HIGH)); } inline int db_splx(int s) { - return (db_setipl(s)); + return (db_setipl(s)); } #endif /* DDB */ @@ -2037,124 +2060,124 @@ db_splx(int s) void mvme_bootstrap(void) { - extern char *edata, *end; - extern int cold; - extern unsigned number_cpus; - extern int kernelstart; - extern int lock_wait_time; - extern vm_offset_t size_memory(void); - extern struct consdev *cn_tab; - extern unsigned vector_list; - struct bugbrdid brdid; - - cold = 1; /* we are still booting */ - - /* zreo out the machine dependant function pointers */ - bzero(&mdfp, sizeof(struct funcp)); - - buginit(); /* init the bug routines */ - bugbrdid(&brdid); - cputyp = brdid.brdno; - - /* to support the M8120. It's based off of MVME187 */ - if (cputyp == 0x8120) - cputyp = CPU_187; - - /* - * set up interrupt and fp exception handlers - * based on the machine. - */ - switch (cputyp) { + extern char *edata, *end; + extern int cold; + extern unsigned number_cpus; + extern int kernelstart; + extern int lock_wait_time; + extern vm_offset_t size_memory(void); + extern struct consdev *cn_tab; + extern unsigned vector_list; + struct bugbrdid brdid; + + cold = 1; /* we are still booting */ + + /* zreo out the machine dependant function pointers */ + bzero(&mdfp, sizeof(struct funcp)); + + buginit(); /* init the bug routines */ + bugbrdid(&brdid); + cputyp = brdid.brdno; + + /* to support the M8120. It's based off of MVME187 */ + if (cputyp == 0x8120) + cputyp = CPU_187; + + /* + * set up interrupt and fp exception handlers + * based on the machine. + */ + switch (cputyp) { #ifdef MVME188 - case CPU_188: - mdfp.interrupt_func = &m188_ext_int; - mdfp.fp_precise_func = &m88100_Xfp_precise; - /* clear and disable all interrupts */ - *int_mask_reg[0] = 0; - *int_mask_reg[1] = 0; - *int_mask_reg[2] = 0; - *int_mask_reg[3] = 0; - break; + case CPU_188: + mdfp.interrupt_func = &m188_ext_int; + mdfp.fp_precise_func = &m88100_Xfp_precise; + /* clear and disable all interrupts */ + *int_mask_reg[0] = 0; + *int_mask_reg[1] = 0; + *int_mask_reg[2] = 0; + *int_mask_reg[3] = 0; + break; #endif /* MVME188 */ #ifdef MVME187 - case CPU_187: - mdfp.interrupt_func = &sbc_ext_int; - mdfp.fp_precise_func = &m88100_Xfp_precise; - break; + case CPU_187: + mdfp.interrupt_func = &sbc_ext_int; + mdfp.fp_precise_func = &m88100_Xfp_precise; + break; #endif /* MVME187 */ #ifdef MVME197 - case CPU_197: - mdfp.interrupt_func = &sbc_ext_int; - mdfp.fp_precise_func = &m88110_Xfp_precise; - set_tcfp(); /* Set Time Critical Floating Point Mode */ - break; + case CPU_197: + mdfp.interrupt_func = &sbc_ext_int; + mdfp.fp_precise_func = &m88110_Xfp_precise; + set_tcfp(); /* Set Time Critical Floating Point Mode */ + break; #endif /* MVME197 */ - default: - panic("mvme_bootstrap: Can't determine cpu type."); - } + default: + panic("mvme_bootstrap: Can't determine cpu type."); + } - /* startup fake console driver. It will be replaced by consinit() */ - cn_tab = &bootcons; + /* startup fake console driver. It will be replaced by consinit() */ + cn_tab = &bootcons; - vm_set_page_size(); + vm_set_page_size(); - first_addr = m88k_round_page(first_addr); + first_addr = m88k_round_page(first_addr); - if (!no_symbols) boothowto |= RB_KDB; + if (!no_symbols) boothowto |= RB_KDB; - last_addr = size_memory(); - cmmu_parity_enable(); + last_addr = size_memory(); + cmmu_parity_enable(); + + printf("%s",version); + identifycpu(); + setup_board_config(); + cmmu_init(); + master_cpu = cmmu_cpu_number(); + set_cpu_number(master_cpu); + printf("CPU%d is master CPU\n", master_cpu); - printf("%s",version); - identifycpu(); - setup_board_config(); - cmmu_init(); - master_cpu = cmmu_cpu_number(); - set_cpu_number(master_cpu); - printf("CPU%d is master CPU\n", master_cpu); - #ifdef notevenclose - if (cputyp == CPU_188 && (boothowto & RB_MINIROOT)) { - int i; - for (i=0; i<MAX_CPUS; i++) { - if(!spin_cpu(i)) - printf("CPU%d started\n", i); - } - } + if (cputyp == CPU_188 && (boothowto & RB_MINIROOT)) { + int i; + for (i=0; i<MAX_CPUS; i++) { + if (!spin_cpu(i)) + printf("CPU%d started\n", i); + } + } #endif - avail_start = first_addr; - avail_end = last_addr; + avail_start = first_addr; + avail_end = last_addr; #ifdef DEBUG - printf("MVME%x boot: memory from 0x%x to 0x%x\n", cputyp, avail_start, avail_end); + printf("MVME%x boot: memory from 0x%x to 0x%x\n", cputyp, avail_start, avail_end); #endif - /* - * Steal one page at the top of physical memory for msgbuf - */ - avail_end -= PAGE_SIZE; - pmap_bootstrap((vm_offset_t)M88K_TRUNC_PAGE((unsigned)&kernelstart) /* = loadpt */, - &avail_start, &avail_end, &virtual_avail, - &virtual_end); - - /* - * Must initialize p_addr before autoconfig or - * the fault handler will get a NULL reference. - */ - proc0.p_addr = proc0paddr; - curproc = &proc0; - curpcb = &proc0paddr->u_pcb; - - /* Initialize cached PTEs for u-area mapping. */ - save_u_area(&proc0, (vm_offset_t)proc0paddr); - - /* - * Map proc0's u-area at the standard address (UADDR). - */ - load_u_area(&proc0); - - /* Initialize the "u-area" pages. */ - bzero((caddr_t)UADDR, UPAGES*NBPG); + /* + * Steal one page at the top of physical memory for msgbuf + */ + avail_end -= PAGE_SIZE; + pmap_bootstrap((vm_offset_t)M88K_TRUNC_PAGE((unsigned)&kernelstart) /* = loadpt */, + &avail_start, &avail_end, &virtual_avail, + &virtual_end); + + /* + * Must initialize p_addr before autoconfig or + * the fault handler will get a NULL reference. + */ + proc0.p_addr = proc0paddr; + curproc = &proc0; + curpcb = &proc0paddr->u_pcb; + + /* Initialize cached PTEs for u-area mapping. */ + save_u_area(&proc0, (vm_offset_t)proc0paddr); + + /* + * Map proc0's u-area at the standard address (UADDR). + */ + load_u_area(&proc0); + + /* Initialize the "u-area" pages. */ + bzero((caddr_t)UADDR, UPAGES*NBPG); #ifdef DEBUG - printf("leaving mvme_bootstrap()\n"); + printf("leaving mvme_bootstrap()\n"); #endif } @@ -2166,23 +2189,23 @@ int bootcnprobe(cp) struct consdev *cp; { - cp->cn_dev = makedev(14, 0); - cp->cn_pri = CN_NORMAL; - return (1); + cp->cn_dev = makedev(14, 0); + cp->cn_pri = CN_NORMAL; + return (1); } int bootcninit(cp) struct consdev *cp; { - /* Nothing to do */ + /* Nothing to do */ } int bootcngetc(dev) dev_t dev; { - return (buginchr()); + return (buginchr()); } void @@ -2190,9 +2213,8 @@ bootcnputc(dev, c) dev_t dev; char c; { - int s; - - if (c == '\n') - bugoutchr('\r'); - bugoutchr(c); + int s; + if (c == '\n') + bugoutchr('\r'); + bugoutchr(c); } diff --git a/sys/arch/mvme88k/mvme88k/pmap.c b/sys/arch/mvme88k/mvme88k/pmap.c index 837ed9cd4f9..67acb97c46d 100644 --- a/sys/arch/mvme88k/mvme88k/pmap.c +++ b/sys/arch/mvme88k/mvme88k/pmap.c @@ -1,4 +1,4 @@ -/* $OpenBSD: pmap.c,v 1.14 2000/12/21 16:54:56 aaron Exp $ */ +/* $OpenBSD: pmap.c,v 1.15 2000/12/28 21:21:24 smurph Exp $ */ /* * Copyright (c) 1996 Nivas Madhur * All rights reserved. @@ -733,6 +733,7 @@ pmap_map(vm_offset_t virt, vm_offset_t start, vm_offset_t end, vm_prot_t prot) #endif *pte = template.pte; +#ifdef MVME197 /* hack for MVME197 */ if (cputyp == CPU_197) { if (i < 32) { @@ -740,7 +741,7 @@ pmap_map(vm_offset_t virt, vm_offset_t start, vm_offset_t end, vm_prot_t prot) i++; } } - +#endif virt += M88K_PGBYTES; template.bits += M88K_PGBYTES; } diff --git a/sys/arch/mvme88k/mvme88k/vm_machdep.c b/sys/arch/mvme88k/mvme88k/vm_machdep.c index f7d4ab78564..41cc589a8cd 100644 --- a/sys/arch/mvme88k/mvme88k/vm_machdep.c +++ b/sys/arch/mvme88k/mvme88k/vm_machdep.c @@ -1,4 +1,4 @@ -/* $OpenBSD: vm_machdep.c,v 1.14 2000/06/08 22:25:21 niklas Exp $ */ +/* $OpenBSD: vm_machdep.c,v 1.15 2000/12/28 21:21:25 smurph Exp $ */ /* * Copyright (c) 1998 Steve Murphree, Jr. @@ -75,28 +75,28 @@ extern vm_map_t iomap_map; * address in each process; in the future we will probably relocate * the frame pointers on the stack after copying. */ -#undef pcb_sp -#ifdef __FORK_BRAINDAMAGE -int -#else void -#endif cpu_fork(struct proc *p1, struct proc *p2, void *stack, size_t stacksize) { struct switchframe *p2sf; int off, ssz; - int cpu; + int cpu; struct ksigframe { void (*func)(struct proc *); void *proc; } *ksfp; + extern struct pcb *curpcb; extern void proc_do_uret(), child_return(); extern void proc_trampoline(); cpu = cpu_number(); - savectx(p1->p_addr); - +/* + savectx(p1->p_addr->u_pcb); +*/ + savectx(curpcb); + + /* copy p1 pcb to p2 */ bcopy((void *)&p1->p_addr->u_pcb, (void *)&p2->p_addr->u_pcb, sizeof(struct pcb)); p2->p_addr->u_pcb.kernel_state.pcb_ipl = 0; @@ -139,11 +139,7 @@ cpu_fork(struct proc *p1, struct proc *p2, void *stack, size_t stacksize) p2->p_addr->u_pcb.kernel_state.pcb_sp = (u_int)ksfp; p2->p_addr->u_pcb.kernel_state.pcb_pc = (u_int)proc_trampoline; -#ifdef __FORK_BRAINDAMAGE - return(0); -#else return; -#endif } void @@ -178,7 +174,16 @@ cpu_exit(struct proc *p) extern volatile void switch_exit(); (void) splimp(); + +#if defined(UVM) + uvmexp.swtch++; +#else + cnt.v_swtch++; +#endif + +#if 1 exit2(p); /* XXX - can't be right! */ +#endif switch_exit(p); /* NOTREACHED */ } diff --git a/sys/arch/mvme88k/stand/Makefile b/sys/arch/mvme88k/stand/Makefile index b74ae3b53b6..404fda74972 100644 --- a/sys/arch/mvme88k/stand/Makefile +++ b/sys/arch/mvme88k/stand/Makefile @@ -1,5 +1,10 @@ -# $OpenBSD: Makefile,v 1.4 1998/08/22 08:57:27 smurph Exp $ +# $OpenBSD: Makefile,v 1.5 2000/12/28 21:21:25 smurph Exp $ +.if ${MACHINE} == "mvme88k" -SUBDIR= bugcrt libbug libsa libz wrtvid bootsd bootxx bootst netboot installboot +SUBDIR= bugcrt libbug libsa libz wrtvid bootsd bootxx bootst netboot #sboot XXX future +.endif + +SUBDIR+=installboot + .include <bsd.subdir.mk> diff --git a/sys/arch/mvme88k/stand/installboot/Makefile b/sys/arch/mvme88k/stand/installboot/Makefile index 1315c134f7c..569cab3fac3 100644 --- a/sys/arch/mvme88k/stand/installboot/Makefile +++ b/sys/arch/mvme88k/stand/installboot/Makefile @@ -1,5 +1,6 @@ -# $OpenBSD: Makefile,v 1.4 1999/09/27 19:30:00 smurph Exp $ +# $OpenBSD: Makefile,v 1.5 2000/12/28 21:21:25 smurph Exp $ +.if ${MACHINE} == "mvme88k" PROG= installboot MAN= installboot.8 MANSUBDIR=/mvme88k @@ -9,7 +10,10 @@ DPADD=${LIBUTIL} LDADD=-lutil CFLAGS+=-O0 # Need this to work in the miniroot - LDSTATIC=-static +.else +NOPROG= +.endif .include <bsd.prog.mk> + |