diff options
| -rw-r--r-- | sys/arch/sparc64/dev/sab.c | 1036 | ||||
| -rw-r--r-- | sys/arch/sparc64/dev/sab82532reg.h | 314 |
2 files changed, 1350 insertions, 0 deletions
diff --git a/sys/arch/sparc64/dev/sab.c b/sys/arch/sparc64/dev/sab.c new file mode 100644 index 00000000000..bee1220a567 --- /dev/null +++ b/sys/arch/sparc64/dev/sab.c @@ -0,0 +1,1036 @@ +/* $OpenBSD: sab.c,v 1.1 2001/10/28 02:19:16 jason Exp $ */ + +/* + * Copyright (c) 2001 Jason L. Wright (jason@thought.net) + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by Jason L. Wright + * 4. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * SAB82532 Dual UART driver + */ + +#include <sys/types.h> +#include <sys/param.h> +#include <sys/systm.h> +#include <sys/device.h> +#include <sys/conf.h> +#include <sys/file.h> +#include <sys/ioctl.h> +#include <sys/kernel.h> +#include <sys/proc.h> +#include <sys/tty.h> +#include <sys/time.h> +#include <sys/syslog.h> + +#include <machine/autoconf.h> +#include <machine/openfirm.h> +#include <machine/bsd_openprom.h> +#include <machine/conf.h> +#include <machine/cpu.h> +#include <machine/eeprom.h> +#include <machine/psl.h> + +#include <dev/cons.h> +#include <ddb/db_output.h> + +#include <sparc64/dev/ebusreg.h> +#include <sparc64/dev/ebusvar.h> +#include <sparc64/dev/cons.h> +#include <sparc64/dev/sab82532reg.h> + +#define SAB_CARD(x) ((minor(x) >> 6) & 3) +#define SAB_PORT(x) (minor(x) & 7) +#define SAB_DIALOUT(x) (minor(x) & 0x10) +#define SABTTY_RBUF_SIZE 1024 /* must be divisible by 2 */ + +struct sab_softc { + struct device sc_dv; + struct intrhand * sc_ih; + bus_space_tag_t sc_bt; + bus_space_handle_t sc_bh; + struct sabtty_softc * sc_child[SAB_NCHAN]; + u_int sc_nchild; + void * sc_softintr; +}; + +struct sabtty_attach_args { + u_int sbt_portno; +}; + +struct sabtty_softc { + struct device sc_dv; + struct sab_softc * sc_parent; + bus_space_tag_t sc_bt; + bus_space_handle_t sc_bh; + struct tty * sc_tty; + u_int sc_portno; + u_int8_t sc_pvr_dtr, sc_pvr_dsr; + u_int8_t sc_imr0, sc_imr1; + int sc_openflags; + u_char * sc_txp; + int sc_txc; + int sc_flags; +#define SABTTYF_STOP 0x01 +#define SABTTYF_DONE 0x02 +#define SABTTYF_RINGOVERFLOW 0x04 +#define SABTTYF_CDCHG 0x08 + u_int8_t sc_rbuf[SABTTY_RBUF_SIZE]; + u_int8_t *sc_rend, *sc_rput, *sc_rget; +}; + +#define SAB_READ(sc,r) \ + bus_space_read_1((sc)->sc_bt, (sc)->sc_bh, (r)) +#define SAB_WRITE(sc,r,v) \ + bus_space_write_1((sc)->sc_bt, (sc)->sc_bh, (r), (v)) + +int sab_match __P((struct device *, void *, void *)); +void sab_attach __P((struct device *, struct device *, void *)); +int sab_print __P((void *, const char *)); +int sab_intr __P((void *)); +void sab_softintr __P((void *)); + +int sabtty_match __P((struct device *, void *, void *)); +void sabtty_attach __P((struct device *, struct device *, void *)); +void sabtty_start __P((struct tty *)); +int sabtty_param __P((struct tty *, struct termios *)); +int sabtty_intr __P((struct sabtty_softc *, int *)); +void sabtty_softintr __P((struct sabtty_softc *)); +int sabtty_mdmctrl __P((struct sabtty_softc *, int, int)); +void sabtty_cec_wait __P((struct sabtty_softc *)); +void sabtty_tec_wait __P((struct sabtty_softc *)); +void sabtty_reset __P((struct sabtty_softc *)); +void sabtty_flush __P((struct sabtty_softc *)); +int sabtty_speed __P((int)); + +int sabttyopen __P((dev_t, int, int, struct proc *)); +int sabttyclose __P((dev_t, int, int, struct proc *)); +int sabttyread __P((dev_t, struct uio *, int)); +int sabttywrite __P((dev_t, struct uio *, int)); +int sabttyioctl __P((dev_t, u_long, caddr_t, int, struct proc *)); +int sabttystop __P((struct tty *, int)); +struct tty *sabttytty __P((dev_t)); + +struct cfattach sab_ca = { + sizeof(struct sab_softc), sab_match, sab_attach +}; + +struct cfdriver sab_cd = { + NULL, "sab", DV_DULL +}; + +struct cfattach sabtty_ca = { + sizeof(struct sabtty_softc), sabtty_match, sabtty_attach +}; + +struct cfdriver sabtty_cd = { + NULL, "sabtty", DV_TTY +}; + +struct sabtty_rate { + int baud; + int n, m; +}; + +struct sabtty_rate sabtty_baudtable[] = { + { 50, 35, 10 }, + { 75, 47, 9 }, + { 110, 32, 9 }, + { 134, 53, 8 }, + { 150, 47, 8 }, + { 200, 35, 8 }, + { 300, 47, 7 }, + { 600, 47, 6 }, + { 1200, 47, 5 }, + { 1800, 31, 5 }, + { 2400, 47, 4 }, + { 4800, 47, 3 }, + { 9600, 47, 2 }, + { 19200, 47, 1 }, + { 38400, 23, 1 }, + { 57600, 15, 1 }, + { 115200, 7, 1 }, + { 230400, 3, 1 }, + { 460800, 1, 1 }, + { 76800, 11, 1 }, + { 153600, 5, 1 }, + { 307200, 3, 1 }, + { 614400, 3, 0 }, + { 921600, 0, 1 }, +}; + +int +sab_match(parent, match, aux) + struct device *parent; + void *match, *aux; +{ + struct ebus_attach_args *ea = aux; + + if (strcmp(ea->ea_name, "se") == 0) + return (1); + return (0); +} + +void +sab_attach(parent, self, aux) + struct device *parent; + struct device *self; + void *aux; +{ + struct sab_softc *sc = (struct sab_softc *)self; + struct ebus_attach_args *ea = aux; + u_int8_t r; + u_int i; + + sc->sc_bt = ea->ea_bustag; + + /* Use prom mapping, if available. */ + if (ea->ea_nvaddrs) + sc->sc_bh = (bus_space_handle_t)ea->ea_vaddrs[0]; + else if (ebus_bus_map(sc->sc_bt, 0, + EBUS_PADDR_FROM_REG(&ea->ea_regs[0]), ea->ea_regs[0].size, + BUS_SPACE_MAP_LINEAR, 0, &sc->sc_bh) != 0) { + printf(": can't map register space\n"); + return; + } + + sc->sc_ih = bus_intr_establish(ea->ea_bustag, ea->ea_intrs[0], + IPL_TTY, 0, sab_intr, sc); + if (sc->sc_ih == NULL) { + printf(": can't map interrupt\n"); + return; + } + + sc->sc_softintr = softintr_establish(IPL_TTY, sab_softintr, sc); + if (sc->sc_softintr == NULL) { + printf(": can't get soft intr\n"); + return; + } + + printf(": rev "); + r = SAB_READ(sc, SAB_VSTR) & SAB_VSTR_VMASK; + switch (r) { + case SAB_VSTR_V_1: + printf("1"); + break; + case SAB_VSTR_V_2: + printf("2"); + break; + case SAB_VSTR_V_32: + printf("3.2"); + break; + default: + printf("unknown(0x%x)", r); + break; + } + printf("\n"); + + /* Set all pins, except DTR pins to be inputs */ + SAB_WRITE(sc, SAB_PCR, ~(SAB_PVR_DTR_A | SAB_PVR_DTR_B)); + /* Disable port interrupts */ + SAB_WRITE(sc, SAB_PIM, 0xff); + SAB_WRITE(sc, SAB_PVR, SAB_PVR_DTR_A | SAB_PVR_DTR_B | SAB_PVR_MAGIC); + SAB_WRITE(sc, SAB_IPC, SAB_IPC_ICPL); + + for (i = 0; i < SAB_NCHAN; i++) { + struct sabtty_attach_args sta; + + sta.sbt_portno = i; + sc->sc_child[i] = (struct sabtty_softc *)config_found_sm(self, + &sta, sab_print, sabtty_match); + if (sc->sc_child[i] != NULL) + sc->sc_nchild++; + } +} + +int +sab_print(args, name) + void *args; + const char *name; +{ + struct sabtty_attach_args *sa = args; + + if (name) + printf("sabtty at %s", name); + printf(" port %d", sa->sbt_portno); + return (UNCONF); +} + +int +sab_intr(vsc) + void *vsc; +{ + struct sab_softc *sc = vsc; + int r = 0, needsoft = 0; + u_int8_t gis; + + gis = SAB_READ(sc, SAB_GIS); + + /* channel A */ + if ((gis & (SAB_GIS_ISA1 | SAB_GIS_ISA0)) && sc->sc_child[0] && + sc->sc_child[0]->sc_tty) + r |= sabtty_intr(sc->sc_child[0], &needsoft); + + /* channel B */ + if ((gis & (SAB_GIS_ISB1 | SAB_GIS_ISB0)) && sc->sc_child[1] && + sc->sc_child[1]->sc_tty) + r |= sabtty_intr(sc->sc_child[1], &needsoft); + + if (needsoft) + softintr_schedule(sc->sc_softintr); + + return (r); +} + +void +sab_softintr(vsc) + void *vsc; +{ + struct sab_softc *sc = vsc; + + if (sc->sc_child[0] && sc->sc_child[0]->sc_tty) + sabtty_softintr(sc->sc_child[0]); + if (sc->sc_child[1] && sc->sc_child[1]->sc_tty) + sabtty_softintr(sc->sc_child[1]); +} + +int +sabtty_match(parent, match, aux) + struct device *parent; + void *match, *aux; +{ + struct sabtty_attach_args *sa = aux; + + if (sa->sbt_portno < SAB_NCHAN) + return (1); + return (0); +} + +void +sabtty_attach(parent, self, aux) + struct device *parent; + struct device *self; + void *aux; +{ + struct sabtty_softc *sc = (struct sabtty_softc *)self; + struct sabtty_attach_args *sa = aux; + int r; + + sc->sc_tty = ttymalloc(); + if (sc->sc_tty == NULL) { + printf(": failed to allocate tty\n"); + return; + } + tty_attach(sc->sc_tty); + sc->sc_tty->t_oproc = sabtty_start; + sc->sc_tty->t_param = sabtty_param; + + sc->sc_parent = (struct sab_softc *)parent; + sc->sc_bt = sc->sc_parent->sc_bt; + sc->sc_portno = sa->sbt_portno; + sc->sc_rend = sc->sc_rbuf + SABTTY_RBUF_SIZE; + + switch (sa->sbt_portno) { + case 0: /* port A */ + sc->sc_pvr_dtr = SAB_PVR_DTR_A; + sc->sc_pvr_dsr = SAB_PVR_DSR_A; + r = bus_space_subregion(sc->sc_bt, sc->sc_parent->sc_bh, + SAB_CHAN_A, SAB_CHANLEN, &sc->sc_bh); + break; + case 1: /* port B */ + sc->sc_pvr_dtr = SAB_PVR_DTR_B; + sc->sc_pvr_dsr = SAB_PVR_DSR_B; + r = bus_space_subregion(sc->sc_bt, sc->sc_parent->sc_bh, + SAB_CHAN_B, SAB_CHANLEN, &sc->sc_bh); + break; + default: + printf(": invalid channel: %u\n", sa->sbt_portno); + return; + } + if (r != 0) { + printf(": failed to allocate register subregion\n"); + return; + } + + sabtty_reset(sc); + printf("\n"); +} + +int +sabtty_intr(sc, needsoftp) + struct sabtty_softc *sc; + int *needsoftp; +{ + u_int8_t isr0, isr1; + int i, len = 0, needsoft = 0, r = 0, clearfifo = 0; + + isr0 = SAB_READ(sc, SAB_ISR0); + isr1 = SAB_READ(sc, SAB_ISR1); + + if (isr0 || isr1) + r = 1; + + if (isr0 & SAB_ISR0_RPF) { + len = 32; + clearfifo = 1; + } + if (isr0 & SAB_ISR0_TCD) { + len = (32 - 1) & SAB_READ(sc, SAB_RBCL); + clearfifo = 1; + } + if (isr0 & SAB_ISR0_TIME) { + sabtty_cec_wait(sc); + SAB_WRITE(sc, SAB_CMDR, SAB_CMDR_RFRD); + } + if (isr0 & SAB_ISR0_RFO) { + sc->sc_flags |= SABTTYF_RINGOVERFLOW; + clearfifo = 1; + } + if (len != 0) { + u_int8_t *ptr; + + ptr = sc->sc_rput; + for (i = 0; i < len; i++) { + *ptr++ = SAB_READ(sc, SAB_RFIFO); + if (ptr == sc->sc_rend) + ptr = sc->sc_rbuf; + if (ptr == sc->sc_rget) { + if (ptr == sc->sc_rbuf) + ptr = sc->sc_rend; + ptr--; + sc->sc_flags |= SABTTYF_RINGOVERFLOW; + } + } + sc->sc_rput = ptr; + needsoft = 1; + } + + if (clearfifo) { + sabtty_cec_wait(sc); + SAB_WRITE(sc, SAB_CMDR, SAB_CMDR_RMC); + } + + if (isr0 & SAB_ISR0_CDSC) { + sc->sc_flags |= SABTTYF_CDCHG; + needsoft = 1; + } + + if (isr1 & SAB_ISR1_XPR) { + r = 1; + if ((sc->sc_flags & SABTTYF_STOP) == 0) { + len = 32; + if (sc->sc_txc < 32) + len = sc->sc_txc; + for (i = 0; i < len; i++) { + SAB_WRITE(sc, SAB_XFIFO + i, *sc->sc_txp); + sc->sc_txp++; + sc->sc_txc--; + } + if (i != 0) { + sabtty_cec_wait(sc); + SAB_WRITE(sc, SAB_CMDR, SAB_CMDR_XF); + } + } + + if ((sc->sc_txc == 0) || (sc->sc_flags & SABTTYF_STOP)) { + sc->sc_imr1 |= SAB_IMR1_XPR; + SAB_WRITE(sc, SAB_IMR1, sc->sc_imr1); + sc->sc_flags &= ~SABTTYF_STOP; + sc->sc_flags |= SABTTYF_DONE; + needsoft = 1; + } + } + + if (needsoft) + *needsoftp = needsoft; + return (r); +} + +void +sabtty_softintr(sc) + struct sabtty_softc *sc; +{ + struct tty *tp = sc->sc_tty; + int s, flags; + u_int8_t r; + + if (tp == NULL) + return; + + if ((tp->t_state & TS_ISOPEN) == 0) + return; + + while (sc->sc_rget != sc->sc_rput) { + int data; + u_int8_t stat; + + data = sc->sc_rget[0]; + stat = sc->sc_rget[1]; + sc->sc_rget += 2; + if (stat & SAB_RSTAT_PE) + data |= TTY_PE; + if (stat & SAB_RSTAT_FE) + data |= TTY_FE; + if (sc->sc_rget == sc->sc_rend) + sc->sc_rget = sc->sc_rbuf; + + (*linesw[tp->t_line].l_rint)(data, tp); + } + + s = splhigh(); + flags = sc->sc_flags; + sc->sc_flags &= ~(SABTTYF_DONE|SABTTYF_CDCHG|SABTTYF_RINGOVERFLOW); + splx(s); + + if (flags & SABTTYF_CDCHG) { + s = spltty(); + r = SAB_READ(sc, SAB_VSTR) & SAB_VSTR_CD; + splx(s); + + (*linesw[tp->t_line].l_modem)(tp, r); + } + + if (flags & SABTTYF_RINGOVERFLOW) + log(LOG_WARNING, "%s: ring overflow\n", sc->sc_dv.dv_xname); + + if (flags & SABTTYF_DONE) { + ndflush(&tp->t_outq, sc->sc_txp - tp->t_outq.c_cf); + tp->t_state &= ~TS_BUSY; + (*linesw[tp->t_line].l_start)(tp); + } +} + +int +sabttyopen(dev, flags, mode, p) + dev_t dev; + int flags, mode; + struct proc *p; +{ + struct sab_softc *bc; + struct sabtty_softc *sc; + struct tty *tp; + int card = SAB_CARD(dev), port = SAB_PORT(dev), s; + + if (card >= sab_cd.cd_ndevs) + return (ENXIO); + bc = sab_cd.cd_devs[card]; + if (bc == NULL) + return (ENXIO); + + if (port >= bc->sc_nchild) + return (ENXIO); + sc = bc->sc_child[port]; + if (sc == NULL) + return (ENXIO); + + tp = sc->sc_tty; + tp->t_dev = dev; + + if ((tp->t_state & TS_ISOPEN) == 0) { + tp->t_state |= TS_WOPEN; + + ttychars(tp); + tp->t_iflag = TTYDEF_IFLAG; + tp->t_oflag = TTYDEF_OFLAG; + tp->t_cflag = TTYDEF_CFLAG; + if (sc->sc_openflags & TIOCFLAG_CLOCAL) + tp->t_cflag |= CLOCAL; + if (sc->sc_openflags & TIOCFLAG_CRTSCTS) + tp->t_cflag |= CRTSCTS; + if (sc->sc_openflags & TIOCFLAG_MDMBUF) + tp->t_cflag |= MDMBUF; + tp->t_lflag = TTYDEF_LFLAG; + tp->t_ispeed = tp->t_ospeed = TTYDEF_SPEED; + + sc->sc_rput = sc->sc_rget = sc->sc_rbuf; + + s = spltty(); + + sabtty_reset(sc); + sabtty_param(tp, &tp->t_termios); + ttsetwater(tp); + + sc->sc_imr0 = SAB_IMR0_PERR | SAB_IMR0_FERR | SAB_IMR0_PLLA; + SAB_WRITE(sc, SAB_IMR0, sc->sc_imr0); + + sc->sc_imr1 = SAB_IMR1_BRKT | SAB_IMR1_ALLS | SAB_IMR1_XDU | + SAB_IMR1_TIN | SAB_IMR1_CSC | SAB_IMR1_XMR | SAB_IMR1_XPR; + SAB_WRITE(sc, SAB_IMR1, sc->sc_imr1); + SAB_WRITE(sc, SAB_CCR0, SAB_READ(sc, SAB_CCR0) | SAB_CCR0_PU); + sabtty_flush(sc); + + if ((sc->sc_openflags & TIOCFLAG_SOFTCAR) || + (SAB_READ(sc, SAB_VSTR) & SAB_VSTR_CD)) + tp->t_state |= TS_CARR_ON; + else + tp->t_state &= ~TS_CARR_ON; + } else if ((tp->t_state & TS_XCLUDE) && + (!suser(p->p_ucred, &p->p_acflag))) { + return (EBUSY); + } else { + s = spltty(); + } + + if ((flags & O_NONBLOCK) == 0) { + while ((tp->t_cflag & CLOCAL) == 0 && + (tp->t_state & TS_CARR_ON) == 0) { + int error; + + tp->t_state |= TS_WOPEN; + error = ttysleep(tp, &tp->t_rawq, TTIPRI | PCATCH, + "sabttycd", 0); + if (error != 0) { + splx(s); + tp->t_state &= ~TS_WOPEN; + return (error); + } + } + } + + splx(s); + + return ((*linesw[tp->t_line].l_open)(dev, tp)); +} + +int +sabttyclose(dev, flags, mode, p) + dev_t dev; + int flags, mode; + struct proc *p; +{ + struct sab_softc *bc = sab_cd.cd_devs[SAB_CARD(dev)]; + struct sabtty_softc *sc = bc->sc_child[SAB_PORT(dev)]; + struct tty *tp = sc->sc_tty; + int s; + + (*linesw[tp->t_line].l_close)(tp, flags); + s = spltty(); + + if ((tp->t_cflag & HUPCL) || ((tp->t_state & TS_ISOPEN) == 0)) { + sabtty_mdmctrl(sc, 0, DMSET); + sabtty_flush(sc); + sabtty_reset(sc); + } + splx(s); + ttyclose(tp); + return (0); +} + +int +sabttyread(dev, uio, flags) + dev_t dev; + struct uio *uio; + int flags; +{ + struct sab_softc *bc = sab_cd.cd_devs[SAB_CARD(dev)]; + struct sabtty_softc *sc = bc->sc_child[SAB_PORT(dev)]; + struct tty *tp = sc->sc_tty; + + return ((*linesw[tp->t_line].l_read)(tp, uio, flags)); +} + +int +sabttywrite(dev, uio, flags) + dev_t dev; + struct uio *uio; + int flags; +{ + struct sab_softc *bc = sab_cd.cd_devs[SAB_CARD(dev)]; + struct sabtty_softc *sc = bc->sc_child[SAB_PORT(dev)]; + struct tty *tp = sc->sc_tty; + + return ((*linesw[tp->t_line].l_write)(tp, uio, flags)); +} + +int +sabttyioctl(dev, cmd, data, flags, p) + dev_t dev; + u_long cmd; + caddr_t data; + int flags; + struct proc *p; +{ + struct sab_softc *bc = sab_cd.cd_devs[SAB_CARD(dev)]; + struct sabtty_softc *sc = bc->sc_child[SAB_PORT(dev)]; + struct tty *tp = sc->sc_tty; + int error; + + error = (*linesw[tp->t_line].l_ioctl)(tp, cmd, data, flags, p); + if (error >= 0) + return (error); + + error = ttioctl(tp, cmd, data, flags, p); + if (error >= 0) + return (error); + + error = 0; + + switch (cmd) { + case TIOCSBRK: + SAB_WRITE(sc, SAB_DAFO, + SAB_READ(sc, SAB_DAFO) | SAB_DAFO_XBRK); + break; + case TIOCCBRK: + SAB_WRITE(sc, SAB_DAFO, + SAB_READ(sc, SAB_DAFO) & ~SAB_DAFO_XBRK); + break; + case TIOCSDTR: + sabtty_mdmctrl(sc, TIOCM_DTR, DMBIS); + break; + case TIOCCDTR: + sabtty_mdmctrl(sc, TIOCM_DTR, DMBIC); + break; + case TIOCMBIS: + sabtty_mdmctrl(sc, *((int *)data), DMBIS); + break; + case TIOCMBIC: + sabtty_mdmctrl(sc, *((int *)data), DMBIC); + break; + case TIOCMGET: + *((int *)data) = sabtty_mdmctrl(sc, 0, DMGET); + break; + case TIOCMSET: + sabtty_mdmctrl(sc, *((int *)data), DMSET); + break; + case TIOCGFLAGS: + *((int *)data) = sc->sc_openflags; + break; + case TIOCSFLAGS: + if (suser(p->p_ucred, &p->p_acflag)) + error = EPERM; + else + sc->sc_openflags = *((int *)data) & + (TIOCFLAG_SOFTCAR | TIOCFLAG_CLOCAL | + TIOCFLAG_CRTSCTS | TIOCFLAG_MDMBUF); + break; + default: + error = ENOTTY; + } + + return (error); +} + +struct tty * +sabttytty(dev) + dev_t dev; +{ + struct sab_softc *bc = sab_cd.cd_devs[SAB_CARD(dev)]; + struct sabtty_softc *sc = bc->sc_child[SAB_PORT(dev)]; + + return (sc->sc_tty); +} + +int +sabttystop(tp, flags) + struct tty *tp; + int flags; +{ + struct sab_softc *bc = sab_cd.cd_devs[SAB_CARD(tp->t_dev)]; + struct sabtty_softc *sc = bc->sc_child[SAB_PORT(tp->t_dev)]; + int s; + + s = spltty(); + if (tp->t_state & TS_BUSY) { + if ((tp->t_state & TS_TTSTOP) == 0) + tp->t_state |= TS_FLUSH; + sc->sc_flags |= SABTTYF_STOP; + } + splx(s); + return (0); +} + +int +sabtty_mdmctrl(sc, bits, how) + struct sabtty_softc *sc; + int bits, how; +{ + u_int8_t r; + int s; + + s = spltty(); + switch (how) { + case DMGET: + bits = 0; + if (SAB_READ(sc, SAB_STAR) & SAB_STAR_CTS) + bits |= TIOCM_CTS; + if ((SAB_READ(sc, SAB_VSTR) & SAB_VSTR_CD) == 0) + bits |= TIOCM_CD; + + r = SAB_READ(sc, SAB_PVR); + if ((r & sc->sc_pvr_dtr) == 0) + bits |= TIOCM_DTR; + if ((r & sc->sc_pvr_dsr) == 0) + bits |= TIOCM_DSR; + + r = SAB_READ(sc, SAB_MODE); + if ((r & (SAB_MODE_RTS|SAB_MODE_FRTS)) == SAB_MODE_RTS) + bits |= TIOCM_RTS; + break; + case DMSET: + r = SAB_READ(sc, SAB_MODE); + if (bits & TIOCM_RTS) { + r &= ~SAB_MODE_FRTS; + r |= SAB_MODE_RTS; + } else + r |= SAB_MODE_FRTS | SAB_MODE_RTS; + SAB_WRITE(sc, SAB_MODE, r); + + r = SAB_READ(sc, SAB_PVR); + if (bits & TIOCM_DTR) + r &= ~sc->sc_pvr_dtr; + else + r |= sc->sc_pvr_dtr; + SAB_WRITE(sc, SAB_PVR, r); + break; + case DMBIS: + if (bits & TIOCM_RTS) { + r = SAB_READ(sc, SAB_MODE); + r &= ~SAB_MODE_FRTS; + r |= SAB_MODE_RTS; + SAB_WRITE(sc, SAB_MODE, r); + } + if (bits & TIOCM_DTR) { + r = SAB_READ(sc, SAB_PVR); + r &= ~sc->sc_pvr_dtr; + SAB_WRITE(sc, SAB_PVR, r); + } + break; + case DMBIC: + if (bits & TIOCM_RTS) { + r = SAB_READ(sc, SAB_MODE); + r |= SAB_MODE_FRTS | SAB_MODE_RTS; + SAB_WRITE(sc, SAB_MODE, r); + } + if (bits & TIOCM_DTR) { + r = SAB_READ(sc, SAB_PVR); + r |= sc->sc_pvr_dtr; + SAB_WRITE(sc, SAB_PVR, r); + } + break; + } + splx(s); + return (bits); +} + +int +sabtty_param(tp, t) + struct tty *tp; + struct termios *t; +{ + struct sab_softc *bc = sab_cd.cd_devs[SAB_CARD(tp->t_dev)]; + struct sabtty_softc *sc = bc->sc_child[SAB_PORT(tp->t_dev)]; + int s, ospeed; + u_int8_t dafo, r; + + ospeed = sabtty_speed(t->c_ospeed); + if (ospeed < 0 || (t->c_ispeed && t->c_ispeed != t->c_ospeed)) + return (EINVAL); + + s = spltty(); + + /* hang up line if ospeed is zero, otherwise raise dtr */ + sabtty_mdmctrl(sc, TIOCM_DTR, + (t->c_ospeed == 0) ? DMBIC : DMBIS); + + dafo = SAB_READ(sc, SAB_DAFO); + + if (t->c_cflag & CSTOPB) + dafo |= SAB_DAFO_STOP; + else + dafo &= ~SAB_DAFO_STOP; + + dafo &= ~SAB_DAFO_CHL_CSIZE; + switch (t->c_cflag & CSIZE) { + case CS5: + dafo |= SAB_DAFO_CHL_CS5; + break; + case CS6: + dafo |= SAB_DAFO_CHL_CS6; + break; + case CS7: + dafo |= SAB_DAFO_CHL_CS7; + break; + default: + dafo |= SAB_DAFO_CHL_CS8; + break; + } + + dafo &= ~SAB_DAFO_PARMASK; + if (t->c_cflag & PARENB) { + if (tp->t_cflag & PARODD) + dafo |= SAB_DAFO_PAR_ODD; + else + dafo |= SAB_DAFO_PAR_EVEN; + } else + dafo |= SAB_DAFO_PAR_NONE; + + if (ospeed != 0) { + SAB_WRITE(sc, SAB_BGR, ospeed & 0xff); + r = SAB_READ(sc, SAB_CCR2); + r &= ~(SAB_CCR2_BR9 | SAB_CCR2_BR8); + r |= (ospeed >> 2) & (SAB_CCR2_BR9 | SAB_CCR2_BR8); + SAB_WRITE(sc, SAB_CCR2, r); + } + + r = SAB_READ(sc, SAB_MODE); + r |= SAB_MODE_RAC; + if (t->c_cflag & CRTSCTS) { + r &= ~(SAB_MODE_RTS | SAB_MODE_FCTS); + r |= SAB_MODE_FRTS; + sc->sc_imr1 &= ~SAB_IMR1_CSC; + } else { + r |= SAB_MODE_RTS | SAB_MODE_FCTS; + r &= ~SAB_MODE_FRTS; + sc->sc_imr1 |= SAB_IMR1_CSC; + } + SAB_WRITE(sc, SAB_MODE, r); + SAB_WRITE(sc, SAB_IMR1, sc->sc_imr1); + + splx(s); + return (0); +} + +void +sabtty_start(tp) + struct tty *tp; +{ + struct sab_softc *bc = sab_cd.cd_devs[SAB_CARD(tp->t_dev)]; + struct sabtty_softc *sc = bc->sc_child[SAB_PORT(tp->t_dev)]; + int s; + + s = spltty(); + if ((tp->t_state & (TS_TTSTOP | TS_TIMEOUT | TS_BUSY)) == 0) { + if (tp->t_outq.c_cc <= tp->t_lowat) { + if (tp->t_state & TS_ASLEEP) { + tp->t_state &= ~TS_ASLEEP; + wakeup(&tp->t_outq); + } + selwakeup(&tp->t_wsel); + } + if (tp->t_outq.c_cc) { + sc->sc_txc = ndqb(&tp->t_outq, 0); + sc->sc_txp = tp->t_outq.c_cf; + tp->t_state |= TS_BUSY; + sc->sc_imr1 &= ~SAB_IMR1_XPR; + SAB_WRITE(sc, SAB_IMR1, sc->sc_imr1); + } + } + splx(s); +} + +void +sabtty_cec_wait(sc) + struct sabtty_softc *sc; +{ + int i = 50000; + + for (;;) { + if ((SAB_READ(sc, SAB_STAR) & SAB_STAR_CEC) == 0) + return; + if (--i == 0) + break; + DELAY(1); + } + if (i == 0) + printf("%s: cec timeout\n", sc->sc_dv.dv_xname); +} + +void +sabtty_tec_wait(sc) + struct sabtty_softc *sc; +{ + int i = 200000; + + for (;;) { + if ((SAB_READ(sc, SAB_STAR) & SAB_STAR_TEC) == 0) + return; + if (--i == 0) + break; + DELAY(1); + } + if (i == 0) + printf("%s: tec timeout\n", sc->sc_dv.dv_xname); +} + +void +sabtty_reset(sc) + struct sabtty_softc *sc; +{ + /* power down */ + SAB_WRITE(sc, SAB_CCR0, 0); + + /* set basic configuration */ + SAB_WRITE(sc, SAB_CCR0, + SAB_CCR0_MCE | SAB_CCR0_SC_NRZ | SAB_CCR0_SM_ASYNC); + SAB_WRITE(sc, SAB_CCR1, SAB_CCR1_ODS | SAB_CCR1_BCR | SAB_CCR1_CM_7); + SAB_WRITE(sc, SAB_CCR2, SAB_CCR2_BDF | SAB_CCR2_SSEL | SAB_CCR2_TOE); + SAB_WRITE(sc, SAB_CCR3, 0); + SAB_WRITE(sc, SAB_CCR4, SAB_CCR4_MCK4 | SAB_CCR4_EBRG); + SAB_WRITE(sc, SAB_MODE, SAB_MODE_RTS | SAB_MODE_FCTS | SAB_MODE_RAC); + SAB_WRITE(sc, SAB_RFC, + SAB_RFC_DPS | SAB_RFC_RFDF | SAB_RFC_RFTH_32CHAR); + + /* clear interrupts */ + sc->sc_imr0 = sc->sc_imr1 = 0xff; + SAB_WRITE(sc, SAB_IMR0, sc->sc_imr0); + SAB_WRITE(sc, SAB_IMR1, sc->sc_imr1); + SAB_READ(sc, SAB_ISR0); + SAB_READ(sc, SAB_ISR1); +} + +void +sabtty_flush(sc) + struct sabtty_softc *sc; +{ + /* clear rx fifo */ + sabtty_cec_wait(sc); + SAB_WRITE(sc, SAB_CMDR, SAB_CMDR_RRES); + + /* clear tx fifo */ + sabtty_cec_wait(sc); + SAB_WRITE(sc, SAB_CMDR, SAB_CMDR_XRES); +} + +int +sabtty_speed(rate) + int rate; +{ + int i, len, r; + + if (rate == 0) + return (0); + len = sizeof(sabtty_baudtable)/sizeof(sabtty_baudtable[0]); + for (i = 0; i < len; i++) { + if (rate == sabtty_baudtable[i].baud) { + r = sabtty_baudtable[i].n | + (sabtty_baudtable[i].m << 6); + return (r); + } + } + return (-1); +} diff --git a/sys/arch/sparc64/dev/sab82532reg.h b/sys/arch/sparc64/dev/sab82532reg.h new file mode 100644 index 00000000000..89cc76b2c79 --- /dev/null +++ b/sys/arch/sparc64/dev/sab82532reg.h @@ -0,0 +1,314 @@ +/* $OpenBSD: sab82532reg.h,v 1.1 2001/10/28 02:19:16 jason Exp $ */ + +/* + * Copyright (c) 2001 Jason L. Wright (jason@thought.net) + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by Jason L. Wright + * 4. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * Register definitions for SAB82532 based on "Enhanced Serial Communication + * Controller ESCC2 Version 3.2 User's Manual 07.96" from: + * http://www.infineon.com + */ + +#define SAB_NCHAN 2 /* number of channels */ +#define SAB_CHANLEN 0x40 /* length of channel register set */ + +#define SAB_CHAN_A 0x00 /* channel A register offset */ +#define SAB_CHAN_B 0x40 /* channel B register offset */ + +#define SAB_RFIFO 0x00 /* r: rx fifo */ +#define SAB_XFIFO 0x00 /* w: tx fifo */ +#define SAB_STAR 0x20 /* r: status register */ +#define SAB_CMDR 0x20 /* w: command register */ +#define SAB_MODE 0x22 /* rw: mode register */ +#define SAB_TIMR 0x23 /* rw: timer register */ +#define SAB_XON 0x24 /* rw: xon character */ +#define SAB_XOFF 0x25 /* rw: xoff character */ +#define SAB_TCR 0x26 /* rw: termination character */ +#define SAB_DAFO 0x27 /* rw: data format */ +#define SAB_RFC 0x28 /* rw: rfifo control register */ +#define SAB_RBCL 0x2a /* r: rx byte count low */ +#define SAB_TBCL 0x2a /* w: tx byte count low */ +#define SAB_RBCH 0x2b /* r: rx byte count high */ +#define SAB_XBCH 0x2b /* w: tx byte count high */ +#define SAB_CCR0 0x2c /* rw: channel configuration register 0 */ +#define SAB_CCR1 0x2d /* rw: channel configuration register 1 */ +#define SAB_CCR2 0x2e /* rw: channel configuration register 2 */ +#define SAB_CCR3 0x2f /* rw: channel configuration register 3 */ +#define SAB_TSAX 0x30 /* w: time-slot assignment register tx */ +#define SAB_TSAR 0x31 /* w: time-slot assignment register rx */ +#define SAB_XCCR 0x32 /* w: tx channel capacity register */ +#define SAB_RCCR 0x33 /* w: receive channel capacity register */ +#define SAB_VSTR 0x34 /* r: version status */ +#define SAB_BGR 0x34 /* w: baud rate generator */ +#define SAB_TIC 0x35 /* w: transmit immediate character */ +#define SAB_MXN 0x36 /* w: mask xon character */ +#define SAB_MXF 0x37 /* w: mask xoff character */ +#define SAB_GIS 0x38 /* r: global interrupt status */ +#define SAB_IVA 0x38 /* w: interrupt vector address */ +#define SAB_IPC 0x39 /* rw: interrupt port configuration */ +#define SAB_ISR0 0x3a /* r: interrupt status 0 */ +#define SAB_IMR0 0x3a /* w: interrupt mask 0 */ +#define SAB_ISR1 0x3b /* r: interrupt status 1 */ +#define SAB_IMR1 0x3b /* w: interrupt mask 1 */ +#define SAB_PVR 0x3c /* rw: port value register */ +#define SAB_PIS 0x3d /* r: port interrupt status */ +#define SAB_PIM 0x3d /* w: port interrupt mask */ +#define SAB_PCR 0x3e /* w: port configuration register */ +#define SAB_CCR4 0x3f /* rw: channel configuration register 4 */ + +/* SAB_STAR: status register */ +#define SAB_STAR_XDOV 0x80 /* transmit data overflow */ +#define SAB_STAR_XFW 0x40 /* transmit fifo write enable */ +#define SAB_STAR_RFNE 0x20 /* rfifo not empty */ +#define SAB_STAR_FCS 0x10 /* flow control status */ +#define SAB_STAR_TEC 0x08 /* tx immediate char is executing */ +#define SAB_STAR_CEC 0x04 /* command is executing */ +#define SAB_STAR_CTS 0x02 /* cts status: 0:inactive/high,1:active/low */ + +/* SAB_CMDR: command register */ +#define SAB_CMDR_RMC 0x80 /* receive message complete */ +#define SAB_CMDR_RRES 0x40 /* receiver reset */ +#define SAB_CMDR_RFRD 0x20 /* receive fifo read enable */ +#define SAB_CMDR_STI 0x10 /* start timer */ +#define SAB_CMDR_XF 0x08 /* transmit frame */ +#define SAB_CMDR_XRES 0x01 /* transmit reset */ + +/* SAB_MODE: mode register */ +#define SAB_MODE_FRTS 0x40 /* flow control using rts */ +#define SAB_MODE_FCTS 0x20 /* flow control using cts */ +#define SAB_MODE_FLON 0x10 /* flow control on */ +#define SAB_MODE_RAC 0x08 /* receiver active */ +#define SAB_MODE_RTS 0x04 /* request to send */ +#define SAB_MODE_TRS 0x02 /* timer resolution */ +#define SAB_MODE_TLP 0x01 /* test loop */ + +/* SAB_TIMR: timer register */ +#define SAB_TIMR_CNT 0xe0 /* count mask */ +#define SAB_TIMR_VAL 0x1f /* value mask */ + +/* SAB_DAFO: data format */ +#define SAB_DAFO_XBRK 0x40 /* transmit break */ +#define SAB_DAFO_STOP 0x20 /* stop bit: 0:1 bit, 1:2 bits */ +#define SAB_DAFO_PAR1 0x10 /* parity 1, see below */ +#define SAB_DAFO_PAR0 0x08 /* parity 0, see below */ +#define SAB_DAFO_PARE 0x04 /* parity enable */ +#define SAB_DAFO_CHL1 0x02 /* character length 1, see below */ +#define SAB_DAFO_CHL0 0x01 /* character length 0, see below */ + +#define SAB_DAFO_CHL_CSIZE (SAB_DAFO_CHL1|SAB_DAFO_CHL0) +#define SAB_DAFO_CHL_CS5 (SAB_DAFO_CHL1|SAB_DAFO_CHL0) +#define SAB_DAFO_CHL_CS6 (SAB_DAFO_CHL1) +#define SAB_DAFO_CHL_CS7 (SAB_DAFO_CHL0) +#define SAB_DAFO_CHL_CS8 (0) + +#define SAB_DAFO_PARMASK (SAB_DAFO_PAR1|SAB_DAFO_PAR0|SAB_DAFO_PARE) +#define SAB_DAFO_PAR_MARK (SAB_DAFO_PAR1|SAB_DAFO_PAR0|SAB_DAFO_PARE) +#define SAB_DAFO_PAR_EVEN (SAB_DAFO_PAR1|SAB_DAFO_PARE) +#define SAB_DAFO_PAR_ODD (SAB_DAFO_PAR0|SAB_DAFO_PARE) +#define SAB_DAFO_PAR_SPACE (SAB_DAFO_PARE) +#define SAB_DAFO_PAR_NONE (0) + +/* SAB_RFC: rfifo control register */ +#define SAB_RFC_DPS 0x40 /* disable parity storage */ +#define SAB_RFC_DXS 0x20 /* disable storage of xon/xoff characters */ +#define SAB_RFC_RFDF 0x10 /* rfifo data format: 0 data,1 data+stat */ +#define SAB_RFC_RFTH1 0x08 /* rfifo threshold level 1, see below */ +#define SAB_RFC_RFTH0 0x04 /* rfifo threshold level 0, see below */ +#define SAB_RFC_TCDE 0x01 /* termination character detection enable */ + +#define SAB_RFC_RFTH_MASK (SAB_RFC_RFTH1|SAB_RFC_RFTH0) +#define SAB_RFC_RFTH_32CHAR (SAB_RFC_RFTH1|SAB_RFC_RFTH0) +#define SAB_RFC_RFTH_16CHAR (SAB_RFC_RFTH1) +#define SAB_RFC_RFTH_4CHAR (SAB_RFC_RFTH0) +#define SAB_RFC_RFTH_1CHAR (0) + +/* SAB_RBCH: received byte count high */ +#define SAB_RBCH_DMA 0x80 /* read back of XBCH DMA bit */ +#define SAB_RBCH_CAS 0x20 /* read back of XBCH CAS bit */ +#define SAB_RBCH_CNT 0x0f /* ms 4 bits of rx byte count (not used) */ + +/* SAB_XBCH: transmit byte count high */ +#define SAB_XBCH_DMA 0x80 /* dma mode: 1:dma, 0:interrupt */ +#define SAB_XBCH_CAS 0x20 /* carrier detect auto-start */ +#define SAB_XBCH_XC 0x10 /* transmit continuously */ +#define SAB_XBCH_CNT 0x0f /* ms 4 bits of tx byte count */ + +/* SAB_CCR0: channel configuration register 0 */ +#define SAB_CCR0_PU 0x80 /* 0:power-down, 1:power-up */ +#define SAB_CCR0_MCE 0x40 /* master clock enable */ +#define SAB_CCR0_SC2 0x10 /* serial port config 2, see below */ +#define SAB_CCR0_SC1 0x08 /* serial port config 1, see below */ +#define SAB_CCR0_SC0 0x04 /* serial port config 0, see below */ +#define SAB_CCR0_SM1 0x02 /* serial mode 1, see below */ +#define SAB_CCR0_SM0 0x01 /* serial mode 0, see below */ + +#define SAB_CCR0_SC_MASK (SAB_CCR0_SC2|SAB_CCR0_SC1|SAB_CCR0_SC0) +#define SAB_CCR0_SC_NRZ (0) +#define SAB_CCR0_SC_NRZI (SAB_CCR0_SC1) +#define SAB_CCR0_SC_FM0 (SAB_CCR0_SC2) +#define SAB_CCR0_SC_FM1 (SAB_CCR0_SC2|SAB_CCR0_SC0) +#define SAB_CCR0_SC_MANCHESTER (SAB_CCR0_SC2|SAB_CCR0_SC1) + +#define SAB_CCR0_SM_MASK (SAB_CCR0_SM1|SAB_CCR0_SM0) +#define SAB_CCR0_SM_DLC (0) +#define SAB_CCR0_SM_DLCLOOP (SAB_CCR0_SM0) +#define SAB_CCR0_SM_BISYNC (SAB_CCR0_SM1) +#define SAB_CCR0_SM_ASYNC (SAB_CCR0_SM1|SAB_CCR0_SM0) + +/* SAB_CCR1: channel configuration register 1 */ +#define SAB_CCR1_ODS 0x10 /* Output driver select:1:pushpull,0:odrain */ +#define SAB_CCR1_BCR 0x08 /* bit clock rate: 1:async, 0:isochronous */ +#define SAB_CCR1_CM2 0x04 /* clock mode 2, see below */ +#define SAB_CCR1_CM1 0x02 /* clock mode 1, see below */ +#define SAB_CCR1_CM0 0x01 /* clock mode 0, see below */ + +#define SAB_CCR1_CM_MASK (SAB_CCR1_CM2|SAB_CCR1_CM1|SAB_CCR1_CM0) +#define SAB_CCR1_CM_7 (SAB_CCR1_CM2|SAB_CCR1_CM1|SAB_CCR1_CM0) + +/* SAB_CCR2: channel configuration register 2, depends on clock mode above */ +/* clock mode 0a, 1, 4, 5 */ +#define SAB_CCR2_SOC1 0x80 /* special output 1, below */ +#define SAB_CCR2_SOC0 0x40 /* special output 0, below */ +#define SAB_CCR2_SOC_MASK (SAB_CCR2_SOC1|SAB_CCR2_SOC0) +#define SAB_CCR2_SOC_RTSHIGH (SAB_CCR2_SOC1) +#define SAB_CCR2_SOC_RTSNORM (0) +#define SAB_CCR2_SOC_RTSRX (SAB_CCR2_SOC1|SAB_CCR2_SOC0) +/* clock mode 0b, 2, 3, 6, 7 */ +#define SAB_CCR2_BR9 0x80 /* baud rate bit 9 */ +#define SAB_CCR2_BR8 0x40 /* baud rate bit 8 */ +#define SAB_CCR2_BDF 0x20 /* baud rate division factor: 0:1: 1:BRG */ +#define SAB_CCR2_SSEL 0x10 /* clock source select */ +/* clock mode 5 */ +#define SAB_CCR2_XCS0 0x20 /* tx clock shift, bit 0 */ +#define SAB_CCR2_RCS0 0x10 /* rx clock shift, bit 0 */ +/* clock mode 0b, 2, 3, 4, 5, 6, 7 */ +#define SAB_CCR2_TOE 0x08 /* tx clock output enable */ +/* clock mode 0a, 0b, 1, 2, 3, 4, 5, 6, 7 */ +#define SAB_CCR2_RWX 0x04 /* read/write exchange (dma mode only) */ +#define SAB_CCR2_DIV 0x01 /* data inversion (nrz) */ + +/* SAB_CCR3: channel configuration register 3 (v2 or greater) */ +#define SAB_CCR3_PSD 0x01 /* dpll phase shift disable (nrz/nrzi) */ + +/* SAB_TSAX: time-slot assignment register transmit (clock mode 5 only) */ +#define SAB_TSAX_TSNX 0xfc /* time-slot number transmit */ +#define SAB_TSAX_XCS2 0x02 /* transmit clock shift bit 2 */ +#define SAB_TSAX_XCS1 0x01 /* transmit clock shift bit 1 */ + +/* SAB_TSAR: time-slot assignment register receive (clock mode 5 only) */ +#define SAB_TSAR_TSNR 0xfc /* time-slot number receive */ +#define SAB_TSAR_RCS2 0x02 /* receive clock shift bit 2 */ +#define SAB_TSAR_RCS1 0x01 /* receive clock shift bit 1 */ + +/* SAB_VSTR: version status register */ +#define SAB_VSTR_CD 0x80 /* carrier detect status */ +#define SAB_VSTR_DPLA 0x40 /* dpll asynchronous */ +#define SAB_VSTR_VMASK 0x0f /* chip version mask: */ +#define SAB_VSTR_V_1 0x00 /* version 1 */ +#define SAB_VSTR_V_2 0x01 /* version 2 */ +#define SAB_VSTR_V_32 0x02 /* version 3.2 */ + +/* SAB_GIS: global interrupt status register */ +#define SAB_GIS_PI 0x80 /* universal port interrupt */ +#define SAB_GIS_ISA1 0x08 /* interrupt status a1 */ +#define SAB_GIS_ISA0 0x04 /* interrupt status a0 */ +#define SAB_GIS_ISB1 0x02 /* interrupt status b1 */ +#define SAB_GIS_ISB0 0x01 /* interrupt status b0 */ + +/* SAB_IVA: interrupt vector address */ +#define SAB_IVA_MASK 0xf8 /* interrupt vector address mask */ + +/* SAB_IPC: interrupt port configuration */ +#define SAB_IPC_VIS 0x80 /* masked interrupt bits visible */ +#define SAB_IPC_SLAMASK 0x18 /* slave address mask */ +#define SAB_IPC_CASM 0x04 /* cascading mode */ +#define SAB_IPC_ICMASK 0x03 /* port config mask: */ +#define SAB_IPC_ICOD 0x00 /* open drain output */ +#define SAB_IPC_ICPL 0x01 /* push/pull active low output */ +#define SAB_IPC_ICPH 0x03 /* push/pull active high output */ + +/* SAB_ISR0: interrupt status 0 */ +#define SAB_ISR0_TCD 0x80 /* termination character detected */ +#define SAB_ISR0_TIME 0x40 /* time-out limit exceeded */ +#define SAB_ISR0_PERR 0x20 /* parity error */ +#define SAB_ISR0_FERR 0x10 /* framing error */ +#define SAB_ISR0_PLLA 0x08 /* dpll asynchronous */ +#define SAB_ISR0_CDSC 0x04 /* carrier detect status change */ +#define SAB_ISR0_RFO 0x02 /* rfifo overflow */ +#define SAB_ISR0_RPF 0x01 /* receive pool full */ + +/* SAB_ISR1: interrupt status 1 */ +#define SAB_ISR1_BRK 0x80 /* break detected */ +#define SAB_ISR1_BRKT 0x40 /* break terminated */ +#define SAB_ISR1_ALLS 0x20 /* all sent */ +#define SAB_ISR1_XOFF 0x10 /* xoff detected */ +#define SAB_ISR1_TIN 0x08 /* timer interrupt */ +#define SAB_ISR1_CSC 0x04 /* clear to send status change */ +#define SAB_ISR1_XON 0x02 /* xon detected */ +#define SAB_ISR1_XPR 0x01 /* transmit pool ready */ + +/* SAB_IMR0: interrupt mask 0 */ +#define SAB_IMR0_TCD 0x80 /* termination character detected */ +#define SAB_IMR0_TIME 0x40 /* time-out limit exceeded */ +#define SAB_IMR0_PERR 0x20 /* parity error */ +#define SAB_IMR0_FERR 0x10 /* framing error */ +#define SAB_IMR0_PLLA 0x08 /* dpll asynchronous */ +#define SAB_IMR0_CDSC 0x04 /* carrier detect status change */ +#define SAB_IMR0_RFO 0x02 /* rfifo overflow */ +#define SAB_IMR0_RPF 0x01 /* receive pool full */ + +/* SAB_ISR1: interrupt mask 1 */ +#define SAB_IMR1_BRK 0x80 /* break detected */ +#define SAB_IMR1_BRKT 0x40 /* break terminated */ +#define SAB_IMR1_ALLS 0x20 /* all sent */ +#define SAB_IMR1_XDU 0x10 /* xoff detected */ +#define SAB_IMR1_TIN 0x08 /* timer interrupt */ +#define SAB_IMR1_CSC 0x04 /* clear to send status change */ +#define SAB_IMR1_XMR 0x02 /* xon detected */ +#define SAB_IMR1_XPR 0x01 /* transmit pool ready */ + +/* SAB_PVR: port value register */ +#define SAB_PVR_DSR_A 0x01 /* port A DSR */ +#define SAB_PVR_DTR_A 0x02 /* port A DTR */ +#define SAB_PVR_DTR_B 0x04 /* port B DTR */ +#define SAB_PVR_DSR_B 0x08 /* port B DSR */ +#define SAB_PVR_MAGIC 0x10 /* dunno... */ + +/* SAB_CCR4: channel configuration register 4 */ +#define SAB_CCR4_MCK4 0x80 /* master clock divide by 4 */ +#define SAB_CCR4_EBRG 0x40 /* enhanced baud rate generator mode */ +#define SAB_CCR4_TST1 0x20 /* test pin */ +#define SAB_CCR4_ICD 0x10 /* invert polarity of carrier detect */ + +/* Receive status byte */ +#define SAB_RSTAT_PE 0x80 /* parity error */ +#define SAB_RSTAT_FE 0x40 /* framing error */ +#define SAB_RSTAT_PAR 0x01 /* parity bit */ |