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-rw-r--r--sys/dev/pci/piixpm.c35
-rw-r--r--sys/dev/pci/piixreg.h62
2 files changed, 65 insertions, 32 deletions
diff --git a/sys/dev/pci/piixpm.c b/sys/dev/pci/piixpm.c
index e3e5d6d5e60..04ab1b5c547 100644
--- a/sys/dev/pci/piixpm.c
+++ b/sys/dev/pci/piixpm.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: piixpm.c,v 1.4 2005/12/25 09:44:54 grange Exp $ */
+/* $OpenBSD: piixpm.c,v 1.5 2005/12/25 15:04:48 grange Exp $ */
/*
* Copyright (c) 2005 Alexander Yurchenko <grange@openbsd.org>
@@ -33,6 +33,8 @@
#include <dev/pci/pcireg.h>
#include <dev/pci/pcivar.h>
+#include <dev/pci/piixreg.h>
+
#include <dev/i2c/i2cvar.h>
#ifdef PIIXPM_DEBUG
@@ -44,37 +46,6 @@
#define PIIXPM_DELAY 100
#define PIIXPM_TIMEOUT 1
-/* Register definitions */
-#define PIIX_SMB_BASE 0x90 /* SMBus base address */
-#define PIIX_SMB_HOSTC 0xd0 /* host configuration */
-#define PIIX_SMB_HOSTC_HSTEN (1 << 16) /* enable host controller */
-#define PIIX_SMB_HOSTC_SMI (0 << 17) /* SMI */
-#define PIIX_SMB_HOSTC_IRQ (4 << 17) /* IRQ */
-
-#define PIIX_SMB_HS 0x00 /* host status */
-#define PIIX_SMB_HS_BUSY (1 << 0) /* running a command */
-#define PIIX_SMB_HS_INTR (1 << 1) /* command completed */
-#define PIIX_SMB_HS_DEVERR (1 << 2) /* command error */
-#define PIIX_SMB_HS_BUSERR (1 << 3) /* transaction collision */
-#define PIIX_SMB_HS_FAILED (1 << 4) /* failed bus transaction */
-#define PIIX_SMB_HS_BITS "\020\001BUSY\002INTR\003DEVERR\004BUSERR\005FAILED"
-#define PIIX_SMB_HC 0x02 /* host control */
-#define PIIX_SMB_HC_INTREN (1 << 0) /* enable interrupts */
-#define PIIX_SMB_HC_KILL (1 << 1) /* kill current transaction */
-#define PIIX_SMB_HC_CMD_QUICK (0 << 2) /* QUICK command */
-#define PIIX_SMB_HC_CMD_BYTE (1 << 2) /* BYTE command */
-#define PIIX_SMB_HC_CMD_BDATA (2 << 2) /* BYTE DATA command */
-#define PIIX_SMB_HC_CMD_WDATA (3 << 2) /* WORD DATA command */
-#define PIIX_SMB_HC_CMD_BLOCK (5 << 2) /* BLOCK command */
-#define PIIX_SMB_HC_START (1 << 6) /* start transaction */
-#define PIIX_SMB_HCMD 0x03 /* host command */
-#define PIIX_SMB_TXSLVA 0x04 /* transmit slave address */
-#define PIIX_SMB_TXSLVA_READ (1 << 0) /* read direction */
-#define PIIX_SMB_TXSLVA_ADDR(x) (((x) & 0x7f) << 1) /* 7-bit address */
-#define PIIX_SMB_HD0 0x05 /* host data 0 */
-#define PIIX_SMB_HD1 0x06 /* host data 1 */
-#define PIIX_SMB_HBDB 0x07 /* host block data byte */
-
struct piixpm_softc {
struct device sc_dev;
diff --git a/sys/dev/pci/piixreg.h b/sys/dev/pci/piixreg.h
new file mode 100644
index 00000000000..ccad3a6c094
--- /dev/null
+++ b/sys/dev/pci/piixreg.h
@@ -0,0 +1,62 @@
+/* $OpenBSD: piixreg.h,v 1.1 2005/12/25 15:04:48 grange Exp $ */
+
+/*
+ * Copyright (c) 2005 Alexander Yurchenko <grange@openbsd.org>
+ *
+ * Permission to use, copy, modify, and distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _DEV_PCI_PIIXREG_H_
+#define _DEV_PCI_PIIXREG_H_
+
+/*
+ * Intel PCI-to-ISA / IDE Xcelerator (PIIX) register definitions.
+ */
+
+/*
+ * Power management registers.
+ */
+
+/* PCI configuration registers */
+#define PIIX_SMB_BASE 0x90 /* SMBus base address */
+#define PIIX_SMB_HOSTC 0xd0 /* SMBus host configuration */
+#define PIIX_SMB_HOSTC_HSTEN (1 << 16) /* enable host controller */
+#define PIIX_SMB_HOSTC_SMI (0 << 17) /* SMI */
+#define PIIX_SMB_HOSTC_IRQ (4 << 17) /* IRQ */
+
+/* SMBus I/O registers */
+#define PIIX_SMB_HS 0x00 /* host status */
+#define PIIX_SMB_HS_BUSY (1 << 0) /* running a command */
+#define PIIX_SMB_HS_INTR (1 << 1) /* command completed */
+#define PIIX_SMB_HS_DEVERR (1 << 2) /* command error */
+#define PIIX_SMB_HS_BUSERR (1 << 3) /* transaction collision */
+#define PIIX_SMB_HS_FAILED (1 << 4) /* failed bus transaction */
+#define PIIX_SMB_HS_BITS "\020\001BUSY\002INTR\003DEVERR\004BUSERR\005FAILED"
+#define PIIX_SMB_HC 0x02 /* host control */
+#define PIIX_SMB_HC_INTREN (1 << 0) /* enable interrupts */
+#define PIIX_SMB_HC_KILL (1 << 1) /* kill current transaction */
+#define PIIX_SMB_HC_CMD_QUICK (0 << 2) /* QUICK command */
+#define PIIX_SMB_HC_CMD_BYTE (1 << 2) /* BYTE command */
+#define PIIX_SMB_HC_CMD_BDATA (2 << 2) /* BYTE DATA command */
+#define PIIX_SMB_HC_CMD_WDATA (3 << 2) /* WORD DATA command */
+#define PIIX_SMB_HC_CMD_BLOCK (5 << 2) /* BLOCK command */
+#define PIIX_SMB_HC_START (1 << 6) /* start transaction */
+#define PIIX_SMB_HCMD 0x03 /* host command */
+#define PIIX_SMB_TXSLVA 0x04 /* transmit slave address */
+#define PIIX_SMB_TXSLVA_READ (1 << 0) /* read direction */
+#define PIIX_SMB_TXSLVA_ADDR(x) (((x) & 0x7f) << 1) /* 7-bit address */
+#define PIIX_SMB_HD0 0x05 /* host data 0 */
+#define PIIX_SMB_HD1 0x06 /* host data 1 */
+#define PIIX_SMB_HBDB 0x07 /* host block data byte */
+
+#endif /* !_DEV_PCI_PIIXREG_H_ */