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-rw-r--r--sys/dev/cardbus/if_athn_cardbus.c54
-rw-r--r--sys/dev/ic/ar5008.c53
-rw-r--r--sys/dev/ic/ar9003.c48
-rw-r--r--sys/dev/ic/ar9280.c13
-rw-r--r--sys/dev/ic/ar9285.c13
-rw-r--r--sys/dev/ic/ar9287.c12
-rw-r--r--sys/dev/ic/ar9380.c11
-rw-r--r--sys/dev/ic/athn.c51
-rw-r--r--sys/dev/ic/athnreg.h9
-rw-r--r--sys/dev/ic/athnvar.h38
-rw-r--r--sys/dev/pci/if_athn_pci.c54
11 files changed, 301 insertions, 55 deletions
diff --git a/sys/dev/cardbus/if_athn_cardbus.c b/sys/dev/cardbus/if_athn_cardbus.c
index 57304f84291..01c228ce95b 100644
--- a/sys/dev/cardbus/if_athn_cardbus.c
+++ b/sys/dev/cardbus/if_athn_cardbus.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: if_athn_cardbus.c,v 1.10 2010/09/06 19:20:21 deraadt Exp $ */
+/* $OpenBSD: if_athn_cardbus.c,v 1.11 2010/12/31 14:06:05 damien Exp $ */
/*-
* Copyright (c) 2009 Damien Bergamini <damien.bergamini@free.fr>
@@ -62,19 +62,24 @@ struct athn_cardbus_softc {
cardbus_devfunc_t sc_ct;
pcitag_t sc_tag;
void *sc_ih;
+ bus_space_tag_t sc_st;
+ bus_space_handle_t sc_sh;
bus_size_t sc_mapsize;
pcireg_t sc_bar_val;
int sc_intrline;
pci_chipset_tag_t sc_pc;
};
-int athn_cardbus_match(struct device *, void *, void *);
-void athn_cardbus_attach(struct device *, struct device *, void *);
-int athn_cardbus_detach(struct device *, int);
-int athn_cardbus_enable(struct athn_softc *);
-void athn_cardbus_disable(struct athn_softc *);
-void athn_cardbus_power(struct athn_softc *, int);
-void athn_cardbus_setup(struct athn_cardbus_softc *);
+int athn_cardbus_match(struct device *, void *, void *);
+void athn_cardbus_attach(struct device *, struct device *, void *);
+int athn_cardbus_detach(struct device *, int);
+int athn_cardbus_enable(struct athn_softc *);
+void athn_cardbus_disable(struct athn_softc *);
+void athn_cardbus_power(struct athn_softc *, int);
+void athn_cardbus_setup(struct athn_cardbus_softc *);
+uint32_t athn_cardbus_read(struct athn_softc *, uint32_t);
+void athn_cardbus_write(struct athn_softc *, uint32_t, uint32_t);
+void athn_cardbus_write_barrier(struct athn_softc *);
struct cfattach athn_cardbus_ca = {
sizeof (struct athn_cardbus_softc),
@@ -124,9 +129,13 @@ athn_cardbus_attach(struct device *parent, struct device *self, void *aux)
sc->sc_disable = athn_cardbus_disable;
sc->sc_power = athn_cardbus_power;
+ sc->ops.read = athn_cardbus_read;
+ sc->ops.write = athn_cardbus_write;
+ sc->ops.write_barrier = athn_cardbus_write_barrier;
+
/* Map control/status registers. */
error = Cardbus_mapreg_map(ct, CARDBUS_BASE0_REG,
- PCI_MAPREG_TYPE_MEM, 0, &sc->sc_st, &sc->sc_sh, &base,
+ PCI_MAPREG_TYPE_MEM, 0, &csc->sc_st, &csc->sc_sh, &base,
&csc->sc_mapsize);
if (error != 0) {
printf(": can't map mem space\n");
@@ -159,7 +168,7 @@ athn_cardbus_detach(struct device *self, int flags)
cardbus_intr_disestablish(cc, cf, csc->sc_ih);
/* Release bus space and close window. */
- Cardbus_mapreg_unmap(ct, CARDBUS_BASE0_REG, sc->sc_st, sc->sc_sh,
+ Cardbus_mapreg_unmap(ct, CARDBUS_BASE0_REG, csc->sc_st, csc->sc_sh,
csc->sc_mapsize);
return (0);
@@ -257,3 +266,28 @@ athn_cardbus_setup(struct athn_cardbus_softc *csc)
reg |= 168 << PCI_LATTIMER_SHIFT;
pci_conf_write(pc, csc->sc_tag, PCI_BHLC_REG, reg);
}
+
+uint32_t
+athn_cardbus_read(struct athn_softc *sc, uint32_t addr)
+{
+ struct athn_cardbus_softc *csc = (struct athn_cardbus_softc *)sc;
+
+ return (bus_space_read_4(csc->sc_st, csc->sc_sh, addr));
+}
+
+void
+athn_cardbus_write(struct athn_softc *sc, uint32_t addr, uint32_t val)
+{
+ struct athn_cardbus_softc *csc = (struct athn_cardbus_softc *)sc;
+
+ bus_space_write_4(csc->sc_st, csc->sc_sh, addr, val);
+}
+
+void
+athn_cardbus_write_barrier(struct athn_softc *sc)
+{
+ struct athn_cardbus_softc *csc = (struct athn_cardbus_softc *)sc;
+
+ bus_space_barrier(csc->sc_st, csc->sc_sh, 0, csc->sc_mapsize,
+ BUS_SPACE_BARRIER_WRITE);
+}
diff --git a/sys/dev/ic/ar5008.c b/sys/dev/ic/ar5008.c
index 40fa9d8476b..5e03a334897 100644
--- a/sys/dev/ic/ar5008.c
+++ b/sys/dev/ic/ar5008.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: ar5008.c,v 1.14 2010/11/07 18:00:42 damien Exp $ */
+/* $OpenBSD: ar5008.c,v 1.15 2010/12/31 14:06:05 damien Exp $ */
/*-
* Copyright (c) 2009 Damien Bergamini <damien.bergamini@free.fr>
@@ -371,6 +371,7 @@ ar5008_gpio_write(struct athn_softc *sc, int pin, int set)
else
reg &= ~(1 << pin);
AR_WRITE(sc, AR_GPIO_IN_OUT, reg);
+ AR_WRITE_BARRIER(sc);
}
void
@@ -382,6 +383,7 @@ ar5008_gpio_config_input(struct athn_softc *sc, int pin)
reg &= ~(AR_GPIO_OE_OUT_DRV_M << (pin * 2));
reg |= AR_GPIO_OE_OUT_DRV_NO << (pin * 2);
AR_WRITE(sc, AR_GPIO_OE_OUT, reg);
+ AR_WRITE_BARRIER(sc);
}
void
@@ -404,6 +406,7 @@ ar5008_gpio_config_output(struct athn_softc *sc, int pin, int type)
reg &= ~(AR_GPIO_OE_OUT_DRV_M << (pin * 2));
reg |= AR_GPIO_OE_OUT_DRV_ALL << (pin * 2);
AR_WRITE(sc, AR_GPIO_OE_OUT, reg);
+ AR_WRITE_BARRIER(sc);
}
void
@@ -422,6 +425,7 @@ ar5008_rfsilent_init(struct athn_softc *sc)
AR_SETBITS(sc, AR_GPIO_INTR_POL,
AR_GPIO_INTR_POL_PIN(sc->rfsilent_pin));
}
+ AR_WRITE_BARRIER(sc);
}
int
@@ -674,6 +678,7 @@ ar5008_rx_enable(struct athn_softc *sc)
/* Enable Rx. */
AR_WRITE(sc, AR_RXDP, SIMPLEQ_FIRST(&rxq->head)->bf_daddr);
AR_WRITE(sc, AR_CR, AR_CR_RXE);
+ AR_WRITE_BARRIER(sc);
}
#if NBPFILTER > 0
@@ -784,6 +789,7 @@ ar5008_rx_process(struct athn_softc *sc)
ds->ds_status8));
/* HW will not "move" RXDP in this case, so do it. */
AR_WRITE(sc, AR_RXDP, nbf->bf_daddr);
+ AR_WRITE_BARRIER(sc);
ifp->if_ierrors++;
goto skip;
}
@@ -911,6 +917,7 @@ ar5008_rx_process(struct athn_softc *sc)
/* Re-enable Rx. */
AR_WRITE(sc, AR_CR, AR_CR_RXE);
+ AR_WRITE_BARRIER(sc);
return (0);
}
@@ -1101,6 +1108,7 @@ ar5008_swba_intr(struct athn_softc *sc)
/* Kick Tx. */
AR_WRITE(sc, AR_Q_TXE, 1 << ATHN_QID_BEACON);
+ AR_WRITE_BARRIER(sc);
return (0);
}
#endif
@@ -1152,8 +1160,8 @@ ar5008_intr(struct athn_softc *sc)
AR_ISR_TXERR | AR_ISR_TXEOL))
ar5008_tx_intr(sc);
+ intr5 = AR_READ(sc, AR_ISR_S5_S);
if (intr & AR_ISR_GENTMR) {
- intr5 = AR_READ(sc, AR_ISR_S5_S);
if (intr5 & AR_ISR_GENTMR) {
DPRINTF(("GENTMR trigger=%d thresh=%d\n",
MS(intr5, AR_ISR_S5_GENTIMER_TRIG),
@@ -1161,7 +1169,6 @@ ar5008_intr(struct athn_softc *sc)
}
}
- intr5 = AR_READ(sc, AR_ISR_S5_S);
if (intr5 & AR_ISR_S5_TIM_TIMER)
/* TBD */;
}
@@ -1542,6 +1549,7 @@ ar5008_tx(struct athn_softc *sc, struct mbuf *m, struct ieee80211_node *ni,
/* Kick Tx. */
AR_WRITE(sc, AR_Q_TXE, 1 << qid);
+ AR_WRITE_BARRIER(sc);
return (0);
}
@@ -1560,6 +1568,7 @@ ar5008_set_rf_mode(struct athn_softc *sc, struct ieee80211_channel *c)
reg |= AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE;
}
AR_WRITE(sc, AR_PHY_MODE, reg);
+ AR_WRITE_BARRIER(sc);
}
static __inline uint32_t
@@ -1599,6 +1608,7 @@ ar5008_rf_bus_release(struct athn_softc *sc)
/* Release the RF Bus grant. */
AR_WRITE(sc, AR_PHY_RFBUS_REQ, 0);
+ AR_WRITE_BARRIER(sc);
}
void
@@ -1629,6 +1639,7 @@ ar5008_set_phy(struct athn_softc *sc, struct ieee80211_channel *c,
AR_WRITE(sc, AR_GTXTO, SM(AR_GTXTO_TIMEOUT_LIMIT, 25));
/* Set carrier sense timeout. */
AR_WRITE(sc, AR_CST, SM(AR_CST_TIMEOUT_LIMIT, 15));
+ AR_WRITE_BARRIER(sc);
}
void
@@ -1656,6 +1667,7 @@ ar5008_set_delta_slope(struct athn_softc *sc, struct ieee80211_channel *c,
reg = RW(reg, AR_PHY_HALFGI_DSC_EXP, exp);
reg = RW(reg, AR_PHY_HALFGI_DSC_MAN, man);
AR_WRITE(sc, AR_PHY_HALFGI, reg);
+ AR_WRITE_BARRIER(sc);
}
void
@@ -1663,6 +1675,7 @@ ar5008_enable_antenna_diversity(struct athn_softc *sc)
{
AR_SETBITS(sc, AR_PHY_CCK_DETECT,
AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV);
+ AR_WRITE_BARRIER(sc);
}
void
@@ -1673,6 +1686,7 @@ ar5008_init_baseband(struct athn_softc *sc)
synth_delay = ar5008_synth_delay(sc);
/* Activate the PHY (includes baseband activate and synthesizer on). */
AR_WRITE(sc, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
+ AR_WRITE_BARRIER(sc);
DELAY(AR_BASE_PHY_ACTIVE_DELAY + synth_delay);
}
@@ -1680,6 +1694,7 @@ void
ar5008_disable_phy(struct athn_softc *sc)
{
AR_WRITE(sc, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
+ AR_WRITE_BARRIER(sc);
}
void
@@ -1698,6 +1713,7 @@ ar5008_init_chains(struct athn_softc *sc)
AR_WRITE(sc, AR_PHY_CAL_CHAINMASK, sc->rxchainmask);
}
AR_WRITE(sc, AR_SELFGEN_MASK, sc->txchainmask);
+ AR_WRITE_BARRIER(sc);
}
void
@@ -1706,6 +1722,7 @@ ar5008_set_rxchains(struct athn_softc *sc)
if (sc->rxchainmask == 0x3 || sc->rxchainmask == 0x5) {
AR_WRITE(sc, AR_PHY_RX_CHAINMASK, sc->rxchainmask);
AR_WRITE(sc, AR_PHY_CAL_CHAINMASK, sc->rxchainmask);
+ AR_WRITE_BARRIER(sc);
}
}
@@ -1750,6 +1767,7 @@ ar5008_write_noisefloor(struct athn_softc *sc, int16_t *nf, int16_t *nf_ext)
reg = RW(reg, AR_PHY_EXT_MAXCCA_PWR, nf_ext[i]);
AR_WRITE(sc, AR_PHY_EXT_CCA(i), reg);
}
+ AR_WRITE_BARRIER(sc);
}
void
@@ -1814,12 +1832,14 @@ ar5008_noisefloor_calib(struct athn_softc *sc)
AR_SETBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_ENABLE_NF);
AR_SETBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NO_UPDATE_NF);
AR_SETBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
+ AR_WRITE_BARRIER(sc);
}
void
ar5008_do_noisefloor_calib(struct athn_softc *sc)
{
AR_SETBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
+ AR_WRITE_BARRIER(sc);
}
void
@@ -1843,6 +1863,7 @@ ar5008_do_calib(struct athn_softc *sc)
DPRINTF(("starting calibration mode=0x%x\n", mode));
AR_SETBITS(sc, AR_PHY_TIMING_CTRL4_0, AR_PHY_TIMING_CTRL4_DO_CAL);
+ AR_WRITE_BARRIER(sc);
}
void
@@ -1924,6 +1945,7 @@ ar5008_calib_iq(struct athn_softc *sc)
/* Apply new settings. */
AR_SETBITS(sc, AR_PHY_TIMING_CTRL4_0,
AR_PHY_TIMING_CTRL4_IQCORR_ENABLE);
+ AR_WRITE_BARRIER(sc);
/* IQ calibration done. */
sc->cur_calib_mask &= ~ATHN_CAL_IQ;
@@ -1974,6 +1996,7 @@ ar5008_calib_adc_gain(struct athn_softc *sc)
/* Apply new settings. */
AR_SETBITS(sc, AR_PHY_NEW_ADC_DC_GAIN_CORR(0),
AR_PHY_NEW_ADC_GAIN_CORR_ENABLE);
+ AR_WRITE_BARRIER(sc);
/* ADC gain calibration done. */
sc->cur_calib_mask &= ~ATHN_CAL_ADC_GAIN;
@@ -2028,6 +2051,7 @@ ar5008_calib_adc_dc_off(struct athn_softc *sc)
/* Apply new settings. */
AR_SETBITS(sc, AR_PHY_NEW_ADC_DC_GAIN_CORR(0),
AR_PHY_NEW_ADC_DC_OFFSET_CORR_ENABLE);
+ AR_WRITE_BARRIER(sc);
/* ADC DC offset calibration done. */
sc->cur_calib_mask &= ~ATHN_CAL_ADC_DC;
@@ -2084,6 +2108,7 @@ ar5008_write_txpower(struct athn_softc *sc, int16_t power[ATHN_POWER_COUNT])
(power[ATHN_POWER_OFDM_DUP] & 0x3f) << 8 |
(power[ATHN_POWER_CCK_DUP ] & 0x3f));
#endif
+ AR_WRITE_BARRIER(sc);
}
void
@@ -2186,6 +2211,7 @@ ar5008_set_viterbi_mask(struct athn_softc *sc, int bin)
p[49] << 6 | p[48] << 4 | p[47] << 2 | p[46] << 0;
AR_WRITE(sc, AR_PHY_BIN_MASK2_4, reg);
AR_WRITE(sc, AR_PHY_VIT_MASK2_P_61_46, reg);
+ AR_WRITE_BARRIER(sc);
}
void
@@ -2229,11 +2255,14 @@ ar5008_hw_init(struct athn_softc *sc, struct ieee80211_channel *c,
(sc->flags & ATHN_FLAG_AN_TOP2_FIXUP))
val &= ~AR_AN_TOP2_PWDCLKIND;
AR_WRITE(sc, ini->regs[i], val);
- if (AR_IS_ANALOG_REG(ini->regs[i]))
+ if (AR_IS_ANALOG_REG(ini->regs[i])) {
+ AR_WRITE_BARRIER(sc);
DELAY(100);
+ }
if ((i & 0x1f) == 0)
DELAY(1);
}
+ AR_WRITE_BARRIER(sc);
if (sc->rx_gain != NULL)
ar9280_reset_rx_gain(sc, c);
@@ -2244,8 +2273,10 @@ ar5008_hw_init(struct athn_softc *sc, struct ieee80211_channel *c,
DPRINTFN(4, ("writing common init vals\n"));
for (i = 0; i < ini->ncmregs; i++) {
AR_WRITE(sc, ini->cmregs[i], ini->cmvals[i]);
- if (AR_IS_ANALOG_REG(ini->cmregs[i]))
+ if (AR_IS_ANALOG_REG(ini->cmregs[i])) {
+ AR_WRITE_BARRIER(sc);
DELAY(100);
+ }
if ((i & 0x1f) == 0)
DELAY(1);
}
@@ -2265,8 +2296,10 @@ ar5008_hw_init(struct athn_softc *sc, struct ieee80211_channel *c,
DPRINTFN(4, ("writing fast pll clock init vals\n"));
for (i = 0; i < ini->nfastregs; i++) {
AR_WRITE(sc, ini->fastregs[i], pvals[i]);
- if (AR_IS_ANALOG_REG(ini->fastregs[i]))
+ if (AR_IS_ANALOG_REG(ini->fastregs[i])) {
+ AR_WRITE_BARRIER(sc);
DELAY(100);
+ }
if ((i & 0x1f) == 0)
DELAY(1);
}
@@ -2295,6 +2328,7 @@ ar5008_hw_init(struct athn_softc *sc, struct ieee80211_channel *c,
AR_PHY_RIFS_INIT_DELAY_M);
}
}
+ AR_WRITE_BARRIER(sc);
ar5008_set_phy(sc, c, extc);
ar5008_init_chains(sc);
@@ -2526,6 +2560,8 @@ ar5008_set_noise_immunity_level(struct athn_softc *sc, int level)
reg = AR_READ(sc, AR_PHY_FIND_SIG);
reg = RW(reg, AR_PHY_FIND_SIG_FIRPWR, high ? -80 : -78);
AR_WRITE(sc, AR_PHY_FIND_SIG, reg);
+
+ AR_WRITE_BARRIER(sc);
}
void
@@ -2554,6 +2590,7 @@ ar5008_enable_ofdm_weak_signal(struct athn_softc *sc)
AR_SETBITS(sc, AR_PHY_SFCORR_LOW,
AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
+ AR_WRITE_BARRIER(sc);
}
void
@@ -2582,6 +2619,7 @@ ar5008_disable_ofdm_weak_signal(struct athn_softc *sc)
AR_CLRBITS(sc, AR_PHY_SFCORR_LOW,
AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
+ AR_WRITE_BARRIER(sc);
}
void
@@ -2592,6 +2630,7 @@ ar5008_set_cck_weak_signal(struct athn_softc *sc, int high)
reg = AR_READ(sc, AR_PHY_CCK_DETECT);
reg = RW(reg, AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK, high ? 6 : 8);
AR_WRITE(sc, AR_PHY_CCK_DETECT, reg);
+ AR_WRITE_BARRIER(sc);
}
void
@@ -2602,6 +2641,7 @@ ar5008_set_firstep_level(struct athn_softc *sc, int level)
reg = AR_READ(sc, AR_PHY_FIND_SIG);
reg = RW(reg, AR_PHY_FIND_SIG_FIRSTEP, level * 4);
AR_WRITE(sc, AR_PHY_FIND_SIG, reg);
+ AR_WRITE_BARRIER(sc);
}
void
@@ -2612,4 +2652,5 @@ ar5008_set_spur_immunity_level(struct athn_softc *sc, int level)
reg = AR_READ(sc, AR_PHY_TIMING5);
reg = RW(reg, AR_PHY_TIMING5_CYCPWR_THR1, (level + 1) * 2);
AR_WRITE(sc, AR_PHY_TIMING5, reg);
+ AR_WRITE_BARRIER(sc);
}
diff --git a/sys/dev/ic/ar9003.c b/sys/dev/ic/ar9003.c
index d8dc9c9b6d1..6afce3f9224 100644
--- a/sys/dev/ic/ar9003.c
+++ b/sys/dev/ic/ar9003.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: ar9003.c,v 1.18 2010/11/10 21:06:44 damien Exp $ */
+/* $OpenBSD: ar9003.c,v 1.19 2010/12/31 14:06:05 damien Exp $ */
/*-
* Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr>
@@ -424,6 +424,7 @@ ar9003_gpio_write(struct athn_softc *sc, int pin, int set)
else
reg &= ~(1 << pin);
AR_WRITE(sc, AR_GPIO_IN_OUT, reg);
+ AR_WRITE_BARRIER(sc);
}
void
@@ -435,6 +436,7 @@ ar9003_gpio_config_input(struct athn_softc *sc, int pin)
reg &= ~(AR_GPIO_OE_OUT_DRV_M << (pin * 2));
reg |= AR_GPIO_OE_OUT_DRV_NO << (pin * 2);
AR_WRITE(sc, AR_GPIO_OE_OUT, reg);
+ AR_WRITE_BARRIER(sc);
}
void
@@ -455,6 +457,7 @@ ar9003_gpio_config_output(struct athn_softc *sc, int pin, int type)
reg &= ~(AR_GPIO_OE_OUT_DRV_M << (pin * 2));
reg |= AR_GPIO_OE_OUT_DRV_ALL << (pin * 2);
AR_WRITE(sc, AR_GPIO_OE_OUT, reg);
+ AR_WRITE_BARRIER(sc);
}
void
@@ -473,6 +476,7 @@ ar9003_rfsilent_init(struct athn_softc *sc)
AR_SETBITS(sc, AR_GPIO_INTR_POL,
AR_GPIO_INTR_POL_PIN(sc->rfsilent_pin));
}
+ AR_WRITE_BARRIER(sc);
}
int
@@ -707,6 +711,7 @@ ar9003_reset_txsring(struct athn_softc *sc)
sc->txsmap->dm_segs[0].ds_addr);
AR_WRITE(sc, AR_Q_STATUS_RING_END,
sc->txsmap->dm_segs[0].ds_addr + sc->txsmap->dm_segs[0].ds_len);
+ AR_WRITE_BARRIER(sc);
}
void
@@ -740,11 +745,13 @@ ar9003_rx_enable(struct athn_softc *sc)
AR_WRITE(sc, AR_LP_RXDP, bf->bf_daddr);
else
AR_WRITE(sc, AR_HP_RXDP, bf->bf_daddr);
+ AR_WRITE_BARRIER(sc);
SIMPLEQ_INSERT_TAIL(&rxq->head, bf, bf_list);
}
}
/* Enable Rx. */
AR_WRITE(sc, AR_CR, 0);
+ AR_WRITE_BARRIER(sc);
}
#if NBPFILTER > 0
@@ -955,10 +962,12 @@ ar9003_rx_process(struct athn_softc *sc, int qid)
AR_WRITE(sc, AR_LP_RXDP, bf->bf_daddr);
else
AR_WRITE(sc, AR_HP_RXDP, bf->bf_daddr);
+ AR_WRITE_BARRIER(sc);
SIMPLEQ_INSERT_TAIL(&rxq->head, bf, bf_list);
/* Re-enable Rx. */
AR_WRITE(sc, AR_CR, 0);
+ AR_WRITE_BARRIER(sc);
return (0);
}
@@ -1052,6 +1061,7 @@ ar9003_tx_process(struct athn_softc *sc)
/* Queue buffers that are waiting if there is new room. */
if (--txq->queued < AR9003_TX_QDEPTH && txq->wait != NULL) {
AR_WRITE(sc, AR_QTXDP(qid), txq->wait->bf_daddr);
+ AR_WRITE_BARRIER(sc);
txq->wait = SIMPLEQ_NEXT(txq->wait, bf_list);
}
return (0);
@@ -1174,6 +1184,7 @@ ar9003_swba_intr(struct athn_softc *sc)
/* Kick Tx. */
AR_WRITE(sc, AR_Q_TXE, 1 << ATHN_QID_BEACON);
+ AR_WRITE_BARRIER(sc);
return (0);
}
#endif
@@ -1612,9 +1623,10 @@ ar9003_tx(struct athn_softc *sc, struct mbuf *m, struct ieee80211_node *ni,
SIMPLEQ_INSERT_TAIL(&txq->head, bf, bf_list);
/* Queue buffer unless hardware FIFO is already full. */
- if (++txq->queued <= AR9003_TX_QDEPTH)
+ if (++txq->queued <= AR9003_TX_QDEPTH) {
AR_WRITE(sc, AR_QTXDP(qid), bf->bf_daddr);
- else if (txq->wait == NULL)
+ AR_WRITE_BARRIER(sc);
+ } else if (txq->wait == NULL)
txq->wait = bf;
return (0);
}
@@ -1631,6 +1643,7 @@ ar9003_set_rf_mode(struct athn_softc *sc, struct ieee80211_channel *c)
reg |= AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE;
}
AR_WRITE(sc, AR_PHY_MODE, reg);
+ AR_WRITE_BARRIER(sc);
}
static __inline uint32_t
@@ -1670,6 +1683,7 @@ ar9003_rf_bus_release(struct athn_softc *sc)
/* Release the RF Bus grant. */
AR_WRITE(sc, AR_PHY_RFBUS_REQ, 0);
+ AR_WRITE_BARRIER(sc);
}
void
@@ -1699,6 +1713,7 @@ ar9003_set_phy(struct athn_softc *sc, struct ieee80211_channel *c,
AR_WRITE(sc, AR_GTXTO, SM(AR_GTXTO_TIMEOUT_LIMIT, 25));
/* Set carrier sense timeout. */
AR_WRITE(sc, AR_CST, SM(AR_CST_TIMEOUT_LIMIT, 15));
+ AR_WRITE_BARRIER(sc);
}
void
@@ -1726,6 +1741,7 @@ ar9003_set_delta_slope(struct athn_softc *sc, struct ieee80211_channel *c,
reg = RW(reg, AR_PHY_SGI_DSC_EXP, exp);
reg = RW(reg, AR_PHY_SGI_DSC_MAN, man);
AR_WRITE(sc, AR_PHY_SGI_DELTA, reg);
+ AR_WRITE_BARRIER(sc);
}
void
@@ -1733,6 +1749,7 @@ ar9003_enable_antenna_diversity(struct athn_softc *sc)
{
AR_SETBITS(sc, AR_PHY_CCK_DETECT,
AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV);
+ AR_WRITE_BARRIER(sc);
}
void
@@ -1743,6 +1760,7 @@ ar9003_init_baseband(struct athn_softc *sc)
synth_delay = ar9003_synth_delay(sc);
/* Activate the PHY (includes baseband activate and synthesizer on). */
AR_WRITE(sc, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
+ AR_WRITE_BARRIER(sc);
DELAY(AR_BASE_PHY_ACTIVE_DELAY + synth_delay);
}
@@ -1750,6 +1768,7 @@ void
ar9003_disable_phy(struct athn_softc *sc)
{
AR_WRITE(sc, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
+ AR_WRITE_BARRIER(sc);
}
void
@@ -1763,6 +1782,7 @@ ar9003_init_chains(struct athn_softc *sc)
AR_WRITE(sc, AR_PHY_CAL_CHAINMASK, sc->rxchainmask);
AR_WRITE(sc, AR_SELFGEN_MASK, sc->txchainmask);
+ AR_WRITE_BARRIER(sc);
}
void
@@ -1771,6 +1791,7 @@ ar9003_set_rxchains(struct athn_softc *sc)
if (sc->rxchainmask == 0x3 || sc->rxchainmask == 0x5) {
AR_WRITE(sc, AR_PHY_RX_CHAINMASK, sc->rxchainmask);
AR_WRITE(sc, AR_PHY_CAL_CHAINMASK, sc->rxchainmask);
+ AR_WRITE_BARRIER(sc);
}
}
@@ -1809,6 +1830,7 @@ ar9003_write_noisefloor(struct athn_softc *sc, int16_t *nf, int16_t *nf_ext)
reg = RW(reg, AR_PHY_EXT_MAXCCA_PWR, nf_ext[i]);
AR_WRITE(sc, AR_PHY_EXT_CCA(i), reg);
}
+ AR_WRITE_BARRIER(sc);
}
void
@@ -1919,6 +1941,7 @@ ar9003_init_calib(struct athn_softc *sc)
ar9003_calib_tx_iq(sc);
/* Disable and re-enable the PHY chips. */
AR_WRITE(sc, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
+ AR_WRITE_BARRIER(sc);
DELAY(5);
AR_WRITE(sc, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
@@ -1953,11 +1976,13 @@ ar9003_do_calib(struct athn_softc *sc)
AR_WRITE(sc, AR_PHY_TIMING4, reg);
AR_WRITE(sc, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ);
AR_SETBITS(sc, AR_PHY_TIMING4, AR_PHY_TIMING4_DO_CAL);
+ AR_WRITE_BARRIER(sc);
} else if (sc->cur_calib_mask & ATHN_CAL_TEMP) {
AR_SETBITS(sc, AR_PHY_65NM_CH0_THERM,
AR_PHY_65NM_CH0_THERM_LOCAL);
AR_SETBITS(sc, AR_PHY_65NM_CH0_THERM,
AR_PHY_65NM_CH0_THERM_START);
+ AR_WRITE_BARRIER(sc);
}
}
@@ -2032,6 +2057,7 @@ ar9003_calib_iq(struct athn_softc *sc)
/* Apply new settings. */
AR_SETBITS(sc, AR_PHY_RX_IQCAL_CORR_B(0),
AR_PHY_RX_IQCAL_CORR_IQCORR_ENABLE);
+ AR_WRITE_BARRIER(sc);
/* IQ calibration done. */
sc->cur_calib_mask &= ~ATHN_CAL_IQ;
@@ -2218,6 +2244,7 @@ ar9003_calib_tx_iq(struct athn_softc *sc)
reg = RW(reg, AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_I_COFF,
coeff[1]);
AR_WRITE(sc, AR_PHY_RX_IQCAL_CORR_B(i), reg);
+ AR_WRITE_BARRIER(sc);
}
/* Enable Tx IQ correction. */
@@ -2225,6 +2252,7 @@ ar9003_calib_tx_iq(struct athn_softc *sc)
AR_PHY_TX_IQCAL_CONTROL_3_IQCORR_EN);
AR_SETBITS(sc, AR_PHY_RX_IQCAL_CORR_B(0),
AR_PHY_RX_IQCAL_CORR_B0_LOOPBACK_IQCORR_EN);
+ AR_WRITE_BARRIER(sc);
return (0);
}
#undef DELPT
@@ -2291,6 +2319,7 @@ ar9003_paprd_calib(struct athn_softc *sc, struct ieee80211_channel *c)
AR_CLRBITS(sc, AR_PHY_PAPRD_CTRL0_B(i),
AR_PHY_PAPRD_CTRL0_PAPRD_ENABLE);
}
+ AR_WRITE_BARRIER(sc);
/*
* Configure training signal.
@@ -2348,6 +2377,7 @@ ar9003_paprd_calib(struct athn_softc *sc, struct ieee80211_channel *c)
/* Make sure training done bit is clear. */
AR_CLRBITS(sc, AR_PHY_PAPRD_TRAINER_STAT1,
AR_PHY_PAPRD_TRAINER_STAT1_TRAIN_DONE);
+ AR_WRITE_BARRIER(sc);
/* Transmit training signal. */
ar9003_paprd_tx_tone(sc);
@@ -2415,6 +2445,7 @@ ar9003_force_txgain(struct athn_softc *sc, uint32_t txgain)
reg = RW(reg, AR_PHY_TPC_1_FORCED_DAC_GAIN, 0);
reg &= ~AR_PHY_TPC_1_FORCE_DAC_GAIN;
AR_WRITE(sc, AR_PHY_TPC_1, reg);
+ AR_WRITE_BARRIER(sc);
}
void
@@ -2759,6 +2790,7 @@ ar9003_enable_predistorter(struct athn_softc *sc, int chain)
/* Enable digital predistorter for this chain. */
AR_SETBITS(sc, AR_PHY_PAPRD_CTRL0_B(chain),
AR_PHY_PAPRD_CTRL0_PAPRD_ENABLE);
+ AR_WRITE_BARRIER(sc);
}
void
@@ -2879,6 +2911,7 @@ ar9003_write_txpower(struct athn_softc *sc, int16_t power[ATHN_POWER_COUNT])
(power[ATHN_POWER_HT40(15)] & 0x3f) << 8 |
(power[ATHN_POWER_HT40(14)] & 0x3f));
#endif
+ AR_WRITE_BARRIER(sc);
}
void
@@ -2895,6 +2928,7 @@ ar9003_reset_rx_gain(struct athn_softc *sc, struct ieee80211_channel *c)
pvals = prog->vals_5g;
for (i = 0; i < prog->nregs; i++)
AR_WRITE(sc, X(prog->regs[i]), pvals[i]);
+ AR_WRITE_BARRIER(sc);
#undef X
}
@@ -2912,6 +2946,7 @@ ar9003_reset_tx_gain(struct athn_softc *sc, struct ieee80211_channel *c)
pvals = prog->vals_5g;
for (i = 0; i < prog->nregs; i++)
AR_WRITE(sc, X(prog->regs[i]), pvals[i]);
+ AR_WRITE_BARRIER(sc);
#undef X
}
@@ -3001,6 +3036,7 @@ ar9003_hw_init(struct athn_softc *sc, struct ieee80211_channel *c,
reg |= AR_PCU_MISC_MODE2_AGG_WEP_ENABLE_FIX;
reg |= AR_PCU_MISC_MODE2_ENABLE_AGGWEP;
AR_WRITE(sc, AR_PCU_MISC_MODE2, reg);
+ AR_WRITE_BARRIER(sc);
ar9003_set_phy(sc, c, extc);
ar9003_init_chains(sc);
@@ -3094,6 +3130,7 @@ ar9003_set_noise_immunity_level(struct athn_softc *sc, int level)
reg = AR_READ(sc, AR_PHY_FIND_SIG);
reg = RW(reg, AR_PHY_FIND_SIG_FIRPWR, high ? -80 : -78);
AR_WRITE(sc, AR_PHY_FIND_SIG, reg);
+ AR_WRITE_BARRIER(sc);
}
void
@@ -3122,6 +3159,7 @@ ar9003_enable_ofdm_weak_signal(struct athn_softc *sc)
AR_SETBITS(sc, AR_PHY_SFCORR_LOW,
AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
+ AR_WRITE_BARRIER(sc);
}
void
@@ -3150,6 +3188,7 @@ ar9003_disable_ofdm_weak_signal(struct athn_softc *sc)
AR_CLRBITS(sc, AR_PHY_SFCORR_LOW,
AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
+ AR_WRITE_BARRIER(sc);
}
void
@@ -3160,6 +3199,7 @@ ar9003_set_cck_weak_signal(struct athn_softc *sc, int high)
reg = AR_READ(sc, AR_PHY_CCK_DETECT);
reg = RW(reg, AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK, high ? 6 : 8);
AR_WRITE(sc, AR_PHY_CCK_DETECT, reg);
+ AR_WRITE_BARRIER(sc);
}
void
@@ -3170,6 +3210,7 @@ ar9003_set_firstep_level(struct athn_softc *sc, int level)
reg = AR_READ(sc, AR_PHY_FIND_SIG);
reg = RW(reg, AR_PHY_FIND_SIG_FIRSTEP, level * 4);
AR_WRITE(sc, AR_PHY_FIND_SIG, reg);
+ AR_WRITE_BARRIER(sc);
}
void
@@ -3180,4 +3221,5 @@ ar9003_set_spur_immunity_level(struct athn_softc *sc, int level)
reg = AR_READ(sc, AR_PHY_TIMING5);
reg = RW(reg, AR_PHY_TIMING5_CYCPWR_THR1, (level + 1) * 2);
AR_WRITE(sc, AR_PHY_TIMING5, reg);
+ AR_WRITE_BARRIER(sc);
}
diff --git a/sys/dev/ic/ar9280.c b/sys/dev/ic/ar9280.c
index 83b881341b1..9f08325b810 100644
--- a/sys/dev/ic/ar9280.c
+++ b/sys/dev/ic/ar9280.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: ar9280.c,v 1.13 2010/09/03 15:40:08 damien Exp $ */
+/* $OpenBSD: ar9280.c,v 1.14 2010/12/31 14:06:05 damien Exp $ */
/*-
* Copyright (c) 2009 Damien Bergamini <damien.bergamini@free.fr>
@@ -231,8 +231,10 @@ ar9280_set_synth(struct athn_softc *sc, struct ieee80211_channel *c,
AR_WRITE(sc, AR_AN_SYNTH9, reg);
}
}
+ AR_WRITE_BARRIER(sc);
DPRINTFN(4, ("AR9280_PHY_SYNTH_CONTROL=0x%08x\n", phy));
AR_WRITE(sc, AR9280_PHY_SYNTH_CONTROL, phy);
+ AR_WRITE_BARRIER(sc);
return (0);
}
@@ -295,24 +297,28 @@ ar9280_init_from_rom(struct athn_softc *sc, struct ieee80211_channel *c,
reg = RW(reg, AR_AN_RF2G1_CH0_OB, modal->ob);
reg = RW(reg, AR_AN_RF2G1_CH0_DB, modal->db);
AR_WRITE(sc, AR_AN_RF2G1_CH0, reg);
+ AR_WRITE_BARRIER(sc);
DELAY(100);
reg = AR_READ(sc, AR_AN_RF2G1_CH1);
reg = RW(reg, AR_AN_RF2G1_CH1_OB, modal->ob_ch1);
reg = RW(reg, AR_AN_RF2G1_CH1_DB, modal->db_ch1);
AR_WRITE(sc, AR_AN_RF2G1_CH1, reg);
+ AR_WRITE_BARRIER(sc);
DELAY(100);
} else {
reg = AR_READ(sc, AR_AN_RF5G1_CH0);
reg = RW(reg, AR_AN_RF5G1_CH0_OB5, modal->ob);
reg = RW(reg, AR_AN_RF5G1_CH0_DB5, modal->db);
AR_WRITE(sc, AR_AN_RF5G1_CH0, reg);
+ AR_WRITE_BARRIER(sc);
DELAY(100);
reg = AR_READ(sc, AR_AN_RF5G1_CH1);
reg = RW(reg, AR_AN_RF5G1_CH1_OB5, modal->ob_ch1);
reg = RW(reg, AR_AN_RF5G1_CH1_DB5, modal->db_ch1);
AR_WRITE(sc, AR_AN_RF5G1_CH1, reg);
+ AR_WRITE_BARRIER(sc);
DELAY(100);
}
reg = AR_READ(sc, AR_AN_TOP2);
@@ -322,6 +328,7 @@ ar9280_init_from_rom(struct athn_softc *sc, struct ieee80211_channel *c,
else
reg &= ~AR_AN_TOP2_LOCALBIAS;
AR_WRITE(sc, AR_AN_TOP2, reg);
+ AR_WRITE_BARRIER(sc);
DELAY(100);
reg = AR_READ(sc, AR_PHY_XPA_CFG);
@@ -388,6 +395,7 @@ ar9280_init_from_rom(struct athn_softc *sc, struct ieee80211_channel *c,
else
reg &= ~AR_AN_TOP1_DACLPMODE;
AR_WRITE(sc, AR_AN_TOP1, reg);
+ AR_WRITE_BARRIER(sc);
DELAY(100);
reg = AR_READ(sc, AR_PHY_FRAME_CTL);
@@ -400,6 +408,7 @@ ar9280_init_from_rom(struct athn_softc *sc, struct ieee80211_channel *c,
eep->baseEepHeader.desiredScaleCCK);
AR_WRITE(sc, AR_PHY_TX_PWRCTRL9, reg);
}
+ AR_WRITE_BARRIER(sc);
}
void
@@ -523,6 +532,7 @@ ar9280_spur_mitigate(struct athn_softc *sc, struct ieee80211_channel *c,
AR_WRITE(sc, AR_PHY_SFCORR_EXT,
SM(AR_PHY_SFCORR_SPUR_SUBCHNL_SD, spur_subchannel_sd));
+ AR_WRITE_BARRIER(sc);
bin = spur * 320;
ar5008_set_viterbi_mask(sc, bin);
@@ -609,4 +619,5 @@ ar9280_olpc_temp_compensation(struct athn_softc *sc)
reg = RW(reg, AR_PHY_TX_GAIN, txgain);
AR_WRITE(sc, AR_PHY_TX_GAIN_TBL(i), reg);
}
+ AR_WRITE_BARRIER(sc);
}
diff --git a/sys/dev/ic/ar9285.c b/sys/dev/ic/ar9285.c
index a5d12831168..f9085b432a6 100644
--- a/sys/dev/ic/ar9285.c
+++ b/sys/dev/ic/ar9285.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: ar9285.c,v 1.12 2010/08/12 16:34:53 damien Exp $ */
+/* $OpenBSD: ar9285.c,v 1.13 2010/12/31 14:06:05 damien Exp $ */
/*-
* Copyright (c) 2009-2010 Damien Bergamini <damien.bergamini@free.fr>
@@ -309,6 +309,7 @@ ar9285_init_from_rom(struct athn_softc *sc, struct ieee80211_channel *c,
reg = RW(reg, AR9285_AN_RF2G3_DB1_1, db1[1]);
reg = RW(reg, AR9285_AN_RF2G3_DB1_2, db1[2]);
AR_WRITE(sc, AR9285_AN_RF2G3, reg);
+ AR_WRITE_BARRIER(sc);
DELAY(100);
reg = AR_READ(sc, AR9285_AN_RF2G4);
reg = RW(reg, AR9285_AN_RF2G4_DB1_3, db1[3]);
@@ -319,6 +320,7 @@ ar9285_init_from_rom(struct athn_softc *sc, struct ieee80211_channel *c,
reg = RW(reg, AR9285_AN_RF2G4_DB2_3, db2[3]);
reg = RW(reg, AR9285_AN_RF2G4_DB2_4, db2[4]);
AR_WRITE(sc, AR9285_AN_RF2G4, reg);
+ AR_WRITE_BARRIER(sc);
DELAY(100);
reg = AR_READ(sc, AR_PHY_SETTLING);
@@ -362,6 +364,7 @@ ar9285_init_from_rom(struct athn_softc *sc, struct ieee80211_channel *c,
AR_WRITE(sc, AR_PHY_SETTLING, reg);
}
#endif
+ AR_WRITE_BARRIER(sc);
}
void
@@ -421,6 +424,7 @@ ar9285_pa_calib(struct athn_softc *sc)
AR_WRITE(sc, AR9285_AN_RF2G6, reg);
AR_WRITE(sc, AR9285_AN_TOP2, AR9285_AN_TOP2_DEFAULT);
+ AR_WRITE_BARRIER(sc);
DELAY(30);
/* Clear offsets 6-1. */
@@ -431,6 +435,7 @@ ar9285_pa_calib(struct athn_softc *sc)
/* Set offsets 6-1. */
for (i = 6; i >= 1; i--) {
AR_SETBITS(sc, AR9285_AN_RF2G6, AR9285_AN_RF2G6_OFFS(i));
+ AR_WRITE_BARRIER(sc);
DELAY(1);
if (AR_READ(sc, AR9285_AN_RF2G9) & AR9285_AN_RXTXBB1_SPARE9) {
AR_SETBITS(sc, AR9285_AN_RF2G6,
@@ -442,6 +447,7 @@ ar9285_pa_calib(struct athn_softc *sc)
}
/* Set offset 0. */
AR_SETBITS(sc, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP);
+ AR_WRITE_BARRIER(sc);
DELAY(1);
if (AR_READ(sc, AR9285_AN_RF2G9) & AR9285_AN_RXTXBB1_SPARE9)
AR_SETBITS(sc, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP);
@@ -459,6 +465,7 @@ ar9285_pa_calib(struct athn_softc *sc)
reg = AR_READ(sc, AR9285_AN_RF2G6);
reg = RW(reg, AR9285_AN_RF2G6_CCOMP, ccomp_svg);
AR_WRITE(sc, AR9285_AN_RF2G6, reg);
+ AR_WRITE_BARRIER(sc);
}
/*
@@ -507,6 +514,7 @@ ar9285_cl_cal(struct athn_softc *sc, struct ieee80211_channel *c,
AR_SETBITS(sc, AR_PHY_ADC_CTL, AR_PHY_ADC_CTL_OFF_PWDADC);
AR_CLRBITS(sc, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);
AR_CLRBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_FLTR_CAL);
+ AR_WRITE_BARRIER(sc);
return (0);
}
@@ -553,8 +561,10 @@ ar9285_init_calib(struct athn_softc *sc, struct ieee80211_channel *c,
else
reg = RW(reg, AR9285_AN_RF2G5_IC50TX, 0x4);
AR_WRITE(sc, AR9285_AN_RF2G5, reg);
+ AR_WRITE_BARRIER(sc);
error = ar9285_cl_cal(sc, c, extc);
AR_WRITE(sc, AR9285_AN_RF2G5, rf2g5_svg);
+ AR_WRITE_BARRIER(sc);
return (error);
}
@@ -639,6 +649,7 @@ ar9285_set_power_calib(struct athn_softc *sc, struct ieee80211_channel *c)
pdadcs[i + 2] << 16 |
pdadcs[i + 3] << 24);
}
+ AR_WRITE_BARRIER(sc);
}
void
diff --git a/sys/dev/ic/ar9287.c b/sys/dev/ic/ar9287.c
index 7c1b76166d4..381b0ce9ca6 100644
--- a/sys/dev/ic/ar9287.c
+++ b/sys/dev/ic/ar9287.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: ar9287.c,v 1.14 2010/08/12 16:32:31 damien Exp $ */
+/* $OpenBSD: ar9287.c,v 1.15 2010/12/31 14:06:05 damien Exp $ */
/*-
* Copyright (c) 2009 Damien Bergamini <damien.bergamini@free.fr>
@@ -245,6 +245,7 @@ ar9287_init_from_rom(struct athn_softc *sc, struct ieee80211_channel *c,
reg = RW(reg, AR9287_AN_RF2G3_OB_QAM, modal->ob_qam);
reg = RW(reg, AR9287_AN_RF2G3_OB_PAL_OFF, modal->ob_pal_off);
AR_WRITE(sc, AR9287_AN_RF2G3_CH0, reg);
+ AR_WRITE_BARRIER(sc);
DELAY(100);
reg = AR_READ(sc, AR9287_AN_RF2G3_CH1);
@@ -255,6 +256,7 @@ ar9287_init_from_rom(struct athn_softc *sc, struct ieee80211_channel *c,
reg = RW(reg, AR9287_AN_RF2G3_OB_QAM, modal->ob_qam);
reg = RW(reg, AR9287_AN_RF2G3_OB_PAL_OFF, modal->ob_pal_off);
AR_WRITE(sc, AR9287_AN_RF2G3_CH1, reg);
+ AR_WRITE_BARRIER(sc);
DELAY(100);
reg = AR_READ(sc, AR_PHY_RF_CTL2);
@@ -265,6 +267,7 @@ ar9287_init_from_rom(struct athn_softc *sc, struct ieee80211_channel *c,
reg = AR_READ(sc, AR9287_AN_TOP2);
reg = RW(reg, AR9287_AN_TOP2_XPABIAS_LVL, modal->xpaBiasLvl);
AR_WRITE(sc, AR9287_AN_TOP2, reg);
+ AR_WRITE_BARRIER(sc);
DELAY(100);
}
@@ -378,6 +381,7 @@ ar9287_set_power_calib(struct athn_softc *sc, struct ieee80211_channel *c)
reg = RW(reg, AR_PHY_TPCRG1_PD_GAIN_1, xpdgains[0]);
reg = RW(reg, AR_PHY_TPCRG1_PD_GAIN_2, xpdgains[1]);
AR_WRITE(sc, AR_PHY_TPCRG1, reg);
+ AR_WRITE_BARRIER(sc);
for (i = 0; i < AR9287_MAX_CHAINS; i++) {
if (!(sc->txchainmask & (1 << i)))
@@ -401,6 +405,7 @@ ar9287_set_power_calib(struct athn_softc *sc, struct ieee80211_channel *c)
reg = RW(reg, AR_PHY_TX_PWRCTRL_OLPC_PWR, txpower);
AR_WRITE(sc, AR_PHY_CH0_TX_PWRCTRL11 + offset, reg);
+ AR_WRITE_BARRIER(sc);
continue; /* That's it for open loop mode. */
}
@@ -430,6 +435,7 @@ ar9287_set_power_calib(struct athn_softc *sc, struct ieee80211_channel *c)
pdadcs[j + 2] << 16 |
pdadcs[j + 3] << 24);
}
+ AR_WRITE_BARRIER(sc);
}
}
@@ -551,6 +557,7 @@ ar9287_olpc_init(struct athn_softc *sc)
reg = RW(reg, AR9287_AN_TXPC0_TXPCMODE,
AR9287_AN_TXPC0_TXPCMODE_TEMPSENSE);
AR_WRITE(sc, AR9287_AN_TXPC0, reg);
+ AR_WRITE_BARRIER(sc);
DELAY(100);
}
@@ -587,6 +594,7 @@ ar9287_olpc_temp_compensation(struct athn_softc *sc)
reg = AR_READ(sc, AR_PHY_CH1_TX_PWRCTRL11);
reg = RW(reg, AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP, tcomp);
AR_WRITE(sc, AR_PHY_CH1_TX_PWRCTRL11, reg);
+ AR_WRITE_BARRIER(sc);
}
void
@@ -600,6 +608,7 @@ ar9287_1_3_enable_async_fifo(struct athn_softc *sc)
AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
AR_SETBITS(sc, AR_MAC_PCU_ASYNC_FIFO_REG3,
AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
+ AR_WRITE_BARRIER(sc);
}
void
@@ -626,4 +635,5 @@ ar9287_1_3_setup_async_fifo(struct athn_softc *sc)
AR_WRITE(sc, AR_AHB_MODE, reg);
AR_SETBITS(sc, AR_PCU_MISC_MODE2, AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
+ AR_WRITE_BARRIER(sc);
}
diff --git a/sys/dev/ic/ar9380.c b/sys/dev/ic/ar9380.c
index 6b90f8727f9..6e50027417a 100644
--- a/sys/dev/ic/ar9380.c
+++ b/sys/dev/ic/ar9380.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: ar9380.c,v 1.7 2010/11/10 21:06:44 damien Exp $ */
+/* $OpenBSD: ar9380.c,v 1.8 2010/12/31 14:06:05 damien Exp $ */
/*-
* Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr>
@@ -253,13 +253,16 @@ ar9380_set_synth(struct athn_softc *sc, struct ieee80211_channel *c,
/* Enable Long Shift Select for synthesizer. */
AR_SETBITS(sc, AR_PHY_65NM_CH0_SYNTH4,
AR_PHY_SYNTH4_LONG_SHIFT_SELECT);
+ AR_WRITE_BARRIER(sc);
/* Program synthesizer. */
phy = (chansel << 2) | AR9380_FRACMODE;
DPRINTFN(4, ("AR_PHY_65NM_CH0_SYNTH7=0x%08x\n", phy));
AR_WRITE(sc, AR_PHY_65NM_CH0_SYNTH7, phy);
+ AR_WRITE_BARRIER(sc);
/* Toggle Load Synth Channel bit. */
AR_WRITE(sc, AR_PHY_65NM_CH0_SYNTH7, phy | AR9380_LOAD_SYNTH);
+ AR_WRITE_BARRIER(sc);
return (0);
}
@@ -361,6 +364,7 @@ ar9380_init_from_rom(struct athn_softc *sc, struct ieee80211_channel *c,
AR_RTC_REG_CONTROL1_SWREG_PROGRAM);
} else
AR_SETBITS(sc, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_SWREG_PRD);
+ AR_WRITE_BARRIER(sc);
}
void
@@ -386,6 +390,7 @@ ar9380_spur_mitigate_cck(struct athn_softc *sc, struct ieee80211_channel *c,
reg = RW(reg, AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ, 0);
reg &= ~AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT;
AR_WRITE(sc, AR_PHY_CCK_SPUR_MIT, reg);
+ AR_WRITE_BARRIER(sc);
return;
}
freq = (spur * 524288) / 11;
@@ -400,6 +405,7 @@ ar9380_spur_mitigate_cck(struct athn_softc *sc, struct ieee80211_channel *c,
reg = RW(reg, AR_PHY_CCK_SPUR_MIT_SPUR_FILTER_TYPE, 0x2);
reg |= AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT;
AR_WRITE(sc, AR_PHY_CCK_SPUR_MIT, reg);
+ AR_WRITE_BARRIER(sc);
}
void
@@ -440,6 +446,7 @@ ar9380_spur_mitigate_ofdm(struct athn_softc *sc, struct ieee80211_channel *c,
reg &= ~AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT;
reg &= ~AR_PHY_SPUR_REG_ENABLE_MASK_PPM;
AR_WRITE(sc, AR_PHY_SPUR_REG, reg);
+ AR_WRITE_BARRIER(sc);
freq = c->ic_freq;
#ifndef IEEE80211_NO_HT
@@ -541,6 +548,7 @@ ar9380_spur_mitigate_ofdm(struct athn_softc *sc, struct ieee80211_channel *c,
reg = RW(reg, AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A, idx);
reg = RW(reg, AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A, 0x0c);
AR_WRITE(sc, AR_PHY_CHAN_SPUR_MASK, reg);
+ AR_WRITE_BARRIER(sc);
}
void
@@ -747,4 +755,5 @@ ar9380_set_correction(struct athn_softc *sc, struct ieee80211_channel *c)
reg = AR_READ(sc, AR_PHY_TPC_18);
reg = RW(reg, AR_PHY_TPC_18_THERM_CAL, temp0);
AR_WRITE(sc, AR_PHY_TPC_18, reg);
+ AR_WRITE_BARRIER(sc);
}
diff --git a/sys/dev/ic/athn.c b/sys/dev/ic/athn.c
index 6719cecf029..8c88d91895a 100644
--- a/sys/dev/ic/athn.c
+++ b/sys/dev/ic/athn.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: athn.c,v 1.63 2010/08/27 17:08:00 jsg Exp $ */
+/* $OpenBSD: athn.c,v 1.64 2010/12/31 14:06:05 damien Exp $ */
/*-
* Copyright (c) 2009 Damien Bergamini <damien.bergamini@free.fr>
@@ -482,6 +482,7 @@ athn_rx_start(struct athn_softc *sc)
/* Start PCU Rx. */
AR_CLRBITS(sc, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT);
+ AR_WRITE_BARRIER(sc);
}
void
@@ -502,6 +503,7 @@ athn_set_rxfilter(struct athn_softc *sc, uint32_t rfilt)
AR_WRITE(sc, AR_PHY_ERR, 0);
AR_CLRBITS(sc, AR_RXCFG, AR_RXCFG_ZLFDMA);
#endif
+ AR_WRITE_BARRIER(sc);
}
int
@@ -595,6 +597,7 @@ athn_reset_power_on(struct athn_softc *sc)
}
/* RTC reset and clear. */
AR_WRITE(sc, AR_RTC_RESET, 0);
+ AR_WRITE_BARRIER(sc);
DELAY(2);
if (!AR_SREV_9380_10_OR_LATER(sc))
AR_WRITE(sc, AR_RC, 0);
@@ -637,6 +640,7 @@ athn_reset(struct athn_softc *sc, int cold)
AR_WRITE(sc, AR_RTC_RC, AR_RTC_RC_MAC_WARM |
(cold ? AR_RTC_RC_MAC_COLD : 0));
+ AR_WRITE_BARRIER(sc);
DELAY(50);
AR_WRITE(sc, AR_RTC_RC, 0);
for (ntries = 0; ntries < 1000; ntries++) {
@@ -650,6 +654,7 @@ athn_reset(struct athn_softc *sc, int cold)
return (ETIMEDOUT);
}
AR_WRITE(sc, AR_RC, 0);
+ AR_WRITE_BARRIER(sc);
return (0);
}
@@ -667,6 +672,7 @@ athn_set_power_awake(struct athn_softc *sc)
athn_init_pll(sc, NULL);
}
AR_SETBITS(sc, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN);
+ AR_WRITE_BARRIER(sc);
DELAY(50); /* Give chip the chance to awake. */
/* Poll until RTC is ON. */
@@ -683,6 +689,7 @@ athn_set_power_awake(struct athn_softc *sc)
}
AR_CLRBITS(sc, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
+ AR_WRITE_BARRIER(sc);
return (0);
}
@@ -700,6 +707,7 @@ athn_set_power_sleep(struct athn_softc *sc)
*/
if (!AR_SREV_5416(sc))
AR_CLRBITS(sc, AR_RTC_RESET, AR_RTC_RESET_EN);
+ AR_WRITE_BARRIER(sc);
}
void
@@ -736,8 +744,10 @@ athn_init_pll(struct athn_softc *sc, const struct ieee80211_channel *c)
}
DPRINTFN(5, ("AR_RTC_PLL_CONTROL=0x%08x\n", pll));
AR_WRITE(sc, AR_RTC_PLL_CONTROL, pll);
+ AR_WRITE_BARRIER(sc);
DELAY(100);
AR_WRITE(sc, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
+ AR_WRITE_BARRIER(sc);
}
void
@@ -749,6 +759,7 @@ athn_write_serdes(struct athn_softc *sc, const uint32_t val[9])
for (i = 0; i < 288 / 32; i++)
AR_WRITE(sc, AR_PCIE_SERDES, val[i]);
AR_WRITE(sc, AR_PCIE_SERDES2, 0);
+ AR_WRITE_BARRIER(sc);
}
void
@@ -766,6 +777,7 @@ athn_config_pcie(struct athn_softc *sc)
#else
AR_WRITE(sc, AR_WA, ATHN_PCIE_WAEN);
#endif
+ AR_WRITE_BARRIER(sc);
}
void
@@ -909,6 +921,8 @@ athn_reset_key(struct athn_softc *sc, int entry)
AR_WRITE(sc, AR_KEYTABLE_MAC0(entry), 0);
AR_WRITE(sc, AR_KEYTABLE_MAC1(entry), 0);
+
+ AR_WRITE_BARRIER(sc);
}
int
@@ -987,6 +1001,7 @@ athn_set_key(struct ieee80211com *ic, struct ieee80211_node *ni,
lo = hi = 0;
AR_WRITE(sc, AR_KEYTABLE_MAC0(entry), lo);
AR_WRITE(sc, AR_KEYTABLE_MAC1(entry), hi | AR_KEYTABLE_VALID);
+ AR_WRITE_BARRIER(sc);
return (0);
}
@@ -1044,6 +1059,7 @@ athn_btcoex_init(struct athn_softc *sc)
reg = RW(reg, AR_GPIO_INPUT_MUX1_BT_ACTIVE,
AR_GPIO_BTACTIVE_PIN);
AR_WRITE(sc, AR_GPIO_INPUT_MUX1, reg);
+ AR_WRITE_BARRIER(sc);
ops->gpio_config_input(sc, AR_GPIO_BTACTIVE_PIN);
} else { /* 3-wire. */
@@ -1057,6 +1073,7 @@ athn_btcoex_init(struct athn_softc *sc)
reg = RW(reg, AR_GPIO_INPUT_MUX1_BT_PRIORITY,
AR_GPIO_BTPRIORITY_PIN);
AR_WRITE(sc, AR_GPIO_INPUT_MUX1, reg);
+ AR_WRITE_BARRIER(sc);
ops->gpio_config_input(sc, AR_GPIO_BTACTIVE_PIN);
ops->gpio_config_input(sc, AR_GPIO_BTPRIORITY_PIN);
@@ -1086,6 +1103,7 @@ athn_btcoex_enable(struct athn_softc *sc)
AR_SETBITS(sc, AR_QUIET1, AR_QUIET1_QUIET_ACK_CTS_ENABLE);
AR_CLRBITS(sc, AR_PCU_MISC, AR_PCU_BT_ANT_PREVENT_RX);
+ AR_WRITE_BARRIER(sc);
ops->gpio_config_output(sc, AR_GPIO_WLANACTIVE_PIN,
AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL);
@@ -1098,6 +1116,7 @@ athn_btcoex_enable(struct athn_softc *sc)
reg &= ~(0x3 << (AR_GPIO_WLANACTIVE_PIN * 2));
reg |= 0x2 << (AR_GPIO_WLANACTIVE_PIN * 2);
AR_WRITE(sc, AR_GPIO_PDPU, reg);
+ AR_WRITE_BARRIER(sc);
/* Disable PCIe Active State Power Management (ASPM). */
if (sc->sc_disable_aspm != NULL)
@@ -1123,6 +1142,7 @@ athn_btcoex_disable(struct athn_softc *sc)
AR_WRITE(sc, AR_BT_COEX_MODE2, 0);
/* XXX Stop periodic timer. */
}
+ AR_WRITE_BARRIER(sc);
/* XXX Restore ASPM setting? */
}
#endif
@@ -1416,6 +1436,7 @@ athn_ani_restart(struct athn_softc *sc)
AR_WRITE(sc, AR_PHY_ERR_2, 0);
AR_WRITE(sc, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
AR_WRITE(sc, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
+ AR_WRITE_BARRIER(sc);
ani->listen_time = 0;
ani->ofdm_phy_err_count = 0;
@@ -1465,9 +1486,10 @@ athn_ani_monitor(struct athn_softc *sc)
AR_WRITE(sc, AR_PHY_ERR_2, ani->cck_phy_err_base);
AR_WRITE(sc, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
}
- if (phy1 < ani->ofdm_phy_err_base || phy2 < ani->cck_phy_err_base)
+ if (phy1 < ani->ofdm_phy_err_base || phy2 < ani->cck_phy_err_base) {
+ AR_WRITE_BARRIER(sc);
return;
-
+ }
ani->ofdm_phy_err_count = phy1 - ani->ofdm_phy_err_base;
ani->cck_phy_err_count = phy2 - ani->cck_phy_err_base;
@@ -1562,6 +1584,7 @@ athn_init_dma(struct athn_softc *sc)
AR_WRITE(sc, AR_PCU_TXBUF_CTRL, AR_SREV_9285(sc) ?
AR9285_PCU_TXBUF_CTRL_USABLE_SIZE :
AR_PCU_TXBUF_CTRL_USABLE_SIZE);
+ AR_WRITE_BARRIER(sc);
/* Reset Tx status ring. */
if (AR_SREV_9380_10_OR_LATER(sc))
@@ -1583,6 +1606,7 @@ athn_inc_tx_trigger_level(struct athn_softc *sc)
return; /* Already at max. */
reg = RW(reg, AR_TXCFG_FTRIG, ftrig + 1);
AR_WRITE(sc, AR_TXCFG, reg);
+ AR_WRITE_BARRIER(sc);
}
int
@@ -1614,6 +1638,7 @@ athn_rx_abort(struct athn_softc *sc)
}
DPRINTF(("Rx failed to go idle in 10ms\n"));
AR_CLRBITS(sc, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT);
+ AR_WRITE_BARRIER(sc);
return (ETIMEDOUT);
}
@@ -1671,8 +1696,10 @@ athn_stop_tx_dma(struct athn_softc *sc, int qid)
break;
}
AR_SETBITS(sc, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
+ AR_WRITE_BARRIER(sc);
DELAY(200);
AR_CLRBITS(sc, AR_TIMER_MODE, AR_QUIET_TIMER_EN);
+ AR_WRITE_BARRIER(sc);
for (ntries = 0; ntries < 40; ntries++) {
if (!athn_tx_pending(sc, qid))
@@ -1683,6 +1710,7 @@ athn_stop_tx_dma(struct athn_softc *sc, int qid)
AR_CLRBITS(sc, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
}
AR_WRITE(sc, AR_Q_TXD, 0);
+ AR_WRITE_BARRIER(sc);
}
int
@@ -1768,6 +1796,7 @@ athn_init_tx_queues(struct athn_softc *sc)
AR_WRITE(sc, AR_IMR_S0, 0x00ff0000);
/* Enable EOL interrupts for all Tx queues except UAPSD. */
AR_WRITE(sc, AR_IMR_S1, 0x00df0000);
+ AR_WRITE_BARRIER(sc);
}
void
@@ -1834,6 +1863,8 @@ athn_set_sta_timers(struct athn_softc *sc)
/* Set TSF out-of-range threshold (fixed at 16k us). */
AR_WRITE(sc, AR_TSFOOR_THRESHOLD, 0x4240);
+
+ AR_WRITE_BARRIER(sc);
}
#ifndef IEEE80211_STA_ONLY
@@ -1860,6 +1891,8 @@ athn_set_hostap_timers(struct athn_softc *sc)
AR_WRITE(sc, AR_TIMER_MODE,
AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN);
+
+ AR_WRITE_BARRIER(sc);
}
#endif
@@ -1895,6 +1928,7 @@ athn_set_opmode(struct athn_softc *sc)
AR_WRITE(sc, AR_STA_ID1, reg);
break;
}
+ AR_WRITE_BARRIER(sc);
}
void
@@ -1905,6 +1939,7 @@ athn_set_bss(struct athn_softc *sc, struct ieee80211_node *ni)
AR_WRITE(sc, AR_BSS_ID0, LE_READ_4(&bssid[0]));
AR_WRITE(sc, AR_BSS_ID1, LE_READ_2(&bssid[4]) |
SM(AR_BSS_ID1_AID, IEEE80211_AID(ni->ni_associd)));
+ AR_WRITE_BARRIER(sc);
}
void
@@ -1931,6 +1966,7 @@ athn_enable_interrupts(struct athn_softc *sc)
AR_WRITE(sc, AR_INTR_SYNC_ENABLE, sc->isync);
AR_WRITE(sc, AR_INTR_SYNC_MASK, sc->isync);
+ AR_WRITE_BARRIER(sc);
}
void
@@ -1952,6 +1988,7 @@ athn_disable_interrupts(struct athn_softc *sc)
AR_IMR_S2_TSFOOR | AR_IMR_S2_GTT | AR_IMR_S2_CST);
AR_CLRBITS(sc, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
+ AR_WRITE_BARRIER(sc);
}
void
@@ -1970,6 +2007,7 @@ athn_init_qos(struct athn_softc *sc)
AR_WRITE(sc, AR_TXOP_4_7, 0xffffffff);
AR_WRITE(sc, AR_TXOP_8_11, 0xffffffff);
AR_WRITE(sc, AR_TXOP_12_15, 0xffffffff);
+ AR_WRITE_BARRIER(sc);
}
int
@@ -2168,6 +2206,8 @@ athn_hw_reset(struct athn_softc *sc, struct ieee80211_channel *c,
/* Default is little-endian, turn on swapping for big-endian. */
AR_WRITE(sc, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
#endif
+ AR_WRITE_BARRIER(sc);
+
return (0);
}
@@ -2315,6 +2355,7 @@ athn_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg)
reg = (reg & ~AR_RX_FILTER_BEACON) |
AR_RX_FILTER_MYBEACON;
AR_WRITE(sc, AR_RX_FILTER, reg);
+ AR_WRITE_BARRIER(sc);
}
athn_enable_interrupts(sc);
@@ -2356,6 +2397,7 @@ athn_updateedca(struct ieee80211com *ic)
} else
AR_WRITE(sc, AR_DCHNTIME(qid), 0);
}
+ AR_WRITE_BARRIER(sc);
#undef ATHN_EXP2
}
@@ -2389,6 +2431,7 @@ athn_updateslot(struct ieee80211com *ic)
slot = (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20;
AR_WRITE(sc, AR_D_GBL_IFS_SLOT, slot * athn_clock_rate(sc));
+ AR_WRITE_BARRIER(sc);
}
void
@@ -2502,6 +2545,7 @@ athn_set_multi(struct athn_softc *sc)
done:
AR_WRITE(sc, AR_MCAST_FIL0, lo);
AR_WRITE(sc, AR_MCAST_FIL1, hi);
+ AR_WRITE_BARRIER(sc);
}
int
@@ -2710,6 +2754,7 @@ athn_stop(struct ifnet *ifp, int disable)
AR_WRITE(sc, AR_MIBC, AR_MIBC_CMC);
AR_WRITE(sc, AR_FILT_OFDM, 0);
AR_WRITE(sc, AR_FILT_CCK, 0);
+ AR_WRITE_BARRIER(sc);
athn_set_rxfilter(sc, 0);
athn_stop_rx_dma(sc);
diff --git a/sys/dev/ic/athnreg.h b/sys/dev/ic/athnreg.h
index 172aa035979..edfa1fd2644 100644
--- a/sys/dev/ic/athnreg.h
+++ b/sys/dev/ic/athnreg.h
@@ -1,4 +1,4 @@
-/* $OpenBSD: athnreg.h,v 1.13 2010/06/21 19:54:28 damien Exp $ */
+/* $OpenBSD: athnreg.h,v 1.14 2010/12/31 14:06:05 damien Exp $ */
/*-
* Copyright (c) 2009 Damien Bergamini <damien.bergamini@free.fr>
@@ -1440,10 +1440,13 @@ static const uint32_t ar_nonpcie_serdes[] = {
* Macros to access registers.
*/
#define AR_READ(sc, reg) \
- bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))
+ sc->ops.read((sc), (reg))
#define AR_WRITE(sc, reg, val) \
- bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))
+ sc->ops.write((sc), (reg), (val))
+
+#define AR_WRITE_BARRIER(sc) \
+ sc->ops.write_barrier((sc))
#define AR_SETBITS(sc, reg, mask) \
AR_WRITE(sc, reg, AR_READ(sc, reg) | (mask))
diff --git a/sys/dev/ic/athnvar.h b/sys/dev/ic/athnvar.h
index 8b777734700..090e66b424e 100644
--- a/sys/dev/ic/athnvar.h
+++ b/sys/dev/ic/athnvar.h
@@ -1,4 +1,4 @@
-/* $OpenBSD: athnvar.h,v 1.25 2010/11/10 21:06:44 damien Exp $ */
+/* $OpenBSD: athnvar.h,v 1.26 2010/12/31 14:06:05 damien Exp $ */
/*-
* Copyright (c) 2009 Damien Bergamini <damien.bergamini@free.fr>
@@ -16,7 +16,9 @@
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
-/*#define ATHN_BT_COEXISTENCE 1*/
+#ifdef notyet
+#define ATHN_BT_COEXISTENCE 1
+#endif
#ifdef ATHN_DEBUG
#define DPRINTF(x) do { if (athn_debug > 0) printf x; } while (0)
@@ -346,6 +348,11 @@ struct athn_calib {
struct athn_softc;
struct athn_ops {
+ /* Bus callbacks. */
+ uint32_t (*read)(struct athn_softc *, uint32_t);
+ void (*write)(struct athn_softc *, uint32_t, uint32_t);
+ void (*write_barrier)(struct athn_softc *);
+
void (*setup)(struct athn_softc *);
void (*set_txpower)(struct athn_softc *, struct ieee80211_channel *,
struct ieee80211_channel *);
@@ -417,8 +424,6 @@ struct athn_softc {
enum ieee80211_state, int);
bus_dma_tag_t sc_dmat;
- bus_space_tag_t sc_st;
- bus_space_handle_t sc_sh;
struct timeout scan_to;
struct timeout calib_to;
@@ -426,20 +431,21 @@ struct athn_softc {
u_int flags;
#define ATHN_FLAG_PCIE (1 << 0)
-#define ATHN_FLAG_OLPC (1 << 1)
-#define ATHN_FLAG_PAPRD (1 << 2)
-#define ATHN_FLAG_FAST_PLL_CLOCK (1 << 3)
-#define ATHN_FLAG_RFSILENT (1 << 4)
-#define ATHN_FLAG_RFSILENT_REVERSED (1 << 5)
-#define ATHN_FLAG_BTCOEX2WIRE (1 << 6)
-#define ATHN_FLAG_BTCOEX3WIRE (1 << 7)
+#define ATHN_FLAG_USB (1 << 1)
+#define ATHN_FLAG_OLPC (1 << 2)
+#define ATHN_FLAG_PAPRD (1 << 3)
+#define ATHN_FLAG_FAST_PLL_CLOCK (1 << 4)
+#define ATHN_FLAG_RFSILENT (1 << 5)
+#define ATHN_FLAG_RFSILENT_REVERSED (1 << 6)
+#define ATHN_FLAG_BTCOEX2WIRE (1 << 7)
+#define ATHN_FLAG_BTCOEX3WIRE (1 << 8)
/* Shortcut. */
#define ATHN_FLAG_BTCOEX (ATHN_FLAG_BTCOEX2WIRE | ATHN_FLAG_BTCOEX3WIRE)
-#define ATHN_FLAG_11A (1 << 8)
-#define ATHN_FLAG_11G (1 << 9)
-#define ATHN_FLAG_11N (1 << 10)
-#define ATHN_FLAG_AN_TOP2_FIXUP (1 << 11)
-#define ATHN_FLAG_NON_ENTERPRISE (1 << 12)
+#define ATHN_FLAG_11A (1 << 9)
+#define ATHN_FLAG_11G (1 << 10)
+#define ATHN_FLAG_11N (1 << 11)
+#define ATHN_FLAG_AN_TOP2_FIXUP (1 << 12)
+#define ATHN_FLAG_NON_ENTERPRISE (1 << 13)
uint8_t ngpiopins;
int led_pin;
diff --git a/sys/dev/pci/if_athn_pci.c b/sys/dev/pci/if_athn_pci.c
index e219d848f74..37a64f0a7cd 100644
--- a/sys/dev/pci/if_athn_pci.c
+++ b/sys/dev/pci/if_athn_pci.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: if_athn_pci.c,v 1.8 2010/08/04 19:49:49 damien Exp $ */
+/* $OpenBSD: if_athn_pci.c,v 1.9 2010/12/31 14:06:05 damien Exp $ */
/*-
* Copyright (c) 2009 Damien Bergamini <damien.bergamini@free.fr>
@@ -65,17 +65,22 @@ struct athn_pci_softc {
pci_chipset_tag_t sc_pc;
pcitag_t sc_tag;
void *sc_ih;
+ bus_space_tag_t sc_st;
+ bus_space_handle_t sc_sh;
bus_size_t sc_mapsize;
int sc_cap_off;
struct workq_task sc_resume_wqt;
};
-int athn_pci_match(struct device *, void *, void *);
-void athn_pci_attach(struct device *, struct device *, void *);
-int athn_pci_detach(struct device *, int);
-int athn_pci_activate(struct device *, int);
-void athn_pci_resume(void *, void *);
-void athn_pci_disable_aspm(struct athn_softc *);
+int athn_pci_match(struct device *, void *, void *);
+void athn_pci_attach(struct device *, struct device *, void *);
+int athn_pci_detach(struct device *, int);
+int athn_pci_activate(struct device *, int);
+void athn_pci_resume(void *, void *);
+uint32_t athn_pci_read(struct athn_softc *, uint32_t);
+void athn_pci_write(struct athn_softc *, uint32_t, uint32_t);
+void athn_pci_write_barrier(struct athn_softc *);
+void athn_pci_disable_aspm(struct athn_softc *);
struct cfattach athn_pci_ca = {
sizeof (struct athn_pci_softc),
@@ -121,6 +126,10 @@ athn_pci_attach(struct device *parent, struct device *self, void *aux)
psc->sc_pc = pa->pa_pc;
psc->sc_tag = pa->pa_tag;
+ sc->ops.read = athn_pci_read;
+ sc->ops.write = athn_pci_write;
+ sc->ops.write_barrier = athn_pci_write_barrier;
+
/*
* Get the offset of the PCI Express Capability Structure in PCI
* Configuration Space (Linux hardcodes it as 0x60.)
@@ -157,8 +166,8 @@ athn_pci_attach(struct device *parent, struct device *self, void *aux)
/* Map control/status registers. */
memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, PCI_MAPREG_START);
- error = pci_mapreg_map(pa, PCI_MAPREG_START, memtype, 0, &sc->sc_st,
- &sc->sc_sh, NULL, &psc->sc_mapsize, 0);
+ error = pci_mapreg_map(pa, PCI_MAPREG_START, memtype, 0, &psc->sc_st,
+ &psc->sc_sh, NULL, &psc->sc_mapsize, 0);
if (error != 0) {
printf(": can't map mem space\n");
return;
@@ -194,7 +203,7 @@ athn_pci_detach(struct device *self, int flags)
pci_intr_disestablish(psc->sc_pc, psc->sc_ih);
}
if (psc->sc_mapsize > 0)
- bus_space_unmap(sc->sc_st, sc->sc_sh, psc->sc_mapsize);
+ bus_space_unmap(psc->sc_st, psc->sc_sh, psc->sc_mapsize);
return (0);
}
@@ -230,6 +239,31 @@ athn_pci_resume(void *arg1, void *arg2)
splx(s);
}
+uint32_t
+athn_pci_read(struct athn_softc *sc, uint32_t addr)
+{
+ struct athn_pci_softc *psc = (struct athn_pci_softc *)sc;
+
+ return (bus_space_read_4(psc->sc_st, psc->sc_sh, addr));
+}
+
+void
+athn_pci_write(struct athn_softc *sc, uint32_t addr, uint32_t val)
+{
+ struct athn_pci_softc *psc = (struct athn_pci_softc *)sc;
+
+ bus_space_write_4(psc->sc_st, psc->sc_sh, addr, val);
+}
+
+void
+athn_pci_write_barrier(struct athn_softc *sc)
+{
+ struct athn_pci_softc *psc = (struct athn_pci_softc *)sc;
+
+ bus_space_barrier(psc->sc_st, psc->sc_sh, 0, psc->sc_mapsize,
+ BUS_SPACE_BARRIER_WRITE);
+}
+
void
athn_pci_disable_aspm(struct athn_softc *sc)
{
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-01 11:26:23 +0000