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-rw-r--r--sys/dev/mii/brgphy.c20
-rw-r--r--sys/dev/pci/if_bge.c50
-rw-r--r--sys/dev/pci/if_bgereg.h72
3 files changed, 72 insertions, 70 deletions
diff --git a/sys/dev/mii/brgphy.c b/sys/dev/mii/brgphy.c
index d357d5a5908..f5f920a8814 100644
--- a/sys/dev/mii/brgphy.c
+++ b/sys/dev/mii/brgphy.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: brgphy.c,v 1.103 2013/12/28 03:30:40 deraadt Exp $ */
+/* $OpenBSD: brgphy.c,v 1.104 2014/02/01 01:51:27 brad Exp $ */
/*
* Copyright (c) 2000
@@ -215,7 +215,7 @@ brgphy_attach(struct device *parent, struct device *self, void *aux)
if (strcmp(devname, "bge") == 0) {
bge_sc = mii->mii_ifp->if_softc;
- if (bge_sc->bge_flags & BGE_10_100_ONLY)
+ if (bge_sc->bge_phy_flags & BGE_PHY_10_100_ONLY)
fast_ether = 1;
} else if (strcmp(devname, "bnx") == 0)
bnx_sc = mii->mii_ifp->if_softc;
@@ -821,17 +821,17 @@ brgphy_reset_bge(struct mii_softc *sc)
}
}
- if (bge_sc->bge_flags & BGE_PHY_ADC_BUG)
+ if (bge_sc->bge_phy_flags & BGE_PHY_ADC_BUG)
brgphy_adc_bug(sc);
- if (bge_sc->bge_flags & BGE_PHY_5704_A0_BUG)
+ if (bge_sc->bge_phy_flags & BGE_PHY_5704_A0_BUG)
brgphy_5704_a0_bug(sc);
- if (bge_sc->bge_flags & BGE_PHY_BER_BUG)
+ if (bge_sc->bge_phy_flags & BGE_PHY_BER_BUG)
brgphy_ber_bug(sc);
- else if (bge_sc->bge_flags & BGE_PHY_JITTER_BUG) {
+ else if (bge_sc->bge_phy_flags & BGE_PHY_JITTER_BUG) {
PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x0c00);
PHY_WRITE(sc, BRGPHY_MII_DSP_ADDR_REG, 0x000a);
- if (bge_sc->bge_flags & BGE_PHY_ADJUST_TRIM) {
+ if (bge_sc->bge_phy_flags & BGE_PHY_ADJUST_TRIM) {
PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, 0x110b);
PHY_WRITE(sc, BRGPHY_TEST1, BRGPHY_TEST1_TRIM_EN |
0x4);
@@ -841,7 +841,7 @@ brgphy_reset_bge(struct mii_softc *sc)
PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x0400);
}
- if (bge_sc->bge_flags & BGE_PHY_CRC_BUG)
+ if (bge_sc->bge_phy_flags & BGE_PHY_CRC_BUG)
brgphy_crc_bug(sc);
/* Set Jumbo frame settings in the PHY. */
@@ -854,11 +854,11 @@ brgphy_reset_bge(struct mii_softc *sc)
PHY_WRITE(sc, BRGPHY_MII_EPHY_PTEST, 0x12);
/* Enable Ethernet@Wirespeed */
- if (!(bge_sc->bge_flags & BGE_NO_ETH_WIRE_SPEED))
+ if (!(bge_sc->bge_phy_flags & BGE_PHY_NO_WIRESPEED))
brgphy_eth_wirespeed(sc);
/* Enable Link LED on Dell boxes */
- if (bge_sc->bge_flags & BGE_NO_3LED) {
+ if (bge_sc->bge_phy_flags & BGE_PHY_NO_3LED) {
PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL,
PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL)
& ~BRGPHY_PHY_EXTCTL_3_LED);
diff --git a/sys/dev/pci/if_bge.c b/sys/dev/pci/if_bge.c
index c768a511d64..559c58f3a96 100644
--- a/sys/dev/pci/if_bge.c
+++ b/sys/dev/pci/if_bge.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: if_bge.c,v 1.349 2014/01/31 01:16:10 brad Exp $ */
+/* $OpenBSD: if_bge.c,v 1.350 2014/02/01 01:51:27 brad Exp $ */
/*
* Copyright (c) 2001 Wind River Systems
@@ -2257,9 +2257,9 @@ bge_blockinit(struct bge_softc *sc)
BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB |
BGE_MACMODE_FRMHDR_DMA_ENB;
- if (sc->bge_flags & BGE_PHY_FIBER_TBI)
+ if (sc->bge_flags & BGE_FIBER_TBI)
val |= BGE_PORTMODE_TBI;
- else if (sc->bge_flags & BGE_PHY_FIBER_MII)
+ else if (sc->bge_flags & BGE_FIBER_MII)
val |= BGE_PORTMODE_GMII;
else
val |= BGE_PORTMODE_MII;
@@ -2441,7 +2441,7 @@ bge_blockinit(struct bge_softc *sc)
BGE_MACSTAT_LINK_CHANGED);
/* Enable PHY auto polling (for MII/GMII only) */
- if (sc->bge_flags & BGE_PHY_FIBER_TBI) {
+ if (sc->bge_flags & BGE_FIBER_TBI) {
CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK);
} else {
if ((sc->bge_flags & BGE_CPMU_PRESENT) != 0)
@@ -2748,7 +2748,7 @@ bge_attach(struct device *parent, struct device *self, void *aux)
if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 ||
BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701) &&
PCI_VENDOR(subid) == DELL_VENDORID)
- sc->bge_flags |= BGE_NO_3LED;
+ sc->bge_phy_flags |= BGE_PHY_NO_3LED;
misccfg = CSR_READ_4(sc, BGE_MISC_CFG);
misccfg &= BGE_MISCCFG_BOARD_ID_MASK;
@@ -2773,23 +2773,23 @@ bge_attach(struct device *parent, struct device *self, void *aux)
PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57791 ||
PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57795 ||
BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906)
- sc->bge_flags |= BGE_10_100_ONLY;
+ sc->bge_phy_flags |= BGE_PHY_10_100_ONLY;
if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 ||
(BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 &&
(sc->bge_chipid != BGE_CHIPID_BCM5705_A0 &&
sc->bge_chipid != BGE_CHIPID_BCM5705_A1)) ||
BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906)
- sc->bge_flags |= BGE_NO_ETH_WIRE_SPEED;
+ sc->bge_phy_flags |= BGE_PHY_NO_WIRESPEED;
if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 ||
sc->bge_chipid == BGE_CHIPID_BCM5701_B0)
- sc->bge_flags |= BGE_PHY_CRC_BUG;
+ sc->bge_phy_flags |= BGE_PHY_CRC_BUG;
if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5703_AX ||
BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5704_AX)
- sc->bge_flags |= BGE_PHY_ADC_BUG;
+ sc->bge_phy_flags |= BGE_PHY_ADC_BUG;
if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0)
- sc->bge_flags |= BGE_PHY_5704_A0_BUG;
+ sc->bge_phy_flags |= BGE_PHY_5704_A0_BUG;
if ((BGE_IS_5705_PLUS(sc)) &&
BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906 &&
@@ -2802,11 +2802,11 @@ bge_attach(struct device *parent, struct device *self, void *aux)
BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5787) {
if (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5722 &&
PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5756)
- sc->bge_flags |= BGE_PHY_JITTER_BUG;
+ sc->bge_phy_flags |= BGE_PHY_JITTER_BUG;
if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5755M)
- sc->bge_flags |= BGE_PHY_ADJUST_TRIM;
+ sc->bge_phy_flags |= BGE_PHY_ADJUST_TRIM;
} else
- sc->bge_flags |= BGE_PHY_BER_BUG;
+ sc->bge_phy_flags |= BGE_PHY_BER_BUG;
}
/* Identify chips with APE processor. */
@@ -3057,9 +3057,9 @@ bge_attach(struct device *parent, struct device *self, void *aux)
if (PCI_PRODUCT(subid) == SK_SUBSYSID_9D41 ||
(hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) {
if (BGE_IS_5700_FAMILY(sc))
- sc->bge_flags |= BGE_PHY_FIBER_TBI;
+ sc->bge_flags |= BGE_FIBER_TBI;
else
- sc->bge_flags |= BGE_PHY_FIBER_MII;
+ sc->bge_flags |= BGE_FIBER_MII;
}
/* Take advantage of single-shot MSI. */
@@ -3085,7 +3085,7 @@ bge_attach(struct device *parent, struct device *self, void *aux)
printf(": %s, address %s\n", intrstr,
ether_sprintf(sc->arpcom.ac_enaddr));
- if (sc->bge_flags & BGE_PHY_FIBER_TBI) {
+ if (sc->bge_flags & BGE_FIBER_TBI) {
ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd,
bge_ifmedia_sts);
ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL);
@@ -3103,7 +3103,7 @@ bge_attach(struct device *parent, struct device *self, void *aux)
ifmedia_init(&sc->bge_mii.mii_media, 0, bge_ifmedia_upd,
bge_ifmedia_sts);
mii_flags = MIIF_DOPAUSE;
- if (sc->bge_flags & BGE_PHY_FIBER_MII)
+ if (sc->bge_flags & BGE_FIBER_MII)
mii_flags |= MIIF_HAVEFIBER;
mii_attach(&sc->bge_dev, &sc->bge_mii, 0xffffffff,
sc->bge_phy_addr, MII_OFFSET_ANY, mii_flags);
@@ -3370,7 +3370,7 @@ bge_reset(struct bge_softc *sc)
* adjustment to ensure the SERDES drive level is set
* to 1.2V.
*/
- if (sc->bge_flags & BGE_PHY_FIBER_TBI &&
+ if (sc->bge_flags & BGE_FIBER_TBI &&
BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) {
val = CSR_READ_4(sc, BGE_SERDES_CFG);
val = (val & ~0xFFF) | 0x880;
@@ -3718,7 +3718,7 @@ bge_tick(void *xsc)
else
bge_stats_update(sc);
- if (sc->bge_flags & BGE_PHY_FIBER_TBI) {
+ if (sc->bge_flags & BGE_FIBER_TBI) {
/*
* Since in TBI mode auto-polling can't be used we should poll
* link status manually. Here we register pending link event
@@ -4302,7 +4302,7 @@ bge_ifmedia_upd(struct ifnet *ifp)
struct ifmedia *ifm = &sc->bge_ifmedia;
/* If this is a 1000baseX NIC, enable the TBI port. */
- if (sc->bge_flags & BGE_PHY_FIBER_TBI) {
+ if (sc->bge_flags & BGE_FIBER_TBI) {
if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
return (EINVAL);
switch(IFM_SUBTYPE(ifm->ifm_media)) {
@@ -4379,7 +4379,7 @@ bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
struct bge_softc *sc = ifp->if_softc;
struct mii_data *mii = &sc->bge_mii;
- if (sc->bge_flags & BGE_PHY_FIBER_TBI) {
+ if (sc->bge_flags & BGE_FIBER_TBI) {
ifmr->ifm_status = IFM_AVALID;
ifmr->ifm_active = IFM_ETHER;
if (CSR_READ_4(sc, BGE_MAC_STS) &
@@ -4439,7 +4439,7 @@ bge_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
case SIOCSIFMEDIA:
/* XXX Flow control is not supported for 1000BASE-SX */
- if (sc->bge_flags & BGE_PHY_FIBER_TBI) {
+ if (sc->bge_flags & BGE_FIBER_TBI) {
ifr->ifr_media &= ~IFM_ETH_FMASK;
sc->bge_flowflags = 0;
}
@@ -4459,7 +4459,7 @@ bge_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
}
/* FALLTHROUGH */
case SIOCGIFMEDIA:
- if (sc->bge_flags & BGE_PHY_FIBER_TBI) {
+ if (sc->bge_flags & BGE_FIBER_TBI) {
error = ifmedia_ioctl(ifp, ifr, &sc->bge_ifmedia,
command);
} else {
@@ -4603,7 +4603,7 @@ bge_stop(struct bge_softc *sc)
* unchanged so that things will be put back to normal when
* we bring the interface back up.
*/
- if (!(sc->bge_flags & BGE_PHY_FIBER_TBI)) {
+ if (!(sc->bge_flags & BGE_FIBER_TBI)) {
mii = &sc->bge_mii;
itmp = ifp->if_flags;
ifp->if_flags |= IFF_UP;
@@ -4669,7 +4669,7 @@ bge_link_upd(struct bge_softc *sc)
return;
}
- if (sc->bge_flags & BGE_PHY_FIBER_TBI) {
+ if (sc->bge_flags & BGE_FIBER_TBI) {
status = CSR_READ_4(sc, BGE_MAC_STS);
if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) {
if (!BGE_STS_BIT(sc, BGE_STS_LINK)) {
diff --git a/sys/dev/pci/if_bgereg.h b/sys/dev/pci/if_bgereg.h
index e1b8419579b..66c3122a86e 100644
--- a/sys/dev/pci/if_bgereg.h
+++ b/sys/dev/pci/if_bgereg.h
@@ -1,4 +1,4 @@
-/* $OpenBSD: if_bgereg.h,v 1.121 2014/01/28 14:08:29 sthen Exp $ */
+/* $OpenBSD: if_bgereg.h,v 1.122 2014/02/01 01:51:27 brad Exp $ */
/*
* Copyright (c) 2001 Wind River Systems
@@ -2843,40 +2843,42 @@ struct bge_softc {
u_int32_t bge_mps;
u_int32_t bge_expmrq;
u_int32_t bge_lasttag;
- u_int64_t bge_flags;
-#define BGE_TXRING_VALID 0x0000000000000001ULL
-#define BGE_RXRING_VALID 0x0000000000000002ULL
-#define BGE_JUMBO_RXRING_VALID 0x0000000000000004ULL
-#define BGE_RX_ALIGNBUG 0x0000000000000008ULL
-#define BGE_NO_3LED 0x0000000000000010ULL
-#define BGE_PCIX 0x0000000000000020ULL
-#define BGE_PCIE 0x0000000000000040ULL
-#define BGE_ASF_MODE 0x0000000000000080ULL
-#define BGE_NO_EEPROM 0x0000000000000100ULL
-#define BGE_JUMBO_CAPABLE 0x0000000000000200ULL
-#define BGE_10_100_ONLY 0x0000000000000400ULL
-#define BGE_PHY_FIBER_TBI 0x0000000000000800ULL
-#define BGE_PHY_FIBER_MII 0x0000000000001000ULL
-#define BGE_PHY_CRC_BUG 0x0000000000002000ULL
-#define BGE_PHY_ADC_BUG 0x0000000000004000ULL
-#define BGE_PHY_5704_A0_BUG 0x0000000000008000ULL
-#define BGE_PHY_JITTER_BUG 0x0000000000010000ULL
-#define BGE_PHY_BER_BUG 0x0000000000020000ULL
-#define BGE_PHY_ADJUST_TRIM 0x0000000000040000ULL
-#define BGE_NO_ETH_WIRE_SPEED 0x0000000000080000ULL
-#define BGE_IS_5788 0x0000000000100000ULL
-#define BGE_5705_PLUS 0x0000000000200000ULL
-#define BGE_575X_PLUS 0x0000000000400000ULL
-#define BGE_5755_PLUS 0x0000000000800000ULL
-#define BGE_5714_FAMILY 0x0000000001000000ULL
-#define BGE_5700_FAMILY 0x0000000002000000ULL
-#define BGE_5717_PLUS 0x0000000004000000ULL
-#define BGE_57765_PLUS 0x0000000008000000ULL
-#define BGE_APE 0x0000000010000000ULL
-#define BGE_CPMU_PRESENT 0x0000000020000000ULL
-#define BGE_TAGGED_STATUS 0x0000000040000000ULL
-#define BGE_MSI 0x0000000080000000ULL
-#define BGE_RDMA_BUG 0x0000000100000000ULL
+ u_int32_t bge_flags;
+#define BGE_TXRING_VALID 0x00000001
+#define BGE_RXRING_VALID 0x00000002
+#define BGE_JUMBO_RXRING_VALID 0x00000004
+#define BGE_RX_ALIGNBUG 0x00000008
+#define BGE_PCIX 0x00000010
+#define BGE_PCIE 0x00000020
+#define BGE_ASF_MODE 0x00000040
+#define BGE_NO_EEPROM 0x00000080
+#define BGE_JUMBO_CAPABLE 0x00000100
+#define BGE_FIBER_TBI 0x00000200
+#define BGE_FIBER_MII 0x00000400
+#define BGE_IS_5788 0x00000800
+#define BGE_5705_PLUS 0x00001000
+#define BGE_575X_PLUS 0x00002000
+#define BGE_5755_PLUS 0x00004000
+#define BGE_5714_FAMILY 0x00008000
+#define BGE_5700_FAMILY 0x00010000
+#define BGE_5717_PLUS 0x00020000
+#define BGE_57765_PLUS 0x00040000
+#define BGE_APE 0x00080000
+#define BGE_CPMU_PRESENT 0x00100000
+#define BGE_TAGGED_STATUS 0x00200000
+#define BGE_MSI 0x00400000
+#define BGE_RDMA_BUG 0x00800000
+
+ u_int32_t bge_phy_flags;
+#define BGE_PHY_NO_3LED 0x00000001
+#define BGE_PHY_10_100_ONLY 0x00000002
+#define BGE_PHY_CRC_BUG 0x00000004
+#define BGE_PHY_ADC_BUG 0x00000008
+#define BGE_PHY_5704_A0_BUG 0x00008010
+#define BGE_PHY_JITTER_BUG 0x00000020
+#define BGE_PHY_BER_BUG 0x00000040
+#define BGE_PHY_ADJUST_TRIM 0x00000080
+#define BGE_PHY_NO_WIRESPEED 0x00000100
bus_dma_tag_t bge_dmatag;
u_int32_t bge_mfw_flags; /* Management F/W flags */
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-29 18:43:16 +0000