diff options
| -rw-r--r-- | sys/arch/alpha/pci/mcpciareg.h | 4 | ||||
| -rw-r--r-- | sys/arch/macppc/dev/if_mc.c | 4 | ||||
| -rw-r--r-- | sys/arch/powerpc/powerpc/pmap.c | 4 | ||||
| -rw-r--r-- | sys/dev/mii/inphyreg.h | 4 | ||||
| -rw-r--r-- | sys/dev/pci/if_lge.c | 4 | ||||
| -rw-r--r-- | sys/dev/pci/if_wb.c | 4 | ||||
| -rw-r--r-- | sys/dev/pci/igc_defines.h | 4 | ||||
| -rw-r--r-- | sys/dev/pci/pciide_cmd_reg.h | 6 | ||||
| -rw-r--r-- | sys/lib/libkern/arch/arm/memmove.S | 4 |
9 files changed, 19 insertions, 19 deletions
diff --git a/sys/arch/alpha/pci/mcpciareg.h b/sys/arch/alpha/pci/mcpciareg.h index db55206056e..14c37eb7c51 100644 --- a/sys/arch/alpha/pci/mcpciareg.h +++ b/sys/arch/alpha/pci/mcpciareg.h @@ -1,4 +1,4 @@ -/* $OpenBSD: mcpciareg.h,v 1.1 2007/03/16 21:22:27 robert Exp $ */ +/* $OpenBSD: mcpciareg.h,v 1.2 2024/09/06 10:54:08 jsg Exp $ */ /* $NetBSD: mcpciareg.h,v 1.7 2006/05/17 21:32:59 drochner Exp $ */ /* @@ -109,7 +109,7 @@ * - (8+x)(9+y*2).F000.3EFF * * (8+x)(9+y*2).F000.3F00, N/A PCIy Interrupt ACK0 - * (8+x)(9+y*2).F000.3F40 PCIy INteruppt ACK1 + * (8+x)(9+y*2).F000.3F40 PCIy Interrupt ACK1 * * (8+x)(9+y*2).F000.3F80 N/A Unused * - (8+x)(9+y*2).FFFF.FFFF diff --git a/sys/arch/macppc/dev/if_mc.c b/sys/arch/macppc/dev/if_mc.c index bfa22d85239..4e48f1759a1 100644 --- a/sys/arch/macppc/dev/if_mc.c +++ b/sys/arch/macppc/dev/if_mc.c @@ -1,4 +1,4 @@ -/* $OpenBSD: if_mc.c,v 1.34 2024/05/22 05:51:49 jsg Exp $ */ +/* $OpenBSD: if_mc.c,v 1.35 2024/09/06 10:54:08 jsg Exp $ */ /* $NetBSD: if_mc.c,v 1.9.16.1 2006/06/21 14:53:13 yamt Exp $ */ /*- @@ -96,7 +96,7 @@ #define MACE_FIFOCC 12 /* FIFO Configuration Control (read/write) */ #define MACE_MACCC 13 /* MAC Configuration Control (read/write) */ #define MACE_PLSCC 14 /* PLS Configuration Control (read/write) */ -#define MACE_PHYCC 15 /* PHY Confiuration Control (read/write) */ +#define MACE_PHYCC 15 /* PHY Configuration Control (read/write) */ #define MACE_CHIPIDL 16 /* Chip ID Register [07-00] (read only) */ #define MACE_CHIPIDH 17 /* Chip ID Register [15-08] (read only) */ #define MACE_IAC 18 /* Internal Address Configuration (read/write) */ diff --git a/sys/arch/powerpc/powerpc/pmap.c b/sys/arch/powerpc/powerpc/pmap.c index 4755a79888f..bb781646f4b 100644 --- a/sys/arch/powerpc/powerpc/pmap.c +++ b/sys/arch/powerpc/powerpc/pmap.c @@ -1,4 +1,4 @@ -/* $OpenBSD: pmap.c,v 1.184 2024/05/22 05:51:49 jsg Exp $ */ +/* $OpenBSD: pmap.c,v 1.185 2024/09/06 10:54:08 jsg Exp $ */ /* * Copyright (c) 2015 Martin Pieuchot @@ -2247,7 +2247,7 @@ pte_spill_r(u_int32_t va, u_int32_t msr, u_int32_t dsisr, int exec_fault) if (msr & PSL_PR) return 0; - /* if copyin, throw to full excption handler */ + /* if copyin, throw to full exception handler */ if (VP_SR(va) == PPC_USER_SR) return 0; diff --git a/sys/dev/mii/inphyreg.h b/sys/dev/mii/inphyreg.h index 624cf861925..ec286d3d558 100644 --- a/sys/dev/mii/inphyreg.h +++ b/sys/dev/mii/inphyreg.h @@ -1,4 +1,4 @@ -/* $OpenBSD: inphyreg.h,v 1.5 2008/06/26 05:42:16 ray Exp $ */ +/* $OpenBSD: inphyreg.h,v 1.6 2024/09/06 10:54:08 jsg Exp $ */ /* $NetBSD: inphyreg.h,v 1.1 1998/08/11 00:00:28 thorpej Exp $ */ /*- @@ -60,7 +60,7 @@ #define SCTRL_SCRBYPASS 0x8000 /* scrambler bypass */ #define SCTRL_4B5BNYPASS 0x4000 /* 4bit to 5bit bypass */ #define SCTRL_FTHP 0x2000 /* force transmit H-pattern */ -#define SCTRL_F34TP 0x1000 /* force 34 transmit patter */ +#define SCTRL_F34TP 0x1000 /* force 34 transmit pattern */ #define SCTRL_GOODLINK 0x0800 /* 100baseTX link good */ #define SCTRL_TCSD 0x0200 /* transmit carrier sense disable */ #define SCTRL_DDPD 0x0100 /* disable dynamic power-down */ diff --git a/sys/dev/pci/if_lge.c b/sys/dev/pci/if_lge.c index 543cf3049b9..4753418bd89 100644 --- a/sys/dev/pci/if_lge.c +++ b/sys/dev/pci/if_lge.c @@ -1,4 +1,4 @@ -/* $OpenBSD: if_lge.c,v 1.81 2024/05/24 06:02:53 jsg Exp $ */ +/* $OpenBSD: if_lge.c,v 1.82 2024/09/06 10:54:08 jsg Exp $ */ /* * Copyright (c) 2001 Wind River Systems * Copyright (c) 1997, 1998, 1999, 2000, 2001 @@ -1063,7 +1063,7 @@ lge_init(void *xsc) CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_VLAN_RX|LGE_MODE1_VLAN_TX| LGE_MODE1_VLAN_STRIP|LGE_MODE1_VLAN_INSERT); - /* Workarond: FIFO overflow */ + /* Workaround: FIFO overflow */ CSR_WRITE_2(sc, LGE_RXFIFO_HIWAT, 0x3FFF); CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL1|LGE_IMR_RXFIFO_WAT); diff --git a/sys/dev/pci/if_wb.c b/sys/dev/pci/if_wb.c index d7ff8f36a78..a36b9e32834 100644 --- a/sys/dev/pci/if_wb.c +++ b/sys/dev/pci/if_wb.c @@ -1,4 +1,4 @@ -/* $OpenBSD: if_wb.c,v 1.77 2024/05/24 06:02:57 jsg Exp $ */ +/* $OpenBSD: if_wb.c,v 1.78 2024/09/06 10:54:08 jsg Exp $ */ /* * Copyright (c) 1997, 1998 @@ -1304,7 +1304,7 @@ wb_start(struct ifnet *ifp) * the own bit is clear because the chip cleared it * and where the own bit is clear because we haven't * set it yet. The magic value WB_UNSET is just some - * ramdomly chosen number which doesn't have the own + * randomly chosen number which doesn't have the own * bit set. When we actually transmit the frame, the * status word will have _only_ the own bit set, so * the txeoc handler will be able to tell if it needs diff --git a/sys/dev/pci/igc_defines.h b/sys/dev/pci/igc_defines.h index 3618aa45aff..d7bbbed0c6f 100644 --- a/sys/dev/pci/igc_defines.h +++ b/sys/dev/pci/igc_defines.h @@ -1,4 +1,4 @@ -/* $OpenBSD: igc_defines.h,v 1.1 2021/10/31 14:52:57 patrick Exp $ */ +/* $OpenBSD: igc_defines.h,v 1.2 2024/09/06 10:54:08 jsg Exp $ */ /*- * Copyright 2021 Intel Corp @@ -749,7 +749,7 @@ /* TTQF SCTP Bit, shift with IGC_TTQF_PROTOCOL_SHIFT */ #define IGC_TTQF_PROTOCOL_SCTP 0x2 #define IGC_TTQF_PROTOCOL_SHIFT 5 /* TTQF Protocol Shift */ -#define IGC_TTQF_QUEUE_SHIFT 16 /* TTQF Queue Shfit */ +#define IGC_TTQF_QUEUE_SHIFT 16 /* TTQF Queue Shift */ #define IGC_TTQF_RX_QUEUE_MASK 0x70000 /* TTQF Queue Mask */ #define IGC_TTQF_MASK_ENABLE 0x10000000 /* TTQF Mask Enable Bit */ #define IGC_IMIR_CLEAR_MASK 0xF001FFFF /* IMIR Reg Clear Mask */ diff --git a/sys/dev/pci/pciide_cmd_reg.h b/sys/dev/pci/pciide_cmd_reg.h index f0fea8cf5fe..67f1228f95a 100644 --- a/sys/dev/pci/pciide_cmd_reg.h +++ b/sys/dev/pci/pciide_cmd_reg.h @@ -1,4 +1,4 @@ -/* $OpenBSD: pciide_cmd_reg.h,v 1.11 2010/07/23 07:47:13 jsg Exp $ */ +/* $OpenBSD: pciide_cmd_reg.h,v 1.12 2024/09/06 10:54:08 jsg Exp $ */ /* $NetBSD: pciide_cmd_reg.h,v 1.9 2000/08/02 20:23:46 bouyer Exp $ */ /* @@ -78,12 +78,12 @@ #define CMD_DMA 0x00 #define CMD_DMA_MULTIPLE 0x01 #define CMD_DMA_LINE 0x03 -/* the followings bits are only for 0646U/646U2/648/649 */ +/* the following bits are only for 0646U/646U2/648/649 */ #define CMD_DMA_IRQ(chan) (0x4 << (chan)) #define CMD_DMA_IRQ_DIS(chan) (0x10 << (chan)) #define CMD_DMA_RST 0x40 -/* the followings are only for 0646U/646U2/648/649 */ +/* the following is only for 0646U/646U2/648/649 */ /* busmaster control/status register */ #define CMD_BICSR 0x79 #define CMD_BICSR_80(chan) (0x01 << (chan)) diff --git a/sys/lib/libkern/arch/arm/memmove.S b/sys/lib/libkern/arch/arm/memmove.S index 3d57f95b054..96064806aef 100644 --- a/sys/lib/libkern/arch/arm/memmove.S +++ b/sys/lib/libkern/arch/arm/memmove.S @@ -1,6 +1,6 @@ -/* $OpenBSD: memmove.S,v 1.2 2004/02/01 05:47:10 drahn Exp $ */ +/* $OpenBSD: memmove.S,v 1.3 2024/09/06 10:54:08 jsg Exp $ */ /* $NetBSD: memmove.S,v 1.2 2001/11/20 00:29:20 chris Exp $ */ /* - * placeholder to keep the make system happy, memove is actually in memcpy.S + * placeholder to keep the make system happy, memmove is actually in memcpy.S */ |