diff options
4 files changed, 29 insertions, 9 deletions
diff --git a/sys/dev/pci/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.c b/sys/dev/pci/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.c index 89ed5ee9cde..2fde5c360cf 100644 --- a/sys/dev/pci/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.c +++ b/sys/dev/pci/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.c @@ -81,8 +81,17 @@ out_rq: i915_request_add(rq); - if (!err && i915_request_wait(rq, 0, msecs_to_jiffies(500)) < 0) - err = -ETIME; + if (!err) { + /* + * Start timeout for i915_request_wait only after considering one possible + * pending GSC-HECI submission cycle on the other (non-privileged) path. + */ + if (wait_for(i915_request_started(rq), GSC_HECI_REPLY_LATENCY_MS)) + drm_dbg(&gsc_uc_to_gt(gsc)->i915->drm, + "Delay in gsc-heci-priv submission to gsccs-hw"); + if (i915_request_wait(rq, 0, msecs_to_jiffies(GSC_HECI_REPLY_LATENCY_MS)) < 0) + err = -ETIME; + } i915_request_put(rq); @@ -186,6 +195,13 @@ out_rq: i915_request_add(rq); if (!err) { + /* + * Start timeout for i915_request_wait only after considering one possible + * pending GSC-HECI submission cycle on the other (privileged) path. + */ + if (wait_for(i915_request_started(rq), GSC_HECI_REPLY_LATENCY_MS)) + drm_dbg(&gsc_uc_to_gt(gsc)->i915->drm, + "Delay in gsc-heci-non-priv submission to gsccs-hw"); if (i915_request_wait(rq, I915_WAIT_INTERRUPTIBLE, msecs_to_jiffies(timeout_ms)) < 0) err = -ETIME; diff --git a/sys/dev/pci/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.h b/sys/dev/pci/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.h index 09d3fbdad05..c4308291c00 100644 --- a/sys/dev/pci/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.h +++ b/sys/dev/pci/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.h @@ -12,6 +12,12 @@ struct i915_vma; struct intel_context; struct intel_gsc_uc; +#define GSC_HECI_REPLY_LATENCY_MS 500 +/* + * Max FW response time is 500ms, but this should be counted from the time the + * command has hit the GSC-CS hardware, not the preceding handoff to GuC CTB. + */ + struct intel_gsc_mtl_header { u32 validity_marker; #define GSC_HECI_VALIDITY_MARKER 0xA578875A diff --git a/sys/dev/pci/drm/i915/pxp/intel_pxp_gsccs.c b/sys/dev/pci/drm/i915/pxp/intel_pxp_gsccs.c index 86f58a5bddd..cc81a462492 100644 --- a/sys/dev/pci/drm/i915/pxp/intel_pxp_gsccs.c +++ b/sys/dev/pci/drm/i915/pxp/intel_pxp_gsccs.c @@ -111,7 +111,7 @@ gsccs_send_message(struct intel_pxp *pxp, ret = intel_gsc_uc_heci_cmd_submit_nonpriv(>->uc.gsc, exec_res->ce, &pkt, exec_res->bb_vaddr, - GSC_REPLY_LATENCY_MS); + GSC_HECI_REPLY_LATENCY_MS); if (ret) { drm_err(&i915->drm, "failed to send gsc PXP msg (%d)\n", ret); goto unlock; diff --git a/sys/dev/pci/drm/i915/pxp/intel_pxp_gsccs.h b/sys/dev/pci/drm/i915/pxp/intel_pxp_gsccs.h index 298ad38e6c7..9aae779c4da 100644 --- a/sys/dev/pci/drm/i915/pxp/intel_pxp_gsccs.h +++ b/sys/dev/pci/drm/i915/pxp/intel_pxp_gsccs.h @@ -8,16 +8,14 @@ #include <linux/types.h> +#include "gt/uc/intel_gsc_uc_heci_cmd_submit.h" + struct intel_pxp; -#define GSC_REPLY_LATENCY_MS 210 -/* - * Max FW response time is 200ms, to which we add 10ms to account for overhead - * such as request preparation, GuC submission to hw and pipeline completion times. - */ #define GSC_PENDING_RETRY_MAXCOUNT 40 #define GSC_PENDING_RETRY_PAUSE_MS 50 -#define GSCFW_MAX_ROUND_TRIP_LATENCY_MS (GSC_PENDING_RETRY_MAXCOUNT * GSC_PENDING_RETRY_PAUSE_MS) +#define GSCFW_MAX_ROUND_TRIP_LATENCY_MS (GSC_HECI_REPLY_LATENCY_MS + \ + (GSC_PENDING_RETRY_MAXCOUNT * GSC_PENDING_RETRY_PAUSE_MS)) #ifdef CONFIG_DRM_I915_PXP void intel_pxp_gsccs_fini(struct intel_pxp *pxp); |