diff options
| -rw-r--r-- | sys/dev/pci/drm/i915/intel_dp.c | 14 |
1 files changed, 12 insertions, 2 deletions
diff --git a/sys/dev/pci/drm/i915/intel_dp.c b/sys/dev/pci/drm/i915/intel_dp.c index 51eaa071254..d8adf2807df 100644 --- a/sys/dev/pci/drm/i915/intel_dp.c +++ b/sys/dev/pci/drm/i915/intel_dp.c @@ -1,4 +1,4 @@ -/* $OpenBSD: intel_dp.c,v 1.3 2013/04/04 21:26:19 kettenis Exp $ */ +/* $OpenBSD: intel_dp.c,v 1.4 2013/04/08 05:46:12 jsg Exp $ */ /* * Copyright © 2008 Intel Corporation * @@ -911,6 +911,7 @@ intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode, struct intel_dp_m_n m_n; int pipe = intel_crtc->pipe; enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder; + int target_clock; /* * Find the lane count in the intel_encoder private @@ -926,13 +927,22 @@ intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode, } } + target_clock = mode->clock; + for_each_encoder_on_crtc(dev, crtc, intel_encoder) { + if (intel_encoder->type == INTEL_OUTPUT_EDP) { + target_clock = intel_edp_target_clock(intel_encoder, + mode); + break; + } + } + /* * Compute the GMCH and Link ratios. The '3' here is * the number of bytes_per_pixel post-LUT, which we always * set up for 8-bits of R/G/B, or 3 bytes total. */ intel_dp_compute_m_n(intel_crtc->bpp, lane_count, - mode->clock, adjusted_mode->clock, &m_n); + target_clock, adjusted_mode->clock, &m_n); if (IS_HASWELL(dev)) { I915_WRITE(PIPE_DATA_M1(cpu_transcoder), |