diff options
| -rw-r--r-- | share/man/man4/Makefile | 4 | ||||
| -rw-r--r-- | share/man/man4/ale.4 | 84 | ||||
| -rw-r--r-- | share/man/man4/pci.4 | 6 | ||||
| -rw-r--r-- | sys/dev/pci/files.pci | 7 | ||||
| -rw-r--r-- | sys/dev/pci/if_ale.c | 2045 | ||||
| -rw-r--r-- | sys/dev/pci/if_alereg.h | 965 |
6 files changed, 3106 insertions, 5 deletions
diff --git a/share/man/man4/Makefile b/share/man/man4/Makefile index 8ee43499746..d465d672a93 100644 --- a/share/man/man4/Makefile +++ b/share/man/man4/Makefile @@ -1,10 +1,10 @@ -# $OpenBSD: Makefile,v 1.477 2009/01/25 17:30:48 miod Exp $ +# $OpenBSD: Makefile,v 1.478 2009/02/25 03:05:32 kevlo Exp $ MAN= aac.4 ac97.4 acphy.4 \ acpi.4 acpiac.4 acpiasus.4 acpibat.4 acpibtn.4 acpicpu.4 acpidock.4 \ acpiec.4 acpihpet.4 acpimadt.4 acpiprt.4 acpithinkpad.4 acpitimer.4 \ acpitz.4 acx.4 adc.4 addcom.4 adl.4 admcts.4 admlc.4 admtemp.4 \ - admtm.4 admtmp.4 admtt.4 adt.4 adtfsm.4 adv.4 age.4 agp.4 \ + admtm.4 admtmp.4 admtt.4 adt.4 adtfsm.4 adv.4 age.4 ale.4 agp.4 \ aha.4 ahb.4 ahc.4 ahci.4 \ ahd.4 aic.4 akbd.4 alipm.4 amdiic.4 amdpm.4 ami.4 amphy.4 ams.4 \ an.4 andl.4 aps.4 arc.4 aria.4 art.4 \ diff --git a/share/man/man4/ale.4 b/share/man/man4/ale.4 new file mode 100644 index 00000000000..8bb98fa1a3c --- /dev/null +++ b/share/man/man4/ale.4 @@ -0,0 +1,84 @@ +.\" $OpenBSD: ale.4,v 1.1 2009/02/25 03:05:32 kevlo Exp $ +.\" +.\" Copyright (c) 2009 Kevin Lo <kevlo@openbsd.org> +.\" +.\" Permission to use, copy, modify, and distribute this software for any +.\" purpose with or without fee is hereby granted, provided that the above +.\" copyright notice and this permission notice appear in all copies. +.\" +.\" THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +.\" WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +.\" MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +.\" ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +.\" WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +.\" ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +.\" OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +.\" +.Dd $Mdocdate: February 25 2009 $ +.Dt ALE 4 +.Os +.Sh NAME +.Nm ale +.Nd Atheros AR8121/AR8113/AR8114 10/100/Gigabit Ethernet device +.Sh SYNOPSIS +.Cd "ale* at pci?" +.Cd "atphy* at mii?" +.Sh DESCRIPTION +The +.Nm +driver provides support for Ethernet interfaces based on the +Atheros AR8121/AR8113/AR8114 Ethernet chipset. +.Pp +The +.Nm +driver supports IPv4 receive IP/TCP/UDP checksum offload and VLAN +tag insertion and stripping. +.Pp +The following +.Ar media +types are supported: +.Pp +.Bl -tag -width autoselect -compact +.It Cm autoselect +Enable autoselection of the media type and options. +.It Cm 10baseT +Set 10Mbps operation. +.It Cm 100baseTX +Set 100Mbps (Fast Ethernet) operation. +.It Cm 1000baseT +Set 1000Mbps (Gigabit Ethernet) operation. +.El +.Pp +For more information on configuring this device, see +.Xr ifconfig 8 . +To view a list of media types and options supported by the card, try +.Ic ifconfig <device> media . +For example, +.Ic ifconfig ale0 media . +.Sh SEE ALSO +.Xr arp 4 , +.Xr atphy 4 , +.Xr ifmedia 4 , +.Xr intro 4 , +.Xr netintro 4 , +.Xr pci 4 , +.Xr hostname.if 5 , +.Xr ifconfig 8 +.Sh HISTORY +The +.Nm +device driver first appeared in +.Ox 4.5 . +.Sh AUTHORS +.An -nosplit +The +.Nm +driver was written by +.An Pyun YongHyeon +for +.Fx +and ported to +.Ox +by +.An Kevin Lo +.Aq kevlo@openbsd.org . diff --git a/share/man/man4/pci.4 b/share/man/man4/pci.4 index 15da2b81dd2..eb07f6ea4e9 100644 --- a/share/man/man4/pci.4 +++ b/share/man/man4/pci.4 @@ -1,4 +1,4 @@ -.\" $OpenBSD: pci.4,v 1.266 2009/01/16 06:05:28 jmc Exp $ +.\" $OpenBSD: pci.4,v 1.267 2009/02/25 03:05:32 kevlo Exp $ .\" $NetBSD: pci.4,v 1.29 2000/04/01 00:32:23 tsarna Exp $ .\" .\" Copyright (c) 2000 Theo de Raadt. All rights reserved. @@ -31,7 +31,7 @@ .\" (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF .\" THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. .\" -.Dd $Mdocdate: January 16 2009 $ +.Dd $Mdocdate: February 25 2009 $ .Dt PCI 4 .Os .Sh NAME @@ -162,6 +162,8 @@ LSI Logic & Dell MegaRAID SAS RAID controller .Bl -tag -width 10n -offset ind -compact .It Xr age 4 Attansic L1 10/100/Gigabit Ethernet device +.It Xr ale 4 +Atheros AR8121/AR8113/AR8114 10/100/Gigabit Ethernet device .It Xr art 4 Accoom Networks Artery T1/E1 network adapters .It Xr bce 4 diff --git a/sys/dev/pci/files.pci b/sys/dev/pci/files.pci index a20fdf93a09..8f940fee333 100644 --- a/sys/dev/pci/files.pci +++ b/sys/dev/pci/files.pci @@ -1,4 +1,4 @@ -# $OpenBSD: files.pci,v 1.258 2009/01/16 05:00:34 kevlo Exp $ +# $OpenBSD: files.pci,v 1.259 2009/02/25 03:05:32 kevlo Exp $ # $NetBSD: files.pci,v 1.20 1996/09/24 17:47:15 christos Exp $ # # Config file and device description for machine-independent PCI code. @@ -637,6 +637,11 @@ device age: ether, ifnet, mii, ifmedia, mii_phy attach age at pci file dev/pci/if_age.c age +# Attansic/Atheros L1E Gigabit Ethernet +device ale: ether, ifnet, mii, ifmedia, mii_phy +attach ale at pci +file dev/pci/if_ale.c ale + # AMD-76x PM and SMBus controller device amdpm: i2cbus attach amdpm at pci diff --git a/sys/dev/pci/if_ale.c b/sys/dev/pci/if_ale.c new file mode 100644 index 00000000000..fdba7451845 --- /dev/null +++ b/sys/dev/pci/if_ale.c @@ -0,0 +1,2045 @@ +/* $OpenBSD: if_ale.c,v 1.1 2009/02/25 03:05:32 kevlo Exp $ */ +/*- + * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org> + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice unmodified, this list of conditions, and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD: src/sys/dev/ale/if_ale.c,v 1.3 2008/12/03 09:01:12 yongari Exp $ + */ + +/* Driver for Atheros AR8121/AR8113/AR8114 PCIe Ethernet. */ + +#include "bpfilter.h" +#include "vlan.h" + +#include <sys/param.h> +#include <sys/proc.h> +#include <sys/endian.h> +#include <sys/systm.h> +#include <sys/types.h> +#include <sys/sockio.h> +#include <sys/mbuf.h> +#include <sys/queue.h> +#include <sys/kernel.h> +#include <sys/device.h> +#include <sys/timeout.h> +#include <sys/socket.h> + +#include <machine/bus.h> + +#include <net/if.h> +#include <net/if_dl.h> +#include <net/if_llc.h> +#include <net/if_media.h> + +#ifdef INET +#include <netinet/in.h> +#include <netinet/in_systm.h> +#include <netinet/in_var.h> +#include <netinet/ip.h> +#include <netinet/if_ether.h> +#endif + +#include <net/if_types.h> +#include <net/if_vlan_var.h> + +#if NBPFILTER > 0 +#include <net/bpf.h> +#endif + +#include <dev/rndvar.h> + +#include <dev/mii/mii.h> +#include <dev/mii/miivar.h> + +#include <dev/pci/pcireg.h> +#include <dev/pci/pcivar.h> +#include <dev/pci/pcidevs.h> + +#include <dev/pci/if_alereg.h> + +int ale_match(struct device *, void *, void *); +void ale_attach(struct device *, struct device *, void *); +int ale_detach(struct device *, int); + +int ale_miibus_readreg(struct device *, int, int); +void ale_miibus_writereg(struct device *, int, int, int); +void ale_miibus_statchg(struct device *); + +int ale_init(struct ifnet *); +void ale_start(struct ifnet *); +int ale_ioctl(struct ifnet *, u_long, caddr_t); +void ale_watchdog(struct ifnet *); +int ale_mediachange(struct ifnet *); +void ale_mediastatus(struct ifnet *, struct ifmediareq *); + +int ale_intr(void *); +int ale_rxeof(struct ale_softc *sc); +void ale_rx_update_page(struct ale_softc *, struct ale_rx_page **, + uint32_t, uint32_t *); +void ale_rxcsum(struct ale_softc *, struct mbuf *, uint32_t); +void ale_txeof(struct ale_softc *); + +int ale_dma_alloc(struct ale_softc *); +void ale_dma_free(struct ale_softc *); +int ale_encap(struct ale_softc *, struct mbuf **); +void ale_init_rx_pages(struct ale_softc *); +void ale_init_tx_ring(struct ale_softc *); + +void ale_stop(struct ale_softc *); +void ale_tick(void *); +void ale_get_macaddr(struct ale_softc *); +void ale_mac_config(struct ale_softc *); +void ale_phy_reset(struct ale_softc *); +void ale_reset(struct ale_softc *); +void ale_rxfilter(struct ale_softc *); +void ale_rxvlan(struct ale_softc *); +void ale_stats_clear(struct ale_softc *); +void ale_stats_update(struct ale_softc *); +void ale_stop_mac(struct ale_softc *); + +const struct pci_matchid ale_devices[] = { + { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_L1E } +}; + +struct cfattach ale_ca = { + sizeof (struct ale_softc), ale_match, ale_attach +}; + +struct cfdriver ale_cd = { + NULL, "ale", DV_IFNET +}; + +int aledebug = 0; +#define DPRINTF(x) do { if (aledebug) printf x; } while (0) + +#define ALE_CSUM_FEATURES (M_TCPV4_CSUM_OUT | M_UDPV4_CSUM_OUT) + +int +ale_miibus_readreg(struct device *dev, int phy, int reg) +{ + struct ale_softc *sc = (struct ale_softc *)dev; + uint32_t v; + int i; + + if (phy != sc->ale_phyaddr) + return (0); + + CSR_WRITE_4(sc, ALE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | + MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); + for (i = ALE_PHY_TIMEOUT; i > 0; i--) { + DELAY(5); + v = CSR_READ_4(sc, ALE_MDIO); + if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) + break; + } + + if (i == 0) { + printf("%s: phy read timeout: phy %d, reg %d\n", + sc->sc_dev.dv_xname, phy, reg); + return (0); + } + + return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); +} + +void +ale_miibus_writereg(struct device *dev, int phy, int reg, int val) +{ + struct ale_softc *sc = (struct ale_softc *)dev; + uint32_t v; + int i; + + if (phy != sc->ale_phyaddr) + return; + + CSR_WRITE_4(sc, ALE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | + (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT | + MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); + for (i = ALE_PHY_TIMEOUT; i > 0; i--) { + DELAY(5); + v = CSR_READ_4(sc, ALE_MDIO); + if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) + break; + } + + if (i == 0) + printf("%s: phy write timeout: phy %d, reg %d\n", + sc->sc_dev.dv_xname, phy, reg); +} + +void +ale_miibus_statchg(struct device *dev) +{ + struct ale_softc *sc = (struct ale_softc *)dev; + struct ifnet *ifp = &sc->sc_arpcom.ac_if; + struct mii_data *mii; + uint32_t reg; + + if ((ifp->if_flags & IFF_RUNNING) == 0) + return; + + mii = &sc->sc_miibus; + + sc->ale_flags &= ~ALE_FLAG_LINK; + if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == + (IFM_ACTIVE | IFM_AVALID)) { + switch (IFM_SUBTYPE(mii->mii_media_active)) { + case IFM_10_T: + case IFM_100_TX: + sc->ale_flags |= ALE_FLAG_LINK; + break; + + case IFM_1000_T: + if ((sc->ale_flags & ALE_FLAG_FASTETHER) == 0) + sc->ale_flags |= ALE_FLAG_LINK; + break; + + default: + break; + } + } + + /* Stop Rx/Tx MACs. */ + ale_stop_mac(sc); + + /* Program MACs with resolved speed/duplex/flow-control. */ + if ((sc->ale_flags & ALE_FLAG_LINK) != 0) { + ale_mac_config(sc); + /* Reenable Tx/Rx MACs. */ + reg = CSR_READ_4(sc, ALE_MAC_CFG); + reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; + CSR_WRITE_4(sc, ALE_MAC_CFG, reg); + } +} + +void +ale_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) +{ + struct ale_softc *sc = ifp->if_softc; + struct mii_data *mii = &sc->sc_miibus; + + mii_pollstat(mii); + ifmr->ifm_status = mii->mii_media_status; + ifmr->ifm_active = mii->mii_media_active; +} + +int +ale_mediachange(struct ifnet *ifp) +{ + struct ale_softc *sc = ifp->if_softc; + struct mii_data *mii = &sc->sc_miibus; + int error; + + if (mii->mii_instance != 0) { + struct mii_softc *miisc; + + LIST_FOREACH(miisc, &mii->mii_phys, mii_list) + mii_phy_reset(miisc); + } + error = mii_mediachg(mii); + + return (error); +} + +int +ale_match(struct device *dev, void *match, void *aux) +{ + return pci_matchbyid((struct pci_attach_args *)aux, ale_devices, + sizeof (ale_devices) / sizeof (ale_devices[0])); +} + +void +ale_get_macaddr(struct ale_softc *sc) +{ + uint32_t ea[2], reg; + int i, vpdc; + + reg = CSR_READ_4(sc, ALE_SPI_CTRL); + if ((reg & SPI_VPD_ENB) != 0) { + reg &= ~SPI_VPD_ENB; + CSR_WRITE_4(sc, ALE_SPI_CTRL, reg); + } + + if (pci_get_capability(sc->sc_pct, sc->sc_pcitag, PCI_CAP_VPD, + &vpdc, NULL)) { + /* + * PCI VPD capability found, let TWSI reload EEPROM. + * This will set ethernet address of controller. + */ + CSR_WRITE_4(sc, ALE_TWSI_CTRL, CSR_READ_4(sc, ALE_TWSI_CTRL) | + TWSI_CTRL_SW_LD_START); + for (i = 100; i > 0; i--) { + DELAY(1000); + reg = CSR_READ_4(sc, ALE_TWSI_CTRL); + if ((reg & TWSI_CTRL_SW_LD_START) == 0) + break; + } + if (i == 0) + printf("%s: reloading EEPROM timeout!\n", + sc->sc_dev.dv_xname); + } else { + if (aledebug) + printf("%s: PCI VPD capability not found!\n", + sc->sc_dev.dv_xname); + } + + ea[0] = CSR_READ_4(sc, ALE_PAR0); + ea[1] = CSR_READ_4(sc, ALE_PAR1); + sc->ale_eaddr[0] = (ea[1] >> 8) & 0xFF; + sc->ale_eaddr[1] = (ea[1] >> 0) & 0xFF; + sc->ale_eaddr[2] = (ea[0] >> 24) & 0xFF; + sc->ale_eaddr[3] = (ea[0] >> 16) & 0xFF; + sc->ale_eaddr[4] = (ea[0] >> 8) & 0xFF; + sc->ale_eaddr[5] = (ea[0] >> 0) & 0xFF; +} + +void +ale_phy_reset(struct ale_softc *sc) +{ + /* Reset magic from Linux. */ + CSR_WRITE_2(sc, ALE_GPHY_CTRL, + GPHY_CTRL_HIB_EN | GPHY_CTRL_HIB_PULSE | GPHY_CTRL_SEL_ANA_RESET | + GPHY_CTRL_PHY_PLL_ON); + DELAY(1000); + CSR_WRITE_2(sc, ALE_GPHY_CTRL, + GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN | GPHY_CTRL_HIB_PULSE | + GPHY_CTRL_SEL_ANA_RESET | GPHY_CTRL_PHY_PLL_ON); + DELAY(1000); + +#define ATPHY_DBG_ADDR 0x1D +#define ATPHY_DBG_DATA 0x1E + + /* Enable hibernation mode. */ + ale_miibus_writereg(&sc->sc_dev, sc->ale_phyaddr, + ATPHY_DBG_ADDR, 0x0B); + ale_miibus_writereg(&sc->sc_dev, sc->ale_phyaddr, + ATPHY_DBG_DATA, 0xBC00); + /* Set Class A/B for all modes. */ + ale_miibus_writereg(&sc->sc_dev, sc->ale_phyaddr, + ATPHY_DBG_ADDR, 0x00); + ale_miibus_writereg(&sc->sc_dev, sc->ale_phyaddr, + ATPHY_DBG_DATA, 0x02EF); + /* Enable 10BT power saving. */ + ale_miibus_writereg(&sc->sc_dev, sc->ale_phyaddr, + ATPHY_DBG_ADDR, 0x12); + ale_miibus_writereg(&sc->sc_dev, sc->ale_phyaddr, + ATPHY_DBG_DATA, 0x4C04); + /* Adjust 1000T power. */ + ale_miibus_writereg(&sc->sc_dev, sc->ale_phyaddr, + ATPHY_DBG_ADDR, 0x04); + ale_miibus_writereg(&sc->sc_dev, sc->ale_phyaddr, + ATPHY_DBG_ADDR, 0x8BBB); + /* 10BT center tap voltage. */ + ale_miibus_writereg(&sc->sc_dev, sc->ale_phyaddr, + ATPHY_DBG_ADDR, 0x05); + ale_miibus_writereg(&sc->sc_dev, sc->ale_phyaddr, + ATPHY_DBG_ADDR, 0x2C46); + +#undef ATPHY_DBG_ADDR +#undef ATPHY_DBG_DATA + DELAY(1000); +} + +void +ale_attach(struct device *parent, struct device *self, void *aux) +{ + struct ale_softc *sc = (struct ale_softc *)self; + struct pci_attach_args *pa = aux; + pci_chipset_tag_t pc = pa->pa_pc; + pci_intr_handle_t ih; + const char *intrstr; + struct ifnet *ifp; + pcireg_t memtype; + int error = 0; + uint32_t rxf_len, txf_len; + + /* + * Allocate IO memory + */ + memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, ALE_PCIR_BAR); + if (pci_mapreg_map(pa, ALE_PCIR_BAR, memtype, 0, &sc->sc_mem_bt, + &sc->sc_mem_bh, NULL, &sc->sc_mem_size, 0)) { + printf(": could not map mem space\n"); + return; + } + + if (pci_intr_map(pa, &ih) != 0) { + printf(": could not map interrupt\n"); + goto fail; + } + + /* + * Allocate IRQ + */ + intrstr = pci_intr_string(pc, ih); + sc->sc_irq_handle = pci_intr_establish(pc, ih, IPL_NET, ale_intr, sc, + sc->sc_dev.dv_xname); + if (sc->sc_irq_handle == NULL) { + printf(": could not establish interrupt"); + if (intrstr != NULL) + printf(" at %s", intrstr); + printf("\n"); + goto fail; + } + printf(": %s", intrstr); + + sc->sc_dmat = pa->pa_dmat; + sc->sc_pct = pa->pa_pc; + sc->sc_pcitag = pa->pa_tag; + + /* Set PHY address. */ + sc->ale_phyaddr = ALE_PHY_ADDR; + + /* Reset PHY. */ + ale_phy_reset(sc); + + /* Reset the ethernet controller. */ + ale_reset(sc); + + /* Get PCI and chip id/revision. */ + sc->ale_rev = PCI_REVISION(pa->pa_class); + if (sc->ale_rev >= 0xF0) { + /* L2E Rev. B. AR8114 */ + sc->ale_flags |= ALE_FLAG_FASTETHER; + } else { + if ((CSR_READ_4(sc, ALE_PHY_STATUS) & PHY_STATUS_100M) != 0) { + /* L1E AR8121 */ + sc->ale_flags |= ALE_FLAG_JUMBO; + } else { + /* L2E Rev. A. AR8113 */ + sc->ale_flags |= ALE_FLAG_FASTETHER; + } + } + + /* + * All known controllers seems to require 4 bytes alignment + * of Tx buffers to make Tx checksum offload with custom + * checksum generation method work. + */ + sc->ale_flags |= ALE_FLAG_TXCSUM_BUG; + + /* + * All known controllers seems to have issues on Rx checksum + * offload for fragmented IP datagrams. + */ + sc->ale_flags |= ALE_FLAG_RXCSUM_BUG; + + /* + * Don't use Tx CMB. It is known to cause RRS update failure + * under certain circumstances. Typical phenomenon of the + * issue would be unexpected sequence number encountered in + * Rx handler. + */ + sc->ale_flags |= ALE_FLAG_TXCMB_BUG; + sc->ale_chip_rev = CSR_READ_4(sc, ALE_MASTER_CFG) >> + MASTER_CHIP_REV_SHIFT; + if (aledebug) { + printf("%s: PCI device revision : 0x%04x\n", + sc->sc_dev.dv_xname, sc->ale_rev); + printf("%s: Chip id/revision : 0x%04x\n", + sc->sc_dev.dv_xname, sc->ale_chip_rev); + } + + /* + * Uninitialized hardware returns an invalid chip id/revision + * as well as 0xFFFFFFFF for Tx/Rx fifo length. + */ + txf_len = CSR_READ_4(sc, ALE_SRAM_TX_FIFO_LEN); + rxf_len = CSR_READ_4(sc, ALE_SRAM_RX_FIFO_LEN); + if (sc->ale_chip_rev == 0xFFFF || txf_len == 0xFFFFFFFF || + rxf_len == 0xFFFFFFF) { + printf("%s: chip revision : 0x%04x, %u Tx FIFO " + "%u Rx FIFO -- not initialized?\n", sc->sc_dev.dv_xname, + sc->ale_chip_rev, txf_len, rxf_len); + goto fail; + } + + if (aledebug) { + printf("%s: %u Tx FIFO, %u Rx FIFO\n", sc->sc_dev.dv_xname, + txf_len, rxf_len); + } + + /* Set max allowable DMA size. */ + sc->ale_dma_rd_burst = DMA_CFG_RD_BURST_128; + sc->ale_dma_wr_burst = DMA_CFG_WR_BURST_128; + + error = ale_dma_alloc(sc); + if (error) + goto fail; + + /* Load station address. */ + ale_get_macaddr(sc); + + ifp = &sc->sc_arpcom.ac_if; + ifp->if_softc = sc; + ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; + ifp->if_init = ale_init; + ifp->if_ioctl = ale_ioctl; + ifp->if_start = ale_start; + ifp->if_watchdog = ale_watchdog; + ifp->if_baudrate = IF_Gbps(1); + IFQ_SET_MAXLEN(&ifp->if_snd, ALE_TX_RING_CNT - 1); + IFQ_SET_READY(&ifp->if_snd); + bcopy(sc->ale_eaddr, sc->sc_arpcom.ac_enaddr, ETHER_ADDR_LEN); + bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); + + ifp->if_capabilities = IFCAP_VLAN_MTU; + +#ifdef ALE_CHECKSUM + ifp->if_capabilities |= IFCAP_CSUM_IPv4 | IFCAP_CSUM_TCPv4 | + IFCAP_CSUM_UDPv4; +#endif + +#if NVLAN > 0 + ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING; +#endif + + printf(", address %s\n", ether_sprintf(sc->sc_arpcom.ac_enaddr)); + + /* Set up MII bus. */ + sc->sc_miibus.mii_ifp = ifp; + sc->sc_miibus.mii_readreg = ale_miibus_readreg; + sc->sc_miibus.mii_writereg = ale_miibus_writereg; + sc->sc_miibus.mii_statchg = ale_miibus_statchg; + + ifmedia_init(&sc->sc_miibus.mii_media, 0, ale_mediachange, + ale_mediastatus); + mii_attach(self, &sc->sc_miibus, 0xffffffff, MII_PHY_ANY, + MII_OFFSET_ANY, 0); + + if (LIST_FIRST(&sc->sc_miibus.mii_phys) == NULL) { + printf("%s: no PHY found!\n", sc->sc_dev.dv_xname); + ifmedia_add(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_MANUAL, + 0, NULL); + ifmedia_set(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_MANUAL); + } else + ifmedia_set(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_AUTO); + + if_attach(ifp); + ether_ifattach(ifp); + + timeout_set(&sc->ale_tick_ch, ale_tick, sc); + + return; +fail: + ale_dma_free(sc); + if (sc->sc_irq_handle != NULL) + pci_intr_disestablish(pc, sc->sc_irq_handle); + if (sc->sc_mem_size) + bus_space_unmap(sc->sc_mem_bt, sc->sc_mem_bh, sc->sc_mem_size); +} + +int +ale_detach(struct device *self, int flags) +{ + struct ale_softc *sc = (struct ale_softc *)self; + struct ifnet *ifp = &sc->sc_arpcom.ac_if; + int s; + + s = splnet(); + ale_stop(sc); + splx(s); + + mii_detach(&sc->sc_miibus, MII_PHY_ANY, MII_OFFSET_ANY); + + /* Delete all remaining media. */ + ifmedia_delete_instance(&sc->sc_miibus.mii_media, IFM_INST_ANY); + + ether_ifdetach(ifp); + if_detach(ifp); + ale_dma_free(sc); + + if (sc->sc_irq_handle != NULL) { + pci_intr_disestablish(sc->sc_pct, sc->sc_irq_handle); + sc->sc_irq_handle = NULL; + } + + return (0); +} + + +int +ale_dma_alloc(struct ale_softc *sc) +{ + struct ale_txdesc *txd; + int nsegs, error, guard_size, i; + + if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) + guard_size = ALE_JUMBO_FRAMELEN; + else + guard_size = ALE_MAX_FRAMELEN; + sc->ale_pagesize = roundup(guard_size + ALE_RX_PAGE_SZ, + ALE_RX_PAGE_ALIGN); + + /* + * Create DMA stuffs for TX ring + */ + error = bus_dmamap_create(sc->sc_dmat, ALE_TX_RING_SZ, 1, + ALE_TX_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->ale_cdata.ale_tx_ring_map); + if (error) + return (ENOBUFS); + + /* Allocate DMA'able memory for TX ring */ + error = bus_dmamem_alloc(sc->sc_dmat, ALE_TX_RING_SZ, + ETHER_ALIGN, 0, &sc->ale_cdata.ale_tx_ring_seg, 1, + &nsegs, BUS_DMA_WAITOK); + if (error) { + printf("%s: could not allocate DMA'able memory for Tx ring.\n", + sc->sc_dev.dv_xname); + return error; + } + + error = bus_dmamem_map(sc->sc_dmat, &sc->ale_cdata.ale_tx_ring_seg, + nsegs, ALE_TX_RING_SZ, (caddr_t *)&sc->ale_cdata.ale_tx_ring, + BUS_DMA_NOWAIT); + if (error) + return (ENOBUFS); + + bzero(sc->ale_cdata.ale_tx_ring, ALE_TX_RING_SZ); + + /* Load the DMA map for Tx ring. */ + error = bus_dmamap_load(sc->sc_dmat, sc->ale_cdata.ale_tx_ring_map, + sc->ale_cdata.ale_tx_ring, ALE_TX_RING_SZ, NULL, BUS_DMA_WAITOK); + if (error) { + printf("%s: could not load DMA'able memory for Tx ring.\n", + sc->sc_dev.dv_xname); + bus_dmamem_free(sc->sc_dmat, + (bus_dma_segment_t *)&sc->ale_cdata.ale_tx_ring, 1); + return error; + } + sc->ale_cdata.ale_tx_ring_paddr = + sc->ale_cdata.ale_tx_ring_map->dm_segs[0].ds_addr; + + for (i = 0; i < ALE_RX_PAGES; i++) { + /* + * Create DMA stuffs for RX pages + */ + error = bus_dmamap_create(sc->sc_dmat, sc->ale_pagesize, 1, + sc->ale_pagesize, 0, BUS_DMA_NOWAIT, + &sc->ale_cdata.ale_rx_page[i].page_map); + if (error) + return (ENOBUFS); + + /* Allocate DMA'able memory for RX pages */ + error = bus_dmamem_alloc(sc->sc_dmat, sc->ale_pagesize, + ETHER_ALIGN, 0, &sc->ale_cdata.ale_rx_page[i].page_seg, + 1, &nsegs, BUS_DMA_WAITOK); + if (error) { + printf("%s: could not allocate DMA'able memory for " + "Rx ring.\n", sc->sc_dev.dv_xname); + return error; + } + error = bus_dmamem_map(sc->sc_dmat, + &sc->ale_cdata.ale_rx_page[i].page_seg, nsegs, + sc->ale_pagesize, + (caddr_t *)&sc->ale_cdata.ale_rx_page[i].page_addr, + BUS_DMA_NOWAIT); + if (error) + return (ENOBUFS); + + bzero(sc->ale_cdata.ale_rx_page[i].page_addr, sc->ale_pagesize); + + /* Load the DMA map for Rx pages. */ + error = bus_dmamap_load(sc->sc_dmat, + sc->ale_cdata.ale_rx_page[i].page_map, + sc->ale_cdata.ale_rx_page[i].page_addr, + sc->ale_pagesize, NULL, BUS_DMA_WAITOK); + if (error) { + printf("%s: could not load DMA'able memory for " + "Rx pages.\n", sc->sc_dev.dv_xname); + bus_dmamem_free(sc->sc_dmat, + (bus_dma_segment_t *)sc->ale_cdata.ale_rx_page[i].page_addr, 1); + return error; + } + sc->ale_cdata.ale_rx_page[i].page_paddr = + sc->ale_cdata.ale_rx_page[i].page_map->dm_segs[0].ds_addr; + } + + /* + * Create DMA stuffs for Tx CMB. + */ + error = bus_dmamap_create(sc->sc_dmat, ALE_TX_CMB_SZ, 1, + ALE_TX_CMB_SZ, 0, BUS_DMA_NOWAIT, &sc->ale_cdata.ale_tx_cmb_map); + if (error) + return (ENOBUFS); + + /* Allocate DMA'able memory for Tx CMB. */ + error = bus_dmamem_alloc(sc->sc_dmat, ALE_TX_CMB_SZ, ETHER_ALIGN, 0, + &sc->ale_cdata.ale_tx_cmb_seg, 1, &nsegs, BUS_DMA_WAITOK); + + if (error) { + printf("%s: could not allocate DMA'able memory for Tx CMB.\n", + sc->sc_dev.dv_xname); + return error; + } + + error = bus_dmamem_map(sc->sc_dmat, &sc->ale_cdata.ale_tx_cmb_seg, + nsegs, ALE_TX_CMB_SZ, (caddr_t *)&sc->ale_cdata.ale_tx_cmb, + BUS_DMA_NOWAIT); + if (error) + return (ENOBUFS); + + bzero(sc->ale_cdata.ale_tx_cmb, ALE_TX_CMB_SZ); + + /* Load the DMA map for Tx CMB. */ + error = bus_dmamap_load(sc->sc_dmat, sc->ale_cdata.ale_tx_cmb_map, + sc->ale_cdata.ale_tx_cmb, ALE_TX_CMB_SZ, NULL, BUS_DMA_WAITOK); + if (error) { + printf("%s: could not load DMA'able memory for Tx CMB.\n", + sc->sc_dev.dv_xname); + bus_dmamem_free(sc->sc_dmat, + (bus_dma_segment_t *)&sc->ale_cdata.ale_tx_cmb, 1); + return error; + } + + sc->ale_cdata.ale_tx_cmb_paddr = + sc->ale_cdata.ale_tx_cmb_map->dm_segs[0].ds_addr; + + for (i = 0; i < ALE_RX_PAGES; i++) { + /* + * Create DMA stuffs for Rx CMB. + */ + error = bus_dmamap_create(sc->sc_dmat, ALE_RX_CMB_SZ, 1, + ALE_RX_CMB_SZ, 0, BUS_DMA_NOWAIT, + &sc->ale_cdata.ale_rx_page[i].cmb_map); + if (error) + return (ENOBUFS); + + /* Allocate DMA'able memory for Rx CMB */ + error = bus_dmamem_alloc(sc->sc_dmat, ALE_RX_CMB_SZ, + ETHER_ALIGN, 0, &sc->ale_cdata.ale_rx_page[i].cmb_seg, 1, + &nsegs, BUS_DMA_WAITOK); + if (error) { + printf("%s: could not allocate DMA'able memory for " + "Rx CMB\n", sc->sc_dev.dv_xname); + return error; + } + error = bus_dmamem_map(sc->sc_dmat, + &sc->ale_cdata.ale_rx_page[i].cmb_seg, nsegs, + ALE_RX_CMB_SZ, + (caddr_t *)&sc->ale_cdata.ale_rx_page[i].cmb_addr, + BUS_DMA_NOWAIT); + if (error) + return (ENOBUFS); + + bzero(sc->ale_cdata.ale_rx_page[i].cmb_addr, ALE_RX_CMB_SZ); + + /* Load the DMA map for Rx CMB */ + error = bus_dmamap_load(sc->sc_dmat, + sc->ale_cdata.ale_rx_page[i].cmb_map, + sc->ale_cdata.ale_rx_page[i].cmb_addr, + ALE_RX_CMB_SZ, NULL, BUS_DMA_WAITOK); + if (error) { + printf("%s: could not load DMA'able memory for Rx CMB" + "\n", sc->sc_dev.dv_xname); + bus_dmamem_free(sc->sc_dmat, + (bus_dma_segment_t *)&sc->ale_cdata.ale_rx_page[i].cmb_addr, 1); + return error; + } + sc->ale_cdata.ale_rx_page[i].cmb_paddr = + sc->ale_cdata.ale_rx_page[i].cmb_map->dm_segs[0].ds_addr; + } + + + /* Create DMA maps for Tx buffers. */ + for (i = 0; i < ALE_TX_RING_CNT; i++) { + txd = &sc->ale_cdata.ale_txdesc[i]; + txd->tx_m = NULL; + txd->tx_dmamap = NULL; + error = bus_dmamap_create(sc->sc_dmat, ALE_TSO_MAXSIZE, + ALE_MAXTXSEGS, ALE_TSO_MAXSEGSIZE, 0, BUS_DMA_NOWAIT, + &txd->tx_dmamap); + if (error) { + printf("%s: could not create Tx dmamap.\n", + sc->sc_dev.dv_xname); + return error; + } + } + + return (0); +} + +void +ale_dma_free(struct ale_softc *sc) +{ + struct ale_txdesc *txd; + int i; + + /* Tx buffers. */ + for (i = 0; i < ALE_TX_RING_CNT; i++) { + txd = &sc->ale_cdata.ale_txdesc[i]; + if (txd->tx_dmamap != NULL) { + bus_dmamap_destroy(sc->sc_dmat, txd->tx_dmamap); + txd->tx_dmamap = NULL; + } + } + + /* Tx descriptor ring. */ + if (sc->ale_cdata.ale_tx_ring_map != NULL) + bus_dmamap_unload(sc->sc_dmat, sc->ale_cdata.ale_tx_ring_map); + if (sc->ale_cdata.ale_tx_ring_map != NULL && + sc->ale_cdata.ale_tx_ring != NULL) + bus_dmamem_free(sc->sc_dmat, + (bus_dma_segment_t *)sc->ale_cdata.ale_tx_ring, 1); + sc->ale_cdata.ale_tx_ring = NULL; + sc->ale_cdata.ale_tx_ring_map = NULL; + + /* Rx page block. */ + for (i = 0; i < ALE_RX_PAGES; i++) { + if (sc->ale_cdata.ale_rx_page[i].page_map != NULL) + bus_dmamap_unload(sc->sc_dmat, + sc->ale_cdata.ale_rx_page[i].page_map); + if (sc->ale_cdata.ale_rx_page[i].page_map != NULL && + sc->ale_cdata.ale_rx_page[i].page_addr != NULL) + bus_dmamem_free(sc->sc_dmat, + (bus_dma_segment_t *)sc->ale_cdata.ale_rx_page[i].page_addr, 1); + sc->ale_cdata.ale_rx_page[i].page_addr = NULL; + sc->ale_cdata.ale_rx_page[i].page_map = NULL; + } + + /* Rx CMB. */ + for (i = 0; i < ALE_RX_PAGES; i++) { + if (sc->ale_cdata.ale_rx_page[i].cmb_map != NULL) + bus_dmamap_unload(sc->sc_dmat, + sc->ale_cdata.ale_rx_page[i].cmb_map); + if (sc->ale_cdata.ale_rx_page[i].cmb_map != NULL && + sc->ale_cdata.ale_rx_page[i].cmb_addr != NULL) + bus_dmamem_free(sc->sc_dmat, + (bus_dma_segment_t *)sc->ale_cdata.ale_rx_page[i].cmb_addr, 1); + sc->ale_cdata.ale_rx_page[i].cmb_addr = NULL; + sc->ale_cdata.ale_rx_page[i].cmb_map = NULL; + } + + /* Tx CMB. */ + if (sc->ale_cdata.ale_tx_cmb_map != NULL) + bus_dmamap_unload(sc->sc_dmat, sc->ale_cdata.ale_tx_cmb_map); + if (sc->ale_cdata.ale_tx_cmb_map != NULL && + sc->ale_cdata.ale_tx_cmb != NULL) + bus_dmamem_free(sc->sc_dmat, + (bus_dma_segment_t *)sc->ale_cdata.ale_tx_cmb, 1); + sc->ale_cdata.ale_tx_cmb = NULL; + sc->ale_cdata.ale_tx_cmb_map = NULL; + +} + +int +ale_encap(struct ale_softc *sc, struct mbuf **m_head) +{ + struct ale_txdesc *txd, *txd_last; + struct tx_desc *desc; + struct mbuf *m; + bus_dmamap_t map; + uint32_t cflags, poff, vtag; + int error, i, nsegs, prod; + + m = *m_head; + cflags = vtag = 0; + poff = 0; + + prod = sc->ale_cdata.ale_tx_prod; + txd = &sc->ale_cdata.ale_txdesc[prod]; + txd_last = txd; + map = txd->tx_dmamap; + + error = bus_dmamap_load_mbuf(sc->sc_dmat, map, *m_head, BUS_DMA_NOWAIT); + + if (error != 0) { + bus_dmamap_unload(sc->sc_dmat, map); + error = EFBIG; + } + if (error == EFBIG) { + error = 0; + + MGETHDR(m, M_DONTWAIT, MT_DATA); + if (m == NULL) { + printf("%s: can't defrag TX mbuf\n", + sc->sc_dev.dv_xname); + m_freem(*m_head); + *m_head = NULL; + return (ENOBUFS); + } + + M_DUP_PKTHDR(m, *m_head); + if ((*m_head)->m_pkthdr.len > MHLEN) { + MCLGET(m, M_DONTWAIT); + if (!(m->m_flags & M_EXT)) { + m_freem(*m_head); + m_freem(m); + *m_head = NULL; + return (ENOBUFS); + } + } + m_copydata(*m_head, 0, (*m_head)->m_pkthdr.len, + mtod(m, caddr_t)); + m_freem(*m_head); + m->m_len = m->m_pkthdr.len; + *m_head = m; + + error = bus_dmamap_load_mbuf(sc->sc_dmat, map, *m_head, + BUS_DMA_NOWAIT); + + if (error != 0) { + printf("%s: could not load defragged TX mbuf\n", + sc->sc_dev.dv_xname); + if (!error) { + bus_dmamap_unload(sc->sc_dmat, map); + error = EFBIG; + } + m_freem(*m_head); + *m_head = NULL; + return (error); + } + } else if (error) { + printf("%s: could not load TX mbuf\n", sc->sc_dev.dv_xname); + return (error); + } + + nsegs = map->dm_nsegs; + + if (nsegs == 0) { + m_freem(*m_head); + *m_head = NULL; + return (EIO); + } + + /* Check descriptor overrun. */ + if (sc->ale_cdata.ale_tx_cnt + nsegs >= ALE_TX_RING_CNT - 2) { + bus_dmamap_unload(sc->sc_dmat, map); + return (ENOBUFS); + } + bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, + BUS_DMASYNC_PREWRITE); + + m = *m_head; + /* Configure Tx checksum offload. */ + if ((m->m_pkthdr.csum_flags & ALE_CSUM_FEATURES) != 0) { + /* + * AR81xx supports Tx custom checksum offload feature + * that offloads single 16bit checksum computation. + * So you can choose one among IP, TCP and UDP. + * Normally driver sets checksum start/insertion + * position from the information of TCP/UDP frame as + * TCP/UDP checksum takes more time than that of IP. + * However it seems that custom checksum offload + * requires 4 bytes aligned Tx buffers due to hardware + * bug. + * AR81xx also supports explicit Tx checksum computation + * if it is told that the size of IP header and TCP + * header(for UDP, the header size does not matter + * because it's fixed length). However with this scheme + * TSO does not work so you have to choose one either + * TSO or explicit Tx checksum offload. I chosen TSO + * plus custom checksum offload with work-around which + * will cover most common usage for this consumer + * ethernet controller. The work-around takes a lot of + * CPU cycles if Tx buffer is not aligned on 4 bytes + * boundary, though. + */ + cflags |= ALE_TD_CXSUM; + /* Set checksum start offset. */ + cflags |= (poff << ALE_TD_CSUM_PLOADOFFSET_SHIFT); + } + +#if NVLAN > 0 + /* Configure VLAN hardware tag insertion. */ + if (m->m_flags & M_VLANTAG) { + vtag = ALE_TX_VLAN_TAG(m->m_pkthdr.ether_vtag); + vtag = ((vtag << ALE_TD_VLAN_SHIFT) & ALE_TD_VLAN_MASK); + cflags |= ALE_TD_INSERT_VLAN_TAG; + } +#endif + + desc = NULL; + for (i = 0; i < nsegs; i++) { + desc = &sc->ale_cdata.ale_tx_ring[prod]; + desc->addr = htole64(map->dm_segs[i].ds_addr); + desc->len = + htole32(ALE_TX_BYTES(map->dm_segs[i].ds_len) | vtag); + desc->flags = htole32(cflags); + sc->ale_cdata.ale_tx_cnt++; + ALE_DESC_INC(prod, ALE_TX_RING_CNT); + } + /* Update producer index. */ + sc->ale_cdata.ale_tx_prod = prod; + + /* Finally set EOP on the last descriptor. */ + prod = (prod + ALE_TX_RING_CNT - 1) % ALE_TX_RING_CNT; + desc = &sc->ale_cdata.ale_tx_ring[prod]; + desc->flags |= htole32(ALE_TD_EOP); + + /* Swap dmamap of the first and the last. */ + txd = &sc->ale_cdata.ale_txdesc[prod]; + map = txd_last->tx_dmamap; + txd_last->tx_dmamap = txd->tx_dmamap; + txd->tx_dmamap = map; + txd->tx_m = m; + + /* Sync descriptors. */ + bus_dmamap_sync(sc->sc_dmat, sc->ale_cdata.ale_tx_ring_map, 0, + sc->ale_cdata.ale_tx_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); + + return (0); +} + +void +ale_start(struct ifnet *ifp) +{ + struct ale_softc *sc = ifp->if_softc; + struct mbuf *m_head; + int enq; + + if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) + return; + + /* Reclaim transmitted frames. */ + if (sc->ale_cdata.ale_tx_cnt >= ALE_TX_DESC_HIWAT) + ale_txeof(sc); + + enq = 0; + for (;;) { + IFQ_DEQUEUE(&ifp->if_snd, m_head); + if (m_head == NULL) + break; + + /* + * Pack the data into the transmit ring. If we + * don't have room, set the OACTIVE flag and wait + * for the NIC to drain the ring. + */ + if (ale_encap(sc, &m_head)) { + if (m_head == NULL) + break; + ifp->if_flags |= IFF_OACTIVE; + break; + } + enq = 1; + +#if NBPFILTER > 0 + /* + * If there's a BPF listener, bounce a copy of this frame + * to him. + */ + if (ifp->if_bpf != NULL) + bpf_mtap_ether(ifp->if_bpf, m_head, BPF_DIRECTION_OUT); +#endif + } + + if (enq) { + /* Kick. */ + CSR_WRITE_4(sc, ALE_MBOX_TPD_PROD_IDX, + sc->ale_cdata.ale_tx_prod); + + /* Set a timeout in case the chip goes out to lunch. */ + ifp->if_timer = ALE_TX_TIMEOUT; + } +} + +void +ale_watchdog(struct ifnet *ifp) +{ + struct ale_softc *sc = ifp->if_softc; + + if ((sc->ale_flags & ALE_FLAG_LINK) == 0) { + printf("%s: watchdog timeout (missed link)\n", + sc->sc_dev.dv_xname); + ifp->if_oerrors++; + ale_init(ifp); + return; + } + + printf("%s: watchdog timeout\n", sc->sc_dev.dv_xname); + ifp->if_oerrors++; + ale_init(ifp); + + if (!IFQ_IS_EMPTY(&ifp->if_snd)) + ale_start(ifp); +} + +int +ale_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) +{ + struct ale_softc *sc = ifp->if_softc; + struct mii_data *mii = &sc->sc_miibus; + struct ifaddr *ifa = (struct ifaddr *)data; + struct ifreq *ifr = (struct ifreq *)data; + int s, error = 0; + + s = splnet(); + + switch (cmd) { + case SIOCSIFADDR: + ifp->if_flags |= IFF_UP; + if (!(ifp->if_flags & IFF_RUNNING)) + ale_init(ifp); +#ifdef INET + if (ifa->ifa_addr->sa_family == AF_INET) + arp_ifinit(&sc->sc_arpcom, ifa); +#endif + break; + + case SIOCSIFFLAGS: + if (ifp->if_flags & IFF_UP) { + if (ifp->if_flags & IFF_RUNNING) + error = ENETRESET; + else + ale_init(ifp); + } else { + if (ifp->if_flags & IFF_RUNNING) + ale_stop(sc); + } + break; + + case SIOCSIFMEDIA: + case SIOCGIFMEDIA: + error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); + break; + + default: + error = ether_ioctl(ifp, &sc->sc_arpcom, cmd, data); + break; + } + + if (error == ENETRESET) { + if (ifp->if_flags & IFF_RUNNING) + ale_rxfilter(sc); + error = 0; + } + + splx(s); + return (error); +} + +void +ale_mac_config(struct ale_softc *sc) +{ + struct mii_data *mii; + uint32_t reg; + + mii = &sc->sc_miibus; + reg = CSR_READ_4(sc, ALE_MAC_CFG); + reg &= ~(MAC_CFG_FULL_DUPLEX | MAC_CFG_TX_FC | MAC_CFG_RX_FC | + MAC_CFG_SPEED_MASK); + /* Reprogram MAC with resolved speed/duplex. */ + switch (IFM_SUBTYPE(mii->mii_media_active)) { + case IFM_10_T: + case IFM_100_TX: + reg |= MAC_CFG_SPEED_10_100; + break; + case IFM_1000_T: + reg |= MAC_CFG_SPEED_1000; + break; + } + if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { + reg |= MAC_CFG_FULL_DUPLEX; +#ifdef notyet + if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) + reg |= MAC_CFG_TX_FC; + if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) + reg |= MAC_CFG_RX_FC; +#endif + } + CSR_WRITE_4(sc, ALE_MAC_CFG, reg); +} + +void +ale_stats_clear(struct ale_softc *sc) +{ + struct smb sb; + uint32_t *reg; + int i; + + for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; reg++) { + CSR_READ_4(sc, ALE_RX_MIB_BASE + i); + i += sizeof(uint32_t); + } + /* Read Tx statistics. */ + for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; reg++) { + CSR_READ_4(sc, ALE_TX_MIB_BASE + i); + i += sizeof(uint32_t); + } +} + +void +ale_stats_update(struct ale_softc *sc) +{ + struct ifnet *ifp = &sc->sc_arpcom.ac_if; + struct ale_hw_stats *stat; + struct smb sb, *smb; + uint32_t *reg; + int i; + + stat = &sc->ale_stats; + smb = &sb; + + /* Read Rx statistics. */ + for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; reg++) { + *reg = CSR_READ_4(sc, ALE_RX_MIB_BASE + i); + i += sizeof(uint32_t); + } + /* Read Tx statistics. */ + for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; reg++) { + *reg = CSR_READ_4(sc, ALE_TX_MIB_BASE + i); + i += sizeof(uint32_t); + } + + /* Rx stats. */ + stat->rx_frames += smb->rx_frames; + stat->rx_bcast_frames += smb->rx_bcast_frames; + stat->rx_mcast_frames += smb->rx_mcast_frames; + stat->rx_pause_frames += smb->rx_pause_frames; + stat->rx_control_frames += smb->rx_control_frames; + stat->rx_crcerrs += smb->rx_crcerrs; + stat->rx_lenerrs += smb->rx_lenerrs; + stat->rx_bytes += smb->rx_bytes; + stat->rx_runts += smb->rx_runts; + stat->rx_fragments += smb->rx_fragments; + stat->rx_pkts_64 += smb->rx_pkts_64; + stat->rx_pkts_65_127 += smb->rx_pkts_65_127; + stat->rx_pkts_128_255 += smb->rx_pkts_128_255; + stat->rx_pkts_256_511 += smb->rx_pkts_256_511; + stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023; + stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518; + stat->rx_pkts_1519_max += smb->rx_pkts_1519_max; + stat->rx_pkts_truncated += smb->rx_pkts_truncated; + stat->rx_fifo_oflows += smb->rx_fifo_oflows; + stat->rx_rrs_errs += smb->rx_rrs_errs; + stat->rx_alignerrs += smb->rx_alignerrs; + stat->rx_bcast_bytes += smb->rx_bcast_bytes; + stat->rx_mcast_bytes += smb->rx_mcast_bytes; + stat->rx_pkts_filtered += smb->rx_pkts_filtered; + + /* Tx stats. */ + stat->tx_frames += smb->tx_frames; + stat->tx_bcast_frames += smb->tx_bcast_frames; + stat->tx_mcast_frames += smb->tx_mcast_frames; + stat->tx_pause_frames += smb->tx_pause_frames; + stat->tx_excess_defer += smb->tx_excess_defer; + stat->tx_control_frames += smb->tx_control_frames; + stat->tx_deferred += smb->tx_deferred; + stat->tx_bytes += smb->tx_bytes; + stat->tx_pkts_64 += smb->tx_pkts_64; + stat->tx_pkts_65_127 += smb->tx_pkts_65_127; + stat->tx_pkts_128_255 += smb->tx_pkts_128_255; + stat->tx_pkts_256_511 += smb->tx_pkts_256_511; + stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023; + stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518; + stat->tx_pkts_1519_max += smb->tx_pkts_1519_max; + stat->tx_single_colls += smb->tx_single_colls; + stat->tx_multi_colls += smb->tx_multi_colls; + stat->tx_late_colls += smb->tx_late_colls; + stat->tx_excess_colls += smb->tx_excess_colls; + stat->tx_abort += smb->tx_abort; + stat->tx_underrun += smb->tx_underrun; + stat->tx_desc_underrun += smb->tx_desc_underrun; + stat->tx_lenerrs += smb->tx_lenerrs; + stat->tx_pkts_truncated += smb->tx_pkts_truncated; + stat->tx_bcast_bytes += smb->tx_bcast_bytes; + stat->tx_mcast_bytes += smb->tx_mcast_bytes; + + /* Update counters in ifnet. */ + ifp->if_opackets += smb->tx_frames; + + ifp->if_collisions += smb->tx_single_colls + + smb->tx_multi_colls * 2 + smb->tx_late_colls + + smb->tx_abort * HDPX_CFG_RETRY_DEFAULT; + + /* + * XXX + * tx_pkts_truncated counter looks suspicious. It constantly + * increments with no sign of Tx errors. This may indicate + * the counter name is not correct one so I've removed the + * counter in output errors. + */ + ifp->if_oerrors += smb->tx_abort + smb->tx_late_colls + + smb->tx_underrun; + + ifp->if_ipackets += smb->rx_frames; + + ifp->if_ierrors += smb->rx_crcerrs + smb->rx_lenerrs + + smb->rx_runts + smb->rx_pkts_truncated + + smb->rx_fifo_oflows + smb->rx_rrs_errs + + smb->rx_alignerrs; +} + +int +ale_intr(void *xsc) +{ + struct ale_softc *sc = xsc; + struct ifnet *ifp = &sc->sc_arpcom.ac_if; + uint32_t status; + + status = CSR_READ_4(sc, ALE_INTR_STATUS); + if ((status & ALE_INTRS) == 0) + return (0); + + /* Acknowledge and disable interrupts. */ + CSR_WRITE_4(sc, ALE_INTR_STATUS, status | INTR_DIS_INT); + + if (ifp->if_flags & IFF_RUNNING) { + int error; + + error = ale_rxeof(sc); + if (error) { + sc->ale_stats.reset_brk_seq++; + ale_init(ifp); + return (0); + } + + if (status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST)) { + if (status & INTR_DMA_RD_TO_RST) + printf("%s: DMA read error! -- resetting\n", + sc->sc_dev.dv_xname); + if (status & INTR_DMA_WR_TO_RST) + printf("%s: DMA write error! -- resetting\n", + sc->sc_dev.dv_xname); + ale_init(ifp); + return (0); + } + + ale_txeof(sc); + if (!IFQ_IS_EMPTY(&ifp->if_snd)) + ale_start(ifp); + } + + /* Re-enable interrupts. */ + CSR_WRITE_4(sc, ALE_INTR_STATUS, 0x7FFFFFFF); + return (1); +} + +void +ale_txeof(struct ale_softc *sc) +{ + struct ifnet *ifp = &sc->sc_arpcom.ac_if; + struct ale_txdesc *txd; + uint32_t cons, prod; + int prog; + + if (sc->ale_cdata.ale_tx_cnt == 0) + return; + + bus_dmamap_sync(sc->sc_dmat, sc->ale_cdata.ale_tx_ring_map, 0, + sc->ale_cdata.ale_tx_ring_map->dm_mapsize, BUS_DMASYNC_POSTREAD); + if ((sc->ale_flags & ALE_FLAG_TXCMB_BUG) == 0) { + bus_dmamap_sync(sc->sc_dmat, sc->ale_cdata.ale_tx_cmb_map, 0, + sc->ale_cdata.ale_tx_cmb_map->dm_mapsize, + BUS_DMASYNC_POSTREAD); + prod = *sc->ale_cdata.ale_tx_cmb & TPD_CNT_MASK; + } else + prod = CSR_READ_2(sc, ALE_TPD_CONS_IDX); + cons = sc->ale_cdata.ale_tx_cons; + /* + * Go through our Tx list and free mbufs for those + * frames which have been transmitted. + */ + for (prog = 0; cons != prod; prog++, + ALE_DESC_INC(cons, ALE_TX_RING_CNT)) { + if (sc->ale_cdata.ale_tx_cnt <= 0) + break; + prog++; + ifp->if_flags &= ~IFF_OACTIVE; + sc->ale_cdata.ale_tx_cnt--; + txd = &sc->ale_cdata.ale_txdesc[cons]; + if (txd->tx_m != NULL) { + /* Reclaim transmitted mbufs. */ + bus_dmamap_unload(sc->sc_dmat, txd->tx_dmamap); + m_freem(txd->tx_m); + txd->tx_m = NULL; + } + } + + if (prog > 0) { + sc->ale_cdata.ale_tx_cons = cons; + /* + * Unarm watchdog timer only when there is no pending + * Tx descriptors in queue. + */ + if (sc->ale_cdata.ale_tx_cnt == 0) + ifp->if_timer = 0; + } +} + +void +ale_rx_update_page(struct ale_softc *sc, struct ale_rx_page **page, + uint32_t length, uint32_t *prod) +{ + struct ale_rx_page *rx_page; + + rx_page = *page; + /* Update consumer position. */ + rx_page->cons += roundup(length + sizeof(struct rx_rs), + ALE_RX_PAGE_ALIGN); + if (rx_page->cons >= ALE_RX_PAGE_SZ) { + /* + * End of Rx page reached, let hardware reuse + * this page. + */ + rx_page->cons = 0; + *rx_page->cmb_addr = 0; + bus_dmamap_sync(sc->sc_dmat, rx_page->cmb_map, 0, + rx_page->cmb_map->dm_mapsize, BUS_DMASYNC_PREWRITE); + CSR_WRITE_1(sc, ALE_RXF0_PAGE0 + sc->ale_cdata.ale_rx_curp, + RXF_VALID); + /* Switch to alternate Rx page. */ + sc->ale_cdata.ale_rx_curp ^= 1; + rx_page = *page = + &sc->ale_cdata.ale_rx_page[sc->ale_cdata.ale_rx_curp]; + /* Page flipped, sync CMB and Rx page. */ + bus_dmamap_sync(sc->sc_dmat, rx_page->page_map, 0, + rx_page->page_map->dm_mapsize, BUS_DMASYNC_POSTREAD); + bus_dmamap_sync(sc->sc_dmat, rx_page->cmb_map, 0, + rx_page->cmb_map->dm_mapsize, BUS_DMASYNC_POSTREAD); + /* Sync completed, cache updated producer index. */ + *prod = *rx_page->cmb_addr; + } +} + + +/* + * It seems that AR81xx controller can compute partial checksum. + * The partial checksum value can be used to accelerate checksum + * computation for fragmented TCP/UDP packets. Upper network stack + * already takes advantage of the partial checksum value in IP + * reassembly stage. But I'm not sure the correctness of the + * partial hardware checksum assistance due to lack of data sheet. + * In addition, the Rx feature of controller that requires copying + * for every frames effectively nullifies one of most nice offload + * capability of controller. + */ +void +ale_rxcsum(struct ale_softc *sc, struct mbuf *m, uint32_t status) +{ + struct ip *ip; + char *p; + + if ((status & ALE_RD_IPCSUM_NOK) == 0) + m->m_pkthdr.csum_flags |= M_IPV4_CSUM_IN_OK; + + if ((sc->ale_flags & ALE_FLAG_RXCSUM_BUG) == 0) { + if (((status & ALE_RD_IPV4_FRAG) == 0) && + ((status & (ALE_RD_TCP | ALE_RD_UDP)) != 0) && + ((status & ALE_RD_TCP_UDPCSUM_NOK) == 0)) { + m->m_pkthdr.csum_flags |= + M_TCP_CSUM_IN_OK | M_UDP_CSUM_IN_OK; + } + } else { + if ((status & (ALE_RD_TCP | ALE_RD_UDP)) != 0 && + (status & ALE_RD_TCP_UDPCSUM_NOK) == 0) { + p = mtod(m, char *); + p += ETHER_HDR_LEN; + if ((status & ALE_RD_802_3) != 0) + p += LLC_SNAPFRAMELEN; +#if NVLAN > 0 + if (status & ALE_RD_VLAN) + p += EVL_ENCAPLEN; +#endif + ip = (struct ip *)p; + if (ip->ip_off != 0 && (status & ALE_RD_IPV4_DF) == 0) + return; + m->m_pkthdr.csum_flags |= + M_TCP_CSUM_IN_OK | M_UDP_CSUM_IN_OK; + } + } + /* + * Don't mark bad checksum for TCP/UDP frames + * as fragmented frames may always have set + * bad checksummed bit of frame status. + */ +} + +/* Process received frames. */ +int +ale_rxeof(struct ale_softc *sc) +{ + struct ifnet *ifp = &sc->sc_arpcom.ac_if; + struct ale_rx_page *rx_page; + struct rx_rs *rs; + struct mbuf *m; + uint32_t length, prod, seqno, status; + int prog; + + rx_page = &sc->ale_cdata.ale_rx_page[sc->ale_cdata.ale_rx_curp]; + bus_dmamap_sync(sc->sc_dmat, rx_page->cmb_map, 0, + rx_page->cmb_map->dm_mapsize, BUS_DMASYNC_POSTREAD); + bus_dmamap_sync(sc->sc_dmat, rx_page->page_map, 0, + rx_page->page_map->dm_mapsize, BUS_DMASYNC_POSTREAD); + /* + * Don't directly access producer index as hardware may + * update it while Rx handler is in progress. It would + * be even better if there is a way to let hardware + * know how far driver processed its received frames. + * Alternatively, hardware could provide a way to disable + * CMB updates until driver acknowledges the end of CMB + * access. + */ + prod = *rx_page->cmb_addr; + for (prog = 0; ; prog++) { + if (rx_page->cons >= prod) + break; + rs = (struct rx_rs *)(rx_page->page_addr + rx_page->cons); + seqno = ALE_RX_SEQNO(letoh32(rs->seqno)); + if (sc->ale_cdata.ale_rx_seqno != seqno) { + /* + * Normally I believe this should not happen unless + * severe driver bug or corrupted memory. However + * it seems to happen under certain conditions which + * is triggered by abrupt Rx events such as initiation + * of bulk transfer of remote host. It's not easy to + * reproduce this and I doubt it could be related + * with FIFO overflow of hardware or activity of Tx + * CMB updates. I also remember similar behaviour + * seen on RealTek 8139 which uses resembling Rx + * scheme. + */ + if (aledebug) + printf("%s: garbled seq: %u, expected: %u -- " + "resetting!\n", sc->sc_dev.dv_xname, + seqno, sc->ale_cdata.ale_rx_seqno); + return (EIO); + } + /* Frame received. */ + sc->ale_cdata.ale_rx_seqno++; + length = ALE_RX_BYTES(letoh32(rs->length)); + status = letoh32(rs->flags); + if (status & ALE_RD_ERROR) { + /* + * We want to pass the following frames to upper + * layer regardless of error status of Rx return + * status. + * + * o IP/TCP/UDP checksum is bad. + * o frame length and protocol specific length + * does not match. + */ + if (status & (ALE_RD_CRC | ALE_RD_CODE | + ALE_RD_DRIBBLE | ALE_RD_RUNT | ALE_RD_OFLOW | + ALE_RD_TRUNC)) { + ale_rx_update_page(sc, &rx_page, length, &prod); + continue; + } + } + /* + * m_devget(9) is major bottle-neck of ale(4)(It comes + * from hardware limitation). For jumbo frames we could + * get a slightly better performance if driver use + * m_getjcl(9) with proper buffer size argument. However + * that would make code more complicated and I don't + * think users would expect good Rx performance numbers + * on these low-end consumer ethernet controller. + */ + m = m_devget((char *)(rs + 1), length - ETHER_CRC_LEN, + ETHER_ALIGN, ifp, NULL); + if (m == NULL) { + ifp->if_iqdrops++; + ale_rx_update_page(sc, &rx_page, length, &prod); + continue; + } + if (status & ALE_RD_IPV4) + ale_rxcsum(sc, m, status); +#if NVLAN > 0 + if (status & ALE_RD_VLAN) { + uint32_t vtags = ALE_RX_VLAN(letoh32(rs->vtags)); + m->m_pkthdr.ether_vtag = ALE_RX_VLAN_TAG(vtags); + m->m_flags |= M_VLANTAG; + } +#endif + + +#if NBPFILTER > 0 + if (ifp->if_bpf) + bpf_mtap_ether(ifp->if_bpf, m, BPF_DIRECTION_IN); +#endif + + /* Pass it to upper layer. */ + ether_input_mbuf(ifp, m); + + ale_rx_update_page(sc, &rx_page, length, &prod); + } + + return 0; +} + +void +ale_tick(void *xsc) +{ + struct ale_softc *sc = xsc; + struct mii_data *mii = &sc->sc_miibus; + int s; + + s = splnet(); + mii_tick(mii); + ale_stats_update(sc); + + timeout_add_sec(&sc->ale_tick_ch, 1); + splx(s); +} + +void +ale_reset(struct ale_softc *sc) +{ + uint32_t reg; + int i; + + /* Initialize PCIe module. From Linux. */ + CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000); + + CSR_WRITE_4(sc, ALE_MASTER_CFG, MASTER_RESET); + for (i = ALE_RESET_TIMEOUT; i > 0; i--) { + DELAY(10); + if ((CSR_READ_4(sc, ALE_MASTER_CFG) & MASTER_RESET) == 0) + break; + } + if (i == 0) + printf("%s: master reset timeout!\n", sc->sc_dev.dv_xname); + + for (i = ALE_RESET_TIMEOUT; i > 0; i--) { + if ((reg = CSR_READ_4(sc, ALE_IDLE_STATUS)) == 0) + break; + DELAY(10); + } + + if (i == 0) + printf("%s: reset timeout(0x%08x)!\n", sc->sc_dev.dv_xname, + reg); +} + +int +ale_init(struct ifnet *ifp) +{ + struct ale_softc *sc = ifp->if_softc; + struct mii_data *mii; + uint8_t eaddr[ETHER_ADDR_LEN]; + bus_addr_t paddr; + uint32_t reg, rxf_hi, rxf_lo; + + /* + * Cancel any pending I/O. + */ + ale_stop(sc); + + /* + * Reset the chip to a known state. + */ + ale_reset(sc); + + /* Initialize Tx descriptors, DMA memory blocks. */ + ale_init_rx_pages(sc); + ale_init_tx_ring(sc); + + /* Reprogram the station address. */ + bcopy(LLADDR(ifp->if_sadl), eaddr, ETHER_ADDR_LEN); + CSR_WRITE_4(sc, ALE_PAR0, + eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]); + CSR_WRITE_4(sc, ALE_PAR1, eaddr[0] << 8 | eaddr[1]); + + /* + * Clear WOL status and disable all WOL feature as WOL + * would interfere Rx operation under normal environments. + */ + CSR_READ_4(sc, ALE_WOL_CFG); + CSR_WRITE_4(sc, ALE_WOL_CFG, 0); + + /* + * Set Tx descriptor/RXF0/CMB base addresses. They share + * the same high address part of DMAable region. + */ + paddr = sc->ale_cdata.ale_tx_ring_paddr; + CSR_WRITE_4(sc, ALE_TPD_ADDR_HI, ALE_ADDR_HI(paddr)); + CSR_WRITE_4(sc, ALE_TPD_ADDR_LO, ALE_ADDR_LO(paddr)); + CSR_WRITE_4(sc, ALE_TPD_CNT, + (ALE_TX_RING_CNT << TPD_CNT_SHIFT) & TPD_CNT_MASK); + + /* Set Rx page base address, note we use single queue. */ + paddr = sc->ale_cdata.ale_rx_page[0].page_paddr; + CSR_WRITE_4(sc, ALE_RXF0_PAGE0_ADDR_LO, ALE_ADDR_LO(paddr)); + paddr = sc->ale_cdata.ale_rx_page[1].page_paddr; + CSR_WRITE_4(sc, ALE_RXF0_PAGE1_ADDR_LO, ALE_ADDR_LO(paddr)); + + /* Set Tx/Rx CMB addresses. */ + paddr = sc->ale_cdata.ale_tx_cmb_paddr; + CSR_WRITE_4(sc, ALE_TX_CMB_ADDR_LO, ALE_ADDR_LO(paddr)); + paddr = sc->ale_cdata.ale_rx_page[0].cmb_paddr; + CSR_WRITE_4(sc, ALE_RXF0_CMB0_ADDR_LO, ALE_ADDR_LO(paddr)); + paddr = sc->ale_cdata.ale_rx_page[1].cmb_paddr; + CSR_WRITE_4(sc, ALE_RXF0_CMB1_ADDR_LO, ALE_ADDR_LO(paddr)); + + /* Mark RXF0 is valid. */ + CSR_WRITE_1(sc, ALE_RXF0_PAGE0, RXF_VALID); + CSR_WRITE_1(sc, ALE_RXF0_PAGE1, RXF_VALID); + /* + * No need to initialize RFX1/RXF2/RXF3. We don't use + * multi-queue yet. + */ + + /* Set Rx page size, excluding guard frame size. */ + CSR_WRITE_4(sc, ALE_RXF_PAGE_SIZE, ALE_RX_PAGE_SZ); + + /* Tell hardware that we're ready to load DMA blocks. */ + CSR_WRITE_4(sc, ALE_DMA_BLOCK, DMA_BLOCK_LOAD); + + /* Set Rx/Tx interrupt trigger threshold. */ + CSR_WRITE_4(sc, ALE_INT_TRIG_THRESH, (1 << INT_TRIG_RX_THRESH_SHIFT) | + (4 << INT_TRIG_TX_THRESH_SHIFT)); + /* + * XXX + * Set interrupt trigger timer, its purpose and relation + * with interrupt moderation mechanism is not clear yet. + */ + CSR_WRITE_4(sc, ALE_INT_TRIG_TIMER, + ((ALE_USECS(10) << INT_TRIG_RX_TIMER_SHIFT) | + (ALE_USECS(1000) << INT_TRIG_TX_TIMER_SHIFT))); + + /* Configure interrupt moderation timer. */ + sc->ale_int_rx_mod = ALE_IM_RX_TIMER_DEFAULT; + reg = ALE_USECS(sc->ale_int_rx_mod) << IM_TIMER_RX_SHIFT; + reg |= ALE_USECS(sc->ale_int_tx_mod) << IM_TIMER_TX_SHIFT; + CSR_WRITE_4(sc, ALE_IM_TIMER, reg); + reg = CSR_READ_4(sc, ALE_MASTER_CFG); + reg &= ~(MASTER_CHIP_REV_MASK | MASTER_CHIP_ID_MASK); + reg &= ~(MASTER_IM_RX_TIMER_ENB | MASTER_IM_TX_TIMER_ENB); + if (ALE_USECS(sc->ale_int_rx_mod) != 0) + reg |= MASTER_IM_RX_TIMER_ENB; + if (ALE_USECS(sc->ale_int_tx_mod) != 0) + reg |= MASTER_IM_TX_TIMER_ENB; + CSR_WRITE_4(sc, ALE_MASTER_CFG, reg); + CSR_WRITE_2(sc, ALE_INTR_CLR_TIMER, ALE_USECS(1000)); + + /* Set Maximum frame size of controller. */ + if (ifp->if_mtu < ETHERMTU) + sc->ale_max_frame_size = ETHERMTU; + else + sc->ale_max_frame_size = ifp->if_mtu; + sc->ale_max_frame_size += ETHER_HDR_LEN + EVL_ENCAPLEN + ETHER_CRC_LEN; + CSR_WRITE_4(sc, ALE_FRAME_SIZE, sc->ale_max_frame_size); + + /* Configure IPG/IFG parameters. */ + CSR_WRITE_4(sc, ALE_IPG_IFG_CFG, + ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & IPG_IFG_IPGT_MASK) | + ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & IPG_IFG_MIFG_MASK) | + ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & IPG_IFG_IPG1_MASK) | + ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & IPG_IFG_IPG2_MASK)); + + /* Set parameters for half-duplex media. */ + CSR_WRITE_4(sc, ALE_HDPX_CFG, + ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) & + HDPX_CFG_LCOL_MASK) | + ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) & + HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN | + ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) & + HDPX_CFG_ABEBT_MASK) | + ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) & + HDPX_CFG_JAMIPG_MASK)); + + /* Configure Tx jumbo frame parameters. */ + if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) { + if (ifp->if_mtu < ETHERMTU) + reg = sc->ale_max_frame_size; + else if (ifp->if_mtu < 6 * 1024) + reg = (sc->ale_max_frame_size * 2) / 3; + else + reg = sc->ale_max_frame_size / 2; + CSR_WRITE_4(sc, ALE_TX_JUMBO_THRESH, + roundup(reg, TX_JUMBO_THRESH_UNIT) >> + TX_JUMBO_THRESH_UNIT_SHIFT); + } + + /* Configure TxQ. */ + reg = (128 << (sc->ale_dma_rd_burst >> DMA_CFG_RD_BURST_SHIFT)) + << TXQ_CFG_TX_FIFO_BURST_SHIFT; + reg |= (TXQ_CFG_TPD_BURST_DEFAULT << TXQ_CFG_TPD_BURST_SHIFT) & + TXQ_CFG_TPD_BURST_MASK; + CSR_WRITE_4(sc, ALE_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE | TXQ_CFG_ENB); + + /* Configure Rx jumbo frame & flow control parameters. */ + if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) { + reg = roundup(sc->ale_max_frame_size, RX_JUMBO_THRESH_UNIT); + CSR_WRITE_4(sc, ALE_RX_JUMBO_THRESH, + (((reg >> RX_JUMBO_THRESH_UNIT_SHIFT) << + RX_JUMBO_THRESH_MASK_SHIFT) & RX_JUMBO_THRESH_MASK) | + ((RX_JUMBO_LKAH_DEFAULT << RX_JUMBO_LKAH_SHIFT) & + RX_JUMBO_LKAH_MASK)); + reg = CSR_READ_4(sc, ALE_SRAM_RX_FIFO_LEN); + rxf_hi = (reg * 7) / 10; + rxf_lo = (reg * 3)/ 10; + CSR_WRITE_4(sc, ALE_RX_FIFO_PAUSE_THRESH, + ((rxf_lo << RX_FIFO_PAUSE_THRESH_LO_SHIFT) & + RX_FIFO_PAUSE_THRESH_LO_MASK) | + ((rxf_hi << RX_FIFO_PAUSE_THRESH_HI_SHIFT) & + RX_FIFO_PAUSE_THRESH_HI_MASK)); + } + + /* Disable RSS. */ + CSR_WRITE_4(sc, ALE_RSS_IDT_TABLE0, 0); + CSR_WRITE_4(sc, ALE_RSS_CPU, 0); + + /* Configure RxQ. */ + CSR_WRITE_4(sc, ALE_RXQ_CFG, + RXQ_CFG_ALIGN_32 | RXQ_CFG_CUT_THROUGH_ENB | RXQ_CFG_ENB); + + /* Configure DMA parameters. */ + reg = 0; + if ((sc->ale_flags & ALE_FLAG_TXCMB_BUG) == 0) + reg |= DMA_CFG_TXCMB_ENB; + CSR_WRITE_4(sc, ALE_DMA_CFG, + DMA_CFG_OUT_ORDER | DMA_CFG_RD_REQ_PRI | DMA_CFG_RCB_64 | + sc->ale_dma_rd_burst | reg | + sc->ale_dma_wr_burst | DMA_CFG_RXCMB_ENB | + ((DMA_CFG_RD_DELAY_CNT_DEFAULT << DMA_CFG_RD_DELAY_CNT_SHIFT) & + DMA_CFG_RD_DELAY_CNT_MASK) | + ((DMA_CFG_WR_DELAY_CNT_DEFAULT << DMA_CFG_WR_DELAY_CNT_SHIFT) & + DMA_CFG_WR_DELAY_CNT_MASK)); + + /* + * Hardware can be configured to issue SMB interrupt based + * on programmed interval. Since there is a callout that is + * invoked for every hz in driver we use that instead of + * relying on periodic SMB interrupt. + */ + CSR_WRITE_4(sc, ALE_SMB_STAT_TIMER, ALE_USECS(0)); + + /* Clear MAC statistics. */ + ale_stats_clear(sc); + + /* + * Configure Tx/Rx MACs. + * - Auto-padding for short frames. + * - Enable CRC generation. + * Actual reconfiguration of MAC for resolved speed/duplex + * is followed after detection of link establishment. + * AR81xx always does checksum computation regardless of + * MAC_CFG_RXCSUM_ENB bit. In fact, setting the bit will + * cause Rx handling issue for fragmented IP datagrams due + * to silicon bug. + */ + reg = MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | MAC_CFG_FULL_DUPLEX | + ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) & + MAC_CFG_PREAMBLE_MASK); + if ((sc->ale_flags & ALE_FLAG_FASTETHER) != 0) + reg |= MAC_CFG_SPEED_10_100; + else + reg |= MAC_CFG_SPEED_1000; + CSR_WRITE_4(sc, ALE_MAC_CFG, reg); + + /* Set up the receive filter. */ + ale_rxfilter(sc); + ale_rxvlan(sc); + + /* Acknowledge all pending interrupts and clear it. */ + CSR_WRITE_4(sc, ALE_INTR_MASK, ALE_INTRS); + CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF); + CSR_WRITE_4(sc, ALE_INTR_STATUS, 0); + + sc->ale_flags &= ~ALE_FLAG_LINK; + + /* Switch to the current media. */ + mii = &sc->sc_miibus; + mii_mediachg(mii); + + timeout_add_sec(&sc->ale_tick_ch, 1); + + ifp->if_flags |= IFF_RUNNING; + ifp->if_flags &= ~IFF_OACTIVE; + + return 0; +} + +void +ale_stop(struct ale_softc *sc) +{ + struct ifnet *ifp = &sc->sc_arpcom.ac_if; + struct ale_txdesc *txd; + uint32_t reg; + int i; + + /* + * Mark the interface down and cancel the watchdog timer. + */ + ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); + ifp->if_timer = 0; + + timeout_del(&sc->ale_tick_ch); + sc->ale_flags &= ~ALE_FLAG_LINK; + + ale_stats_update(sc); + + /* Disable interrupts. */ + CSR_WRITE_4(sc, ALE_INTR_MASK, 0); + CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF); + + /* Disable queue processing and DMA. */ + reg = CSR_READ_4(sc, ALE_TXQ_CFG); + reg &= ~TXQ_CFG_ENB; + CSR_WRITE_4(sc, ALE_TXQ_CFG, reg); + reg = CSR_READ_4(sc, ALE_RXQ_CFG); + reg &= ~RXQ_CFG_ENB; + CSR_WRITE_4(sc, ALE_RXQ_CFG, reg); + reg = CSR_READ_4(sc, ALE_DMA_CFG); + reg &= ~(DMA_CFG_TXCMB_ENB | DMA_CFG_RXCMB_ENB); + CSR_WRITE_4(sc, ALE_DMA_CFG, reg); + DELAY(1000); + + /* Stop Rx/Tx MACs. */ + ale_stop_mac(sc); + + /* Disable interrupts again? XXX */ + CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF); + + /* + * Free TX mbufs still in the queues. + */ + for (i = 0; i < ALE_TX_RING_CNT; i++) { + txd = &sc->ale_cdata.ale_txdesc[i]; + if (txd->tx_m != NULL) { + bus_dmamap_unload(sc->sc_dmat, txd->tx_dmamap); + m_freem(txd->tx_m); + txd->tx_m = NULL; + } + } +} + +void +ale_stop_mac(struct ale_softc *sc) +{ + uint32_t reg; + int i; + + reg = CSR_READ_4(sc, ALE_MAC_CFG); + if ((reg & (MAC_CFG_TX_ENB | MAC_CFG_RX_ENB)) != 0) { + reg &= ~MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; + CSR_WRITE_4(sc, ALE_MAC_CFG, reg); + } + + for (i = ALE_TIMEOUT; i > 0; i--) { + reg = CSR_READ_4(sc, ALE_IDLE_STATUS); + if (reg == 0) + break; + DELAY(10); + } + if (i == 0) + printf("%s: could not disable Tx/Rx MAC(0x%08x)!\n", + sc->sc_dev.dv_xname, reg); +} + +void +ale_init_tx_ring(struct ale_softc *sc) +{ + struct ale_txdesc *txd; + int i; + + sc->ale_cdata.ale_tx_prod = 0; + sc->ale_cdata.ale_tx_cons = 0; + sc->ale_cdata.ale_tx_cnt = 0; + + bzero(sc->ale_cdata.ale_tx_ring, ALE_TX_RING_SZ); + bzero(sc->ale_cdata.ale_tx_cmb, ALE_TX_CMB_SZ); + for (i = 0; i < ALE_TX_RING_CNT; i++) { + txd = &sc->ale_cdata.ale_txdesc[i]; + txd->tx_m = NULL; + } + *sc->ale_cdata.ale_tx_cmb = 0; + bus_dmamap_sync(sc->sc_dmat, sc->ale_cdata.ale_tx_cmb_map, 0, + sc->ale_cdata.ale_tx_cmb_map->dm_mapsize, BUS_DMASYNC_PREWRITE); + bus_dmamap_sync(sc->sc_dmat, sc->ale_cdata.ale_tx_ring_map, 0, + sc->ale_cdata.ale_tx_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); +} + +void +ale_init_rx_pages(struct ale_softc *sc) +{ + struct ale_rx_page *rx_page; + int i; + + sc->ale_cdata.ale_rx_seqno = 0; + sc->ale_cdata.ale_rx_curp = 0; + + for (i = 0; i < ALE_RX_PAGES; i++) { + rx_page = &sc->ale_cdata.ale_rx_page[i]; + bzero(rx_page->page_addr, sc->ale_pagesize); + bzero(rx_page->cmb_addr, ALE_RX_CMB_SZ); + rx_page->cons = 0; + *rx_page->cmb_addr = 0; + bus_dmamap_sync(sc->sc_dmat, rx_page->page_map, 0, + rx_page->page_map->dm_mapsize, BUS_DMASYNC_PREWRITE); + bus_dmamap_sync(sc->sc_dmat, rx_page->cmb_map, 0, + rx_page->cmb_map->dm_mapsize, BUS_DMASYNC_PREWRITE); + } +} + +void +ale_rxvlan(struct ale_softc *sc) +{ + struct ifnet *ifp = &sc->sc_arpcom.ac_if; + uint32_t reg; + + reg = CSR_READ_4(sc, ALE_MAC_CFG); + reg &= ~MAC_CFG_VLAN_TAG_STRIP; + if (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) + reg |= MAC_CFG_VLAN_TAG_STRIP; + CSR_WRITE_4(sc, ALE_MAC_CFG, reg); +} + +void +ale_rxfilter(struct ale_softc *sc) +{ + struct arpcom *ac = &sc->sc_arpcom; + struct ifnet *ifp = &ac->ac_if; + struct ether_multi *enm; + struct ether_multistep step; + uint32_t crc; + uint32_t mchash[2]; + uint32_t rxcfg; + + rxcfg = CSR_READ_4(sc, ALE_MAC_CFG); + rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC); + ifp->if_flags &= ~IFF_ALLMULTI; + + /* + * Always accept broadcast frames. + */ + rxcfg |= MAC_CFG_BCAST; + + if (ifp->if_flags & IFF_PROMISC || ac->ac_multirangecnt > 0) { + ifp->if_flags |= IFF_ALLMULTI; + if (ifp->if_flags & IFF_PROMISC) + rxcfg |= MAC_CFG_PROMISC; + else + rxcfg |= MAC_CFG_ALLMULTI; + mchash[0] = mchash[1] = 0xFFFFFFFF; + } else { + /* Program new filter. */ + bzero(mchash, sizeof(mchash)); + + ETHER_FIRST_MULTI(step, ac, enm); + while (enm != NULL) { + crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); + + mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); + ETHER_NEXT_MULTI(step, enm); + } + } + + CSR_WRITE_4(sc, ALE_MAR0, mchash[0]); + CSR_WRITE_4(sc, ALE_MAR1, mchash[1]); + CSR_WRITE_4(sc, ALE_MAC_CFG, rxcfg); +} diff --git a/sys/dev/pci/if_alereg.h b/sys/dev/pci/if_alereg.h new file mode 100644 index 00000000000..add42a99f88 --- /dev/null +++ b/sys/dev/pci/if_alereg.h @@ -0,0 +1,965 @@ +/* $OpenBSD: if_alereg.h,v 1.1 2009/02/25 03:05:32 kevlo Exp $ */ +/*- + * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org> + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice unmodified, this list of conditions, and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMATES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMATE. + * + * $FreeBSD: src/sys/dev/ale/if_alereg.h,v 1.1 2008/11/12 09:52:06 yongari Exp $ + */ + +#ifndef _IF_ALEREG_H +#define _IF_ALEREG_H + +#define ALE_PCIR_BAR 0x10 + +#define ALE_SPI_CTRL 0x200 +#define SPI_VPD_ENB 0x00002000 + +#define ALE_SPI_ADDR 0x204 /* 16bits */ + +#define ALE_SPI_DATA 0x208 + +#define ALE_SPI_CONFIG 0x20C + +#define ALE_SPI_OP_PROGRAM 0x210 /* 8bits */ + +#define ALE_SPI_OP_SC_ERASE 0x211 /* 8bits */ + +#define ALE_SPI_OP_CHIP_ERASE 0x212 /* 8bits */ + +#define ALE_SPI_OP_RDID 0x213 /* 8bits */ + +#define ALE_SPI_OP_WREN 0x214 /* 8bits */ + +#define ALE_SPI_OP_RDSR 0x215 /* 8bits */ + +#define ALE_SPI_OP_WRSR 0x216 /* 8bits */ + +#define ALE_SPI_OP_READ 0x217 /* 8bits */ + +#define ALE_TWSI_CTRL 0x218 +#define TWSI_CTRL_SW_LD_START 0x00000800 +#define TWSI_CTRL_HW_LD_START 0x00001000 +#define TWSI_CTRL_LD_EXIST 0x00400000 + +#define ALE_DEV_MISC_CTRL 0x21C + +#define ALE_PCIE_PHYMISC 0x1000 +#define PCIE_PHYMISC_FORCE_RCV_DET 0x00000004 + +#define ALE_MASTER_CFG 0x1400 +#define MASTER_RESET 0x00000001 +#define MASTER_MTIMER_ENB 0x00000002 +#define MASTER_IM_TX_TIMER_ENB 0x00000004 +#define MASTER_MANUAL_INT_ENB 0x00000008 +#define MASTER_IM_RX_TIMER_ENB 0x00000020 +#define MASTER_INT_RDCLR 0x00000040 +#define MASTER_LED_MODE 0x00000200 +#define MASTER_CHIP_REV_MASK 0x00FF0000 +#define MASTER_CHIP_ID_MASK 0xFF000000 +#define MASTER_CHIP_REV_SHIFT 16 +#define MASTER_CHIP_ID_SHIFT 24 + +/* Number of ticks per usec for AR81xx. */ +#define ALE_TICK_USECS 2 +#define ALE_USECS(x) ((x) / ALE_TICK_USECS) + +#define ALE_MANUAL_TIMER 0x1404 + +#define ALE_IM_TIMER 0x1408 +#define IM_TIMER_TX_MASK 0x0000FFFF +#define IM_TIMER_RX_MASK 0xFFFF0000 +#define IM_TIMER_TX_SHIFT 0 +#define IM_TIMER_RX_SHIFT 16 +#define ALE_IM_TIMER_MIN 0 +#define ALE_IM_TIMER_MAX 130000 /* 130ms */ +#define ALE_IM_RX_TIMER_DEFAULT 30 +#define ALE_IM_TX_TIMER_DEFAULT 1000 + +#define ALE_GPHY_CTRL 0x140C /* 16bits */ +#define GPHY_CTRL_EXT_RESET 0x0001 +#define GPHY_CTRL_PIPE_MOD 0x0002 +#define GPHY_CTRL_BERT_START 0x0010 +#define GPHY_CTRL_GALE_25M_ENB 0x0020 +#define GPHY_CTRL_LPW_EXIT 0x0040 +#define GPHY_CTRL_PHY_IDDQ 0x0080 +#define GPHY_CTRL_PHY_IDDQ_DIS 0x0100 +#define GPHY_CTRL_PCLK_SEL_DIS 0x0200 +#define GPHY_CTRL_HIB_EN 0x0400 +#define GPHY_CTRL_HIB_PULSE 0x0800 +#define GPHY_CTRL_SEL_ANA_RESET 0x1000 +#define GPHY_CTRL_PHY_PLL_ON 0x2000 +#define GPHY_CTRL_PWDOWN_HW 0x4000 + +#define ALE_INTR_CLR_TIMER 0x140E /* 16bits */ + +#define ALE_IDLE_STATUS 0x1410 +#define IDLE_STATUS_RXMAC 0x00000001 +#define IDLE_STATUS_TXMAC 0x00000002 +#define IDLE_STATUS_RXQ 0x00000004 +#define IDLE_STATUS_TXQ 0x00000008 +#define IDLE_STATUS_DMARD 0x00000010 +#define IDLE_STATUS_DMAWR 0x00000020 +#define IDLE_STATUS_SMB 0x00000040 +#define IDLE_STATUS_CMB 0x00000080 + +#define ALE_MDIO 0x1414 +#define MDIO_DATA_MASK 0x0000FFFF +#define MDIO_REG_ADDR_MASK 0x001F0000 +#define MDIO_OP_READ 0x00200000 +#define MDIO_OP_WRITE 0x00000000 +#define MDIO_SUP_PREAMBLE 0x00400000 +#define MDIO_OP_EXECUTE 0x00800000 +#define MDIO_CLK_25_4 0x00000000 +#define MDIO_CLK_25_6 0x02000000 +#define MDIO_CLK_25_8 0x03000000 +#define MDIO_CLK_25_10 0x04000000 +#define MDIO_CLK_25_14 0x05000000 +#define MDIO_CLK_25_20 0x06000000 +#define MDIO_CLK_25_28 0x07000000 +#define MDIO_OP_BUSY 0x08000000 +#define MDIO_DATA_SHIFT 0 +#define MDIO_REG_ADDR_SHIFT 16 + +#define MDIO_REG_ADDR(x) \ + (((x) << MDIO_REG_ADDR_SHIFT) & MDIO_REG_ADDR_MASK) +/* Default PHY address. */ +#define ALE_PHY_ADDR 0 + +#define ALE_PHY_STATUS 0x1418 +#define PHY_STATUS_100M 0x00020000 + +/* Packet memory BIST. */ +#define ALE_BIST0 0x141C +#define BIST0_ENB 0x00000001 +#define BIST0_SRAM_FAIL 0x00000002 +#define BIST0_FUSE_FLAG 0x00000004 + +/* PCIe retry buffer BIST. */ +#define ALE_BIST1 0x1420 +#define BIST1_ENB 0x00000001 +#define BIST1_SRAM_FAIL 0x00000002 +#define BIST1_FUSE_FLAG 0x00000004 + +#define ALE_SERDES_LOCK 0x1424 +#define SERDES_LOCK_DET 0x00000001 +#define SERDES_LOCK_DET_ENB 0x00000002 + +#define ALE_MAC_CFG 0x1480 +#define MAC_CFG_TX_ENB 0x00000001 +#define MAC_CFG_RX_ENB 0x00000002 +#define MAC_CFG_TX_FC 0x00000004 +#define MAC_CFG_RX_FC 0x00000008 +#define MAC_CFG_LOOP 0x00000010 +#define MAC_CFG_FULL_DUPLEX 0x00000020 +#define MAC_CFG_TX_CRC_ENB 0x00000040 +#define MAC_CFG_TX_AUTO_PAD 0x00000080 +#define MAC_CFG_TX_LENCHK 0x00000100 +#define MAC_CFG_RX_JUMBO_ENB 0x00000200 +#define MAC_CFG_PREAMBLE_MASK 0x00003C00 +#define MAC_CFG_VLAN_TAG_STRIP 0x00004000 +#define MAC_CFG_PROMISC 0x00008000 +#define MAC_CFG_TX_PAUSE 0x00010000 +#define MAC_CFG_SCNT 0x00020000 +#define MAC_CFG_SYNC_RST_TX 0x00040000 +#define MAC_CFG_SPEED_MASK 0x00300000 +#define MAC_CFG_SPEED_10_100 0x00100000 +#define MAC_CFG_SPEED_1000 0x00200000 +#define MAC_CFG_DBG_TX_BACKOFF 0x00400000 +#define MAC_CFG_TX_JUMBO_ENB 0x00800000 +#define MAC_CFG_RXCSUM_ENB 0x01000000 +#define MAC_CFG_ALLMULTI 0x02000000 +#define MAC_CFG_BCAST 0x04000000 +#define MAC_CFG_DBG 0x08000000 +#define MAC_CFG_PREAMBLE_SHIFT 10 +#define MAC_CFG_PREAMBLE_DEFAULT 7 + +#define ALE_IPG_IFG_CFG 0x1484 +#define IPG_IFG_IPGT_MASK 0x0000007F +#define IPG_IFG_MIFG_MASK 0x0000FF00 +#define IPG_IFG_IPG1_MASK 0x007F0000 +#define IPG_IFG_IPG2_MASK 0x7F000000 +#define IPG_IFG_IPGT_SHIFT 0 +#define IPG_IFG_IPGT_DEFAULT 0x60 +#define IPG_IFG_MIFG_SHIFT 8 +#define IPG_IFG_MIFG_DEFAULT 0x50 +#define IPG_IFG_IPG1_SHIFT 16 +#define IPG_IFG_IPG1_DEFAULT 0x40 +#define IPG_IFG_IPG2_SHIFT 24 +#define IPG_IFG_IPG2_DEFAULT 0x60 + +/* Station address. */ +#define ALE_PAR0 0x1488 +#define ALE_PAR1 0x148C + +/* 64bit multicast hash register. */ +#define ALE_MAR0 0x1490 +#define ALE_MAR1 0x1494 + +/* half-duplex parameter configuration. */ +#define ALE_HDPX_CFG 0x1498 +#define HDPX_CFG_LCOL_MASK 0x000003FF +#define HDPX_CFG_RETRY_MASK 0x0000F000 +#define HDPX_CFG_EXC_DEF_EN 0x00010000 +#define HDPX_CFG_NO_BACK_C 0x00020000 +#define HDPX_CFG_NO_BACK_P 0x00040000 +#define HDPX_CFG_ABEBE 0x00080000 +#define HDPX_CFG_ABEBT_MASK 0x00F00000 +#define HDPX_CFG_JAMIPG_MASK 0x0F000000 +#define HDPX_CFG_LCOL_SHIFT 0 +#define HDPX_CFG_LCOL_DEFAULT 0x37 +#define HDPX_CFG_RETRY_SHIFT 12 +#define HDPX_CFG_RETRY_DEFAULT 0x0F +#define HDPX_CFG_ABEBT_SHIFT 20 +#define HDPX_CFG_ABEBT_DEFAULT 0x0A +#define HDPX_CFG_JAMIPG_SHIFT 24 +#define HDPX_CFG_JAMIPG_DEFAULT 0x07 + +#define ALE_FRAME_SIZE 0x149C + +#define ALE_WOL_CFG 0x14A0 +#define WOL_CFG_PATTERN 0x00000001 +#define WOL_CFG_PATTERN_ENB 0x00000002 +#define WOL_CFG_MAGIC 0x00000004 +#define WOL_CFG_MAGIC_ENB 0x00000008 +#define WOL_CFG_LINK_CHG 0x00000010 +#define WOL_CFG_LINK_CHG_ENB 0x00000020 +#define WOL_CFG_PATTERN_DET 0x00000100 +#define WOL_CFG_MAGIC_DET 0x00000200 +#define WOL_CFG_LINK_CHG_DET 0x00000400 +#define WOL_CFG_CLK_SWITCH_ENB 0x00008000 +#define WOL_CFG_PATTERN0 0x00010000 +#define WOL_CFG_PATTERN1 0x00020000 +#define WOL_CFG_PATTERN2 0x00040000 +#define WOL_CFG_PATTERN3 0x00080000 +#define WOL_CFG_PATTERN4 0x00100000 +#define WOL_CFG_PATTERN5 0x00200000 +#define WOL_CFG_PATTERN6 0x00400000 + +/* WOL pattern length. */ +#define ALE_PATTERN_CFG0 0x14A4 +#define PATTERN_CFG_0_LEN_MASK 0x0000007F +#define PATTERN_CFG_1_LEN_MASK 0x00007F00 +#define PATTERN_CFG_2_LEN_MASK 0x007F0000 +#define PATTERN_CFG_3_LEN_MASK 0x7F000000 + +#define ALE_PATTERN_CFG1 0x14A8 +#define PATTERN_CFG_4_LEN_MASK 0x0000007F +#define PATTERN_CFG_5_LEN_MASK 0x00007F00 +#define PATTERN_CFG_6_LEN_MASK 0x007F0000 + +/* RSS */ +#define ALE_RSS_KEY0 0x14B0 + +#define ALE_RSS_KEY1 0x14B4 + +#define ALE_RSS_KEY2 0x14B8 + +#define ALE_RSS_KEY3 0x14BC + +#define ALE_RSS_KEY4 0x14C0 + +#define ALE_RSS_KEY5 0x14C4 + +#define ALE_RSS_KEY6 0x14C8 + +#define ALE_RSS_KEY7 0x14CC + +#define ALE_RSS_KEY8 0x14D0 + +#define ALE_RSS_KEY9 0x14D4 + +#define ALE_RSS_IDT_TABLE4 0x14E0 + +#define ALE_RSS_IDT_TABLE5 0x14E4 + +#define ALE_RSS_IDT_TABLE6 0x14E8 + +#define ALE_RSS_IDT_TABLE7 0x14EC + +#define ALE_SRAM_RD_ADDR 0x1500 + +#define ALE_SRAM_RD_LEN 0x1504 + +#define ALE_SRAM_RRD_ADDR 0x1508 + +#define ALE_SRAM_RRD_LEN 0x150C + +#define ALE_SRAM_TPD_ADDR 0x1510 + +#define ALE_SRAM_TPD_LEN 0x1514 + +#define ALE_SRAM_TRD_ADDR 0x1518 + +#define ALE_SRAM_TRD_LEN 0x151C + +#define ALE_SRAM_RX_FIFO_ADDR 0x1520 + +#define ALE_SRAM_RX_FIFO_LEN 0x1524 + +#define ALE_SRAM_TX_FIFO_ADDR 0x1528 + +#define ALE_SRAM_TX_FIFO_LEN 0x152C + +#define ALE_SRAM_TCPH_ADDR 0x1530 +#define SRAM_TCPH_ADDR_MASK 0x00000FFF +#define SRAM_PATH_ADDR_MASK 0x0FFF0000 +#define SRAM_TCPH_ADDR_SHIFT 0 +#define SRAM_PATH_ADDR_SHIFT 16 + +#define ALE_DMA_BLOCK 0x1534 +#define DMA_BLOCK_LOAD 0x00000001 + +#define ALE_RXF3_ADDR_HI 0x153C + +#define ALE_TPD_ADDR_HI 0x1540 + +#define ALE_RXF0_PAGE0_ADDR_LO 0x1544 + +#define ALE_RXF0_PAGE1_ADDR_LO 0x1548 + +#define ALE_TPD_ADDR_LO 0x154C + +#define ALE_RXF1_ADDR_HI 0x1550 + +#define ALE_RXF2_ADDR_HI 0x1554 + +#define ALE_RXF_PAGE_SIZE 0x1558 + +#define ALE_TPD_CNT 0x155C +#define TPD_CNT_MASK 0x00003FF +#define TPD_CNT_SHIFT 0 + +#define ALE_RSS_IDT_TABLE0 0x1560 + +#define ALE_RSS_IDT_TABLE1 0x1564 + +#define ALE_RSS_IDT_TABLE2 0x1568 + +#define ALE_RSS_IDT_TABLE3 0x156C + +#define ALE_RSS_HASH_VALUE 0x1570 + +#define ALE_RSS_HASH_FLAG 0x1574 + +#define ALE_RSS_CPU 0x157C + +#define ALE_TXQ_CFG 0x1580 +#define TXQ_CFG_TPD_BURST_MASK 0x0000000F +#define TXQ_CFG_ENB 0x00000020 +#define TXQ_CFG_ENHANCED_MODE 0x00000040 +#define TXQ_CFG_TX_FIFO_BURST_MASK 0xFFFF0000 +#define TXQ_CFG_TPD_BURST_SHIFT 0 +#define TXQ_CFG_TPD_BURST_DEFAULT 4 +#define TXQ_CFG_TX_FIFO_BURST_SHIFT 16 +#define TXQ_CFG_TX_FIFO_BURST_DEFAULT 256 + +#define ALE_TX_JUMBO_THRESH 0x1584 +#define TX_JUMBO_THRESH_MASK 0x000007FF +#define TX_JUMBO_THRESH_SHIFT 0 +#define TX_JUMBO_THRESH_UNIT 8 +#define TX_JUMBO_THRESH_UNIT_SHIFT 3 + +#define ALE_RXQ_CFG 0x15A0 +#define RXQ_CFG_ALIGN_32 0x00000000 +#define RXQ_CFG_ALIGN_64 0x00000001 +#define RXQ_CFG_ALIGN_128 0x00000002 +#define RXQ_CFG_ALIGN_256 0x00000003 +#define RXQ_CFG_QUEUE1_ENB 0x00000010 +#define RXQ_CFG_QUEUE2_ENB 0x00000020 +#define RXQ_CFG_QUEUE3_ENB 0x00000040 +#define RXQ_CFG_IPV6_CSUM_VERIFY 0x00000080 +#define RXQ_CFG_RSS_HASH_TBL_LEN_MASK 0x0000FF00 +#define RXQ_CFG_RSS_HASH_IPV4 0x00010000 +#define RXQ_CFG_RSS_HASH_IPV4_TCP 0x00020000 +#define RXQ_CFG_RSS_HASH_IPV6 0x00040000 +#define RXQ_CFG_RSS_HASH_IPV6_TCP 0x00080000 +#define RXQ_CFG_RSS_MODE_DIS 0x00000000 +#define RXQ_CFG_RSS_MODE_SQSINT 0x04000000 +#define RXQ_CFG_RSS_MODE_MQUESINT 0x08000000 +#define RXQ_CFG_RSS_MODE_MQUEMINT 0x0C000000 +#define RXQ_CFG_NIP_QUEUE_SEL_TBL 0x10000000 +#define RXQ_CFG_RSS_HASH_ENB 0x20000000 +#define RXQ_CFG_CUT_THROUGH_ENB 0x40000000 +#define RXQ_CFG_ENB 0x80000000 +#define RXQ_CFG_RSS_HASH_TBL_LEN_SHIFT 8 + +#define ALE_RX_JUMBO_THRESH 0x15A4 /* 16bits */ +#define RX_JUMBO_THRESH_MASK 0x07FF +#define RX_JUMBO_LKAH_MASK 0x7800 +#define RX_JUMBO_THRESH_MASK_SHIFT 0 +#define RX_JUMBO_THRESH_UNIT 8 +#define RX_JUMBO_THRESH_UNIT_SHIFT 3 +#define RX_JUMBO_LKAH_SHIFT 11 +#define RX_JUMBO_LKAH_DEFAULT 1 + +#define ALE_RX_FIFO_PAUSE_THRESH 0x15A8 +#define RX_FIFO_PAUSE_THRESH_LO_MASK 0x00000FFF +#define RX_FIFO_PAUSE_THRESH_HI_MASK 0x0FFF0000 +#define RX_FIFO_PAUSE_THRESH_LO_SHIFT 0 +#define RX_FIFO_PAUSE_THRESH_HI_SHIFT 16 + +#define ALE_CMB_RXF1 0x15B4 + +#define ALE_CMB_RXF2 0x15B8 + +#define ALE_CMB_RXF3 0x15BC + +#define ALE_DMA_CFG 0x15C0 +#define DMA_CFG_IN_ORDER 0x00000001 +#define DMA_CFG_ENH_ORDER 0x00000002 +#define DMA_CFG_OUT_ORDER 0x00000004 +#define DMA_CFG_RCB_64 0x00000000 +#define DMA_CFG_RCB_128 0x00000008 +#define DMA_CFG_RD_BURST_128 0x00000000 +#define DMA_CFG_RD_BURST_256 0x00000010 +#define DMA_CFG_RD_BURST_512 0x00000020 +#define DMA_CFG_RD_BURST_1024 0x00000030 +#define DMA_CFG_RD_BURST_2048 0x00000040 +#define DMA_CFG_RD_BURST_4096 0x00000050 +#define DMA_CFG_WR_BURST_128 0x00000000 +#define DMA_CFG_WR_BURST_256 0x00000080 +#define DMA_CFG_WR_BURST_512 0x00000100 +#define DMA_CFG_WR_BURST_1024 0x00000180 +#define DMA_CFG_WR_BURST_2048 0x00000200 +#define DMA_CFG_WR_BURST_4096 0x00000280 +#define DMA_CFG_RD_REQ_PRI 0x00000400 +#define DMA_CFG_RD_DELAY_CNT_MASK 0x0000F800 +#define DMA_CFG_WR_DELAY_CNT_MASK 0x000F0000 +#define DMA_CFG_TXCMB_ENB 0x00100000 +#define DMA_CFG_RXCMB_ENB 0x00200000 +#define DMA_CFG_RD_BURST_MASK 0x07 +#define DMA_CFG_RD_BURST_SHIFT 4 +#define DMA_CFG_WR_BURST_MASK 0x07 +#define DMA_CFG_WR_BURST_SHIFT 7 +#define DMA_CFG_RD_DELAY_CNT_SHIFT 11 +#define DMA_CFG_WR_DELAY_CNT_SHIFT 16 +#define DMA_CFG_RD_DELAY_CNT_DEFAULT 15 +#define DMA_CFG_WR_DELAY_CNT_DEFAULT 4 + +#define ALE_SMB_STAT_TIMER 0x15C4 + +#define ALE_INT_TRIG_THRESH 0x15C8 +#define INT_TRIG_TX_THRESH_MASK 0x0000FFFF +#define INT_TRIG_RX_THRESH_MASK 0xFFFF0000 +#define INT_TRIG_TX_THRESH_SHIFT 0 +#define INT_TRIG_RX_THRESH_SHIFT 16 + +#define ALE_INT_TRIG_TIMER 0x15CC +#define INT_TRIG_TX_TIMER_MASK 0x0000FFFF +#define INT_TRIG_RX_TIMER_MASK 0x0000FFFF +#define INT_TRIG_TX_TIMER_SHIFT 0 +#define INT_TRIG_RX_TIMER_SHIFT 16 + +#define ALE_RXF1_PAGE0_ADDR_LO 0x15D0 + +#define ALE_RXF1_PAGE1_ADDR_LO 0x15D4 + +#define ALE_RXF2_PAGE0_ADDR_LO 0x15D8 + +#define ALE_RXF2_PAGE1_ADDR_LO 0x15DC + +#define ALE_RXF3_PAGE0_ADDR_LO 0x15E0 + +#define ALE_RXF3_PAGE1_ADDR_LO 0x15E4 + +#define ALE_MBOX_TPD_PROD_IDX 0x15F0 + +#define ALE_RXF0_PAGE0 0x15F4 + +#define ALE_RXF0_PAGE1 0x15F5 + +#define ALE_RXF1_PAGE0 0x15F6 + +#define ALE_RXF1_PAGE1 0x15F7 + +#define ALE_RXF2_PAGE0 0x15F8 + +#define ALE_RXF2_PAGE1 0x15F9 + +#define ALE_RXF3_PAGE0 0x15FA + +#define ALE_RXF3_PAGE1 0x15FB + +#define RXF_VALID 0x01 + +#define ALE_INTR_STATUS 0x1600 +#define INTR_SMB 0x00000001 +#define INTR_TIMER 0x00000002 +#define INTR_MANUAL_TIMER 0x00000004 +#define INTR_RX_FIFO_OFLOW 0x00000008 +#define INTR_RXF0_OFLOW 0x00000010 +#define INTR_RXF1_OFLOW 0x00000020 +#define INTR_RXF2_OFLOW 0x00000040 +#define INTR_RXF3_OFLOW 0x00000080 +#define INTR_TX_FIFO_UNDERRUN 0x00000100 +#define INTR_RX0_PAGE_FULL 0x00000200 +#define INTR_DMA_RD_TO_RST 0x00000400 +#define INTR_DMA_WR_TO_RST 0x00000800 +#define INTR_GPHY 0x00001000 +#define INTR_TX_CREDIT 0x00002000 +#define INTR_GPHY_LOW_PW 0x00004000 +#define INTR_RX_PKT 0x00010000 +#define INTR_TX_PKT 0x00020000 +#define INTR_TX_DMA 0x00040000 +#define INTR_RX_PKT1 0x00080000 +#define INTR_RX_PKT2 0x00100000 +#define INTR_RX_PKT3 0x00200000 +#define INTR_MAC_RX 0x00400000 +#define INTR_MAC_TX 0x00800000 +#define INTR_UNDERRUN 0x01000000 +#define INTR_FRAME_ERROR 0x02000000 +#define INTR_FRAME_OK 0x04000000 +#define INTR_CSUM_ERROR 0x08000000 +#define INTR_PHY_LINK_DOWN 0x10000000 +#define INTR_DIS_INT 0x80000000 + +/* Interrupt Mask Register */ +#define ALE_INTR_MASK 0x1604 + +#define ALE_INTRS \ + (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST | \ + INTR_RX_PKT | INTR_TX_PKT | INTR_RX_FIFO_OFLOW | \ + INTR_TX_FIFO_UNDERRUN) + +/* + * AR81xx requires register access to get MAC statistics + * and the format of statistics seems to be the same of L1 . + */ +#define ALE_RX_MIB_BASE 0x1700 + +#define ALE_TX_MIB_BASE 0x1760 + +/* Statistics counters collected by the MAC. */ +struct smb { + /* Rx stats. */ + uint32_t rx_frames; + uint32_t rx_bcast_frames; + uint32_t rx_mcast_frames; + uint32_t rx_pause_frames; + uint32_t rx_control_frames; + uint32_t rx_crcerrs; + uint32_t rx_lenerrs; + uint32_t rx_bytes; + uint32_t rx_runts; + uint32_t rx_fragments; + uint32_t rx_pkts_64; + uint32_t rx_pkts_65_127; + uint32_t rx_pkts_128_255; + uint32_t rx_pkts_256_511; + uint32_t rx_pkts_512_1023; + uint32_t rx_pkts_1024_1518; + uint32_t rx_pkts_1519_max; + uint32_t rx_pkts_truncated; + uint32_t rx_fifo_oflows; + uint32_t rx_rrs_errs; + uint32_t rx_alignerrs; + uint32_t rx_bcast_bytes; + uint32_t rx_mcast_bytes; + uint32_t rx_pkts_filtered; + /* Tx stats. */ + uint32_t tx_frames; + uint32_t tx_bcast_frames; + uint32_t tx_mcast_frames; + uint32_t tx_pause_frames; + uint32_t tx_excess_defer; + uint32_t tx_control_frames; + uint32_t tx_deferred; + uint32_t tx_bytes; + uint32_t tx_pkts_64; + uint32_t tx_pkts_65_127; + uint32_t tx_pkts_128_255; + uint32_t tx_pkts_256_511; + uint32_t tx_pkts_512_1023; + uint32_t tx_pkts_1024_1518; + uint32_t tx_pkts_1519_max; + uint32_t tx_single_colls; + uint32_t tx_multi_colls; + uint32_t tx_late_colls; + uint32_t tx_excess_colls; + uint32_t tx_abort; + uint32_t tx_underrun; + uint32_t tx_desc_underrun; + uint32_t tx_lenerrs; + uint32_t tx_pkts_truncated; + uint32_t tx_bcast_bytes; + uint32_t tx_mcast_bytes; +} __packed; + +#define ALE_HOST_RXF0_PAGEOFF 0x1800 + +#define ALE_TPD_CONS_IDX 0x1804 + +#define ALE_HOST_RXF1_PAGEOFF 0x1808 + +#define ALE_HOST_RXF2_PAGEOFF 0x180C + +#define ALE_HOST_RXF3_PAGEOFF 0x1810 + +#define ALE_RXF0_CMB0_ADDR_LO 0x1820 + +#define ALE_RXF0_CMB1_ADDR_LO 0x1824 + +#define ALE_RXF1_CMB0_ADDR_LO 0x1828 + +#define ALE_RXF1_CMB1_ADDR_LO 0x182C + +#define ALE_RXF2_CMB0_ADDR_LO 0x1830 + +#define ALE_RXF2_CMB1_ADDR_LO 0x1834 + +#define ALE_RXF3_CMB0_ADDR_LO 0x1838 + +#define ALE_RXF3_CMB1_ADDR_LO 0x183C + +#define ALE_TX_CMB_ADDR_LO 0x1840 + +#define ALE_SMB_ADDR_LO 0x1844 + +/* + * RRS(receive return status) structure. + * + * Note: + * Atheros AR81xx does not support descriptor based DMA on Rx + * instead it just prepends a Rx status structure prior to a + * received frame which also resides on the same Rx buffer. + * This means driver should copy an entire frame from the + * buffer to new mbuf chain which in turn greatly increases CPU + * cycles and effectively nullify the advantage of DMA + * operation of controller. So you should have fast CPU to cope + * with the copy operation. Implementing flow-controls may help + * a lot to minimize Rx FIFO overflows but it's not available + * yet on FreeBSD and hardware doesn't seem to support + * fine-grained Tx/Rx flow controls. + */ +struct rx_rs { + uint32_t seqno; +#define ALE_RD_SEQNO_MASK 0x0000FFFF +#define ALE_RD_HASH_MASK 0xFFFF0000 +#define ALE_RD_SEQNO_SHIFT 0 +#define ALE_RD_HASH_SHIFT 16 +#define ALE_RX_SEQNO(x) \ + (((x) & ALE_RD_SEQNO_MASK) >> ALE_RD_SEQNO_SHIFT) + uint32_t length; +#define ALE_RD_CSUM_MASK 0x0000FFFF +#define ALE_RD_LEN_MASK 0x3FFF0000 +#define ALE_RD_CPU_MASK 0xC0000000 +#define ALE_RD_CSUM_SHIFT 0 +#define ALE_RD_LEN_SHIFT 16 +#define ALE_RD_CPU_SHIFT 30 +#define ALE_RX_CSUM(x) \ + (((x) & ALE_RD_CSUM_MASK) >> ALE_RD_CSUM_SHIFT) +#define ALE_RX_BYTES(x) \ + (((x) & ALE_RD_LEN_MASK) >> ALE_RD_LEN_SHIFT) +#define ALE_RX_CPU(x) \ + (((x) & ALE_RD_CPU_MASK) >> ALE_RD_CPU_SHIFT) + uint32_t flags; +#define ALE_RD_RSS_IPV4 0x00000001 +#define ALE_RD_RSS_IPV4_TCP 0x00000002 +#define ALE_RD_RSS_IPV6 0x00000004 +#define ALE_RD_RSS_IPV6_TCP 0x00000008 +#define ALE_RD_IPV6 0x00000010 +#define ALE_RD_IPV4_FRAG 0x00000020 +#define ALE_RD_IPV4_DF 0x00000040 +#define ALE_RD_802_3 0x00000080 +#define ALE_RD_VLAN 0x00000100 +#define ALE_RD_ERROR 0x00000200 +#define ALE_RD_IPV4 0x00000400 +#define ALE_RD_UDP 0x00000800 +#define ALE_RD_TCP 0x00001000 +#define ALE_RD_BCAST 0x00002000 +#define ALE_RD_MCAST 0x00004000 +#define ALE_RD_PAUSE 0x00008000 +#define ALE_RD_CRC 0x00010000 +#define ALE_RD_CODE 0x00020000 +#define ALE_RD_DRIBBLE 0x00040000 +#define ALE_RD_RUNT 0x00080000 +#define ALE_RD_OFLOW 0x00100000 +#define ALE_RD_TRUNC 0x00200000 +#define ALE_RD_IPCSUM_NOK 0x00400000 +#define ALE_RD_TCP_UDPCSUM_NOK 0x00800000 +#define ALE_RD_LENGTH_NOK 0x01000000 +#define ALE_RD_DES_ADDR_FILTERED 0x02000000 + uint32_t vtags; +#define ALE_RD_HASH_HI_MASK 0x0000FFFF +#define ALE_RD_HASH_HI_SHIFT 0 +#define ALE_RD_VLAN_MASK 0xFFFF0000 +#define ALE_RD_VLAN_SHIFT 16 +#define ALE_RX_VLAN(x) \ + (((x) & ALE_RD_VLAN_MASK) >> ALE_RD_VLAN_SHIFT) +#define ALE_RX_VLAN_TAG(x) \ + (((x) >> 4) | (((x) & 7) << 13) | (((x) & 8) << 9)) +} __packed; + +/* Tx descriptor. */ +struct tx_desc { + uint64_t addr; + uint32_t len; +#define ALE_TD_VLAN_MASK 0xFFFF0000 +#define ALE_TD_PKT_INT 0x00008000 +#define ALE_TD_DMA_INT 0x00004000 +#define ALE_TD_BUFLEN_MASK 0x00003FFF +#define ALE_TD_VLAN_SHIFT 16 +#define ALE_TX_VLAN_TAG(x) \ + (((x) << 4) | ((x) >> 13) | (((x) >> 9) & 8)) +#define ALE_TD_BUFLEN_SHIFT 0 +#define ALE_TX_BYTES(x) \ + (((x) << ALE_TD_BUFLEN_SHIFT) & ALE_TD_BUFLEN_MASK) + uint32_t flags; +#define ALE_TD_MSS 0xFFF80000 +#define ALE_TD_TSO_HDR 0x00040000 +#define ALE_TD_TCPHDR_LEN 0x0003C000 +#define ALE_TD_IPHDR_LEN 0x00003C00 +#define ALE_TD_IPV6HDR_LEN2 0x00003C00 +#define ALE_TD_LLC_SNAP 0x00000200 +#define ALE_TD_VLAN_TAGGED 0x00000100 +#define ALE_TD_UDPCSUM 0x00000080 +#define ALE_TD_TCPCSUM 0x00000040 +#define ALE_TD_IPCSUM 0x00000020 +#define ALE_TD_IPV6HDR_LEN1 0x000000E0 +#define ALE_TD_TSO 0x00000010 +#define ALE_TD_CXSUM 0x00000008 +#define ALE_TD_INSERT_VLAN_TAG 0x00000004 +#define ALE_TD_IPV6 0x00000002 +#define ALE_TD_EOP 0x00000001 + +#define ALE_TD_CSUM_PLOADOFFSET 0x00FF0000 +#define ALE_TD_CSUM_XSUMOFFSET 0xFF000000 +#define ALE_TD_CSUM_XSUMOFFSET_SHIFT 24 +#define ALE_TD_CSUM_PLOADOFFSET_SHIFT 16 +#define ALE_TD_MSS_SHIFT 19 +#define ALE_TD_TCPHDR_LEN_SHIFT 14 +#define ALE_TD_IPHDR_LEN_SHIFT 10 +} __packed; + +#define ALE_TX_RING_CNT 256 /* Should be multiple of 4. */ +#define ALE_TX_RING_CNT_MIN 32 +#define ALE_TX_RING_CNT_MAX 1020 +#define ALE_TX_RING_ALIGN 8 +#define ALE_RX_PAGE_ALIGN 32 +#define ALE_RX_PAGES 2 +#define ALE_CMB_ALIGN 32 + +#define ALE_TSO_MAXSEGSIZE 4096 +#define ALE_TSO_MAXSIZE (65535 + sizeof(struct ether_vlan_header)) +#define ALE_MAXTXSEGS 32 + +#define ALE_ADDR_LO(x) ((uint64_t) (x) & 0xFFFFFFFF) +#define ALE_ADDR_HI(x) ((uint64_t) (x) >> 32) + +/* Water mark to kick reclaiming Tx buffers. */ +#define ALE_TX_DESC_HIWAT (ALE_TX_RING_CNT - ((ALE_TX_RING_CNT * 4) / 10)) + +#define ALE_MSI_MESSAGES 1 +#define ALE_MSIX_MESSAGES 1 + +/* + * TODO : Should get real jumbo MTU size. + * The hardware seems to have trouble in dealing with large + * frame length. If you encounter unstability issue, use + * lower MTU size. + */ +#define ALE_JUMBO_FRAMELEN 8132 +#define ALE_JUMBO_MTU \ + (ALE_JUMBO_FRAMELEN - sizeof(struct ether_vlan_header) - ETHER_CRC_LEN) +#define ALE_MAX_FRAMELEN (ETHER_MAX_LEN + EVL_ENCAPLEN) + +#define ALE_DESC_INC(x, y) ((x) = ((x) + 1) % (y)) + +struct ale_txdesc { + struct mbuf *tx_m; + bus_dmamap_t tx_dmamap; +}; + +struct ale_rx_page { + bus_dmamap_t page_map; + bus_dma_segment_t page_seg; + uint8_t *page_addr; + bus_addr_t page_paddr; + bus_dmamap_t cmb_map; + bus_dma_segment_t cmb_seg; + uint32_t *cmb_addr; + bus_addr_t cmb_paddr; + uint32_t cons; +}; + +struct ale_chain_data{ + struct ale_txdesc ale_txdesc[ALE_TX_RING_CNT]; + bus_dmamap_t ale_tx_ring_map; + bus_dma_segment_t ale_tx_ring_seg; + bus_dmamap_t ale_rx_mblock_map[ALE_RX_PAGES]; + bus_dma_segment_t ale_rx_mblock_seg[ALE_RX_PAGES]; + struct tx_desc *ale_tx_ring; + bus_addr_t ale_tx_ring_paddr; + uint32_t *ale_tx_cmb; + bus_addr_t ale_tx_cmb_paddr; + bus_dmamap_t ale_tx_cmb_map; + bus_dma_segment_t ale_tx_cmb_seg; + + uint32_t ale_tx_prod; + uint32_t ale_tx_cons; + int ale_tx_cnt; + struct ale_rx_page ale_rx_page[ALE_RX_PAGES]; + int ale_rx_curp; + uint16_t ale_rx_seqno; +}; + +#define ALE_TX_RING_SZ \ + (sizeof(struct tx_desc) * ALE_TX_RING_CNT) +#define ALE_RX_PAGE_SZ_MIN (8 * 1024) +#define ALE_RX_PAGE_SZ_MAX (1024 * 1024) +#define ALE_RX_FRAMES_PAGE 128 +#define ALE_RX_PAGE_SZ \ + (roundup(ALE_MAX_FRAMELEN, ALE_RX_PAGE_ALIGN) * ALE_RX_FRAMES_PAGE) +#define ALE_TX_CMB_SZ (sizeof(uint32_t)) +#define ALE_RX_CMB_SZ (sizeof(uint32_t)) + +#define ALE_PROC_MIN (ALE_RX_FRAMES_PAGE / 4) +#define ALE_PROC_MAX \ + ((ALE_RX_PAGE_SZ * ALE_RX_PAGES) / ETHER_MAX_LEN) +#define ALE_PROC_DEFAULT (ALE_PROC_MAX / 4) + +struct ale_hw_stats { + /* Rx stats. */ + uint32_t rx_frames; + uint32_t rx_bcast_frames; + uint32_t rx_mcast_frames; + uint32_t rx_pause_frames; + uint32_t rx_control_frames; + uint32_t rx_crcerrs; + uint32_t rx_lenerrs; + uint64_t rx_bytes; + uint32_t rx_runts; + uint32_t rx_fragments; + uint32_t rx_pkts_64; + uint32_t rx_pkts_65_127; + uint32_t rx_pkts_128_255; + uint32_t rx_pkts_256_511; + uint32_t rx_pkts_512_1023; + uint32_t rx_pkts_1024_1518; + uint32_t rx_pkts_1519_max; + uint32_t rx_pkts_truncated; + uint32_t rx_fifo_oflows; + uint32_t rx_rrs_errs; + uint32_t rx_alignerrs; + uint64_t rx_bcast_bytes; + uint64_t rx_mcast_bytes; + uint32_t rx_pkts_filtered; + /* Tx stats. */ + uint32_t tx_frames; + uint32_t tx_bcast_frames; + uint32_t tx_mcast_frames; + uint32_t tx_pause_frames; + uint32_t tx_excess_defer; + uint32_t tx_control_frames; + uint32_t tx_deferred; + uint64_t tx_bytes; + uint32_t tx_pkts_64; + uint32_t tx_pkts_65_127; + uint32_t tx_pkts_128_255; + uint32_t tx_pkts_256_511; + uint32_t tx_pkts_512_1023; + uint32_t tx_pkts_1024_1518; + uint32_t tx_pkts_1519_max; + uint32_t tx_single_colls; + uint32_t tx_multi_colls; + uint32_t tx_late_colls; + uint32_t tx_excess_colls; + uint32_t tx_abort; + uint32_t tx_underrun; + uint32_t tx_desc_underrun; + uint32_t tx_lenerrs; + uint32_t tx_pkts_truncated; + uint64_t tx_bcast_bytes; + uint64_t tx_mcast_bytes; + /* Misc. */ + uint32_t reset_brk_seq; +}; + +/* + * Software state per device. + */ +struct ale_softc { + struct device sc_dev; + struct arpcom sc_arpcom; + + bus_space_tag_t sc_mem_bt; + bus_space_handle_t sc_mem_bh; + bus_size_t sc_mem_size; + bus_dma_tag_t sc_dmat; + pci_chipset_tag_t sc_pct; + pcitag_t sc_pcitag; + + void *sc_irq_handle; + + struct mii_data sc_miibus; + int ale_phyaddr; + + int ale_rev; + int ale_chip_rev; + uint8_t ale_eaddr[ETHER_ADDR_LEN]; + uint32_t ale_dma_rd_burst; + uint32_t ale_dma_wr_burst; + int ale_flags; +#define ALE_FLAG_PCIE 0x0001 +#define ALE_FLAG_PCIX 0x0002 +#define ALE_FLAG_MSI 0x0004 +#define ALE_FLAG_MSIX 0x0008 +#define ALE_FLAG_PMCAP 0x0010 +#define ALE_FLAG_FASTETHER 0x0020 +#define ALE_FLAG_JUMBO 0x0040 +#define ALE_FLAG_RXCSUM_BUG 0x0080 +#define ALE_FLAG_TXCSUM_BUG 0x0100 +#define ALE_FLAG_TXCMB_BUG 0x0200 +#define ALE_FLAG_DETACH 0x4000 +#define ALE_FLAG_LINK 0x8000 + + struct timeout ale_tick_ch; + struct ale_hw_stats ale_stats; + struct ale_chain_data ale_cdata; + int ale_int_rx_mod; + int ale_int_tx_mod; + int ale_max_frame_size; + int ale_pagesize; + +}; + +/* Register access macros. */ +#define CSR_WRITE_4(_sc, reg, val) \ + bus_space_write_4((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg), (val)) +#define CSR_WRITE_2(_sc, reg, val) \ + bus_space_write_2((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg), (val)) +#define CSR_WRITE_1(_sc, reg, val) \ + bus_space_write_1((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg), (val)) +#define CSR_READ_2(_sc, reg) \ + bus_space_read_2((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg)) +#define CSR_READ_4(_sc, reg) \ + bus_space_read_4((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg)) + +#define ALE_TX_TIMEOUT 5 +#define ALE_RESET_TIMEOUT 100 +#define ALE_TIMEOUT 1000 +#define ALE_PHY_TIMEOUT 1000 + +#endif /* _IF_ALEREG_H */ |