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-rw-r--r--sys/arch/arc/arc/cpu.c13
-rw-r--r--sys/arch/arc/arc/locore.S28
-rw-r--r--sys/arch/arc/arc/machdep.c76
-rw-r--r--sys/arch/arc/conf/GENERIC3
-rw-r--r--sys/arch/arc/conf/files.arc7
-rw-r--r--sys/arch/arc/dev/com_lbus.c6
-rw-r--r--sys/arch/arc/dev/lpt_lbus.c6
-rw-r--r--sys/arch/arc/dev/pccons.c14
-rw-r--r--sys/arch/arc/include/bus.h6
-rw-r--r--sys/arch/arc/include/cpu.h8
-rw-r--r--sys/arch/arc/isa/isa_machdep.h6
-rw-r--r--sys/arch/arc/isa/isabus.c8
-rw-r--r--sys/arch/arc/pci/pbcpcibus.c13
-rw-r--r--sys/arch/arc/pci/pcibrvar.h4
14 files changed, 116 insertions, 82 deletions
diff --git a/sys/arch/arc/arc/cpu.c b/sys/arch/arc/arc/cpu.c
index 1e5ae44f8a8..9db015785d2 100644
--- a/sys/arch/arc/arc/cpu.c
+++ b/sys/arch/arc/arc/cpu.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: cpu.c,v 1.6 1997/03/23 11:34:28 pefo Exp $ */
+/* $OpenBSD: cpu.c,v 1.7 1997/04/10 16:29:04 pefo Exp $ */
/*
* Copyright (c) 1997 Per Fogelstrom
@@ -126,8 +126,8 @@ cpuattach(parent, dev, aux)
case MIPS_R3TOSH:
printf("Toshiba R3000 based CPU");
break;
- case MIPS_R3NKK:
- printf("NKK R3000 based CPU");
+ case MIPS_RM5230:
+ printf("QED RM5230 based CPU");
break;
case MIPS_UNKC2:
default:
@@ -178,8 +178,11 @@ cpuattach(parent, dev, aux)
case MIPS_R3TOSH:
printf("Toshiba R3000 based FPC");
break;
- case MIPS_R3NKK:
- printf("NKK R3000 based FPC");
+ case MIPS_R5000:
+ printf("MIPS R5000 based FPC");
+ break;
+ case MIPS_RM5230:
+ printf("QED RM5230 based FPC");
break;
case MIPS_UNKF1:
default:
diff --git a/sys/arch/arc/arc/locore.S b/sys/arch/arc/arc/locore.S
index aba3e0f0050..89dab508a0e 100644
--- a/sys/arch/arc/arc/locore.S
+++ b/sys/arch/arc/arc/locore.S
@@ -1,4 +1,4 @@
-/* $OpenBSD: locore.S,v 1.10 1997/03/23 11:34:29 pefo Exp $ */
+/* $OpenBSD: locore.S,v 1.11 1997/04/10 16:29:06 pefo Exp $ */
/*
* Copyright (c) 1992, 1993
* The Regents of the University of California. All rights reserved.
@@ -50,7 +50,7 @@
* v 1.1 89/07/10 14:27:41 nelson Exp SPRITE (DECWRL)
*
* from: @(#)locore.s 8.5 (Berkeley) 1/4/94
- * $Id: locore.S,v 1.10 1997/03/23 11:34:29 pefo Exp $
+ * $Id: locore.S,v 1.11 1997/04/10 16:29:06 pefo Exp $
*/
/*
@@ -94,15 +94,14 @@ start:
sw zero, START_FRAME - 8(sp) # Zero out old fp for debugger
li t0, SR_COP_1_BIT # Disable interrupts and
- mtc0 t0, COP_0_STATUS_REG # enable the fp coprocessor
+ mtc0 t0, COP_0_STATUS_REG # enable the fp coprocessor
li sp, KERNELSTACK - START_FRAME # switch to standard stack
- mfc0 t0, COP_0_PRID # read processor ID register
nop
nop # wait for new status to
+ nop # wait for new status to
nop # to be effective
nop
cfc1 t1, FPC_ID # read FPU ID register
- sw t0, cpu_id # save PRID register
sw t1, fpu_id # save FPU ID register
jal main # main(regs)
move a0, zero
@@ -2571,11 +2570,18 @@ END(MachFPTrap)
* The size of the data cache is stored into CpuPrimaryDataCacheSize.
* The size of instruction cache is stored into CpuPrimaryInstCacheSize.
* Alignment mask for cache aliasing test is stored in CpuCacheAliasMask.
+ * cpu_id is set for later decision testing.
+
+XXX Needs support for Cpu controlled L2 caches (SC cpus). XXX
+
*
*----------------------------------------------------------------------------
*/
LEAF(R4K_ConfigCache)
.set noreorder
+ mfc0 t0, COP_0_PRID # read processor ID register
+ nop
+ sw t0, cpu_id # save PRID register
mfc0 v0, COP_0_CONFIG # Get configuration register
mfc0 v1, COP_0_PRID
srl t1, v0, 9 # Get I cache size.
@@ -2602,9 +2608,17 @@ LEAF(R4K_ConfigCache)
addu t2, t2, 16
sw t2, CpuPrimaryDataCacheLSize
and v1, 0xff00
- li t1, (MIPS_R4600 << 8)
+ li t2, 1 # Recognize CPU's with
+ li t1, (MIPS_R4600 << 8) # two way associative caches.
+ beq v1, t1, 1f
+ li t1, (MIPS_R4700 << 8)
+ beq v1, t1, 1f
+ li t1, (MIPS_R5000 << 8)
+ beq v1, t1, 1f
+ li t1, (MIPS_RM5230 << 8)
+ beq v1, t1, 1f
li t2, 1
- bnel v1, t1, 1f
+
li t2, 0
1:
sw t2, CpuTwoWayCache
diff --git a/sys/arch/arc/arc/machdep.c b/sys/arch/arc/arc/machdep.c
index dd29ad4029b..3c63278c3a6 100644
--- a/sys/arch/arc/arc/machdep.c
+++ b/sys/arch/arc/arc/machdep.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: machdep.c,v 1.23 1997/03/23 11:34:30 pefo Exp $ */
+/* $OpenBSD: machdep.c,v 1.24 1997/04/10 16:29:08 pefo Exp $ */
/*
* Copyright (c) 1988 University of Utah.
* Copyright (c) 1992, 1993
@@ -38,7 +38,7 @@
* SUCH DAMAGE.
*
* from: @(#)machdep.c 8.3 (Berkeley) 1/12/94
- * $Id: machdep.c,v 1.23 1997/03/23 11:34:30 pefo Exp $
+ * $Id: machdep.c,v 1.24 1997/04/10 16:29:08 pefo Exp $
*/
/* from: Utah Hdr: machdep.c 1.63 91/04/24 */
@@ -126,7 +126,8 @@ int cputype; /* Mother board type */
int num_tlbentries = 48; /* Size of the CPU tlb */
int ncpu = 1; /* At least one cpu in the system */
int CONADDR; /* Well, ain't it just plain stupid... */
-struct arc_bus_space arc_bus; /* Bus tag for bus.h macros */
+struct arc_bus_space arc_bus_io;/* Bus tag for bus.h macros */
+struct arc_bus_space arc_bus_mem;/* Bus tag for bus.h macros */
char **environment; /* On some arches, pointer to environment */
char eth_hw_addr[6]; /* HW ether addr not stored elsewhere */
@@ -194,11 +195,6 @@ mips_init(argc, argv, envv)
* entries as possible to do something useful :-).
*/
- arc_bus.isa_io_sparse1 = 0;
- arc_bus.isa_io_sparse2 = 0;
- arc_bus.isa_io_sparse4 = 0;
- arc_bus.isa_io_sparse8 = 0;
-
switch (cputype) {
case ACER_PICA_61: /* ALI PICA 61 and MAGNUM is almost the */
case MAGNUM: /* Same kind of hardware. NEC goes here too */
@@ -208,8 +204,8 @@ mips_init(argc, argv, envv)
else {
strcpy(cpu_model, "Acer Pica-61");
}
- arc_bus.isa_io_base = PICA_V_ISA_IO;
- arc_bus.isa_mem_base = PICA_V_ISA_MEM;
+ arc_bus_io.bus_base = PICA_V_ISA_IO;
+ arc_bus_mem.bus_base = PICA_V_ISA_MEM;
CONADDR = PICA_SYS_COM1;
/*
@@ -226,15 +222,15 @@ mips_init(argc, argv, envv)
case DESKSTATION_RPC44:
strcpy(cpu_model, "Deskstation rPC44");
- arc_bus.isa_io_base = 0xb0000000; /*XXX*/
- arc_bus.isa_mem_base = 0xa0000000; /*XXX*/
+ arc_bus_io.bus_base = 0xb0000000; /*XXX*/
+ arc_bus_mem.bus_base = 0xa0000000; /*XXX*/
CONADDR = 0; /* Don't screew the mouse... */
break;
case DESKSTATION_TYNE:
strcpy(cpu_model, "Deskstation Tyne");
- arc_bus.isa_io_base = TYNE_V_ISA_IO;
- arc_bus.isa_mem_base = TYNE_V_ISA_MEM;
+ arc_bus_io.bus_base = TYNE_V_ISA_IO;
+ arc_bus_mem.bus_base = TYNE_V_ISA_MEM;
CONADDR = 0; /* Don't screew the mouse... */
break;
@@ -242,33 +238,40 @@ mips_init(argc, argv, envv)
/* of other options. Systems not having an ARC Bios */
/* Make this more fancy when more comes in here */
+ environment = envv;
cputype = ALGOR_P4032;
strcpy(cpu_model, "Algorithmics P-4032");
- arc_bus.isa_io_base = 0;
- arc_bus.isa_io_sparse1 = 2;
- arc_bus.isa_io_sparse2 = 1;
- arc_bus.isa_io_sparse4 = 0;
- arc_bus.isa_io_sparse8 = 0;
- arc_bus.isa_mem_base = 0;
+ arc_bus_io.bus_sparse1 = 2;
+ arc_bus_io.bus_sparse2 = 1;
+ arc_bus_io.bus_sparse4 = 0;
+ arc_bus_io.bus_sparse8 = 0;
CONADDR = P4032_COM1;
- num_tlbentries = 32;
mem_layout[0].mem_start = 0;
mem_layout[0].mem_size = mips_trunc_page(CACHED_TO_PHYS(kernel_start));
mem_layout[1].mem_start = CACHED_TO_PHYS((int)sysend);
- i = get_simm_size((int *)0, 128*1024*1024);
- mem_layout[1].mem_size = i - (int)(CACHED_TO_PHYS(sysend));
- physmem = i;
+ if(getenv("memsize") != 0) {
+ i = atoi(getenv("memsize"), 10);
+ i = 1024 * 1024 * i;
+ mem_layout[1].mem_size = i - (int)(CACHED_TO_PHYS(sysend));
+ physmem = i;
+ }
+ else {
+ i = get_simm_size((int *)0, 128*1024*1024);
+ mem_layout[1].mem_size = i - (int)(CACHED_TO_PHYS(sysend));
+ physmem = i;
/*XXX Ouch!!! */
- mem_layout[2].mem_start = i;
- mem_layout[2].mem_size = get_simm_size((int *)(i), 0);
- physmem += mem_layout[2].mem_size;
- mem_layout[3].mem_start = i+i/2;
- mem_layout[3].mem_size = get_simm_size((int *)(i+i/2), 0);
- physmem += mem_layout[3].mem_size;
+ mem_layout[2].mem_start = i;
+ mem_layout[2].mem_size = get_simm_size((int *)(i), 0);
+ physmem += mem_layout[2].mem_size;
+ mem_layout[3].mem_start = i+i/2;
+ mem_layout[3].mem_size = get_simm_size((int *)(i+i/2), 0);
+ physmem += mem_layout[3].mem_size;
+ }
/*XXX*/
- environment = envv;
argv[0] = getenv("bootdev");
+ if(argv[0] == 0)
+ argv[0] = "unknown";
break;
@@ -334,6 +337,16 @@ mips_init(argc, argv, envv)
* Now its time to abandon the BIOS and be self supplying.
* Start with cleaning out the TLB. Bye bye Microsoft....
*/
+ cpucfg = R4K_ConfigCache();
+ switch(cpu_id.cpu.cp_imp) {
+ case MIPS_R4300:
+ num_tlbentries = 32;
+ break;
+ default:
+ num_tlbentries = 48;
+ break;
+ }
+
R4K_SetWIRED(0);
R4K_TLBFlush(num_tlbentries);
R4K_SetWIRED(VMWIRED_ENTRIES);
@@ -409,7 +422,6 @@ mips_init(argc, argv, envv)
/*
* Clear out the I and D caches.
*/
- cpucfg = R4K_ConfigCache();
R4K_FlushCache();
/*
diff --git a/sys/arch/arc/conf/GENERIC b/sys/arch/arc/conf/GENERIC
index 1695789a275..89a1c43e8c1 100644
--- a/sys/arch/arc/conf/GENERIC
+++ b/sys/arch/arc/conf/GENERIC
@@ -1,4 +1,4 @@
-# $OpenBSD: GENERIC,v 1.13 1997/03/23 11:34:32 pefo Exp $
+# $OpenBSD: GENERIC,v 1.14 1997/04/10 16:29:11 pefo Exp $
#
# Generic configuration file for MIPS R4x00 ARC Systems
#
@@ -61,6 +61,7 @@ option IPFILTER # IP packet filter for security
# Special options
options MACHINE_NONCONTIG # Support noncontigous memory.
+options PCIVERBOSE # Show as much info about pci as possible.
# Specify storage configuration (its a joke..)
config bsd swap generic
diff --git a/sys/arch/arc/conf/files.arc b/sys/arch/arc/conf/files.arc
index f76e00a4cfc..fe6aaafa4fc 100644
--- a/sys/arch/arc/conf/files.arc
+++ b/sys/arch/arc/conf/files.arc
@@ -1,4 +1,4 @@
-# $OpenBSD: files.arc,v 1.13 1997/03/23 11:34:32 pefo Exp $
+# $OpenBSD: files.arc,v 1.14 1997/04/10 16:29:12 pefo Exp $
#
# maxpartitions must be first item in files.${ARCH}
#
@@ -148,6 +148,11 @@ file arch/arc/dev/lpt_lbus.c lpt & (lpt_pica | lpt_algor)
# PCI Bus support
#
+# PCI VGA display driver
+device pcivga: tty
+attach pcivga at pci
+file arch/arc/pci/pci_vga.c pcivga
+
#
# Common files
#
diff --git a/sys/arch/arc/dev/com_lbus.c b/sys/arch/arc/dev/com_lbus.c
index e837b650481..fc877aad0b8 100644
--- a/sys/arch/arc/dev/com_lbus.c
+++ b/sys/arch/arc/dev/com_lbus.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: com_lbus.c,v 1.2 1997/03/23 11:34:33 pefo Exp $ */
+/* $OpenBSD: com_lbus.c,v 1.3 1997/04/10 16:29:15 pefo Exp $ */
/*
* Copyright (c) 1993, 1994 Charles Hannum.
@@ -99,7 +99,7 @@ com_localbus_probe(parent, match, aux)
if(!BUS_MATCHNAME(ca, "com"))
return(0);
iobase = (long)BUS_CVTADDR(ca);
- iot = &arc_bus;
+ iot = &arc_bus_io;
needioh = 1;
/* if it's in use as console, it's there. */
@@ -133,7 +133,7 @@ com_localbus_attach(parent, self, aux)
sc->sc_swflags = 0;
sc->sc_iobase = iobase = (bus_addr_t)BUS_CVTADDR(ca);
sc->sc_ioh = ioh = (bus_space_handle_t)iobase;
- sc->sc_iot = iot = &arc_bus;
+ sc->sc_iot = iot = &arc_bus_io;
if (iobase == comconsaddr) {
comconsattached = 1;
diff --git a/sys/arch/arc/dev/lpt_lbus.c b/sys/arch/arc/dev/lpt_lbus.c
index 51c82aa5242..fad7e1c3244 100644
--- a/sys/arch/arc/dev/lpt_lbus.c
+++ b/sys/arch/arc/dev/lpt_lbus.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: lpt_lbus.c,v 1.2 1997/03/23 11:34:34 pefo Exp $ */
+/* $OpenBSD: lpt_lbus.c,v 1.3 1997/04/10 16:29:17 pefo Exp $ */
/*
* Copyright (c) 1993, 1994 Charles Hannum.
@@ -101,7 +101,7 @@ lpt_localbus_probe(parent, match, aux)
if(!BUS_MATCHNAME(ca, "lpt"))
return(0);
- iot = &arc_bus;
+ iot = &arc_bus_io;
base = (bus_addr_t)BUS_CVTADDR(ca);
ioh = (bus_space_handle_t)base;
@@ -146,7 +146,7 @@ lpt_localbus_attach(parent, self, aux)
printf("\n");
sc->sc_state = 0;
- iot = sc->sc_iot = &arc_bus;
+ iot = sc->sc_iot = &arc_bus_io;
sc->sc_ioh = (bus_space_handle_t)BUS_CVTADDR(ca);
bus_space_write_1(iot, ioh, lpt_control, LPC_NINIT);
diff --git a/sys/arch/arc/dev/pccons.c b/sys/arch/arc/dev/pccons.c
index 9d857d7dd42..0b4174f589c 100644
--- a/sys/arch/arc/dev/pccons.c
+++ b/sys/arch/arc/dev/pccons.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: pccons.c,v 1.12 1997/03/12 19:16:52 pefo Exp $ */
+/* $OpenBSD: pccons.c,v 1.13 1997/04/10 16:29:19 pefo Exp $ */
/* $NetBSD: pccons.c,v 1.89 1995/05/04 19:35:20 cgd Exp $ */
/*-
@@ -858,12 +858,12 @@ pccninit(cp)
break;
case DESKSTATION_RPC44:
- mono_base += arc_bus.isa_io_base;
- mono_buf += arc_bus.isa_mem_base;
- cga_base += arc_bus.isa_io_base;
- cga_buf = arc_bus.isa_mem_base + 0xa0000;
- kbd_cmdp = arc_bus.isa_io_base + 0x64;
- kbd_datap = arc_bus.isa_io_base + 0x60;
+ mono_base += arc_bus_io.bus_base;
+ mono_buf += arc_bus_mem.bus_base;
+ cga_base += arc_bus_io.bus_base;
+ cga_buf = arc_bus_mem.bus_base + 0xa0000;
+ kbd_cmdp = arc_bus_io.bus_base + 0x64;
+ kbd_datap = arc_bus_io.bus_base + 0x60;
kbc_put8042cmd(CMDBYTE); /* Want XT codes.. */
break;
}
diff --git a/sys/arch/arc/include/bus.h b/sys/arch/arc/include/bus.h
index 4cb19a65187..8ca525ae571 100644
--- a/sys/arch/arc/include/bus.h
+++ b/sys/arch/arc/include/bus.h
@@ -1,4 +1,4 @@
-/* $OpenBSD: bus.h,v 1.11 1997/03/26 14:44:38 pefo Exp $ */
+/* $OpenBSD: bus.h,v 1.12 1997/04/10 16:29:22 pefo Exp $ */
/*
* Copyright (c) 1997 Per Fogelstrom. All rights reserved.
@@ -42,8 +42,6 @@
#define CAT3(a,b,c) a/**/b/**/c
#endif
-#define HIT_FLUSH_DCACHE(addr, len) R4K_HitFlushDCache(addr, len)
-
/*
* Bus access types.
*/
@@ -60,7 +58,7 @@ struct arc_bus_space {
u_int8_t bus_sparse8; /* Sparse addressing shift count */
};
-extern struct arc_bus_space arc_bus;
+extern struct arc_bus_space arc_bus_io, arc_bus_mem;
/*
* Access methods for bus resources
diff --git a/sys/arch/arc/include/cpu.h b/sys/arch/arc/include/cpu.h
index 9109b6cd0b1..f9b81386545 100644
--- a/sys/arch/arc/include/cpu.h
+++ b/sys/arch/arc/include/cpu.h
@@ -1,4 +1,4 @@
-/* $OpenBSD: cpu.h,v 1.6 1997/03/23 11:34:34 pefo Exp $ */
+/* $OpenBSD: cpu.h,v 1.7 1997/04/10 16:29:24 pefo Exp $ */
/*-
* Copyright (c) 1992, 1993
@@ -376,7 +376,8 @@ union cpuprid {
#define MIPS_R4600 0x20 /* QED R4600 Orion ISA III */
#define MIPS_R4700 0x21 /* QED R4700 Orion ISA III */
#define MIPS_R3TOSH 0x22 /* Toshiba R3000 based CPU ISA I */
-#define MIPS_R3NKK 0x23 /* NKK R3000 based CPU ISA I */
+#define MIPS_R5000 0x23 /* MIPS R5000 based CPU ISA IV */
+#define MIPS_RM5230 0x28 /* QED RM5230 based CPU ISA IV */
/*
* MIPS FPU types
@@ -395,7 +396,8 @@ union cpuprid {
#define MIPS_R4600 0x20 /* QED R4600 Orion ISA III */
#define MIPS_R3SONY 0x21 /* Sony R3000 based FPU ISA I */
#define MIPS_R3TOSH 0x22 /* Toshiba R3000 based FPU ISA I */
-#define MIPS_R3NKK 0x23 /* NKK R3000 based FPU ISA I */
+#define MIPS_R5010 0x23 /* MIPS R5000 based FPU ISA IV */
+#define MIPS_RM5230 0x28 /* QED RM5230 based FPU ISA IV */
#if defined(_KERNEL) && !defined(_LOCORE)
union cpuprid cpu_id;
diff --git a/sys/arch/arc/isa/isa_machdep.h b/sys/arch/arc/isa/isa_machdep.h
index d714d2e94e5..5186a287c94 100644
--- a/sys/arch/arc/isa/isa_machdep.h
+++ b/sys/arch/arc/isa/isa_machdep.h
@@ -1,4 +1,4 @@
-/* $OpenBSD: isa_machdep.h,v 1.3 1997/03/12 19:16:58 pefo Exp $ */
+/* $OpenBSD: isa_machdep.h,v 1.4 1997/04/10 16:29:27 pefo Exp $ */
/*
* Copyright (c) 1996 Per Fogelstrom
@@ -40,8 +40,8 @@ typedef struct arc_isa_bus *isa_chipset_tag_t;
* However, the cpu executes an instruction every 7.5ns
* so the bus is much slower so it doesn't matter, really.
*/
-#define isa_outb(x,y) outb(arc_bus.isa_io_base + (x), y)
-#define isa_inb(x) inb(arc_bus.isa_io_base + (x))
+#define isa_outb(x,y) outb(arc_bus_io.bus_base + (x), y)
+#define isa_inb(x) inb(arc_bus_io.bus_base + (x))
struct arc_isa_bus {
void *ic_data;
diff --git a/sys/arch/arc/isa/isabus.c b/sys/arch/arc/isa/isabus.c
index ab8d79944be..acce947fc7e 100644
--- a/sys/arch/arc/isa/isabus.c
+++ b/sys/arch/arc/isa/isabus.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: isabus.c,v 1.8 1997/03/12 19:16:59 pefo Exp $ */
+/* $OpenBSD: isabus.c,v 1.9 1997/04/10 16:29:28 pefo Exp $ */
/* $NetBSD: isa.c,v 1.33 1995/06/28 04:30:51 cgd Exp $ */
/*-
@@ -193,8 +193,8 @@ isabrattach(parent, self, aux)
sc->arc_isa_cs.ic_intr_disestablish = isabr_intr_disestablish;
iba.iba_busname = "isa";
- iba.iba_iot = (bus_space_tag_t)&arc_bus;
- iba.iba_memt = (bus_space_tag_t)&arc_bus;
+ iba.iba_iot = (bus_space_tag_t)&arc_bus_io;
+ iba.iba_memt = (bus_space_tag_t)&arc_bus_mem;
iba.iba_ic = &sc->arc_isa_cs;
config_found(self, &iba, isabrprint);
}
@@ -209,7 +209,7 @@ isabrprint(aux, pnp)
if (pnp)
printf("%s at %s", ca->ca_name, pnp);
printf(" isa_io_base 0x%lx isa_mem_base 0x%lx",
- arc_bus.isa_io_base, arc_bus.isa_mem_base);
+ arc_bus_io.bus_base, arc_bus_mem.bus_base);
return (UNCONF);
}
diff --git a/sys/arch/arc/pci/pbcpcibus.c b/sys/arch/arc/pci/pbcpcibus.c
index 61a48bc0368..a92d7043aad 100644
--- a/sys/arch/arc/pci/pbcpcibus.c
+++ b/sys/arch/arc/pci/pbcpcibus.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: pbcpcibus.c,v 1.2 1997/03/23 11:34:35 pefo Exp $ */
+/* $OpenBSD: pbcpcibus.c,v 1.3 1997/04/10 16:29:31 pefo Exp $ */
/*
* Copyright (c) 1997 Per Fogelstrom
@@ -121,12 +121,11 @@ pbcpcibrattach(parent, self, aux)
lcp = sc->sc_pcibr = &pbc_config;
- sc->sc_bus_space.isa_io_base = V96X_PCI_MEM_SPACE;
- sc->sc_bus_space.isa_mem_base = V96X_PCI_MEM_SPACE;
- sc->sc_bus_space.isa_io_sparse1 = 0;
- sc->sc_bus_space.isa_io_sparse2 = 0;
- sc->sc_bus_space.isa_io_sparse4 = 0;
- sc->sc_bus_space.isa_io_sparse8 = 0;
+ sc->sc_bus_space.bus_base = V96X_PCI_MEM_SPACE;
+ sc->sc_bus_space.bus_sparse1 = 0;
+ sc->sc_bus_space.bus_sparse2 = 0;
+ sc->sc_bus_space.bus_sparse4 = 0;
+ sc->sc_bus_space.bus_sparse8 = 0;
lcp->lc_pc.pc_conf_v = lcp;
lcp->lc_pc.pc_attach_hook = pbc_attach_hook;
diff --git a/sys/arch/arc/pci/pcibrvar.h b/sys/arch/arc/pci/pcibrvar.h
index a03964316ca..5994df85659 100644
--- a/sys/arch/arc/pci/pcibrvar.h
+++ b/sys/arch/arc/pci/pcibrvar.h
@@ -1,4 +1,4 @@
-/* $OpenBSD: pcibrvar.h,v 1.1 1997/03/12 19:17:02 pefo Exp $ */
+/* $OpenBSD: pcibrvar.h,v 1.2 1997/04/10 16:29:32 pefo Exp $ */
/*
* Copyright (c) 1997 Per Fogelstrom
@@ -42,7 +42,7 @@ struct pcibr_config {
struct pcibr_softc {
struct device sc_dev;
struct pcibr_config *sc_pcibr;
- struct arc_bus_space sc_bus_space;
+ struct arc_bus_space sc_bus_space; /* Same for I/O and Mem */
};
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-19 18:17:38 +0000