diff options
| -rw-r--r-- | sys/arch/i386/conf/GENERIC | 3 | ||||
| -rw-r--r-- | sys/dev/pci/files.pci | 7 | ||||
| -rw-r--r-- | sys/dev/pci/if_al.c | 2046 | ||||
| -rw-r--r-- | sys/dev/pci/if_alreg.h | 674 |
4 files changed, 2728 insertions, 2 deletions
diff --git a/sys/arch/i386/conf/GENERIC b/sys/arch/i386/conf/GENERIC index 8871b9da4ab..640cf0477ae 100644 --- a/sys/arch/i386/conf/GENERIC +++ b/sys/arch/i386/conf/GENERIC @@ -1,4 +1,4 @@ -# $OpenBSD: GENERIC,v 1.134 1999/10/26 13:12:49 downsj Exp $ +# $OpenBSD: GENERIC,v 1.135 1999/10/28 21:53:55 aaron Exp $ # $NetBSD: GENERIC,v 1.48 1996/05/20 18:17:23 mrg Exp $ # # GENERIC -- everything that's currently supported @@ -237,6 +237,7 @@ pn* at pci? dev ? function ? # Lite-On PNIC ethernet wb* at pci? dev ? function ? # Winbond W89C840F ethernet ti* at pci? dev ? function ? # Alteon Tigon 1Gb ethernet ax* at pci? dev ? function ? # ASIX AX88140A ethernet +al* at pci? dev ? function ? # ADMtek AL981/AN985 ethernet skc* at pci? dev ? function ? # SysKonnect GEnesis 984x sk* at skc? # each port of above diff --git a/sys/dev/pci/files.pci b/sys/dev/pci/files.pci index 555763fa4a5..9218250af61 100644 --- a/sys/dev/pci/files.pci +++ b/sys/dev/pci/files.pci @@ -1,4 +1,4 @@ -# $OpenBSD: files.pci,v 1.51 1999/10/26 13:06:14 downsj Exp $ +# $OpenBSD: files.pci,v 1.52 1999/10/28 21:53:55 aaron Exp $ # $NetBSD: files.pci,v 1.20 1996/09/24 17:47:15 christos Exp $ # # Config file and device description for machine-independent PCI code. @@ -189,6 +189,11 @@ device ax: ether, ifnet, ifmedia attach ax at pci file dev/pci/if_ax.c ax +# ADMtek AL981/AN985 ethernet +device al: ether, ifnet, ifmedia +attach al at pci +file dev/pci/if_al.c al + # Industrial Computer Source WDT-50x device wdt: pcibus attach wdt at pci diff --git a/sys/dev/pci/if_al.c b/sys/dev/pci/if_al.c new file mode 100644 index 00000000000..4c242c679e4 --- /dev/null +++ b/sys/dev/pci/if_al.c @@ -0,0 +1,2046 @@ +/* $OpenBSD: if_al.c,v 1.1 1999/10/28 21:53:55 aaron Exp $ */ +/* + * Copyright (c) 1997, 1998, 1999 + * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by Bill Paul. + * 4. Neither the name of the author nor the names of any co-contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + * + * $FreeBSD: src/sys/pci/if_al.c,v 1.14 1999/09/25 17:29:01 wpaul Exp $ + */ + +/* + * ADMtek AL981 Comet and AN985 Centaur fast ethernet PCI NIC driver. + * Datasheets for the AL981 are available from http://www.admtek.com.tw. + * + * Written by Bill Paul <wpaul@ee.columbia.edu> + * Electrical Engineering Department + * Columbia University, New York City + */ + +/* + * The ADMtek AL981 Comet is still another DEC 21x4x clone. It's + * a reasonably close copy of the tulip, except for the receiver filter + * programming. Where the DEC chip has a special setup frame that + * needs to be downloaded into the transmit DMA engine, the ADMtek chip + * has physical address and multicast address registers. + * + * The AN985 is an update to the AL981 which is mostly the same, except + * for the following things: + * - The AN985 uses a 99C66 EEPROM which requires a slightly different + * bit sequence to initiate a read. + * - The AN985 uses a serial MII interface instead of providing direct + * access to the PHY registers (it uses an internal PHY though). + * Although the datasheet for the AN985 is not yet available, you can + * use an AL981 datasheet as a reference for most of the chip functions, + * except for the MII interface which matches the DEC 21x4x specification + * (bits 16, 17, 18 and 19 in the serial I/O register control the MII). + */ + +#include "bpfilter.h" + +#include <sys/param.h> +#include <sys/systm.h> +#include <sys/mbuf.h> +#include <sys/protosw.h> +#include <sys/socket.h> +#include <sys/ioctl.h> +#include <sys/errno.h> +#include <sys/malloc.h> +#include <sys/kernel.h> + +#include <net/if.h> +#include <net/if_dl.h> +#include <net/if_types.h> + +#include <netinet/in.h> +#include <netinet/in_systm.h> +#include <netinet/in_var.h> +#include <netinet/ip.h> +#include <netinet/if_ether.h> + +#include <net/if_media.h> + +#if NBPFILTER > 0 +#include <net/bpf.h> +#endif + +#include <vm/vm.h> /* for vtophys */ +#include <vm/pmap.h> /* for vtophys */ + +#include <sys/device.h> + +#include <dev/mii/mii.h> +#include <dev/mii/miivar.h> + +#include <dev/pci/pcireg.h> +#include <dev/pci/pcivar.h> +#include <dev/pci/pcidevs.h> + +/* Enable workaround for small transmitter bug. */ +#define AL_TX_STALL_WAR + +#define AL_USEIOSPACE + +#include <dev/pci/if_alreg.h> + +/* + * Various supported PHY vendors/types and their names. Note that + * this driver will work with pretty much any MII-compliant PHY, + * so failure to positively identify the chip is not a fatal error. + */ + +struct al_type al_phys[] = { + { TI_PHY_VENDORID, TI_PHY_10BT, "<TI ThunderLAN 10BT (internal)>" }, + { TI_PHY_VENDORID, TI_PHY_100VGPMI, "<TI TNETE211 100VG Any-LAN>" }, + { NS_PHY_VENDORID, NS_PHY_83840A, "<National Semiconductor DP83840A>"}, + { LEVEL1_PHY_VENDORID, LEVEL1_PHY_LXT970, "<Level 1 LXT970>" }, + { INTEL_PHY_VENDORID, INTEL_PHY_82555, "<Intel 82555>" }, + { SEEQ_PHY_VENDORID, SEEQ_PHY_80220, "<SEEQ 80220>" }, + { 0, 0, "<MII-compliant physical interface>" } +}; + +int al_probe __P((struct device *, void *, void *)); +void al_attach __P((struct device *, struct device *, void *)); +int al_intr __P((void *)); +void al_shutdown __P((void *)); +int al_newbuf __P((struct al_softc *, struct al_desc *, + struct mbuf *)); +int al_encap __P((struct al_softc *, struct mbuf *, u_int32_t *)); +void al_rxeof __P((struct al_softc *)); +void al_txeof __P((struct al_softc *)); +void al_tick __P((void *)); +void al_start __P((struct ifnet *)); +int al_ioctl __P((struct ifnet *, u_long, caddr_t)); +void al_init __P((void *)); +void al_stop __P((struct al_softc *)); +void al_watchdog __P((struct ifnet *)); +int al_ifmedia_upd __P((struct ifnet *)); +void al_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); + +void al_delay __P((struct al_softc *)); +void al_eeprom_idle __P((struct al_softc *)); +void al_eeprom_putbyte __P((struct al_softc *, int)); +void al_eeprom_getword __P((struct al_softc *, int, u_int16_t *)); +void al_read_eeprom __P((struct al_softc *, caddr_t, int, int, int)); + +void al_mii_writebit __P((struct al_softc *, int)); +int al_mii_readbit __P((struct al_softc *)); +void al_mii_sync __P((struct al_softc *)); +void al_mii_send __P((struct al_softc *, u_int32_t, int)); +int al_mii_readreg __P((struct al_softc *, struct al_mii_frame *)); +int al_mii_writereg __P((struct al_softc *, struct al_mii_frame *)); + +u_int16_t al_phy_readreg __P((struct al_softc *, int)); +void al_phy_writereg __P((struct al_softc *, int, int)); + +void al_autoneg_xmit __P((struct al_softc *)); +void al_autoneg_mii __P((struct al_softc *, int, int)); +void al_setmode_mii __P((struct al_softc *, int)); +void al_getmode_mii __P((struct al_softc *)); + + +u_int32_t al_calchash __P((caddr_t)); +void al_setmulti __P((struct al_softc *)); +void al_reset __P((struct al_softc *)); +int al_list_rx_init __P((struct al_softc *)); +int al_list_tx_init __P((struct al_softc *)); + +#ifdef AL_USEIOSPACE +#define AL_RES SYS_RES_IOPORT +#define AL_RID AL_PCI_LOIO +#else +#define AL_RES SYS_RES_MEMORY +#define AL_RID AL_PCI_LOMEM +#endif + +#define AL_SETBIT(sc, reg, x) \ + CSR_WRITE_4(sc, reg, \ + CSR_READ_4(sc, reg) | x) + +#define AL_CLRBIT(sc, reg, x) \ + CSR_WRITE_4(sc, reg, \ + CSR_READ_4(sc, reg) & ~x) + +#define SIO_SET(x) \ + CSR_WRITE_4(sc, AL_SIO, \ + CSR_READ_4(sc, AL_SIO) | x) + +#define SIO_CLR(x) \ + CSR_WRITE_4(sc, AL_SIO, \ + CSR_READ_4(sc, AL_SIO) & ~x) + +void al_delay(sc) + struct al_softc *sc; +{ + int idx; + + for (idx = (300 / 33) + 1; idx > 0; idx--) + CSR_READ_4(sc, AL_BUSCTL); +} + +void al_eeprom_idle(sc) + struct al_softc *sc; +{ + register int i; + + CSR_WRITE_4(sc, AL_SIO, AL_SIO_EESEL); + al_delay(sc); + AL_SETBIT(sc, AL_SIO, AL_SIO_ROMCTL_READ); + al_delay(sc); + AL_SETBIT(sc, AL_SIO, AL_SIO_EE_CS); + al_delay(sc); + AL_SETBIT(sc, AL_SIO, AL_SIO_EE_CLK); + al_delay(sc); + + for (i = 0; i < 25; i++) { + AL_CLRBIT(sc, AL_SIO, AL_SIO_EE_CLK); + al_delay(sc); + AL_SETBIT(sc, AL_SIO, AL_SIO_EE_CLK); + al_delay(sc); + } + + AL_CLRBIT(sc, AL_SIO, AL_SIO_EE_CLK); + al_delay(sc); + AL_CLRBIT(sc, AL_SIO, AL_SIO_EE_CS); + al_delay(sc); + CSR_WRITE_4(sc, AL_SIO, 0x00000000); + + return; +} + +/* + * Send a read command and address to the EEPROM, check for ACK. + */ +void al_eeprom_putbyte(sc, addr) + struct al_softc *sc; + int addr; +{ + register int d, i; + + /* + * The AN985 has a 99C66 EEPROM on it instead of + * a 99C64. It uses a different bit sequence for + * specifying the "read" opcode. + */ + if (sc->al_did == PCI_PRODUCT_ADMTEK_AN985) + d = addr | (AL_EECMD_READ << 2); + else + d = addr | AL_EECMD_READ; + + /* + * Feed in each bit and stobe the clock. + */ + for (i = 0x400; i; i >>= 1) { + if (d & i) { + SIO_SET(AL_SIO_EE_DATAIN); + } else { + SIO_CLR(AL_SIO_EE_DATAIN); + } + al_delay(sc); + SIO_SET(AL_SIO_EE_CLK); + al_delay(sc); + SIO_CLR(AL_SIO_EE_CLK); + al_delay(sc); + } + + return; +} + +/* + * Read a word of data stored in the EEPROM at address 'addr.' + */ +void al_eeprom_getword(sc, addr, dest) + struct al_softc *sc; + int addr; + u_int16_t *dest; +{ + register int i; + u_int16_t word = 0; + + /* Force EEPROM to idle state. */ + al_eeprom_idle(sc); + + /* Enter EEPROM access mode. */ + CSR_WRITE_4(sc, AL_SIO, AL_SIO_EESEL); + al_delay(sc); + AL_SETBIT(sc, AL_SIO, AL_SIO_ROMCTL_READ); + al_delay(sc); + AL_SETBIT(sc, AL_SIO, AL_SIO_EE_CS); + al_delay(sc); + AL_CLRBIT(sc, AL_SIO, AL_SIO_EE_CLK); + al_delay(sc); + + /* + * Send address of word we want to read. + */ + al_eeprom_putbyte(sc, addr); + + /* + * Start reading bits from EEPROM. + */ + for (i = 0x8000; i; i >>= 1) { + SIO_SET(AL_SIO_EE_CLK); + al_delay(sc); + if (CSR_READ_4(sc, AL_SIO) & AL_SIO_EE_DATAOUT) + word |= i; + al_delay(sc); + SIO_CLR(AL_SIO_EE_CLK); + al_delay(sc); + } + + /* Turn off EEPROM access mode. */ + al_eeprom_idle(sc); + + *dest = word; + + return; +} + +/* + * Read a sequence of words from the EEPROM. + */ +void al_read_eeprom(sc, dest, off, cnt, swap) + struct al_softc *sc; + caddr_t dest; + int off; + int cnt; + int swap; +{ + int i; + u_int16_t word = 0, *ptr; + + for (i = 0; i < cnt; i++) { + al_eeprom_getword(sc, off + i, &word); + ptr = (u_int16_t *)(dest + (i * 2)); + if (swap) + *ptr = ntohs(word); + else + *ptr = word; + } + + return; +} + +/* + * Write a bit to the MII bus. + */ +void al_mii_writebit(sc, bit) + struct al_softc *sc; + int bit; +{ + if (bit) + CSR_WRITE_4(sc, AL_SIO, AL_SIO_ROMCTL_WRITE|AL_SIO_MII_DATAOUT); + else + CSR_WRITE_4(sc, AL_SIO, AL_SIO_ROMCTL_WRITE); + + AL_SETBIT(sc, AL_SIO, AL_SIO_MII_CLK); + AL_CLRBIT(sc, AL_SIO, AL_SIO_MII_CLK); + + return; +} + +/* + * Read a bit from the MII bus. + */ +int al_mii_readbit(sc) + struct al_softc *sc; +{ + CSR_WRITE_4(sc, AL_SIO, AL_SIO_ROMCTL_READ|AL_SIO_MII_DIR); + CSR_READ_4(sc, AL_SIO); + AL_SETBIT(sc, AL_SIO, AL_SIO_MII_CLK); + AL_CLRBIT(sc, AL_SIO, AL_SIO_MII_CLK); + if (CSR_READ_4(sc, AL_SIO) & AL_SIO_MII_DATAIN) + return(1); + + return(0); +} + +/* + * Sync the PHYs by setting data bit and strobing the clock 32 times. + */ +void al_mii_sync(sc) + struct al_softc *sc; +{ + register int i; + + CSR_WRITE_4(sc, AL_SIO, AL_SIO_ROMCTL_WRITE); + + for (i = 0; i < 32; i++) + al_mii_writebit(sc, 1); + + return; +} + +/* + * Clock a series of bits through the MII. + */ +void al_mii_send(sc, bits, cnt) + struct al_softc *sc; + u_int32_t bits; + int cnt; +{ + int i; + + for (i = (0x1 << (cnt - 1)); i; i >>= 1) + al_mii_writebit(sc, bits & i); +} + +/* + * Read an PHY register through the MII. + */ +int al_mii_readreg(sc, frame) + struct al_softc *sc; + struct al_mii_frame *frame; + +{ + int i, ack, s; + + s = splimp(); + + /* + * Set up frame for RX. + */ + frame->mii_stdelim = AL_MII_STARTDELIM; + frame->mii_opcode = AL_MII_READOP; + frame->mii_turnaround = 0; + frame->mii_data = 0; + + /* + * Sync the PHYs. + */ + al_mii_sync(sc); + + /* + * Send command/address info. + */ + al_mii_send(sc, frame->mii_stdelim, 2); + al_mii_send(sc, frame->mii_opcode, 2); + al_mii_send(sc, frame->mii_phyaddr, 5); + al_mii_send(sc, frame->mii_regaddr, 5); + +#ifdef notdef + /* Idle bit */ + al_mii_writebit(sc, 1); + al_mii_writebit(sc, 0); +#endif + + /* Check for ack */ + ack = al_mii_readbit(sc); + + /* + * Now try reading data bits. If the ack failed, we still + * need to clock through 16 cycles to keep the PHY(s) in sync. + */ + if (ack) { + for(i = 0; i < 16; i++) { + al_mii_readbit(sc); + } + goto fail; + } + + for (i = 0x8000; i; i >>= 1) { + if (!ack) { + if (al_mii_readbit(sc)) + frame->mii_data |= i; + } + } + +fail: + + al_mii_writebit(sc, 0); + al_mii_writebit(sc, 0); + + splx(s); + + if (ack) + return(1); + return(0); +} + +/* + * Write to a PHY register through the MII. + */ +int al_mii_writereg(sc, frame) + struct al_softc *sc; + struct al_mii_frame *frame; + +{ + int s; + + s = splimp(); + /* + * Set up frame for TX. + */ + + frame->mii_stdelim = AL_MII_STARTDELIM; + frame->mii_opcode = AL_MII_WRITEOP; + frame->mii_turnaround = AL_MII_TURNAROUND; + + /* + * Sync the PHYs. + */ + al_mii_sync(sc); + + al_mii_send(sc, frame->mii_stdelim, 2); + al_mii_send(sc, frame->mii_opcode, 2); + al_mii_send(sc, frame->mii_phyaddr, 5); + al_mii_send(sc, frame->mii_regaddr, 5); + al_mii_send(sc, frame->mii_turnaround, 2); + al_mii_send(sc, frame->mii_data, 16); + + /* Idle bit. */ + al_mii_writebit(sc, 0); + al_mii_writebit(sc, 0); + + splx(s); + + return(0); +} + + u_int16_t al_phy_readreg(sc, reg) + struct al_softc *sc; + int reg; +{ + u_int16_t rval = 0; + u_int16_t phy_reg = 0; + struct al_mii_frame frame; + + if (sc->al_did == PCI_PRODUCT_ADMTEK_AN985) { + if (sc->al_phy_addr != 1) + return(0); + frame.mii_phyaddr = sc->al_phy_addr; + frame.mii_regaddr = reg; + al_mii_readreg(sc, &frame); + return(frame.mii_data); + } + + switch(reg) { + case PHY_BMCR: + phy_reg = AL_BMCR; + break; + case PHY_BMSR: + phy_reg = AL_BMSR; + break; + case PHY_VENID: + phy_reg = AL_VENID; + break; + case PHY_DEVID: + phy_reg = AL_DEVID; + break; + case PHY_ANAR: + phy_reg = AL_ANAR; + break; + case PHY_LPAR: + phy_reg = AL_LPAR; + break; + case PHY_ANEXP: + phy_reg = AL_ANER; + break; + default: + printf("al%d: read: bad phy register %x\n", + sc->al_unit, reg); + break; + } + + rval = CSR_READ_4(sc, phy_reg) & 0x0000FFFF; + + return(rval); +} + +void al_phy_writereg(sc, reg, data) + struct al_softc *sc; + int reg; + int data; +{ + u_int16_t phy_reg = 0; + struct al_mii_frame frame; + + if (sc->al_did == PCI_PRODUCT_ADMTEK_AN985) { + if (sc->al_phy_addr != 1) + return; + frame.mii_phyaddr = sc->al_phy_addr; + frame.mii_regaddr = reg; + frame.mii_data = data; + al_mii_writereg(sc, &frame); + return; + } + + switch(reg) { + case PHY_BMCR: + phy_reg = AL_BMCR; + break; + case PHY_BMSR: + phy_reg = AL_BMSR; + break; + case PHY_VENID: + phy_reg = AL_VENID; + break; + case PHY_DEVID: + phy_reg = AL_DEVID; + break; + case PHY_ANAR: + phy_reg = AL_ANAR; + break; + case PHY_LPAR: + phy_reg = AL_LPAR; + break; + case PHY_ANEXP: + phy_reg = AL_ANER; + break; + default: + printf("al%d: phy_write: bad phy register %x\n", + sc->al_unit, reg); + break; + } + + CSR_WRITE_4(sc, phy_reg, data); + + return; +} + +/* + * Initiate an autonegotiation session. + */ +void al_autoneg_xmit(sc) + struct al_softc *sc; +{ + u_int16_t phy_sts; + + al_phy_writereg(sc, PHY_BMCR, PHY_BMCR_RESET); + DELAY(500); + while(al_phy_readreg(sc, PHY_BMCR) + & PHY_BMCR_RESET); + + phy_sts = al_phy_readreg(sc, PHY_BMCR); + phy_sts |= PHY_BMCR_AUTONEGENBL|PHY_BMCR_AUTONEGRSTR; + al_phy_writereg(sc, PHY_BMCR, phy_sts); + + return; +} + +/* + * Invoke autonegotiation on a PHY. + */ +void al_autoneg_mii(sc, flag, verbose) + struct al_softc *sc; + int flag; + int verbose; +{ + u_int16_t phy_sts = 0, media, advert, ability; + struct ifnet *ifp; + struct ifmedia *ifm; + + ifm = &sc->ifmedia; + ifp = &sc->arpcom.ac_if; + + ifm->ifm_media = IFM_ETHER | IFM_AUTO; + + /* + * The 100baseT4 PHY on the 3c905-T4 has the 'autoneg supported' + * bit cleared in the status register, but has the 'autoneg enabled' + * bit set in the control register. This is a contradiction, and + * I'm not sure how to handle it. If you want to force an attempt + * to autoneg for 100baseT4 PHYs, #define FORCE_AUTONEG_TFOUR + * and see what happens. + */ +#ifndef FORCE_AUTONEG_TFOUR + /* + * First, see if autoneg is supported. If not, there's + * no point in continuing. + */ + phy_sts = al_phy_readreg(sc, PHY_BMSR); + if (!(phy_sts & PHY_BMSR_CANAUTONEG)) { + if (verbose) + printf("al%d: autonegotiation not supported\n", + sc->al_unit); + ifm->ifm_media = IFM_ETHER|IFM_10_T|IFM_HDX; + return; + } +#endif + + switch (flag) { + case AL_FLAG_FORCEDELAY: + /* + * XXX Never use this option anywhere but in the probe + * routine: making the kernel stop dead in its tracks + * for three whole seconds after we've gone multi-user + * is really bad manners. + */ + al_autoneg_xmit(sc); + DELAY(5000000); + break; + case AL_FLAG_SCHEDDELAY: + /* + * Wait for the transmitter to go idle before starting + * an autoneg session, otherwise al_start() may clobber + * our timeout, and we don't want to allow transmission + * during an autoneg session since that can screw it up. + */ + if (sc->al_cdata.al_tx_cons != 0) { + sc->al_want_auto = 1; + return; + } + al_autoneg_xmit(sc); + ifp->if_timer = 5; + sc->al_autoneg = 1; + sc->al_want_auto = 0; + return; + break; + case AL_FLAG_DELAYTIMEO: + ifp->if_timer = 0; + sc->al_autoneg = 0; + break; + default: + printf("al%d: invalid autoneg flag: %d\n", sc->al_unit, flag); + return; + } + + if (al_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_AUTONEGCOMP) { + if (verbose) + printf("al%d: autoneg complete, ", sc->al_unit); + phy_sts = al_phy_readreg(sc, PHY_BMSR); + } else { + if (verbose) + printf("al%d: autoneg not complete, ", sc->al_unit); + } + + media = al_phy_readreg(sc, PHY_BMCR); + + /* Link is good. Report modes and set duplex mode. */ + if (al_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT) { + if (verbose) + printf("link status good "); + advert = al_phy_readreg(sc, PHY_ANAR); + ability = al_phy_readreg(sc, PHY_LPAR); + + if (advert & PHY_ANAR_100BT4 && ability & PHY_ANAR_100BT4) { + ifm->ifm_media = IFM_ETHER|IFM_100_T4; + media |= PHY_BMCR_SPEEDSEL; + media &= ~PHY_BMCR_DUPLEX; + printf("(100baseT4)\n"); + } else if (advert & PHY_ANAR_100BTXFULL && + ability & PHY_ANAR_100BTXFULL) { + ifm->ifm_media = IFM_ETHER|IFM_100_TX|IFM_FDX; + media |= PHY_BMCR_SPEEDSEL; + media |= PHY_BMCR_DUPLEX; + printf("(full-duplex, 100Mbps)\n"); + } else if (advert & PHY_ANAR_100BTXHALF && + ability & PHY_ANAR_100BTXHALF) { + ifm->ifm_media = IFM_ETHER|IFM_100_TX|IFM_HDX; + media |= PHY_BMCR_SPEEDSEL; + media &= ~PHY_BMCR_DUPLEX; + printf("(half-duplex, 100Mbps)\n"); + } else if (advert & PHY_ANAR_10BTFULL && + ability & PHY_ANAR_10BTFULL) { + ifm->ifm_media = IFM_ETHER|IFM_10_T|IFM_FDX; + media &= ~PHY_BMCR_SPEEDSEL; + media |= PHY_BMCR_DUPLEX; + printf("(full-duplex, 10Mbps)\n"); + } else if (advert & PHY_ANAR_10BTHALF && + ability & PHY_ANAR_10BTHALF) { + ifm->ifm_media = IFM_ETHER|IFM_10_T|IFM_HDX; + media &= ~PHY_BMCR_SPEEDSEL; + media &= ~PHY_BMCR_DUPLEX; + printf("(half-duplex, 10Mbps)\n"); + } + + media &= ~PHY_BMCR_AUTONEGENBL; + + /* Set ASIC's duplex mode to match the PHY. */ + al_phy_writereg(sc, PHY_BMCR, media); + } else { + if (verbose) + printf("no carrier\n"); + } + + al_init(sc); + + if (sc->al_tx_pend) { + sc->al_autoneg = 0; + sc->al_tx_pend = 0; + al_start(ifp); + } + + return; +} + +void al_getmode_mii(sc) + struct al_softc *sc; +{ + u_int16_t bmsr; + struct ifnet *ifp; + + ifp = &sc->arpcom.ac_if; + + bmsr = al_phy_readreg(sc, PHY_BMSR); + + /* fallback */ + sc->ifmedia.ifm_media = IFM_ETHER|IFM_10_T|IFM_HDX; + + if (bmsr & PHY_BMSR_10BTHALF) { + ifmedia_add(&sc->ifmedia, + IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL); + ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); + } + + if (bmsr & PHY_BMSR_10BTFULL) { + ifmedia_add(&sc->ifmedia, + IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); + sc->ifmedia.ifm_media = IFM_ETHER|IFM_10_T|IFM_FDX; + } + + if (bmsr & PHY_BMSR_100BTXHALF) { + ifp->if_baudrate = 100000000; + ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL); + ifmedia_add(&sc->ifmedia, + IFM_ETHER|IFM_100_TX|IFM_HDX, 0, NULL); + sc->ifmedia.ifm_media = IFM_ETHER|IFM_100_TX|IFM_HDX; + } + + if (bmsr & PHY_BMSR_100BTXFULL) { + ifp->if_baudrate = 100000000; + ifmedia_add(&sc->ifmedia, + IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL); + sc->ifmedia.ifm_media = IFM_ETHER|IFM_100_TX|IFM_FDX; + } + + /* Some also support 100BaseT4. */ + if (bmsr & PHY_BMSR_100BT4) { + ifp->if_baudrate = 100000000; + ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_T4, 0, NULL); + sc->ifmedia.ifm_media = IFM_ETHER|IFM_100_T4; +#ifdef FORCE_AUTONEG_TFOUR + ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0 NULL): + sc->ifmedia.ifm_media = IFM_ETHER|IFM_AUTO; +#endif + } + + if (bmsr & PHY_BMSR_CANAUTONEG) { + ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); + sc->ifmedia.ifm_media = IFM_ETHER|IFM_AUTO; + } + + return; +} + +/* + * Set speed and duplex mode. + */ +void al_setmode_mii(sc, media) + struct al_softc *sc; + int media; +{ + u_int16_t bmcr; + struct ifnet *ifp; + + ifp = &sc->arpcom.ac_if; + + /* + * If an autoneg session is in progress, stop it. + */ + if (sc->al_autoneg) { + printf("al%d: canceling autoneg session\n", sc->al_unit); + ifp->if_timer = sc->al_autoneg = sc->al_want_auto = 0; + bmcr = al_phy_readreg(sc, PHY_BMCR); + bmcr &= ~PHY_BMCR_AUTONEGENBL; + al_phy_writereg(sc, PHY_BMCR, bmcr); + } + + printf("al%d: selecting MII, ", sc->al_unit); + + bmcr = al_phy_readreg(sc, PHY_BMCR); + + bmcr &= ~(PHY_BMCR_AUTONEGENBL|PHY_BMCR_SPEEDSEL| + PHY_BMCR_DUPLEX|PHY_BMCR_LOOPBK); + + if (IFM_SUBTYPE(media) == IFM_100_T4) { + printf("100Mbps/T4, half-duplex\n"); + bmcr |= PHY_BMCR_SPEEDSEL; + bmcr &= ~PHY_BMCR_DUPLEX; + } + + if (IFM_SUBTYPE(media) == IFM_100_TX) { + printf("100Mbps, "); + bmcr |= PHY_BMCR_SPEEDSEL; + } + + if (IFM_SUBTYPE(media) == IFM_10_T) { + printf("10Mbps, "); + bmcr &= ~PHY_BMCR_SPEEDSEL; + } + + if ((media & IFM_GMASK) == IFM_FDX) { + printf("full duplex\n"); + bmcr |= PHY_BMCR_DUPLEX; + } else { + printf("half duplex\n"); + bmcr &= ~PHY_BMCR_DUPLEX; + } + + al_phy_writereg(sc, PHY_BMCR, bmcr); + + return; +} + + +/* + * Calculate CRC of a multicast group address, return the lower 6 bits. + */ +u_int32_t al_calchash(addr) + caddr_t addr; +{ + u_int32_t crc, carry; + int i, j; + u_int8_t c; + + /* Compute CRC for the address value. */ + crc = 0xFFFFFFFF; /* initial value */ + + for (i = 0; i < 6; i++) { + c = *(addr + i); + for (j = 0; j < 8; j++) { + carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); + crc <<= 1; + c >>= 1; + if (carry) + crc = (crc ^ 0x04c11db6) | carry; + } + } + + /* return the filter bit position */ + return((crc >> 26) & 0x0000003F); +} + +void al_setmulti(sc) + struct al_softc *sc; +{ + struct ifnet *ifp; + int h = 0; + u_int32_t hashes[2] = { 0, 0 }; + struct arpcom *ac = &sc->arpcom; + struct ether_multi *enm; + struct ether_multistep step; + u_int32_t rxfilt; + + ifp = &sc->arpcom.ac_if; + + rxfilt = CSR_READ_4(sc, AL_NETCFG); + + if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { + rxfilt |= AL_NETCFG_RX_ALLMULTI; + CSR_WRITE_4(sc, AL_NETCFG, rxfilt); + return; + } else + rxfilt &= ~AL_NETCFG_RX_ALLMULTI; + + /* first, zot all the existing hash bits */ + CSR_WRITE_4(sc, AL_MAR0, 0); + CSR_WRITE_4(sc, AL_MAR1, 0); + + /* now program new ones */ + ETHER_FIRST_MULTI(step, ac, enm); + while (enm != NULL) { + h = al_calchash(enm->enm_addrlo); + if (h < 32) + hashes[0] |= (1 << h); + else + hashes[1] |= (1 << (h - 32)); + ETHER_NEXT_MULTI(step, enm); + } + + CSR_WRITE_4(sc, AL_MAR0, hashes[0]); + CSR_WRITE_4(sc, AL_MAR1, hashes[1]); + CSR_WRITE_4(sc, AL_NETCFG, rxfilt); + + return; +} + +void al_reset(sc) + struct al_softc *sc; +{ + register int i; + + AL_SETBIT(sc, AL_BUSCTL, AL_BUSCTL_RESET); + + for (i = 0; i < AL_TIMEOUT; i++) { + DELAY(10); + if (!(CSR_READ_4(sc, AL_BUSCTL) & AL_BUSCTL_RESET)) + break; + } +#ifdef notdef + if (i == AL_TIMEOUT) + printf("al%d: reset never completed!\n", sc->al_unit); +#endif + CSR_WRITE_4(sc, AL_BUSCTL, AL_BUSCTL_ARBITRATION); + + /* Wait a little while for the chip to get its brains in order. */ + DELAY(1000); + return; +} + +/* + * Probe for an ADMtek chip. Check the PCI vendor and device + * IDs against our list and return a device name if we find a match. + */ +int al_probe(parent, match, aux) + struct device *parent; + void *match; + void *aux; +{ + struct pci_attach_args *pa = (struct pci_attach_args *)aux; + + if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_ADMTEK) + return(0); + + switch (PCI_PRODUCT(pa->pa_id)) { + case PCI_PRODUCT_ADMTEK_AL981: + case PCI_PRODUCT_ADMTEK_AN985: + return(1); + } + + return(0); +} + +/* + * Attach the interface. Allocate softc structures, do ifmedia + * setup and ethernet/BPF attach. + */ +void +al_attach(parent, self, aux) + struct device *parent, *self; + void *aux; +{ + int s, i; +#ifndef AL_USEIOSPACE + vm_offset_t pbase, vbase; +#endif + const char *intrstr = NULL; + u_int32_t command; + struct al_softc *sc = (struct al_softc *)self; + struct pci_attach_args *pa = aux; + pci_chipset_tag_t pc = pa->pa_pc; + pci_intr_handle_t ih; + struct ifnet *ifp; + int media = IFM_ETHER|IFM_100_TX|IFM_FDX; + bus_addr_t iobase; + bus_size_t iosize; + unsigned int round; + caddr_t roundptr; + struct al_type *p; + u_int16_t phy_vid, phy_did, phy_sts; + + s = splimp(); + sc->al_unit = sc->sc_dev.dv_unit; + sc->al_did = pa->pa_id; + + /* + * Handle power management nonsense. + */ + + command = pci_conf_read(pc, pa->pa_tag, AL_PCI_CAPID) & 0x000000FF; + if (command == 0x01) { + + command = pci_conf_read(pc, pa->pa_tag, AL_PCI_PWRMGMTCTRL); + if (command & AL_PSTATE_MASK) { + u_int32_t iobase, membase, irq; + + /* Save important PCI config data. */ + iobase = pci_conf_read(pc, pa->pa_tag, AL_PCI_LOIO); + membase = pci_conf_read(pc, pa->pa_tag, AL_PCI_LOMEM); + irq = pci_conf_read(pc, pa->pa_tag, AL_PCI_INTLINE); + + /* Reset the power state. */ + printf("al%d: chip is in D%d power mode " + "-- setting to D0\n", sc->al_unit, command & AL_PSTATE_MASK); + command &= 0xFFFFFFFC; + pci_conf_write(pc, pa->pa_tag, AL_PCI_PWRMGMTCTRL, command); + + /* Restore PCI config data. */ + pci_conf_write(pc, pa->pa_tag, AL_PCI_LOIO, iobase); + pci_conf_write(pc, pa->pa_tag, AL_PCI_LOMEM, membase); + pci_conf_write(pc, pa->pa_tag, AL_PCI_INTLINE, irq); + } + } + + /* + * Map control/status registers. + */ + command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); + command |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | + PCI_COMMAND_MASTER_ENABLE; + pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); + command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); + +#ifdef AL_USEIOSPACE + if (!(command & PCI_COMMAND_IO_ENABLE)) { + printf(": failed to enable I/O ports\n"); + goto fail; + } + if (pci_io_find(pc, pa->pa_tag, AL_PCI_LOIO, &iobase, &iosize)) { + printf(": can't find I/O space\n"); + goto fail; + } + if (bus_space_map(pa->pa_iot, iobase, iosize, 0, &sc->al_bhandle)) { + printf(": can't map I/O space\n"); + goto fail; + } + sc->al_btag = pa->pa_iot; +#else + if (!(command & PCI_COMMAND_MEM_ENABLE)) { + printf(": failed to enable memory mapping\n"); + goto fail; + } + if (pci_mem_find(pc, pa->pa_tag, AL_PCI_LOMEM, &iobase, &iosize, NULL)){ printf(": can't find mem space\n"); + goto fail; + } + if (bus_space_map(pa->pa_memt, iobase, iosize, 0, &sc->al_bhandle)) { + printf(": can't map mem space\n"); + goto fail; + } + sc->al_btag = pa->pa_memt; +#endif + + /* Allocate interrupt */ + if (pci_intr_map(pc, pa->pa_intrtag, pa->pa_intrpin, pa->pa_intrline, + &ih)) { + printf(": couldn't map interrupt\n"); + goto fail; + } + intrstr = pci_intr_string(pc, ih); + sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, al_intr, sc, + self->dv_xname); + if (sc->sc_ih == NULL) { + printf(": couldn't establish interrupt"); + if (intrstr != NULL) + printf(" at %s", intrstr); + printf("\n"); + goto fail; + } + printf(": %s", intrstr); + + /* Save cache line size. */ + sc->al_cachesize = pci_conf_read(pc, pa->pa_tag, AL_PCI_CACHELEN)&0xFF; + + /* Reset the adapter. */ + al_reset(sc); + + /* + * Get station address from the EEPROM. + */ + al_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr, AL_EE_NODEADDR,3,0); + printf(" address %s\n", ether_sprintf(sc->arpcom.ac_enaddr)); + + sc->al_ldata_ptr = malloc(sizeof(struct al_list_data) + 8, + M_DEVBUF, M_NOWAIT); + if (sc->al_ldata_ptr == NULL) { + printf("%s: no memory for list buffers!\n", sc->al_unit); + goto fail; + } + + sc->al_ldata = (struct al_list_data *)sc->al_ldata_ptr; + round = (unsigned long)sc->al_ldata_ptr & 0xF; + roundptr = sc->al_ldata_ptr; + for (i = 0; i < 8; i++) { + if (round % 8) { + round++; + roundptr++; + } else + break; + } + sc->al_ldata = (struct al_list_data *)roundptr; + bzero(sc->al_ldata, sizeof(struct al_list_data)); + + ifp = &sc->arpcom.ac_if; + ifp->if_softc = sc; + ifp->if_mtu = ETHERMTU; + ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; + ifp->if_ioctl = al_ioctl; + ifp->if_output = ether_output; + ifp->if_start = al_start; + ifp->if_watchdog = al_watchdog; + ifp->if_baudrate = 10000000; + ifp->if_snd.ifq_maxlen = AL_TX_LIST_CNT - 1; + bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); + + for (i = AL_PHYADDR_MIN; i < AL_PHYADDR_MAL + 1; i++) { + sc->al_phy_addr = i; + al_phy_writereg(sc, PHY_BMCR, PHY_BMCR_RESET); + DELAY(500); + while(al_phy_readreg(sc, PHY_BMCR) + & PHY_BMCR_RESET); + if ((phy_sts = al_phy_readreg(sc, PHY_BMSR))) + break; + } + if (phy_sts) { + phy_vid = al_phy_readreg(sc, PHY_VENID); + phy_did = al_phy_readreg(sc, PHY_DEVID); + p = al_phys; + while(p->al_vid) { + if (phy_vid == p->al_vid && + (phy_did | 0x000F) == p->al_did) { + sc->al_pinfo = p; + break; + } + p++; + } + if (sc->al_pinfo == NULL) + sc->al_pinfo = &al_phys[PHY_UNKNOWN]; + } else { +#ifdef DIAGNOSTIC + printf("al%d: MII without any phy!\n", sc->al_unit); +#endif + } + + /* + * Do ifmedia setup. + */ + ifmedia_init(&sc->ifmedia, 0, al_ifmedia_upd, al_ifmedia_sts); + + if (sc->al_pinfo != NULL) { + al_getmode_mii(sc); + al_autoneg_mii(sc, AL_FLAG_FORCEDELAY, 1); + } else { + ifmedia_add(&sc->ifmedia, + IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL); + ifmedia_add(&sc->ifmedia, + IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); + ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); + ifmedia_add(&sc->ifmedia, + IFM_ETHER|IFM_100_TX|IFM_HDX, 0, NULL); + ifmedia_add(&sc->ifmedia, + IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL); + ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL); + ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); + } + + media = sc->ifmedia.ifm_media; + al_stop(sc); + + ifmedia_set(&sc->ifmedia, media); + + /* + * Call MI attach routines. + */ + if_attach(ifp); + ether_ifattach(ifp); + +#if NBPFILTER > 0 + bpfattach(&sc->arpcom.ac_if.if_bpf, ifp, DLT_EN10MB, + sizeof(struct ether_header)); +#endif + shutdownhook_establish(al_shutdown, sc); + +fail: + splx(s); + return; +} + +/* + * Initialize the transmit descriptors. + */ +int al_list_tx_init(sc) + struct al_softc *sc; +{ + struct al_chain_data *cd; + struct al_list_data *ld; + int i; + + cd = &sc->al_cdata; + ld = sc->al_ldata; + for (i = 0; i < AL_TX_LIST_CNT; i++) { + if (i == (AL_TX_LIST_CNT - 1)) { + ld->al_tx_list[i].al_nextdesc = + &ld->al_tx_list[0]; + ld->al_tx_list[i].al_next = + vtophys(&ld->al_tx_list[0]); + } else { + ld->al_tx_list[i].al_nextdesc = + &ld->al_tx_list[i + 1]; + ld->al_tx_list[i].al_next = + vtophys(&ld->al_tx_list[i + 1]); + } + ld->al_tx_list[i].al_mbuf = NULL; + ld->al_tx_list[i].al_data = 0; + ld->al_tx_list[i].al_ctl = 0; + } + + cd->al_tx_prod = cd->al_tx_cons = cd->al_tx_cnt = 0; + + return(0); +} + + +/* + * Initialize the RX descriptors and allocate mbufs for them. Note that + * we arrange the descriptors in a closed ring, so that the last descriptor + * points back to the first. + */ +int al_list_rx_init(sc) + struct al_softc *sc; +{ + struct al_chain_data *cd; + struct al_list_data *ld; + int i; + + cd = &sc->al_cdata; + ld = sc->al_ldata; + + for (i = 0; i < AL_RX_LIST_CNT; i++) { + if (al_newbuf(sc, &ld->al_rx_list[i], NULL) == ENOBUFS) + return(ENOBUFS); + if (i == (AL_RX_LIST_CNT - 1)) { + ld->al_rx_list[i].al_nextdesc = + &ld->al_rx_list[0]; + ld->al_rx_list[i].al_next = + vtophys(&ld->al_rx_list[0]); + } else { + ld->al_rx_list[i].al_nextdesc = + &ld->al_rx_list[i + 1]; + ld->al_rx_list[i].al_next = + vtophys(&ld->al_rx_list[i + 1]); + } + } + + cd->al_rx_prod = 0; + + return(0); +} + +/* + * Initialize an RX descriptor and attach an MBUF cluster. + */ +int al_newbuf(sc, c, m) + struct al_softc *sc; + struct al_desc *c; + struct mbuf *m; +{ + struct mbuf *m_new = NULL; + + if (m == NULL) { + MGETHDR(m_new, M_DONTWAIT, MT_DATA); + if (m_new == NULL) { + printf("al%d: no memory for rx list " + "-- packet dropped!\n", sc->al_unit); + return(ENOBUFS); + } + + MCLGET(m_new, M_DONTWAIT); + if (!(m_new->m_flags & M_EXT)) { + printf("al%d: no memory for rx list " + "-- packet dropped!\n", sc->al_unit); + m_freem(m_new); + return(ENOBUFS); + } + m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; + } else { + m_new = m; + m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; + m_new->m_data = m_new->m_ext.ext_buf; + } + + m_adj(m_new, sizeof(u_int64_t)); + + c->al_mbuf = m_new; + c->al_data = vtophys(mtod(m_new, caddr_t)); + c->al_ctl = AL_RXCTL_RLINK | AL_RXLEN; + c->al_status = AL_RXSTAT_OWN; + + return(0); +} + +/* + * A frame has been uploaded: pass the resulting mbuf chain up to + * the higher level protocols. + */ +void al_rxeof(sc) + struct al_softc *sc; +{ + struct ether_header *eh; + struct mbuf *m; + struct ifnet *ifp; + struct al_desc *cur_rx; + int i, total_len = 0; + u_int32_t rxstat; + + ifp = &sc->arpcom.ac_if; + + i = sc->al_cdata.al_rx_prod; + + while(!(sc->al_ldata->al_rx_list[i].al_status & AL_RXSTAT_OWN)) { + struct mbuf *m0 = NULL; + + cur_rx = &sc->al_ldata->al_rx_list[i]; + rxstat = cur_rx->al_status; + m = cur_rx->al_mbuf; + cur_rx->al_mbuf = NULL; + total_len = AL_RXBYTES(rxstat); + AL_INC(i, AL_RX_LIST_CNT); + + /* + * If an error occurs, update stats, clear the + * status word and leave the mbuf cluster in place: + * it should simply get re-used next time this descriptor + * comes up in the ring. + */ + if (rxstat & AL_RXSTAT_RXERR) { + ifp->if_ierrors++; + if (rxstat & AL_RXSTAT_COLLSEEN) + ifp->if_collisions++; + al_newbuf(sc, cur_rx, m); + al_init(sc); + return; + } + + /* No errors; receive the packet. */ + total_len -= ETHER_CRC_LEN; + + m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, + total_len + ETHER_ALIGN, 0, ifp, NULL); + al_newbuf(sc, cur_rx, m); + if (m0 == NULL) { + ifp->if_ierrors++; + continue; + } + m_adj(m0, ETHER_ALIGN); + m = m0; + + ifp->if_ipackets++; + eh = mtod(m, struct ether_header *); +#if NBPFILTER > 0 + /* + * Handle BPF listeners. Let the BPF user see the packet, but + * don't pass it up to the ether_input() layer unless it's + * a broadcast packet, multicast packet, matches our ethernet + * address or the interface is in promiscuous mode. + */ + if (ifp->if_bpf) + bpf_mtap(ifp->if_bpf, m); +#endif + + /* Remove header from mbuf and pass it on. */ + m_adj(m, sizeof(struct ether_header)); + ether_input(ifp, eh, m); + } + + sc->al_cdata.al_rx_prod = i; + + return; +} + +/* + * A frame was downloaded to the chip. It's safe for us to clean up + * the list buffers. + */ + +void al_txeof(sc) + struct al_softc *sc; +{ + struct al_desc *cur_tx = NULL; + struct ifnet *ifp; + u_int32_t idx; + + ifp = &sc->arpcom.ac_if; + + /* Clear the timeout timer. */ + ifp->if_timer = 0; + + /* + * Go through our tx list and free mbufs for those + * frames that have been transmitted. + */ + idx = sc->al_cdata.al_tx_cons; + while(idx != sc->al_cdata.al_tx_prod) { + u_int32_t txstat; + + cur_tx = &sc->al_ldata->al_tx_list[idx]; + txstat = cur_tx->al_status; + + if (txstat & AL_TXSTAT_OWN) + break; + + if (!(cur_tx->al_ctl & AL_TXCTL_LASTFRAG)) { + sc->al_cdata.al_tx_cnt--; + AL_INC(idx, AL_TX_LIST_CNT); + continue; + } + + if (txstat & AL_TXSTAT_ERRSUM) { + ifp->if_oerrors++; + if (txstat & AL_TXSTAT_EXCESSCOLL) + ifp->if_collisions++; + if (txstat & AL_TXSTAT_LATECOLL) + ifp->if_collisions++; + al_init(sc); + return; + } + + ifp->if_collisions += (txstat & AL_TXSTAT_COLLCNT) >> 3; + + ifp->if_opackets++; + if (cur_tx->al_mbuf != NULL) { + m_freem(cur_tx->al_mbuf); + cur_tx->al_mbuf = NULL; + } + + sc->al_cdata.al_tx_cnt--; + AL_INC(idx, AL_TX_LIST_CNT); + ifp->if_timer = 0; + } + + sc->al_cdata.al_tx_cons = idx; + + if (cur_tx != NULL) + ifp->if_flags &= ~IFF_OACTIVE; + + return; +} + +void al_tick(xsc) + void *xsc; +{ + struct al_softc *sc; + struct mii_data *mii = NULL; + int s; + + s = splimp(); + + sc = xsc; + mii = &sc->sc_mii; + mii_tick(mii); + + timeout(al_tick, sc, hz); + + splx(s); + + return; +}; + +int al_intr(arg) + void *arg; +{ + struct al_softc *sc; + struct ifnet *ifp; + u_int32_t status; + int claimed = 0; + + sc = arg; + ifp = &sc->arpcom.ac_if; + + /* Supress unwanted interrupts */ + if (!(ifp->if_flags & IFF_UP)) { + al_stop(sc); + return(claimed); + } + + /* Disable interrupts. */ + CSR_WRITE_4(sc, AL_IMR, 0x00000000); + + for (;;) { + status = CSR_READ_4(sc, AL_ISR); + if (status) + CSR_WRITE_4(sc, AL_ISR, status); + + if ((status & AL_INTRS) == 0) + break; + + claimed = 1; + + if ((status & AL_ISR_TX_OK) || + (status & AL_ISR_TX_NOBUF)) + al_txeof(sc); + + if (status & AL_ISR_TX_IDLE) { + al_txeof(sc); + if (sc->al_cdata.al_tx_cnt) { + AL_SETBIT(sc, AL_NETCFG, AL_NETCFG_TX_ON); + CSR_WRITE_4(sc, AL_TXSTART, 0xFFFFFFFF); + } + } + + if (status & AL_ISR_TX_UNDERRUN) { + u_int32_t cfg; + cfg = CSR_READ_4(sc, AL_NETCFG); + if ((cfg & AL_NETCFG_TX_THRESH) == AL_TXTHRESH_160BYTES) + AL_SETBIT(sc, AL_NETCFG, AL_NETCFG_STORENFWD); + else + CSR_WRITE_4(sc, AL_NETCFG, cfg + 0x4000); + } + + if (status & AL_ISR_RX_OK) + al_rxeof(sc); + + if ((status & AL_ISR_RX_WATDOGTIMEO) || + (status & AL_ISR_RX_IDLE) || + (status & AL_ISR_RX_NOBUF)) { + al_rxeof(sc); + al_init(sc); + } + + if (status & AL_ISR_BUS_ERR) { + al_reset(sc); + al_init(sc); + } + } + + /* Re-enable interrupts. */ + CSR_WRITE_4(sc, AL_IMR, AL_INTRS); + + if (ifp->if_snd.ifq_head != NULL) { + al_start(ifp); + } + + return(claimed); +} + +/* + * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data + * pointers to the fragment pointers. + */ +int al_encap(sc, m_head, txidx) + struct al_softc *sc; + struct mbuf *m_head; + u_int32_t *txidx; +{ + struct al_desc *f = NULL; + struct mbuf *m; + int frag, cur, cnt = 0; + + /* + * Start packing the mbufs in this chain into + * the fragment pointers. Stop when we run out + * of fragments or hit the end of the mbuf chain. + */ + m = m_head; + cur = frag = *txidx; + + for (m = m_head; m != NULL; m = m->m_next) { + if (m->m_len != 0) { +#ifdef AL_TX_STALL_WAR + /* + * Work around some strange behavior in the Comet. For + * some reason, the transmitter will sometimes wedge if + * we queue up a descriptor chain that wraps from the end + * of the transmit list back to the beginning. If we reach + * the end of the list and still have more packets to queue, + * don't queue them now: end the transmit session here and + * then wait until it finishes before sending the other + * packets. + */ + if (*txidx != sc->al_cdata.al_tx_prod && + frag == (AL_TX_LIST_CNT - 1)) + return(ENOBUFS); +#endif + if ((AL_TX_LIST_CNT - + (sc->al_cdata.al_tx_cnt + cnt)) < 2) + return(ENOBUFS); + f = &sc->al_ldata->al_tx_list[frag]; + f->al_ctl = AL_TXCTL_TLINK | m->m_len; + if (cnt == 0) { + f->al_status = 0; + f->al_ctl |= AL_TXCTL_FIRSTFRAG; + } else + f->al_status = AL_TXSTAT_OWN; + f->al_data = vtophys(mtod(m, vm_offset_t)); + cur = frag; + AL_INC(frag, AL_TX_LIST_CNT); + cnt++; + } + } + + if (m != NULL) + return(ENOBUFS); + + sc->al_ldata->al_tx_list[cur].al_mbuf = m_head; + sc->al_ldata->al_tx_list[cur].al_ctl |= + AL_TXCTL_LASTFRAG|AL_TXCTL_FINT; + sc->al_ldata->al_tx_list[*txidx].al_status |= AL_TXSTAT_OWN; + sc->al_cdata.al_tx_cnt += cnt; + *txidx = frag; + + return(0); +} + +/* + * Main transmit routine. To avoid having to do mbuf copies, we put pointers + * to the mbuf data regions directly in the transmit lists. We also save a + * copy of the pointers since the transmit list fragment pointers are + * physical addresses. + */ + +void al_start(ifp) + struct ifnet *ifp; +{ + struct al_softc *sc; + struct mbuf *m_head = NULL; + u_int32_t idx; + + sc = ifp->if_softc; + + if (ifp->if_flags & IFF_OACTIVE) + return; + + idx = sc->al_cdata.al_tx_prod; + + while(sc->al_ldata->al_tx_list[idx].al_mbuf == NULL) { + IF_DEQUEUE(&ifp->if_snd, m_head); + if (m_head == NULL) + break; + + if (al_encap(sc, m_head, &idx)) { + IF_PREPEND(&ifp->if_snd, m_head); + ifp->if_flags |= IFF_OACTIVE; + break; + } + +#if NBPFILTER > 0 + /* + * If there's a BPF listener, bounce a copy of this frame + * to him. + */ + if (ifp->if_bpf) + bpf_mtap(ifp->if_bpf, m_head); +#endif + } + + /* Transmit */ + sc->al_cdata.al_tx_prod = idx; + CSR_WRITE_4(sc, AL_TXSTART, 0xFFFFFFFF); + + /* + * Set a timeout in case the chip goes out to lunch. + */ + ifp->if_timer = 5; + + return; +} + +void al_init(xsc) + void *xsc; +{ + struct al_softc *sc = xsc; + struct ifnet *ifp = &sc->arpcom.ac_if; + struct mii_data *mii = NULL; + int s; + + s = splimp(); + + mii = &sc->sc_mii; + + /* + * Cancel pending I/O and free all RX/TX buffers. + */ + al_stop(sc); + al_reset(sc); + + /* + * Set cache alignment and burst length. + */ + CSR_WRITE_4(sc, AL_BUSCTL, AL_BUSCTL_ARBITRATION); + AL_SETBIT(sc, AL_BUSCTL, AL_BURSTLEN_16LONG); + switch(sc->al_cachesize) { + case 32: + AL_SETBIT(sc, AL_BUSCTL, AL_CACHEALIGN_32LONG); + break; + case 16: + AL_SETBIT(sc, AL_BUSCTL, AL_CACHEALIGN_16LONG); + break; + case 8: + AL_SETBIT(sc, AL_BUSCTL, AL_CACHEALIGN_8LONG); + break; + case 0: + default: + AL_SETBIT(sc, AL_BUSCTL, AL_CACHEALIGN_NONE); + break; + } + + AL_CLRBIT(sc, AL_NETCFG, AL_NETCFG_HEARTBEAT); + AL_CLRBIT(sc, AL_NETCFG, AL_NETCFG_STORENFWD); + + AL_CLRBIT(sc, AL_NETCFG, AL_NETCFG_TX_THRESH); + + if (IFM_SUBTYPE(sc->ifmedia.ifm_media) == IFM_10_T) + AL_SETBIT(sc, AL_NETCFG, AL_TXTHRESH_160BYTES); + else + AL_SETBIT(sc, AL_NETCFG, AL_TXTHRESH_72BYTES); + + /* Init our MAC address */ + CSR_WRITE_4(sc, AL_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); + CSR_WRITE_4(sc, AL_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); + + /* Init circular RX list. */ + if (al_list_rx_init(sc) == ENOBUFS) { + printf("al%d: initialization failed: no " + "memory for rx buffers\n", sc->al_unit); + al_stop(sc); + (void)splx(s); + return; + } + + /* + * Init tx descriptors. + */ + al_list_tx_init(sc); + + /* If we want promiscuous mode, set the allframes bit. */ + if (ifp->if_flags & IFF_PROMISC) { + AL_SETBIT(sc, AL_NETCFG, AL_NETCFG_RX_PROMISC); + } else { + AL_CLRBIT(sc, AL_NETCFG, AL_NETCFG_RX_PROMISC); + } + + /* + * Load the multicast filter. + */ + al_setmulti(sc); + + /* + * Load the address of the RX list. + */ + CSR_WRITE_4(sc, AL_RXADDR, vtophys(&sc->al_ldata->al_rx_list[0])); + CSR_WRITE_4(sc, AL_TXADDR, vtophys(&sc->al_ldata->al_tx_list[0])); + + /* + * Enable interrupts. + */ + CSR_WRITE_4(sc, AL_IMR, AL_INTRS); + CSR_WRITE_4(sc, AL_ISR, 0xFFFFFFFF); + + /* Enable receiver and transmitter. */ + AL_SETBIT(sc, AL_NETCFG, AL_NETCFG_TX_ON|AL_NETCFG_RX_ON); + CSR_WRITE_4(sc, AL_RXSTART, 0xFFFFFFFF); + + mii_mediachg(mii); + + ifp->if_flags |= IFF_RUNNING; + ifp->if_flags &= ~IFF_OACTIVE; + + (void)splx(s); + + timeout(al_tick, sc, hz); + + return; +} + +/* + * Set media options. + */ +int al_ifmedia_upd(ifp) + struct ifnet *ifp; +{ + struct al_softc *sc; + + sc = ifp->if_softc; + + if (ifp->if_flags & IFF_UP) + al_init(sc); + + return(0); +} + +/* + * Report current media status. + */ +void al_ifmedia_sts(ifp, ifmr) + struct ifnet *ifp; + struct ifmediareq *ifmr; +{ + struct al_softc *sc; + struct mii_data *mii = NULL; + + sc = ifp->if_softc; + + mii = &sc->sc_mii; + mii_pollstat(mii); + ifmr->ifm_active = mii->mii_media_active; + ifmr->ifm_status = mii->mii_media_status; + + return; +} + +int al_ioctl(ifp, command, data) + struct ifnet *ifp; + u_long command; + caddr_t data; +{ + struct al_softc *sc = ifp->if_softc; + struct ifreq *ifr = (struct ifreq *) data; + struct ifaddr *ifa = (struct ifaddr *)data; + int s, error = 0; + + s = splimp(); + + if ((error = ether_ioctl(ifp, &sc->arpcom, command, data)) > 0) { + splx(s); + return error; + } + + switch(command) { + case SIOCSIFADDR: + ifp->if_flags |= IFF_UP; + switch (ifa->ifa_addr->sa_family) { + case AF_INET: + al_init(sc); + arp_ifinit(&sc->arpcom, ifa); + break; + default: + al_init(sc); + break; + } + break; + case SIOCGIFADDR: + case SIOCSIFMTU: + error = ether_ioctl(ifp, &sc->arpcom, command, data); + break; + case SIOCSIFFLAGS: + if (ifp->if_flags & IFF_UP) { + al_init(sc); + } else { + if (ifp->if_flags & IFF_RUNNING) + al_stop(sc); + } + error = 0; + break; + case SIOCADDMULTI: + case SIOCDELMULTI: + al_setmulti(sc); + error = 0; + break; + case SIOCGIFMEDIA: + case SIOCSIFMEDIA: + error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command); + break; + default: + error = EINVAL; + break; + } + + (void)splx(s); + + return(error); +} + +void al_watchdog(ifp) + struct ifnet *ifp; +{ + struct al_softc *sc; + + sc = ifp->if_softc; + + if (sc->al_autoneg) { + al_autoneg_mii(sc, AL_FLAG_DELAYTIMEO, 1); + return; + } + + ifp->if_oerrors++; + printf("al%d: watchdog timeout\n", sc->al_unit); + + if (sc->al_pinfo != NULL) { + if (!(al_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT)) + printf("al%d: no carrier - transceiver " + "cable problem?\n", sc->al_unit); + } + + al_stop(sc); + al_reset(sc); + al_init(sc); + + if (ifp->if_snd.ifq_head != NULL) + al_start(ifp); + + return; +} + +/* + * Stop the adapter and free any mbufs allocated to the + * RX and TX lists. + */ +void al_stop(sc) + struct al_softc *sc; +{ + register int i; + struct ifnet *ifp; + + ifp = &sc->arpcom.ac_if; + ifp->if_timer = 0; + + untimeout(al_tick, sc); + AL_CLRBIT(sc, AL_NETCFG, (AL_NETCFG_RX_ON|AL_NETCFG_TX_ON)); + CSR_WRITE_4(sc, AL_IMR, 0x00000000); + CSR_WRITE_4(sc, AL_TXADDR, 0x00000000); + CSR_WRITE_4(sc, AL_RXADDR, 0x00000000); + + /* + * Free data in the RX lists. + */ + for (i = 0; i < AL_RX_LIST_CNT; i++) { + if (sc->al_ldata->al_rx_list[i].al_mbuf != NULL) { + m_freem(sc->al_ldata->al_rx_list[i].al_mbuf); + sc->al_ldata->al_rx_list[i].al_mbuf = NULL; + } + } + bzero((char *)&sc->al_ldata->al_rx_list, + sizeof(sc->al_ldata->al_rx_list)); + + /* + * Free the TX list buffers. + */ + for (i = 0; i < AL_TX_LIST_CNT; i++) { + if (sc->al_ldata->al_tx_list[i].al_mbuf != NULL) { + m_freem(sc->al_ldata->al_tx_list[i].al_mbuf); + sc->al_ldata->al_tx_list[i].al_mbuf = NULL; + } + } + + bzero((char *)&sc->al_ldata->al_tx_list, + sizeof(sc->al_ldata->al_tx_list)); + + ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); + + return; +} + +/* + * Stop all chip I/O so that the kernel's probe routines don't + * get confused by errant DMAs when rebooting. + */ +void al_shutdown(v) + void *v; +{ + struct al_softc *sc = (struct al_softc *)v; + + al_stop(sc); +} + +struct cfattach al_ca = { + sizeof(struct al_softc), al_probe, al_attach +}; + +struct cfdriver al_cd = { + 0, "al", DV_IFNET +}; + diff --git a/sys/dev/pci/if_alreg.h b/sys/dev/pci/if_alreg.h new file mode 100644 index 00000000000..6a7843cb88c --- /dev/null +++ b/sys/dev/pci/if_alreg.h @@ -0,0 +1,674 @@ +/* $OpenBSD: if_alreg.h,v 1.1 1999/10/28 21:53:55 aaron Exp $ */ +/* + * Copyright (c) 1997, 1998, 1999 + * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by Bill Paul. + * 4. Neither the name of the author nor the names of any co-contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + * + * $FreeBSD: src/sys/pci/if_alreg.h,v 1.4 1999/09/22 05:07:47 wpaul Exp $ + */ + +/* + * COMET register definitions. + */ + +#define AL_BUSCTL 0x00 /* bus control */ +#define AL_TXSTART 0x08 /* tx start demand */ +#define AL_RXSTART 0x10 /* rx start demand */ +#define AL_RXADDR 0x18 /* rx descriptor list start addr */ +#define AL_TXADDR 0x20 /* tx descriptor list start addr */ +#define AL_ISR 0x28 /* interrupt status register */ +#define AL_NETCFG 0x30 /* network config register */ +#define AL_IMR 0x38 /* interrupt mask */ +#define AL_FRAMESDISCARDED 0x40 /* # of discarded frames */ +#define AL_SIO 0x48 /* MII and ROM/EEPROM access */ +#define AL_RESERVED 0x50 +#define AL_GENTIMER 0x58 /* general timer */ +#define AL_GENPORT 0x60 /* general purpose port */ +#define AL_WAKEUP_CTL 0x68 /* wake-up control/status register */ +#define AL_WAKEUP_PAT 0x70 /* wake-up pattern data register */ +#define AL_WATCHDOG 0x78 /* watchdog timer */ +#define AL_ISR2 0x80 /* ISR assist register */ +#define AL_IMR2 0x84 /* IRM assist register */ +#define AL_COMMAND 0x88 /* command register */ +#define AL_PCIPERF 0x8C /* pci perf counter */ +#define AL_PWRMGMT 0x90 /* pwr management command/status */ +#define AL_TXBURST 0x9C /* tx burst counter/timeout */ +#define AL_FLASHPROM 0xA0 /* flash(boot) PROM port */ +#define AL_PAR0 0xA4 /* station address */ +#define AL_PAR1 0xA8 /* station address */ +#define AL_MAR0 0xAC /* multicast hash filter */ +#define AL_MAR1 0xB0 /* multicast hash filter */ +#define AL_BMCR 0xB4 /* built in PHY control */ +#define AL_BMSR 0xB8 /* built in PHY status */ +#define AL_VENID 0xBC /* built in PHY ID0 */ +#define AL_DEVID 0xC0 /* built in PHY ID1 */ +#define AL_ANAR 0xC4 /* built in PHY autoneg advert */ +#define AL_LPAR 0xC8 /* bnilt in PHY link part. ability */ +#define AL_ANER 0xCC /* built in PHY autoneg expansion */ +#define AL_PHY_MODECTL 0xD0 /* mode control */ +#define AL_PHY_CONFIG 0xD4 /* config info and inter status */ +#define AL_PHY_INTEN 0xD8 /* interrupto enable */ +#define AL_PHY_MODECTL_100TX 0xDC /* 100baseTX control/status */ + +/* + * Bus control bits. + */ +#define AL_BUSCTL_RESET 0x00000001 +#define AL_BUSCTL_ARBITRATION 0x00000002 +#define AL_BUSCTL_SKIPLEN 0x0000007C +#define AL_BUSCTL_BIGENDIAN 0x00000080 +#define AL_BUSCTL_BURSTLEN 0x00003F00 +#define AL_BUSCTL_CACHEALIGN 0x0000C000 +#define AL_BUSCTL_XMITPOLL 0x00060000 +#define AL_BUSCTL_BUF_BIGENDIAN 0x00100000 +#define AL_BUSCTL_READMULTI 0x00200000 +#define AL_BUSCTL_READLINE 0x00800000 +#define AL_BUSCTL_WRITEINVAL 0x01000000 + +#define AL_SKIPLEN_1LONG 0x00000004 +#define AL_SKIPLEN_2LONG 0x00000008 +#define AL_SKIPLEN_3LONG 0x00000010 +#define AL_SKIPLEN_4LONG 0x00000020 +#define AL_SKIPLEN_5LONG 0x00000040 + +#define AL_BURSTLEN_UNLIMIT 0x00000000 +#define AL_BURSTLEN_1LONG 0x00000100 +#define AL_BURSTLEN_2LONG 0x00000200 +#define AL_BURSTLEN_4LONG 0x00000400 +#define AL_BURSTLEN_8LONG 0x00000800 +#define AL_BURSTLEN_16LONG 0x00001000 +#define AL_BURSTLEN_32LONG 0x00002000 + +#define AL_CACHEALIGN_NONE 0x00000000 +#define AL_CACHEALIGN_8LONG 0x00004000 +#define AL_CACHEALIGN_16LONG 0x00008000 +#define AL_CACHEALIGN_32LONG 0x0000C000 + +#define AL_TXPOLL_OFF 0x00000000 +#define AL_TXPOLL_200U 0x00020000 +#define AX_TXPOLL_800U 0x00040000 +#define AL_TXPOLL_1600U 0x00060000 + +/* + * Interrupt status bits. + */ +#define AL_ISR_TX_OK 0x00000001 +#define AL_ISR_TX_IDLE 0x00000002 +#define AL_ISR_TX_NOBUF 0x00000004 +#define AL_ISR_TX_JABBERTIMEO 0x00000008 +#define AL_ISR_TX_UNDERRUN 0x00000020 +#define AL_ISR_RX_OK 0x00000040 +#define AL_ISR_RX_NOBUF 0x00000080 +#define AL_ISR_RX_IDLE 0x00000100 +#define AL_ISR_RX_WATDOGTIMEO 0x00000200 +#define AL_ISR_TIMER_EXPIRED 0x00000800 +#define AL_ISR_BUS_ERR 0x00002000 +#define AL_ISR_ABNORMAL 0x00008000 +#define AL_ISR_NORMAL 0x00010000 +#define AL_ISR_RX_STATE 0x000E0000 +#define AL_ISR_TX_STATE 0x00700000 +#define AL_ISR_BUSERRTYPE 0x03800000 + +#define AL_RXSTATE_STOPPED 0x00000000 /* 000 - Stopped */ +#define AL_RXSTATE_FETCH 0x00020000 /* 001 - Fetching descriptor */ +#define AL_RXSTATE_ENDCHECK 0x00040000 /* 010 - check for rx end */ +#define AL_RXSTATE_WAIT 0x00060000 /* 011 - waiting for packet */ +#define AL_RXSTATE_SUSPEND 0x00080000 /* 100 - suspend rx */ +#define AL_RXSTATE_CLOSE 0x000A0000 /* 101 - close tx desc */ +#define AL_RXSTATE_FLUSH 0x000C0000 /* 110 - flush from FIFO */ +#define AL_RXSTATE_DEQUEUE 0x000E0000 /* 111 - dequeue from FIFO */ + +#define AL_TXSTATE_RESET 0x00000000 /* 000 - reset */ +#define AL_TXSTATE_FETCH 0x00100000 /* 001 - fetching descriptor */ +#define AL_TXSTATE_WAITEND 0x00200000 /* 010 - wait for tx end */ +#define AL_TXSTATE_READING 0x00300000 /* 011 - read and enqueue */ +#define AL_TXSTATE_RSVD 0x00400000 /* 100 - reserved */ +#define AL_TXSTATE_SETUP 0x00500000 /* 101 - setup packet */ +#define AL_TXSTATE_SUSPEND 0x00600000 /* 110 - suspend tx */ +#define AL_TXSTATE_CLOSE 0x00700000 /* 111 - close tx desc */ + +/* + * Network config bits. + */ +#define AL_NETCFG_RX_ON 0x00000002 +#define AL_NETCFG_RX_BADFRAMES 0x00000008 +#define AL_NETCFG_RX_BACKOFF 0x00000020 +#define AL_NETCFG_RX_PROMISC 0x00000040 +#define AL_NETCFG_RX_ALLMULTI 0x00000080 +#define AL_NETCFG_OPMODE 0x00000C00 +#define AL_NETCFG_FORCECOLL 0x00001000 +#define AL_NETCFG_TX_ON 0x00002000 +#define AL_NETCFG_TX_THRESH 0x0000C000 +#define AL_NETCFG_HEARTBEAT 0x00080000 /* 0 == ON, 1 == OFF */ +#define AL_NETCFG_STORENFWD 0x00200000 + +#define AL_OPMODE_NORM 0x00000000 +#define AL_OPMODE_INTLOOP 0x00000400 +#define AL_OPMODE_EXTLOOP 0x00000800 + +#define AL_TXTHRESH_72BYTES 0x00000000 +#define AL_TXTHRESH_96BYTES 0x00004000 +#define AL_TXTHRESH_128BYTES 0x00008000 +#define AL_TXTHRESH_160BYTES 0x0000C000 + +/* + * Interrupt mask bits. + */ +#define AL_IMR_TX_OK 0x00000001 +#define AL_IMR_TX_IDLE 0x00000002 +#define AL_IMR_TX_NOBUF 0x00000004 +#define AL_IMR_TX_JABBERTIMEO 0x00000008 +#define AL_IMR_TX_UNDERRUN 0x00000020 +#define AL_IMR_RX_OK 0x00000040 +#define AL_IMR_RX_NOBUF 0x00000080 +#define AL_IMR_RX_IDLE 0x00000100 +#define AL_IMR_RX_WATDOGTIMEO 0x00000200 +#define AL_IMR_TIMER_EXPIRED 0x00000800 +#define AL_IMR_BUS_ERR 0x00002000 +#define AL_IMR_ABNORMAL 0x00008000 +#define AL_IMR_NORMAL 0x00010000 + +#define AL_INTRS \ + (AL_IMR_RX_OK|AL_IMR_TX_OK|AL_IMR_RX_NOBUF|AL_IMR_RX_WATDOGTIMEO|\ + AL_IMR_TX_NOBUF|AL_IMR_TX_UNDERRUN|AL_IMR_BUS_ERR| \ + AL_IMR_ABNORMAL|AL_IMR_NORMAL|AL_IMR_TX_IDLE|AL_IMR_RX_IDLE) + +/* + * Missed packer register. + */ +#define AL_MISSEDPKT_CNT 0x0000FFFF +#define AL_MISSEDPKT_OFLOW 0x00010000 + +/* + * Serial I/O (EEPROM/ROM) bits. + */ +#define AL_SIO_EE_CS 0x00000001 /* EEPROM chip select */ +#define AL_SIO_EE_CLK 0x00000002 /* EEPROM clock */ +#define AL_SIO_EE_DATAIN 0x00000004 /* EEPROM data output */ +#define AL_SIO_EE_DATAOUT 0x00000008 /* EEPROM data input */ +#define AL_SIO_EESEL 0x00000800 +#define AL_SIO_ROMCTL_WRITE 0x00002000 +#define AL_SIO_ROMCTL_READ 0x00004000 +#define AL_SIO_MII_CLK 0x00010000 /* MDIO clock */ +#define AL_SIO_MII_DATAOUT 0x00020000 /* MDIO data out */ +#define AL_SIO_MII_DIR 0x00040000 /* MDIO dir */ +#define AL_SIO_MII_DATAIN 0x00080000 /* MDIO data in */ + +#define AL_EECMD_WRITE 0x140 +#define AL_EECMD_READ 0x180 +#define AL_EECMD_ERASE 0x1c0 + +#define AL_EE_NODEADDR_OFFSET 0x70 +#define AL_EE_NODEADDR 4 + +/* + * General purpose timer register + */ +#define AL_TIMER_VALUE 0x0000FFFF +#define AL_TIMER_CONTINUOUS 0x00010000 + +/* + * Wakeup control/status register. + */ +#define AL_WU_LINKSTS 0x00000001 /* link status changed */ +#define AL_WU_MAGICPKT 0x00000002 /* magic packet received */ +#define AL_WU_WUPKT 0x00000004 /* wake up pkt received */ +#define AL_WU_LINKSTS_ENB 0x00000100 /* enable linksts event */ +#define AL_WU_MAGICPKT_ENB 0x00000200 /* enable magicpkt event */ +#define AL_WU_WUPKT_ENB 0x00000400 /* enable wakeup pkt event */ +#define AL_WU_LINKON_ENB 0x00010000 /* enable link on detect */ +#define AL_WU_LINKOFF_ENB 0x00020000 /* enable link off detect */ +#define AL_WU_WKUPMATCH_PAT5 0x02000000 /* enable wkup pat 5 match */ +#define AL_WU_WKUPMATCH_PAT4 0x04000000 /* enable wkup pat 4 match */ +#define AL_WU_WKUPMATCH_PAT3 0x08000000 /* enable wkup pat 3 match */ +#define AL_WU_WKUPMATCH_PAT2 0x10000000 /* enable wkup pat 2 match */ +#define AL_WU_WKUPMATCH_PAT1 0x20000000 /* enable wkup pat 1 match */ +#define AL_WU_CRCTYPE 0x40000000 /* crc: 0=0000, 1=ffff */ + +/* + * Wakeup pattern structure. + */ +struct al_wu_pattern { + u_int32_t al_wu_bits[4]; +}; + +struct al_wakeup { + struct al_wu_pattern al_wu_pat; + u_int16_t al_wu_crc1; + u_int16_t al_wu_offset1; +}; + +struct al_wakup_record { + struct al_wakeup al_wakeup[5]; +}; + +/* + * Watchdog timer register. + */ +#define AL_WDOG_JABDISABLE 0x00000001 +#define AL_WDOG_NONJABBER 0x00000002 +#define AL_WDOG_JABCLK 0x00000004 +#define AL_WDOG_RXWDOG_DIS 0x00000010 +#define AL_WDOG_RXWDOG_REL 0x00000020 + +/* + * Assistant status register. + */ +#define AL_ISR2_ABNORMAL 0x00008000 +#define AL_ISR2_NORMAL 0x00010000 +#define AL_ISR2_RX_STATE 0x000E0000 +#define AL_ISR2_TX_STATE 0x00700000 +#define AL_ISR2_BUSERRTYPE 0x03800000 +#define AL_ISR2_PAUSE 0x04000000 /* PAUSE frame received */ +#define AL_ISR2_TX_DEFER 0x10000000 +#define AL_ISR2_XCVR_INT 0x20000000 +#define AL_ISR2_RX_EARLY 0x40000000 +#define AL_ISR2_TX_EARLY 0x80000000 + +/* + * Assistant mask register. + */ +#define AL_IMR2_ABNORMAL 0x00008000 +#define AL_IMR2_NORMAL 0x00010000 +#define AL_IMR2_PAUSE 0x04000000 /* PAUSE frame received */ +#define AL_IMR2_TX_DEFER 0x10000000 +#define AL_IMR2_XCVR_INT 0x20000000 +#define AL_IMR2_RX_EARLY 0x40000000 +#define AL_IMR2_TX_EARLY 0x80000000 + +/* + * Command register, some bits loaded from EEPROM. + */ +#define AL_CMD_TXURUN_REC 0x00000001 /* enable TX underflow recovery */ +#define AL_CMD_SOFTWARE_INT 0x00000002 /* software interrupt */ +#define AL_CMD_DRT 0x0000000C /* drain receive threshold */ +#define AL_CMD_RXTHRESH_ENB 0x00000010 /* rx threshold enable */ +#define AL_CMD_PAUSE 0x00000020 +#define AL_CMD_RST_WU_PTR 0x00000040 /* reset wakeup pattern reg. */ +/* Values below loaded from EEPROM. */ +#define AL_CMD_WOL_ENB 0x00040000 /* WOL enable */ +#define AL_CMD_PM_ENB 0x00080000 /* pwr mgmt enable */ +#define AL_CMD_RX_FIFO 0x00300000 +#define AL_CMD_LED_MODE 0x00400000 +#define AL_CMD_CURRENT_MODE 0x70000000 +#define AL_CMD_D3COLD 0x80000000 + +/* + * PCI performance counter. + */ +#define AL_PCI_DW_CNT 0x000000FF +#define AL_PCI_CLK 0xFFFF0000 + +/* + * Power management command and status. + */ +#define AL_PWRM_PWR_STATE 0x00000003 +#define AL_PWRM_PME_EN 0x00000100 +#define AL_PWRM_DSEL 0x00001E00 +#define AL_PWRM_DSCALE 0x00006000 +#define AL_PWRM_PME_STAT 0x00008000 + +/* + * TX burst count / timeout register. + */ +#define AL_TXB_TIMEO 0x00000FFF +#define AL_TXB_BURSTCNT 0x0000F000 + +/* + * Flash PROM register. + */ +#define AL_PROM_DATA 0x0000000F +#define AL_PROM_ADDR 0x01FFFFF0 +#define AL_PROM_WR_ENB 0x04000000 +#define AL_PROM_BRA16_ON 0x80000000 + +/* + * COMET TX/RX list structure. + */ + +struct al_desc { + u_int32_t al_status; + u_int32_t al_ctl; + u_int32_t al_ptr1; + u_int32_t al_ptr2; + /* Driver specific stuff. */ +#ifdef __i386__ + u_int32_t al_pad; +#endif + struct mbuf *al_mbuf; + struct al_desc *al_nextdesc; +}; + +#define al_data al_ptr1 +#define al_next al_ptr2 + +#define AL_RXSTAT_FIFOOFLOW 0x00000001 +#define AL_RXSTAT_CRCERR 0x00000002 +#define AL_RXSTAT_DRIBBLE 0x00000004 +#define AL_RXSTAT_WATCHDOG 0x00000010 +#define AL_RXSTAT_FRAMETYPE 0x00000020 /* 0 == IEEE 802.3 */ +#define AL_RXSTAT_COLLSEEN 0x00000040 +#define AL_RXSTAT_GIANT 0x00000080 +#define AL_RXSTAT_LASTFRAG 0x00000100 +#define AL_RXSTAT_FIRSTFRAG 0x00000200 +#define AL_RXSTAT_MULTICAST 0x00000400 +#define AL_RXSTAT_RUNT 0x00000800 +#define AL_RXSTAT_RXTYPE 0x00003000 +#define AL_RXSTAT_RXERR 0x00008000 +#define AL_RXSTAT_RXLEN 0x3FFF0000 +#define AL_RXSTAT_OWN 0x80000000 + +#define AL_RXBYTES(x) ((x & AL_RXSTAT_RXLEN) >> 16) +#define AL_RXSTAT (AL_RXSTAT_FIRSTFRAG|AL_RXSTAT_LASTFRAG|AL_RXSTAT_OWN) + +#define AL_RXCTL_BUFLEN1 0x00000FFF +#define AL_RXCTL_BUFLEN2 0x00FFF000 +#define AL_RXCTL_RLINK 0x01000000 +#define AL_RXCTL_RLAST 0x02000000 + +#define AL_TXSTAT_DEFER 0x00000001 +#define AL_TXSTAT_UNDERRUN 0x00000002 +#define AL_TXSTAT_LINKFAIL 0x00000003 +#define AL_TXSTAT_COLLCNT 0x00000078 +#define AL_TXSTAT_SQE 0x00000080 +#define AL_TXSTAT_EXCESSCOLL 0x00000100 +#define AL_TXSTAT_LATECOLL 0x00000200 +#define AL_TXSTAT_NOCARRIER 0x00000400 +#define AL_TXSTAT_CARRLOST 0x00000800 +#define AL_TXSTAT_JABTIMEO 0x00004000 +#define AL_TXSTAT_ERRSUM 0x00008000 +#define AL_TXSTAT_OWN 0x80000000 + +#define AL_TXCTL_BUFLEN1 0x000007FF +#define AL_TXCTL_BUFLEN2 0x003FF800 +#define AL_TXCTL_PAD 0x00800000 +#define AL_TXCTL_TLINK 0x01000000 +#define AL_TXCTL_TLAST 0x02000000 +#define AL_TXCTL_NOCRC 0x04000000 +#define AL_TXCTL_FIRSTFRAG 0x20000000 +#define AL_TXCTL_LASTFRAG 0x40000000 +#define AL_TXCTL_FINT 0x80000000 + +#define AL_MAXFRAGS 16 +#define AL_RX_LIST_CNT 64 +#define AL_TX_LIST_CNT 128 +#define AL_MIN_FRAMELEN 60 +#define AL_RXLEN 1536 + +#define AL_INC(x, y) (x) = (x + 1) % y + +struct al_list_data { + struct al_desc al_rx_list[AL_RX_LIST_CNT]; + struct al_desc al_tx_list[AL_TX_LIST_CNT]; +}; + +struct al_chain_data { + int al_tx_prod; + int al_tx_cons; + int al_tx_cnt; + int al_rx_prod; +}; + +struct al_type { + u_int16_t al_vid; + u_int16_t al_did; + char *al_name; +}; + +struct al_mii_frame { + u_int8_t mii_stdelim; + u_int8_t mii_opcode; + u_int8_t mii_phyaddr; + u_int8_t mii_regaddr; + u_int8_t mii_turnaround; + u_int16_t mii_data; +}; + +#define AL_MII_STARTDELIM 0x01 +#define AL_MII_READOP 0x02 +#define AL_MII_WRITEOP 0x01 +#define AL_MII_TURNAROUND 0x02 + +#define AL_FLAG_FORCEDELAY 1 +#define AL_FLAG_SCHEDDELAY 2 +#define AL_FLAG_DELAYTIMEO 3 + +struct al_softc { + struct device sc_dev; /* generic device structure */ + void *sc_ih; /* interrupt handler cookie */ + struct arpcom arpcom; /* interface info */ + struct ifmedia ifmedia; /* media info */ + mii_data_t sc_mii; /* mii bus */ + bus_space_handle_t al_bhandle; /* bus space handle */ + bus_space_tag_t al_btag; /* bus space tag */ + void *al_intrhand; + struct al_type *al_info; /* COMET adapter info */ + struct al_type *al_pinfo; + pci_product_id_t al_did; + u_int8_t al_unit; /* interface number */ + u_int8_t al_type; + u_int8_t al_phy_addr; /* PHY address */ + u_int8_t al_want_auto; + u_int8_t al_autoneg; + u_int8_t al_tx_pend; + struct al_list_data *al_ldata; + caddr_t al_ldata_ptr; + struct al_chain_data al_cdata; + u_int8_t al_cachesize; +}; + +/* + * register space access macros + */ +#define CSR_WRITE_4(sc, reg, val) \ + bus_space_write_4(sc->al_btag, sc->al_bhandle, reg, val) +#define CSR_WRITE_2(sc, reg, val) \ + bus_space_write_2(sc->al_btag, sc->al_bbhandle, reg, val) +#define CSR_WRITE_1(sc, reg, val) \ + bus_space_write_1(sc->al_btag, sc->al_bhandle, reg, val) + +#define CSR_READ_4(sc, reg) \ + bus_space_read_4(sc->al_btag, sc->al_bhandle, reg) +#define CSR_READ_2(sc, reg) \ + bus_space_read_2(sc->al_btag, sc->al_bhandle, reg) +#define CSR_READ_1(sc, reg) \ + bus_space_read_1(sc->al_btag, sc->al_bhandle, reg) + +#define AL_TIMEOUT 1000 +#define ETHER_ALIGN 2 + +/* + * General constants that are fun to know. + * + * ADMtek PCI vendor ID + */ +#define AL_VENDORID 0x1317 + +/* + * AL981 device IDs. + */ +#define AL_DEVICEID_AL981 0x0981 + +/* + * AN985 device IDs. + */ +#define AL_DEVICEID_AN985 0x0985 + +/* + * PCI low memory base and low I/O base register, and + * other PCI registers. + */ + +#define AL_PCI_VENDOR_ID 0x00 +#define AL_PCI_DEVICE_ID 0x02 +#define AL_PCI_COMMAND 0x04 +#define AL_PCI_STATUS 0x06 +#define AL_PCI_REVID 0x08 +#define AL_PCI_CLASSCODE 0x09 +#define AL_PCI_CACHELEN 0x0C +#define AL_PCI_LATENCY_TIMER 0x0D +#define AL_PCI_HEADER_TYPE 0x0E +#define AL_PCI_LOIO 0x10 +#define AL_PCI_LOMEM 0x14 +#define AL_PCI_BIOSROM 0x30 +#define AL_PCI_INTLINE 0x3C +#define AL_PCI_INTPIN 0x3D +#define AL_PCI_MINGNT 0x3E +#define AL_PCI_MINLAT 0x0F +#define AL_PCI_RESETOPT 0x48 +#define AL_PCI_EEPROM_DATA 0x4C + +/* power management registers */ +#define AL_PCI_CAPID 0x44 /* 8 bits */ +#define AL_PCI_NEXTPTR 0x45 /* 8 bits */ +#define AL_PCI_PWRMGMTCAP 0x46 /* 16 bits */ +#define AL_PCI_PWRMGMTCTRL 0x48 /* 16 bits */ + +#define AL_PSTATE_MASK 0x0003 +#define AL_PSTATE_D0 0x0000 +#define AL_PSTATE_D1 0x0001 +#define AL_PSTATE_D2 0x0002 +#define AL_PSTATE_D3 0x0003 +#define AL_PME_EN 0x0010 +#define AL_PME_STATUS 0x8000 + +/* + * Texas Instruments PHY identifiers + */ +#define TI_PHY_VENDORID 0x4000 +#define TI_PHY_10BT 0x501F +#define TI_PHY_100VGPMI 0x502F + +/* + * These ID values are for the NS DP83840A 10/100 PHY + */ +#define NS_PHY_VENDORID 0x2000 +#define NS_PHY_83840A 0x5C0F + +/* + * Level 1 10/100 PHY + */ +#define LEVEL1_PHY_VENDORID 0x7810 +#define LEVEL1_PHY_LXT970 0x000F + +/* + * Intel 82555 10/100 PHY + */ +#define INTEL_PHY_VENDORID 0x0A28 +#define INTEL_PHY_82555 0x015F + +/* + * SEEQ 80220 10/100 PHY + */ +#define SEEQ_PHY_VENDORID 0x0016 +#define SEEQ_PHY_80220 0xF83F + +#define PHY_UNKNOWN 6 + +#define AL_PHYADDR_MIN 0x00 +#define AL_PHYADDR_MAL 0x1F + +#define PHY_BMCR 0x00 +#define PHY_BMSR 0x01 +#define PHY_VENID 0x02 +#define PHY_DEVID 0x03 +#define PHY_ANAR 0x04 +#define PHY_LPAR 0x05 +#define PHY_ANEXP 0x06 + +#define PHY_ANAR_NEXTPAGE 0x8000 +#define PHY_ANAR_RSVD0 0x4000 +#define PHY_ANAR_TLRFLT 0x2000 +#define PHY_ANAR_RSVD1 0x1000 +#define PHY_ANAR_RSVD2 0x0800 +#define PHY_ANAR_RSVD3 0x0400 +#define PHY_ANAR_100BT4 0x0200 +#define PHY_ANAR_100BTXFULL 0x0100 +#define PHY_ANAR_100BTXHALF 0x0080 +#define PHY_ANAR_10BTFULL 0x0040 +#define PHY_ANAR_10BTHALF 0x0020 +#define PHY_ANAR_PROTO4 0x0010 +#define PHY_ANAR_PROTO3 0x0008 +#define PHY_ANAR_PROTO2 0x0004 +#define PHY_ANAR_PROTO1 0x0002 +#define PHY_ANAR_PROTO0 0x0001 + +/* + * These are the register definitions for the PHY (physical layer + * interface chip). + */ +/* + * PHY BMCR Basic Mode Control Register + */ +#define PHY_BMCR_RESET 0x8000 +#define PHY_BMCR_LOOPBK 0x4000 +#define PHY_BMCR_SPEEDSEL 0x2000 +#define PHY_BMCR_AUTONEGENBL 0x1000 +#define PHY_BMCR_RSVD0 0x0800 /* write as zero */ +#define PHY_BMCR_ISOLATE 0x0400 +#define PHY_BMCR_AUTONEGRSTR 0x0200 +#define PHY_BMCR_DUPLEX 0x0100 +#define PHY_BMCR_COLLTEST 0x0080 +#define PHY_BMCR_RSVD1 0x0040 /* write as zero, don't care */ +#define PHY_BMCR_RSVD2 0x0020 /* write as zero, don't care */ +#define PHY_BMCR_RSVD3 0x0010 /* write as zero, don't care */ +#define PHY_BMCR_RSVD4 0x0008 /* write as zero, don't care */ +#define PHY_BMCR_RSVD5 0x0004 /* write as zero, don't care */ +#define PHY_BMCR_RSVD6 0x0002 /* write as zero, don't care */ +#define PHY_BMCR_RSVD7 0x0001 /* write as zero, don't care */ + +/* + * PHY, BMSR Basic Mode Status Register + */ +#define PHY_BMSR_100BT4 0x8000 +#define PHY_BMSR_100BTXFULL 0x4000 +#define PHY_BMSR_100BTXHALF 0x2000 +#define PHY_BMSR_10BTFULL 0x1000 +#define PHY_BMSR_10BTHALF 0x0800 +#define PHY_BMSR_RSVD1 0x0400 /* write as zero, don't care */ +#define PHY_BMSR_RSVD2 0x0200 /* write as zero, don't care */ +#define PHY_BMSR_RSVD3 0x0100 /* write as zero, don't care */ +#define PHY_BMSR_RSVD4 0x0080 /* write as zero, don't care */ +#define PHY_BMSR_MFPRESUP 0x0040 +#define PHY_BMSR_AUTONEGCOMP 0x0020 +#define PHY_BMSR_REMFAULT 0x0010 +#define PHY_BMSR_CANAUTONEG 0x0008 +#define PHY_BMSR_LINKSTAT 0x0004 +#define PHY_BMSR_JABBER 0x0002 +#define PHY_BMSR_EXTENDED 0x0001 + +#ifndef ETHER_CRC_LEN +#define ETHER_CRC_LEN 4 +#endif + +#ifdef __alpha__ +#undef vtophys +#define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va) +#endif + |