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-rw-r--r--sys/dev/pci/drm/intel_display.c20
-rw-r--r--sys/dev/pci/drm/intel_pm.c20
-rw-r--r--sys/dev/pci/drm/intel_ringbuffer.c2
3 files changed, 21 insertions, 21 deletions
diff --git a/sys/dev/pci/drm/intel_display.c b/sys/dev/pci/drm/intel_display.c
index 4c99535423e..23f53ef0f1c 100644
--- a/sys/dev/pci/drm/intel_display.c
+++ b/sys/dev/pci/drm/intel_display.c
@@ -1307,7 +1307,7 @@ ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
for (retries = 50; retries > 0; retries--) {
if (I915_READ_NOTRACE(frame_reg) != frame)
break;
- DELAY(100);
+ DELAY(1000);
}
if (retries == 0)
DRM_DEBUG_KMS("vblank wait timed out\n");
@@ -1353,7 +1353,7 @@ intel_wait_for_vblank(struct drm_device *dev, int pipe)
for (retries = 50; retries > 0; retries--) {
if (I915_READ(pipestat_reg) & PIPE_VBLANK_INTERRUPT_STATUS)
break;
- DELAY(100);
+ DELAY(1000);
}
if (retries == 0)
DRM_DEBUG_KMS("vblank wait timed out\n");
@@ -2212,10 +2212,10 @@ ironlake_disable_pch_transcoder(struct inteldrm_softc *dev_priv,
val &= ~TRANS_ENABLE;
I915_WRITE(reg, val);
/* wait for PCH transcoder off, transcoder state */
- for (retries = 100; retries > 0; retries--) {
+ for (retries = 50; retries > 0; retries--) {
if ((I915_READ(reg) & TRANS_STATE_ENABLE) == 0)
break;
- DELAY(500);
+ DELAY(1000);
}
if (retries == 0)
DRM_ERROR("failed to disable transcoder %d\n", pipe);
@@ -2239,10 +2239,10 @@ lpt_disable_pch_transcoder(struct inteldrm_softc *dev_priv)
val &= ~TRANS_ENABLE;
I915_WRITE(_TRANSACONF, val);
/* wait for PCH transcoder off, transcoder state */
- for (retries = 100; retries > 0; retries--) {
+ for (retries = 50; retries > 0; retries--) {
if ((I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE) == 0)
break;
- DELAY(500);
+ DELAY(1000);
}
if (retries == 0)
DRM_ERROR("Failed to disable PCH transcoder\n");
@@ -3809,10 +3809,10 @@ intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
temp = I915_READ(dslreg);
DELAY(500);
- for (retries = 100; retries > 0; retries--) {
+ for (retries = 10; retries > 0; retries--) {
if (I915_READ(dslreg) != temp)
break;
- DELAY(500);
+ DELAY(1000);
}
if (retries == 0) {
DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
@@ -4946,10 +4946,10 @@ vlv_update_pll(struct drm_crtc *crtc,
dpll |= DPLL_VCO_ENABLE;
I915_WRITE(DPLL(pipe), dpll);
POSTING_READ(DPLL(pipe));
- for (retries = 100; retries > 0; retries--) {
+ for (retries = 1; retries > 0; retries--) {
if ((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV)
break;
- DELAY(100);
+ DELAY(1000);
}
if (retries == 0)
DRM_ERROR("DPLL %d failed to lock\n", pipe);
diff --git a/sys/dev/pci/drm/intel_pm.c b/sys/dev/pci/drm/intel_pm.c
index 05a7a786b09..2402f89b99a 100644
--- a/sys/dev/pci/drm/intel_pm.c
+++ b/sys/dev/pci/drm/intel_pm.c
@@ -182,7 +182,7 @@ i8xx_disable_fbc(struct drm_device *dev)
for (retries = 10; retries > 0; retries--) {
if ((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0)
break;
- DELAY(100);
+ DELAY(1000);
}
if (retries == 0) {
DRM_DEBUG_KMS("FBC idle timed out\n");
@@ -2547,10 +2547,10 @@ ironlake_enable_drps(struct drm_device *dev)
rgvmodectl |= MEMMODE_SWMODE_EN;
I915_WRITE(MEMMODECTL, rgvmodectl);
- for (retries = 100; retries > 0; retries--) {
+ for (retries = 10; retries > 0; retries--) {
if ((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0)
break;
- DELAY(100);
+ DELAY(1000);
}
if (retries == 0)
DRM_ERROR("stuck trying to change perf mode\n");
@@ -2932,7 +2932,7 @@ ironlake_disable_rc6(struct drm_device *dev)
for (retries = 50; retries > 0; retries--) {
if ((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON)
break;
- DELAY(500);
+ DELAY(1000);
}
I915_WRITE(PWRCTXA, 0);
@@ -4312,10 +4312,10 @@ intel_init_power_wells(struct drm_device *dev)
if ((well & HSW_PWR_WELL_STATE) == 0) {
I915_WRITE(power_wells[i], well & HSW_PWR_WELL_ENABLE);
- for (retries = 100; retries > 0; retries--) {
+ for (retries = 20; retries > 0; retries--) {
if (I915_READ(power_wells[i]) & HSW_PWR_WELL_STATE)
break;
- DELAY(200);
+ DELAY(1000);
}
if (retries == 0)
DRM_ERROR("Error enabling power well %lx\n", power_wells[i]);
@@ -4465,11 +4465,11 @@ __gen6_gt_wait_for_thread_c0(struct inteldrm_softc *dev_priv)
/* w/a for a sporadic read returning 0 by waiting for the GT
* thread to wake up.
*/
- for (retries = 100; retries > 0; retries--) {
+ for (retries = 500; retries > 0; retries--) {
if ((I915_READ_NOTRACE(GEN6_GT_THREAD_STATUS_REG) &
gt_thread_status_mask) == 0)
break;
- DELAY(50);
+ DELAY(1000);
}
if (retries == 0)
DRM_ERROR("GT thread status wait timed out\n");
@@ -4705,7 +4705,7 @@ sandybridge_pcode_read(struct inteldrm_softc *dev_priv, u8 mbox, u32 *val)
I915_WRITE(GEN6_PCODE_DATA, *val);
I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
- for (retries = 100; retries > 0; retries--) {
+ for (retries = 500; retries > 0; retries--) {
if ((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0)
break;
DELAY(1000);
@@ -4735,7 +4735,7 @@ sandybridge_pcode_write(struct inteldrm_softc *dev_priv, u8 mbox, u32 val)
I915_WRITE(GEN6_PCODE_DATA, val);
I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
- for (retries = 100; retries > 0; retries--) {
+ for (retries = 500; retries > 0; retries--) {
if ((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0)
break;
DELAY(1000);
diff --git a/sys/dev/pci/drm/intel_ringbuffer.c b/sys/dev/pci/drm/intel_ringbuffer.c
index c206e3bec00..e9b5f0f1686 100644
--- a/sys/dev/pci/drm/intel_ringbuffer.c
+++ b/sys/dev/pci/drm/intel_ringbuffer.c
@@ -461,7 +461,7 @@ init_ring_common(struct intel_ring_buffer *ring)
| RING_VALID);
/* If the head is still not zero, the ring is dead */
- for (retries = 1000; retries > 0; retries--) {
+ for (retries = 50; retries > 0; retries--) {
if ((I915_READ_CTL(ring) & RING_VALID) != 0 &&
I915_READ_START(ring) == obj->gtt_offset &&
(I915_READ_HEAD(ring) & HEAD_ADDR) == 0)
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-21 21:28:22 +0000