diff options
| -rw-r--r-- | sys/dev/ic/ispreg.h | 244 |
1 files changed, 205 insertions, 39 deletions
diff --git a/sys/dev/ic/ispreg.h b/sys/dev/ic/ispreg.h index 75b15f8e37e..2989672e587 100644 --- a/sys/dev/ic/ispreg.h +++ b/sys/dev/ic/ispreg.h @@ -1,37 +1,40 @@ -/* $OpenBSD: ispreg.h,v 1.14 2008/01/21 20:00:33 sobrado Exp $ */ +/* $OpenBSD: ispreg.h,v 1.15 2008/10/25 22:53:30 krw Exp $ */ +/* $FreeBSD: src/sys/dev/isp/ispreg.h,v 1.29 2007/03/10 02:39:54 mjacob Exp $ */ +/*- + * Copyright (c) 1997-2007 by Matthew Jacob + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ /* * Machine Independent (well, as best as possible) register - * definitions for QLogic ISP SCSI adapters. - * - * Copyright (c) 1997, 1998, 1999, 2000 by Matthew Jacob - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice immediately at the beginning of the file, without modification, - * this list of conditions, and the following disclaimer. - * 2. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. + * definitions for Qlogic ISP SCSI adapters. */ #ifndef _ISPREG_H #define _ISPREG_H /* - * Hardware definitions for the QLogic ISP registers. + * Hardware definitions for the Qlogic ISP registers. */ /* @@ -64,6 +67,7 @@ #define PCI_MBOX_REGS_OFF 0x70 #define PCI_MBOX_REGS2100_OFF 0x10 #define PCI_MBOX_REGS2300_OFF 0x40 +#define PCI_MBOX_REGS2400_OFF 0x80 #define SBUS_MBOX_REGS_OFF 0x80 #define PCI_SXP_REGS_OFF 0x80 @@ -110,12 +114,6 @@ #define BIU_NVRAM (BIU_BLOCK+0xE) /* RW : Bus NVRAM */ /* * These are specific to the 2300. - * - * They *claim* you can read BIU_R2HSTSLO with a full 32 bit access - * and get both registers, but I'm a bit dubious about that. But the - * point here is that the top 16 bits are firmware defined bits that - * the RISC processor uses to inform the host about something- usually - * something which was nominally in a mailbox register. */ #define BIU_REQINP (BIU_BLOCK+0x10) /* Request Queue In */ #define BIU_REQOUTP (BIU_BLOCK+0x12) /* Request Queue Out */ @@ -139,6 +137,7 @@ #define ISPR2HST_FPOST 0x16 /* Low 16 bits fast post */ #define ISPR2HST_FPOST_CTIO 0x17 /* Low 16 bits fast post ctio */ +/* fifo command stuff- mostly for SPI */ #define DFIFO_COMMAND (BIU_BLOCK+0x60) /* RW : Command FIFO Port */ #define RDMA2100_CONTROL DFIFO_COMMAND #define DFIFO_DATA (BIU_BLOCK+0x62) /* RW : Data FIFO Port */ @@ -205,6 +204,8 @@ #define BIU2100_FPM0_REGS (2 << 4) /* FPM 0 Regs */ #define BIU2100_FPM1_REGS (3 << 4) /* FPM 1 Regs */ #define BIU2100_PCI64 0x04 /* R: 64 Bit PCI slot */ +#define BIU2100_NVRAM_OFFSET (1 << 14) +#define BIU2100_FLASH_UPPER_64K 0x04 /* RW: Upper 64K Bank Select */ #define BIU2100_FLASH_ENABLE 0x02 /* RW: Enable Flash RAM */ #define BIU2100_SOFT_RESET 0x01 /* SOFT RESET FOR ISP2100 is same bit, but in this register, not ICR */ @@ -218,6 +219,8 @@ #define BIU_ICR_ENABLE_ALL_INTS 0x0002 /* Global enable all inter */ #define BIU_ICR_SOFT_RESET 0x0001 /* Soft Reset of ISP */ +#define BIU_IMASK (BIU_ICR_ENABLE_RISC_INT|BIU_ICR_ENABLE_ALL_INTS) + #define BIU2100_ICR_ENABLE_ALL_INTS 0x8000 #define BIU2100_ICR_ENA_FPM_INT 0x0020 #define BIU2100_ICR_ENA_FB_INT 0x0010 @@ -268,6 +271,7 @@ #define BIU_NVRAM_SELECT 0x0002 #define BIU_NVRAM_DATAOUT 0x0004 #define BIU_NVRAM_DATAIN 0x0008 +#define BIU_NVRAM_BUSY 0x0080 /* 2322/24xx only */ #define ISP_NVRAM_READ 6 /* COMNMAND && DATA DMA CONFIGURATION REGISTER */ @@ -350,6 +354,86 @@ #define DMA_FIFO_PCI_COUNT_MASK 0x00FF /* FIFO Byte count mask */ /* + * 2400 Interface Offsets and Register Definitions + * + * The 2400 looks quite different in terms of registers from other QLogic cards. + * It is getting to be a genuine pain and challenge to keep the same model + * for all. + */ +#define BIU2400_FLASH_ADDR (BIU_BLOCK+0x00) +#define BIU2400_FLASH_DATA (BIU_BLOCK+0x04) +#define BIU2400_CSR (BIU_BLOCK+0x08) +#define BIU2400_ICR (BIU_BLOCK+0x0C) +#define BIU2400_ISR (BIU_BLOCK+0x10) + +#define BIU2400_REQINP (BIU_BLOCK+0x1C) /* Request Queue In */ +#define BIU2400_REQOUTP (BIU_BLOCK+0x20) /* Request Queue Out */ +#define BIU2400_RSPINP (BIU_BLOCK+0x24) /* Response Queue In */ +#define BIU2400_RSPOUTP (BIU_BLOCK+0x28) /* Response Queue Out */ +#define BIU2400_PRI_RQINP (BIU_BLOCK+0x2C) /* Priority Request Q In */ +#define BIU2400_PRI_RSPINP (BIU_BLOCK+0x30) /* Priority Request Q Out */ + +#define BIU2400_ATIO_RSPINP (BIU_BLOCK+0x3C) /* ATIO Queue In */ +#define BIU2400_ATIO_REQINP (BIU_BLOCK+0x40) /* ATIO Queue Out */ + +#define BIU2400_R2HSTSLO (BIU_BLOCK+0x44) +#define BIU2400_R2HSTSHI (BIU_BLOCK+0x46) + +#define BIU2400_HCCR (BIU_BLOCK+0x48) +#define BIU2400_GPIOD (BIU_BLOCK+0x4C) +#define BIU2400_GPIOE (BIU_BLOCK+0x50) +#define BIU2400_HSEMA (BIU_BLOCK+0x58) + +/* BIU2400_FLASH_ADDR definitions */ +#define BIU2400_FLASH_DFLAG (1 << 30) + +/* BIU2400_CSR definitions */ +#define BIU2400_NVERR (1 << 18) +#define BIU2400_DMA_ACTIVE (1 << 17) /* RO */ +#define BIU2400_DMA_STOP (1 << 16) +#define BIU2400_FUNCTION (1 << 15) /* RO */ +#define BIU2400_PCIX_MODE(x) (((x) >> 8) & 0xf) /* RO */ +#define BIU2400_CSR_64BIT (1 << 2) /* RO */ +#define BIU2400_FLASH_ENABLE (1 << 1) +#define BIU2400_SOFT_RESET (1 << 0) + +/* BIU2400_ICR definitions */ +#define BIU2400_ICR_ENA_RISC_INT 0x8 +#define BIU2400_IMASK (BIU2400_ICR_ENA_RISC_INT) + +/* BIU2400_ISR definitions */ +#define BIU2400_ISR_RISC_INT 0x8 + +#define BIU2400_R2HST_INTR BIU_R2HST_INTR +#define BIU2400_R2HST_PAUSED BIU_R2HST_PAUSED +#define BIU2400_R2HST_ISTAT_MASK 0x1f +/* interrupt status meanings */ +#define ISP2400R2HST_ROM_MBX_OK 0x1 /* ROM mailbox cmd done ok */ +#define ISP2400R2HST_ROM_MBX_FAIL 0x2 /* ROM mailbox cmd done fail */ +#define ISP2400R2HST_MBX_OK 0x10 /* mailbox cmd done ok */ +#define ISP2400R2HST_MBX_FAIL 0x11 /* mailbox cmd done fail */ +#define ISP2400R2HST_ASYNC_EVENT 0x12 /* Async Event */ +#define ISP2400R2HST_RSPQ_UPDATE 0x13 /* Response Queue Update */ +#define ISP2400R2HST_ATIO_RSPQ_UPDATE 0x1C /* ATIO Response Queue Update */ +#define ISP2400R2HST_ATIO_RQST_UPDATE 0x1D /* ATIO Request Queue Update */ + +/* BIU2400_HCCR definitions */ + +#define HCCR_2400_CMD_NOP 0x00000000 +#define HCCR_2400_CMD_RESET 0x10000000 +#define HCCR_2400_CMD_CLEAR_RESET 0x20000000 +#define HCCR_2400_CMD_PAUSE 0x30000000 +#define HCCR_2400_CMD_RELEASE 0x40000000 +#define HCCR_2400_CMD_SET_HOST_INT 0x50000000 +#define HCCR_2400_CMD_CLEAR_HOST_INT 0x60000000 +#define HCCR_2400_CMD_CLEAR_RISC_INT 0xA0000000 + +#define HCCR_2400_RISC_ERR(x) (((x) >> 12) & 0x7) /* RO */ +#define HCCR_2400_RISC2HOST_INT (1 << 6) /* RO */ +#define HCCR_2400_RISC_RESET (1 << 5) /* RO */ + + +/* * Mailbox Block Register Offsets */ @@ -371,6 +455,12 @@ #define OUTMAILBOX6 (MBOX_BLOCK+0xC) #define OUTMAILBOX7 (MBOX_BLOCK+0xE) +/* + * Strictly speaking, it's + * SCSI && 2100 : 8 MBOX registers + * 2200: 24 MBOX registers + * 2300/2400: 32 MBOX registers + */ #define MBOX_OFF(n) (MBOX_BLOCK + ((n) << 1)) #define NMBOX(isp) \ (((((isp)->isp_type & ISP_HA_SCSI) >= ISP_HA_SCSI_1040A) || \ @@ -427,7 +517,7 @@ #define SXP_FIFO_STATUS (SXP_BLOCK+0x5C) /* RW*: SCSI FIFO Status */ #define SXP_FIFO_TOP (SXP_BLOCK+0x5E) /* RW*: SCSI FIFO Top Resid */ #define SXP_FIFO_BOTTOM (SXP_BLOCK+0x60) /* RW*: SCSI FIFO Bot Resid */ -#define SXP_TRAN_REG (SXP_BLOCK+0x64) /* RW*: SCSI Transfer Reg */ +#define SXP_TRAN_REG (SXP_BLOCK+0x64) /* RW*: SCSI Transferr Reg */ #define SXP_TRAN_CNT_LO (SXP_BLOCK+0x68) /* RW*: SCSI Trans Count */ #define SXP_TRAN_CNT_HI (SXP_BLOCK+0x6A) /* RW*: SCSI Trans Count */ #define SXP_TRAN_CTR_LO (SXP_BLOCK+0x6C) /* RW*: SCSI Trans Counter */ @@ -659,6 +749,7 @@ #define PCI_HCCR_CMD_PARITY_ERR 0xE000 /* Generate parity error */ #define HCCR_CMD_TEST_MODE 0xF000 /* Set Test Mode */ + #define ISP2100_HCCR_PARITY_ENABLE_2 0x0400 #define ISP2100_HCCR_PARITY_ENABLE_1 0x0200 #define ISP2100_HCCR_PARITY_ENABLE_0 0x0100 @@ -675,13 +766,32 @@ #define PCI_HCCR_BIOS 0x0001 /* W : BIOS enable */ /* + * Defines for Interrupts + */ +#define ISP_INTS_ENABLED(isp) \ + ((IS_SCSI(isp))? \ + (ISP_READ(isp, BIU_ICR) & BIU_IMASK) : \ + (IS_24XX(isp)? (ISP_READ(isp, BIU2400_ICR) & BIU2400_IMASK) : \ + (ISP_READ(isp, BIU_ICR) & BIU2100_IMASK))) + +#define ISP_ENABLE_INTS(isp) \ + (IS_SCSI(isp) ? \ + ISP_WRITE(isp, BIU_ICR, BIU_IMASK) : \ + (IS_24XX(isp) ? \ + (ISP_WRITE(isp, BIU2400_ICR, BIU2400_IMASK)) : \ + (ISP_WRITE(isp, BIU_ICR, BIU2100_IMASK)))) + +#define ISP_DISABLE_INTS(isp) \ + IS_24XX(isp)? ISP_WRITE(isp, BIU2400_ICR, 0) : ISP_WRITE(isp, BIU_ICR, 0) + +/* * NVRAM Definitions (PCI cards only) */ #define ISPBSMX(c, byte, shift, mask) \ (((c)[(byte)] >> (shift)) & (mask)) /* - * QLogic 1020/1040 NVRAM is an array of 128 bytes. + * Qlogic 1020/1040 NVRAM is an array of 128 bytes. * * Some portion of the front of this is for general host adapter properties * This is followed by an array of per-target parameters, and is tailed off @@ -723,9 +833,9 @@ #define ISP_NVRAM_FAST_MTTR_ENABLE(c) ISPBSMX(c, 22, 0, 0x01) #define ISP_NVRAM_TARGOFF 28 -#define ISP_NVARM_TARGSIZE 6 +#define ISP_NVRAM_TARGSIZE 6 #define _IxT(tgt, tidx) \ - (ISP_NVRAM_TARGOFF + (ISP_NVARM_TARGSIZE * (tgt)) + (tidx)) + (ISP_NVRAM_TARGOFF + (ISP_NVRAM_TARGSIZE * (tgt)) + (tidx)) #define ISP_NVRAM_TGT_RENEG(c, t) ISPBSMX(c, _IxT(t, 0), 0, 0x01) #define ISP_NVRAM_TGT_QFRZ(c, t) ISPBSMX(c, _IxT(t, 0), 1, 0x01) #define ISP_NVRAM_TGT_ARQ(c, t) ISPBSMX(c, _IxT(t, 0), 2, 0x01) @@ -741,7 +851,7 @@ #define ISP_NVRAM_TGT_LUN_DISABLE(c, t) ISPBSMX(c, _IxT(t, 3), 5, 0x01) /* - * QLogic 1080/1240 NVRAM is an array of 256 bytes. + * Qlogic 1080/1240 NVRAM is an array of 256 bytes. * * Some portion of the front of this is for general host adapter properties * This is followed by an array of per-target parameters, and is tailed off @@ -924,7 +1034,7 @@ ISPBSMX(c, _IxT16(t, 4, (b)), 7, 0x01) /* - * QLogic 2XXX NVRAM is an array of 256 bytes. + * Qlogic 2100 thru 2300 NVRAM is an array of 256 bytes. * * Some portion of the front of this is for general RISC engine parameters, * mostly reflecting the state of the last INITIALIZE FIRMWARE mailbox command. @@ -954,6 +1064,7 @@ (((u_int64_t)(c)[25]) << 0)) #define ISP2100_NVRAM_HARDLOOPID(c) (c)[26] +#define ISP2100_NVRAM_TOV(c) ((c)[29]) #define ISP2200_NVRAM_NODE_NAME(c) (\ (((u_int64_t)(c)[30]) << 56) | \ @@ -966,6 +1077,15 @@ (((u_int64_t)(c)[37]) << 0)) #define ISP2100_NVRAM_HBA_OPTIONS(c) (c)[70] +#define ISP2100_XFW_OPTIONS(c) ((c)[38] | ((c)[39] << 8)) + +#define ISP2100_RACC_TIMER(c) (c)[40] +#define ISP2100_IDELAY_TIMER(c) (c)[41] + +#define ISP2100_ZFW_OPTIONS(c) ((c)[42] | ((c)[43] << 8)) + +#define ISP2100_SERIAL_LINK(c) ((c)[68] | ((c)[69] << 8)) + #define ISP2100_NVRAM_HBA_DISABLE(c) ISPBSMX(c, 70, 0, 0x01) #define ISP2100_NVRAM_BIOS_DISABLE(c) ISPBSMX(c, 70, 1, 0x01) #define ISP2100_NVRAM_LUN_DISABLE(c) ISPBSMX(c, 70, 2, 0x01) @@ -984,10 +1104,56 @@ (((u_int64_t)(c)[79]) << 0)) #define ISP2100_NVRAM_BOOT_LUN(c) (c)[80] +#define ISP2100_RESET_DELAY(c) (c)[81] #define ISP2200_HBA_FEATURES(c) (c)[232] | ((c)[233] << 8) /* + * Qlogic 2400 NVRAM is an array of 512 bytes with a 32 bit checksum. + */ +#define ISP2400_NVRAM_PORT0_ADDR 0x80 +#define ISP2400_NVRAM_PORT1_ADDR 0x180 +#define ISP2400_NVRAM_SIZE 512 + +#define ISP2400_NVRAM_VERSION(c) ((c)[4] | ((c)[5] << 8)) +#define ISP2400_NVRAM_MAXFRAMELENGTH(c) (((c)[12]) | ((c)[13] << 8)) +#define ISP2400_NVRAM_EXECUTION_THROTTLE(c) (((c)[14]) | ((c)[15] << 8)) +#define ISP2400_NVRAM_EXCHANGE_COUNT(c) (((c)[16]) | ((c)[17] << 8)) +#define ISP2400_NVRAM_HARDLOOPID(c) ((c)[18] | ((c)[19] << 8)) + +#define ISP2400_NVRAM_PORT_NAME(c) (\ + (((u_int64_t)(c)[20]) << 56) | \ + (((u_int64_t)(c)[21]) << 48) | \ + (((u_int64_t)(c)[22]) << 40) | \ + (((u_int64_t)(c)[23]) << 32) | \ + (((u_int64_t)(c)[24]) << 24) | \ + (((u_int64_t)(c)[25]) << 16) | \ + (((u_int64_t)(c)[26]) << 8) | \ + (((u_int64_t)(c)[27]) << 0)) + +#define ISP2400_NVRAM_NODE_NAME(c) (\ + (((u_int64_t)(c)[28]) << 56) | \ + (((u_int64_t)(c)[29]) << 48) | \ + (((u_int64_t)(c)[30]) << 40) | \ + (((u_int64_t)(c)[31]) << 32) | \ + (((u_int64_t)(c)[32]) << 24) | \ + (((u_int64_t)(c)[33]) << 16) | \ + (((u_int64_t)(c)[34]) << 8) | \ + (((u_int64_t)(c)[35]) << 0)) + +#define ISP2400_NVRAM_LOGIN_RETRY_CNT(c) ((c)[36] | ((c)[37] << 8)) +#define ISP2400_NVRAM_LINK_DOWN_ON_NOS(c) ((c)[38] | ((c)[39] << 8)) +#define ISP2400_NVRAM_INTERRUPT_DELAY(c) ((c)[40] | ((c)[41] << 8)) +#define ISP2400_NVRAM_LOGIN_TIMEOUT(c) ((c)[42] | ((c)[43] << 8)) + +#define ISP2400_NVRAM_FIRMWARE_OPTIONS1(c) \ + ((c)[44] | ((c)[45] << 8) | ((c)[46] << 16) | ((c)[47] << 24)) +#define ISP2400_NVRAM_FIRMWARE_OPTIONS2(c) \ + ((c)[48] | ((c)[49] << 8) | ((c)[50] << 16) | ((c)[51] << 24)) +#define ISP2400_NVRAM_FIRMWARE_OPTIONS3(c) \ + ((c)[52] | ((c)[53] << 8) | ((c)[54] << 16) | ((c)[55] << 24)) + +/* * Firmware Crash Dump * * QLogic needs specific information format when they look at firmware crashes. |