diff options
-rw-r--r-- | sys/arch/m68k/include/asm_single.h | 14 | ||||
-rw-r--r-- | sys/arch/m68k/include/cacheops_20.h | 16 | ||||
-rw-r--r-- | sys/arch/m68k/include/cacheops_30.h | 16 | ||||
-rw-r--r-- | sys/arch/m68k/include/cacheops_40.h | 40 | ||||
-rw-r--r-- | sys/arch/m68k/include/cacheops_60.h | 40 | ||||
-rw-r--r-- | sys/arch/mac68k/include/pio.h | 14 | ||||
-rw-r--r-- | sys/arch/mvme68k/include/prom.h | 12 | ||||
-rw-r--r-- | sys/arch/mvme88k/include/asm_macro.h | 28 | ||||
-rw-r--r-- | sys/arch/mvme88k/include/cpu_number.h | 2 | ||||
-rw-r--r-- | sys/arch/mvme88k/include/profile.h | 12 | ||||
-rw-r--r-- | sys/arch/mvme88k/include/prom.h | 6 | ||||
-rw-r--r-- | sys/arch/powerpc/include/cpu.h | 10 |
12 files changed, 105 insertions, 105 deletions
diff --git a/sys/arch/m68k/include/asm_single.h b/sys/arch/m68k/include/asm_single.h index 9e6ca71469d..e362f2f933f 100644 --- a/sys/arch/m68k/include/asm_single.h +++ b/sys/arch/m68k/include/asm_single.h @@ -1,4 +1,4 @@ -/* $OpenBSD: asm_single.h,v 1.2 1998/04/25 07:09:06 d Exp $ */ +/* $OpenBSD: asm_single.h,v 1.3 2001/01/15 19:50:37 deraadt Exp $ */ /* $NetBSD: asm_single.h,v 1.1 1996/09/16 06:03:58 leo Exp $ */ /* @@ -42,18 +42,18 @@ */ #define single_inst_bset_b(var, bit) \ - asm volatile ("orb %0,%1" : : "di" ((u_char)bit), "g" (var)) + __asm__ __volatile__ ("orb %0,%1" : : "di" ((u_char)bit), "g" (var)) #define single_inst_bclr_b(var, bit) \ - asm volatile ("andb %0,%1" : : "di" ((u_char)~(bit)), "g" (var)); + __asm__ __volatile__ ("andb %0,%1" : : "di" ((u_char)~(bit)), "g" (var)); #define single_inst_bset_w(var, bit) \ - asm volatile ("orw %0,%1" : : "di" ((u_short)bit), "g" (var)) + __asm__ __volatile__ ("orw %0,%1" : : "di" ((u_short)bit), "g" (var)) #define single_inst_bclr_w(var, bit) \ - asm volatile ("andw %0,%1" : : "di" ((u_short)~(bit)), "g" (var)); + __asm__ __volatile__ ("andw %0,%1" : : "di" ((u_short)~(bit)), "g" (var)); #define single_inst_bset_l(var, bit) \ - asm volatile ("orl %0,%1" : : "di" ((u_long)bit), "g" (var)) + __asm__ __volatile__ ("orl %0,%1" : : "di" ((u_long)bit), "g" (var)) #define single_inst_bclr_l(var, bit) \ - asm volatile ("andl %0,%1" : : "di" ((u_long)~(bit)), "g" (var)); + __asm__ __volatile__ ("andl %0,%1" : : "di" ((u_long)~(bit)), "g" (var)); #endif /* _M68K_ASM_SINGLE_H */ diff --git a/sys/arch/m68k/include/cacheops_20.h b/sys/arch/m68k/include/cacheops_20.h index 5dc67cd4e22..d5156b6085f 100644 --- a/sys/arch/m68k/include/cacheops_20.h +++ b/sys/arch/m68k/include/cacheops_20.h @@ -1,4 +1,4 @@ -/* $OpenBSD: cacheops_20.h,v 1.1 1997/07/06 07:46:23 downsj Exp $ */ +/* $OpenBSD: cacheops_20.h,v 1.2 2001/01/15 19:50:37 deraadt Exp $ */ /* $NetBSD: cacheops_20.h,v 1.1 1997/06/02 20:26:39 leo Exp $ */ /*- @@ -41,7 +41,7 @@ * Invalidate entire TLB. */ void TBIA_20 __P((void)); -extern inline void +extern __inline__ void TBIA_20() { __asm __volatile (" pflusha"); @@ -51,7 +51,7 @@ TBIA_20() * Invalidate any TLB entry for given VA (TB Invalidate Single) */ void TBIS_20 __P((void *)); -extern inline void +extern __inline__ void TBIS_20(va) void *va; { @@ -63,7 +63,7 @@ TBIS_20(va) * Invalidate supervisor side of TLB */ void TBIAS_20 __P((void)); -extern inline void +extern __inline__ void TBIAS_20() { __asm __volatile (" pflushs #4,#4"); @@ -73,7 +73,7 @@ TBIAS_20() * Invalidate user side of TLB */ void TBIAU_20 __P((void)); -extern inline void +extern __inline__ void TBIAU_20() { __asm __volatile (" pflushs #0,#4;"); @@ -83,14 +83,14 @@ TBIAU_20() * Invalidate instruction cache */ void ICIA_20 __P((void)); -extern inline void +extern __inline__ void ICIA_20() { __asm __volatile (" movc %0,cacr;" : : "d" (IC_CLEAR)); } void ICPA_20 __P((void)); -extern inline void +extern __inline__ void ICPA_20() { __asm __volatile (" movc %0,cacr;" : : "d" (IC_CLEAR)); @@ -109,7 +109,7 @@ ICPA_20() #define DCIAS_20() void PCIA_20 __P((void)); -extern inline void +extern __inline__ void PCIA_20() { __asm __volatile (" movc %0,cacr;" : : "d" (DC_CLEAR)); diff --git a/sys/arch/m68k/include/cacheops_30.h b/sys/arch/m68k/include/cacheops_30.h index 6a9f782361d..f03af6255f3 100644 --- a/sys/arch/m68k/include/cacheops_30.h +++ b/sys/arch/m68k/include/cacheops_30.h @@ -1,4 +1,4 @@ -/* $OpenBSD: cacheops_30.h,v 1.1 1997/07/06 07:46:24 downsj Exp $ */ +/* $OpenBSD: cacheops_30.h,v 1.2 2001/01/15 19:50:37 deraadt Exp $ */ /* $NetBSD: cacheops_30.h,v 1.1 1997/06/02 20:26:40 leo Exp $ */ /*- @@ -41,7 +41,7 @@ * Invalidate entire TLB. */ void TBIA_30 __P((void)); -extern inline void +extern __inline__ void TBIA_30() { int tmp = DC_CLEAR; @@ -54,7 +54,7 @@ TBIA_30() * Invalidate any TLB entry for given VA (TB Invalidate Single) */ void TBIS_30 __P((vm_offset_t)); -extern inline void +extern __inline__ void TBIS_30(va) vm_offset_t va; { @@ -66,7 +66,7 @@ TBIS_30(va) * Invalidate supervisor side of TLB */ void TBIAS_30 __P((void)); -extern inline void +extern __inline__ void TBIAS_30() { __asm __volatile (" pflush #4,#4;" @@ -77,7 +77,7 @@ TBIAS_30() * Invalidate user side of TLB */ void TBIAU_30 __P((void)); -extern inline void +extern __inline__ void TBIAU_30() { __asm __volatile (" pflush #0,#4;" @@ -88,14 +88,14 @@ TBIAU_30() * Invalidate instruction cache */ void ICIA_30 __P((void)); -extern inline void +extern __inline__ void ICIA_30() { __asm __volatile (" movc %0,cacr;" : : "d" (IC_CLEAR)); } void ICPA_30 __P((void)); -extern inline void +extern __inline__ void ICPA_30() { __asm __volatile (" movc %0,cacr;" : : "d" (IC_CLEAR)); @@ -115,7 +115,7 @@ ICPA_30() void PCIA_30 __P((void)); -extern inline void +extern __inline__ void PCIA_30() { __asm __volatile (" movc %0,cacr;" : : "d" (DC_CLEAR)); diff --git a/sys/arch/m68k/include/cacheops_40.h b/sys/arch/m68k/include/cacheops_40.h index 845c9550161..3dd35b447fe 100644 --- a/sys/arch/m68k/include/cacheops_40.h +++ b/sys/arch/m68k/include/cacheops_40.h @@ -1,4 +1,4 @@ -/* $OpenBSD: cacheops_40.h,v 1.1 1997/07/06 07:46:24 downsj Exp $ */ +/* $OpenBSD: cacheops_40.h,v 1.2 2001/01/15 19:50:37 deraadt Exp $ */ /* $NetBSD: cacheops_40.h,v 1.1 1997/06/02 20:26:41 leo Exp $ */ /*- @@ -41,7 +41,7 @@ * Invalidate entire TLB. */ void TBIA_40 __P((void)); -extern inline void +extern __inline__ void TBIA_40() { __asm __volatile (" .word 0xf518" ); /* pflusha */ @@ -51,7 +51,7 @@ TBIA_40() * Invalidate any TLB entry for given VA (TB Invalidate Single) */ void TBIS_40 __P((vm_offset_t)); -extern inline void +extern __inline__ void TBIS_40(va) vm_offset_t va; { @@ -70,7 +70,7 @@ TBIS_40(va) * Invalidate supervisor side of TLB */ void TBIAS_40 __P((void)); -extern inline void +extern __inline__ void TBIAS_40() { /* @@ -83,7 +83,7 @@ TBIAS_40() * Invalidate user side of TLB */ void TBIAU_40 __P((void)); -extern inline void +extern __inline__ void TBIAU_40() { /* @@ -96,14 +96,14 @@ TBIAU_40() * Invalidate instruction cache */ void ICIA_40 __P((void)); -extern inline void +extern __inline__ void ICIA_40() { __asm __volatile (" .word 0xf498;"); /* cinva ic */ } void ICPA_40 __P((void)); -extern inline void +extern __inline__ void ICPA_40() { __asm __volatile (" .word 0xf498;"); /* cinva ic */ @@ -113,28 +113,28 @@ ICPA_40() * Invalidate data cache. */ void DCIA_40 __P((void)); -extern inline void +extern __inline__ void DCIA_40() { __asm __volatile (" .word 0xf478;"); /* cpusha dc */ } void DCIS_40 __P((void)); -extern inline void +extern __inline__ void DCIS_40() { __asm __volatile (" .word 0xf478;"); /* cpusha dc */ } void DCIU_40 __P((void)); -extern inline void +extern __inline__ void DCIU_40() { __asm __volatile (" .word 0xf478;"); /* cpusha dc */ } void DCIAS_40 __P((vm_offset_t)); -extern inline void +extern __inline__ void DCIAS_40(va) vm_offset_t va; { @@ -144,14 +144,14 @@ DCIAS_40(va) } void PCIA_40 __P((void)); -extern inline void +extern __inline__ void PCIA_40() { __asm __volatile (" .word 0xf478;"); /* cpusha dc */ } void DCFA_40 __P((void)); -extern inline void +extern __inline__ void DCFA_40() { __asm __volatile (" .word 0xf478;"); /* cpusha dc */ @@ -159,7 +159,7 @@ DCFA_40() /* invalidate instruction physical cache line */ void ICPL_40 __P((vm_offset_t)); -extern inline void +extern __inline__ void ICPL_40(va) vm_offset_t va; { @@ -170,7 +170,7 @@ ICPL_40(va) /* invalidate instruction physical cache page */ void ICPP_40 __P((vm_offset_t)); -extern inline void +extern __inline__ void ICPP_40(va) vm_offset_t va; { @@ -181,7 +181,7 @@ ICPP_40(va) /* invalidate data physical cache line */ void DCPL_40 __P((vm_offset_t)); -extern inline void +extern __inline__ void DCPL_40(va) vm_offset_t va; { @@ -192,7 +192,7 @@ DCPL_40(va) /* invalidate data physical cache page */ void DCPP_40 __P((vm_offset_t)); -extern inline void +extern __inline__ void DCPP_40(va) vm_offset_t va; { @@ -203,7 +203,7 @@ DCPP_40(va) /* invalidate data physical all */ void DCPA_40 __P((void)); -extern inline void +extern __inline__ void DCPA_40() { __asm __volatile (" .word 0xf458;"); /* cinva dc */ @@ -211,7 +211,7 @@ DCPA_40() /* data cache flush line */ void DCFL_40 __P((vm_offset_t)); -extern inline void +extern __inline__ void DCFL_40(va) vm_offset_t va; { @@ -222,7 +222,7 @@ DCFL_40(va) /* data cache flush page */ void DCFP_40 __P((vm_offset_t)); -extern inline void +extern __inline__ void DCFP_40(va) vm_offset_t va; { diff --git a/sys/arch/m68k/include/cacheops_60.h b/sys/arch/m68k/include/cacheops_60.h index 1c7f8c5983f..6b1c846cab4 100644 --- a/sys/arch/m68k/include/cacheops_60.h +++ b/sys/arch/m68k/include/cacheops_60.h @@ -1,4 +1,4 @@ -/* $OpenBSD: cacheops_60.h,v 1.1 1997/07/06 07:46:25 downsj Exp $ */ +/* $OpenBSD: cacheops_60.h,v 1.2 2001/01/15 19:50:38 deraadt Exp $ */ /* $NetBSD: cacheops_60.h,v 1.1 1997/06/02 20:26:43 leo Exp $ */ /*- @@ -41,7 +41,7 @@ * Invalidate entire TLB. */ void TBIA_60 __P((void)); -extern inline void +extern __inline__ void TBIA_60() { __asm __volatile (" .word 0xf518" ); /* pflusha */ @@ -51,7 +51,7 @@ TBIA_60() * Invalidate any TLB entry for given VA (TB Invalidate Single) */ void TBIS_60 __P((vm_offset_t)); -extern inline void +extern __inline__ void TBIS_60(va) vm_offset_t va; { @@ -74,7 +74,7 @@ TBIS_60(va) * Invalidate supervisor side of TLB */ void TBIAS_60 __P((void)); -extern inline void +extern __inline__ void TBIAS_60() { int tmp; @@ -92,7 +92,7 @@ TBIAS_60() * Invalidate user side of TLB */ void TBIAU_60 __P((void)); -extern inline void +extern __inline__ void TBIAU_60() { int tmp; @@ -110,7 +110,7 @@ TBIAU_60() * Invalidate instruction cache */ void ICIA_60 __P((void)); -extern inline void +extern __inline__ void ICIA_60() { /* inva ic (also clears branch cache) */ @@ -118,7 +118,7 @@ ICIA_60() } void ICPA_60 __P((void)); -extern inline void +extern __inline__ void ICPA_60() { /* inva ic (also clears branch cache) */ @@ -129,28 +129,28 @@ ICPA_60() * Invalidate data cache. */ void DCIA_60 __P((void)); -extern inline void +extern __inline__ void DCIA_60() { __asm __volatile (" .word 0xf478;"); /* cpusha dc */ } void DCIS_60 __P((void)); -extern inline void +extern __inline__ void DCIS_60() { __asm __volatile (" .word 0xf478;"); /* cpusha dc */ } void DCIU_60 __P((void)); -extern inline void +extern __inline__ void DCIU_60() { __asm __volatile (" .word 0xf478;"); /* cpusha dc */ } void DCIAS_60 __P((vm_offset_t)); -extern inline void +extern __inline__ void DCIAS_60(va) vm_offset_t va; { @@ -160,14 +160,14 @@ DCIAS_60(va) } void PCIA_60 __P((void)); -extern inline void +extern __inline__ void PCIA_60() { __asm __volatile (" .word 0xf478;"); /* cpusha dc */ } void DCFA_60 __P((void)); -extern inline void +extern __inline__ void DCFA_60() { __asm __volatile (" .word 0xf478;"); /* cpusha dc */ @@ -175,7 +175,7 @@ DCFA_60() /* invalidate instruction physical cache line */ void ICPL_60 __P((vm_offset_t)); -extern inline void +extern __inline__ void ICPL_60(va) vm_offset_t va; { @@ -186,7 +186,7 @@ ICPL_60(va) /* invalidate instruction physical cache page */ void ICPP_60 __P((vm_offset_t)); -extern inline void +extern __inline__ void ICPP_60(va) vm_offset_t va; { @@ -197,7 +197,7 @@ ICPP_60(va) /* invalidate data physical cache line */ void DCPL_60 __P((vm_offset_t)); -extern inline void +extern __inline__ void DCPL_60(va) vm_offset_t va; { @@ -208,7 +208,7 @@ DCPL_60(va) /* invalidate data physical cache page */ void DCPP_60 __P((vm_offset_t)); -extern inline void +extern __inline__ void DCPP_60(va) vm_offset_t va; { @@ -219,7 +219,7 @@ DCPP_60(va) /* invalidate data physical all */ void DCPA_60 __P((void)); -extern inline void +extern __inline__ void DCPA_60() { __asm __volatile (" .word 0xf458;"); /* cinva dc */ @@ -227,7 +227,7 @@ DCPA_60() /* data cache flush line */ void DCFL_60 __P((vm_offset_t)); -extern inline void +extern __inline__ void DCFL_60(va) vm_offset_t va; { @@ -238,7 +238,7 @@ DCFL_60(va) /* data cache flush page */ void DCFP_60 __P((vm_offset_t)); -extern inline void +extern __inline__ void DCFP_60(va) vm_offset_t va; { diff --git a/sys/arch/mac68k/include/pio.h b/sys/arch/mac68k/include/pio.h index 88fef151f5f..afca5eabe2e 100644 --- a/sys/arch/mac68k/include/pio.h +++ b/sys/arch/mac68k/include/pio.h @@ -1,4 +1,4 @@ -/* $OpenBSD: pio.h,v 1.3 1997/11/30 06:10:32 gene Exp $ */ +/* $OpenBSD: pio.h,v 1.4 2001/01/15 19:50:38 deraadt Exp $ */ /* $NetBSD: pio.h,v 1.3 1994/10/26 08:46:38 cgd Exp $ */ /* @@ -13,29 +13,29 @@ #define inl(y) \ ({ unsigned long _tmp__; \ - asm volatile("inl %1, %0" : "=a" (_tmp__) : "d" ((unsigned short)(y))); \ + __asm__ __volatile__("inl %1, %0" : "=a" (_tmp__) : "d" ((unsigned short)(y))); \ _tmp__; }) #define inw(y) \ ({ unsigned short _tmp__; \ - asm volatile(".byte 0x66; inl %1, %0" : "=a" (_tmp__) : "d" ((unsigned short)(y))); \ + __asm__ __volatile__(".byte 0x66; inl %1, %0" : "=a" (_tmp__) : "d" ((unsigned short)(y))); \ _tmp__; }) #define inb(y) \ ({ unsigned char _tmp__; \ - asm volatile("inb %1, %0" : "=a" (_tmp__) : "d" ((unsigned short)(y))); \ + __asm__ __volatile__("inb %1, %0" : "=a" (_tmp__) : "d" ((unsigned short)(y))); \ _tmp__; }) #define outl(x, y) \ -{ asm volatile("outl %0, %1" : : "a" (y) , "d" ((unsigned short)(x))); } +{ __asm__ __volatile__("outl %0, %1" : : "a" (y) , "d" ((unsigned short)(x))); } #define outw(x, y) \ -{asm volatile(".byte 0x66; outl %0, %1" : : "a" ((unsigned short)(y)) , "d" ((unsigned short)(x))); } +{__asm__ __volatile__(".byte 0x66; outl %0, %1" : : "a" ((unsigned short)(y)) , "d" ((unsigned short)(x))); } #define outb(x, y) \ -{ asm volatile("outb %0, %1" : : "a" ((unsigned char)(y)) , "d" ((unsigned short)(x))); } +{ __asm__ __volatile__("outb %0, %1" : : "a" ((unsigned char)(y)) , "d" ((unsigned short)(x))); } #endif /* _MAC68K_PIO_H_ */ diff --git a/sys/arch/mvme68k/include/prom.h b/sys/arch/mvme68k/include/prom.h index 6cf9350822d..3ab91c3511e 100644 --- a/sys/arch/mvme68k/include/prom.h +++ b/sys/arch/mvme68k/include/prom.h @@ -1,4 +1,4 @@ -/* $OpenBSD: prom.h,v 1.7 1996/05/19 20:05:11 chuck Exp $ */ +/* $OpenBSD: prom.h,v 1.8 2001/01/15 19:50:38 deraadt Exp $ */ /* * Copyright (c) 1995 Theo de Raadt @@ -156,15 +156,15 @@ struct mvmeprom_args { #endif #define MVMEPROM_CALL(x) \ - asm volatile (__CONCAT("trap #15; .short ", __STRING(x)) ) + __asm__ __volatile__ (__CONCAT("trap #15; .short ", __STRING(x)) ) #define MVMEPROM_NOARG() \ - asm volatile ("clrl sp@-") + __asm__ __volatile__ ("clrl sp@-") #define MVMEPROM_ARG1(arg) \ - asm volatile ("movel %0, sp@-"::"d" (arg)) + __asm__ __volatile__ ("movel %0, sp@-"::"d" (arg)) #define MVMEPROM_ARG2(arg) \ - asm volatile ("movel %0, sp@-"::"d" (arg)) + __asm__ __volatile__ ("movel %0, sp@-"::"d" (arg)) #define MVMEPROM_GETRES(ret) \ - asm volatile ("movel sp@+,%0": "=d" (ret):) + __asm__ __volatile__ ("movel sp@+,%0": "=d" (ret):) #define MVMEPROM_RETURN(ret) \ MVMEPROM_GETRES(ret); \ return (ret); /* return a value (int) */ diff --git a/sys/arch/mvme88k/include/asm_macro.h b/sys/arch/mvme88k/include/asm_macro.h index 522db6e0e85..c437fb7a0cf 100644 --- a/sys/arch/mvme88k/include/asm_macro.h +++ b/sys/arch/mvme88k/include/asm_macro.h @@ -1,4 +1,4 @@ -/* $OpenBSD: asm_macro.h,v 1.7 2001/01/14 20:25:23 smurph Exp $ */ +/* $OpenBSD: asm_macro.h,v 1.8 2001/01/15 19:50:38 deraadt Exp $ */ /* * Mach Operating System * Copyright (c) 1993-1991 Carnegie Mellon University @@ -57,13 +57,13 @@ typedef unsigned long m88k_psr_type; * . * . */ -static inline m88k_psr_type disable_interrupts_return_psr(void) +static __inline__ m88k_psr_type disable_interrupts_return_psr(void) { m88k_psr_type temp, oldpsr; - asm volatile ("ldcr %0, cr1" : "=r" (oldpsr)); - asm volatile ("set %1, %0, 1<1>" : "=r" (oldpsr), "=r" (temp)); - asm volatile ("stcr %0, cr1" : "=r" (temp)); - asm volatile ("tcnd ne0, r0, 0"); + __asm__ __volatile__ ("ldcr %0, cr1" : "=r" (oldpsr)); + __asm__ __volatile__ ("set %1, %0, 1<1>" : "=r" (oldpsr), "=r" (temp)); + __asm__ __volatile__ ("stcr %0, cr1" : "=r" (temp)); + __asm__ __volatile__ ("tcnd ne0, r0, 0"); return oldpsr; } #define disable_interrupt() (void)disable_interrupts_return_psr() @@ -71,20 +71,20 @@ static inline m88k_psr_type disable_interrupts_return_psr(void) /* * Sets the PSR. See comments above. */ -static inline void set_psr(m88k_psr_type psr) +static __inline__ void set_psr(m88k_psr_type psr) { - asm volatile ("stcr %0, cr1" :: "r" (psr)); + __asm__ __volatile__ ("stcr %0, cr1" :: "r" (psr)); } /* * Enables interrupts. */ -static inline m88k_psr_type enable_interrupts_return_psr(void) +static __inline__ m88k_psr_type enable_interrupts_return_psr(void) { m88k_psr_type temp, oldpsr; /* need a temporary register */ - asm volatile ("ldcr %0, cr1" : "=r" (oldpsr)); - asm volatile ("clr %1, %0, 1<1>" : "=r" (oldpsr), "=r" (temp)); - asm volatile ("stcr %0, cr1" : "=r" (temp)); + __asm__ __volatile__ ("ldcr %0, cr1" : "=r" (oldpsr)); + __asm__ __volatile__ ("clr %1, %0, 1<1>" : "=r" (oldpsr), "=r" (temp)); + __asm__ __volatile__ ("stcr %0, cr1" : "=r" (temp)); return oldpsr; } #define enable_interrupt() (void)enable_interrupts_return_psr() @@ -95,9 +95,9 @@ static inline m88k_psr_type enable_interrupts_return_psr(void) /* * flushes the data pipeline. */ -static inline void flush_pipeline() +static __inline__ void flush_pipeline() { - asm volatile ("tcnd ne0, r0, 0"); + __asm__ __volatile__ ("tcnd ne0, r0, 0"); } #define db_flush_pipeline flush_pipeline diff --git a/sys/arch/mvme88k/include/cpu_number.h b/sys/arch/mvme88k/include/cpu_number.h index b72b79ca210..f6319e19143 100644 --- a/sys/arch/mvme88k/include/cpu_number.h +++ b/sys/arch/mvme88k/include/cpu_number.h @@ -39,7 +39,7 @@ static __inline__ unsigned cpu_number(void) register unsigned cpu; extern int cputyp; if (cputyp != CPU_188 || number_cpus == 1) return 0; - asm("ldcr %0, cr18" : "=r" (cpu)); + __asm__ ("ldcr %0, cr18" : "=r" (cpu)); return (cpu & 3); } #endif /* ASSEMBLER */ diff --git a/sys/arch/mvme88k/include/profile.h b/sys/arch/mvme88k/include/profile.h index afc807b45cd..94a500c08fc 100644 --- a/sys/arch/mvme88k/include/profile.h +++ b/sys/arch/mvme88k/include/profile.h @@ -1,4 +1,4 @@ -/* $OpenBSD: profile.h,v 1.8 2001/01/14 20:25:24 smurph Exp $ */ +/* $OpenBSD: profile.h,v 1.9 2001/01/15 19:50:38 deraadt Exp $ */ /* * Copyright (c) 1996 Nivas Madhur * Copyright (c) 1992, 1993 @@ -33,14 +33,14 @@ * SUCH DAMAGE. * * from: @(#)profile.h 8.1 (Berkeley) 6/11/93 - * $Id: profile.h,v 1.8 2001/01/14 20:25:24 smurph Exp $ + * $Id: profile.h,v 1.9 2001/01/15 19:50:38 deraadt Exp $ */ #ifndef __MACHINE_PROFILE_H__ #define __MACHINE_PROFILE_H__ #define _MCOUNT_DECL static inline void _mcount #define MCOUNT \ -extern void mcount() asm("mcount"); \ +extern void mcount() __asm__ ("mcount"); \ void \ mcount() \ { \ @@ -52,7 +52,7 @@ mcount() \ * \ * selfret = ret pushed by mcount call \ */ \ - asm volatile("or %0,r1,0" : "=r" (selfret)); \ + __asm__ __volatile__ ("or %0,r1,0" : "=r" (selfret)); \ /* \ * callerret = ret pushed by call into self. \ */ \ @@ -60,8 +60,8 @@ mcount() \ * This may not be right. It all depends on where the \ * caller stores the return address. XXX \ */ \ - asm volatile("addu r10,r31,48"); \ - asm volatile("ld %0,r10,36" : "=r" (callerret)); \ + __asm__ __volatile__("addu r10,r31,48"); \ + __asm__ __volatile__("ld %0,r10,36" : "=r" (callerret)); \ _mcount(callerret, selfret); \ } diff --git a/sys/arch/mvme88k/include/prom.h b/sys/arch/mvme88k/include/prom.h index c8a8a13eac8..2fd9b7a3ec0 100644 --- a/sys/arch/mvme88k/include/prom.h +++ b/sys/arch/mvme88k/include/prom.h @@ -1,4 +1,4 @@ -/* $OpenBSD: prom.h,v 1.5 2001/01/14 20:25:24 smurph Exp $ */ +/* $OpenBSD: prom.h,v 1.6 2001/01/15 19:50:38 deraadt Exp $ */ /* * Copyright (c) 1998 Steve Murphree, Jr. * Copyright (c) 1996 Nivas Madhur @@ -160,8 +160,8 @@ struct mvmeprom_args { #endif #define MVMEPROM_CALL(x) \ - asm volatile ( __CONCAT("or r9,r0,",__STRING(x)) ); \ - asm volatile ("tb0 0,r0,496"); + __asm__ __volatile__ ( __CONCAT("or r9,r0,",__STRING(x)) ); \ + __asm__ __volatile__ ("tb0 0,r0,496"); #define MVMEPROM_REG_DEVLUN "r2" #define MVMEPROM_REG_CTRLLUN "r3" diff --git a/sys/arch/powerpc/include/cpu.h b/sys/arch/powerpc/include/cpu.h index 964844e92ee..7a4c581a067 100644 --- a/sys/arch/powerpc/include/cpu.h +++ b/sys/arch/powerpc/include/cpu.h @@ -1,4 +1,4 @@ -/* $OpenBSD: cpu.h,v 1.3 1997/10/13 10:53:42 pefo Exp $ */ +/* $OpenBSD: cpu.h,v 1.4 2001/01/15 19:50:39 deraadt Exp $ */ /* $NetBSD: cpu.h,v 1.1 1996/09/30 16:34:21 ws Exp $ */ /* @@ -67,15 +67,15 @@ syncicache(from, len) void *p = from; do { - asm volatile ("dcbst 0,%0" :: "r"(p)); + __asm__ __volatile__ ("dcbst 0,%0" :: "r"(p)); p += CACHELINESIZE; } while ((l -= CACHELINESIZE) > 0); - asm volatile ("sync"); + __asm__ __volatile__ ("sync"); do { - asm volatile ("icbi 0,%0" :: "r"(from)); + __asm__ __volatile__ ("icbi 0,%0" :: "r"(from)); from += CACHELINESIZE; } while ((len -= CACHELINESIZE) > 0); - asm volatile ("isync"); + __asm__ __volatile__ ("isync"); } extern char *bootpath; |