diff options
| -rw-r--r-- | sys/arch/i386/i386/pctr.c | 4 | ||||
| -rw-r--r-- | sys/arch/i386/include/pctr.h | 64 | ||||
| -rw-r--r-- | usr.bin/pctr/pctr.c | 10 |
3 files changed, 38 insertions, 40 deletions
diff --git a/sys/arch/i386/i386/pctr.c b/sys/arch/i386/i386/pctr.c index 2acad08b332..a31a53e22e2 100644 --- a/sys/arch/i386/i386/pctr.c +++ b/sys/arch/i386/i386/pctr.c @@ -1,4 +1,4 @@ -/* $OpenBSD: pctr.c,v 1.5 1996/08/14 22:03:15 dm Exp $ */ +/* $OpenBSD: pctr.c,v 1.6 1996/08/16 00:02:36 dm Exp $ */ /* * Pentium performance counter driver for OpenBSD. @@ -182,7 +182,7 @@ pctrioctl (dev_t dev, int cmd, caddr_t data, int fflag, struct proc *p) return p6ctrsel (fflag, cmd, *(u_int *) data); if (usep5ctr) return p5ctrsel (fflag, cmd, *(u_int *) data); - return EINVAL; + return ENODEV; default: return EINVAL; } diff --git a/sys/arch/i386/include/pctr.h b/sys/arch/i386/include/pctr.h index d86d4db116d..e3afcece07f 100644 --- a/sys/arch/i386/include/pctr.h +++ b/sys/arch/i386/include/pctr.h @@ -1,4 +1,4 @@ -/* $OpenBSD: pctr.h,v 1.3 1996/08/14 22:03:16 dm Exp $ */ +/* $OpenBSD: pctr.h,v 1.4 1996/08/16 00:02:36 dm Exp $ */ /* * Pentium performance counter driver for OpenBSD. @@ -10,38 +10,40 @@ * intact). */ -#ifndef _I386_PERFCNT_H_ -#define _I386_PERFCNT_H_ +#ifndef _I386_PCTR_H_ +#define _I386_PCTR_H_ typedef u_quad_t pctrval; #define PCTR_NUM 2 struct pctrst { - u_int pctr_fn[PCTR_NUM]; - pctrval pctr_tsc; - pctrval pctr_hwc[PCTR_NUM]; - pctrval pctr_idl; + u_int pctr_fn[PCTR_NUM]; /* Current settings of hardware counters */ + pctrval pctr_tsc; /* Free-running 64-bit cycle counter */ + pctrval pctr_hwc[PCTR_NUM]; /* Values of the hardware counters */ + pctrval pctr_idl; /* Iterations of the idle loop */ }; /* Bit values in fn fields and PIOCS ioctl's */ -#define P5CTR_K 0x40 /* Monitor kernel-level events */ -#define P5CTR_U 0x80 /* Monitor user-level events */ -#define P5CTR_C 0x100 /* count cycles rather than events */ +#define P5CTR_K 0x40 /* Monitor kernel-level events */ +#define P5CTR_U 0x80 /* Monitor user-level events */ +#define P5CTR_C 0x100 /* count cycles rather than events */ -#define P6CTR_U 0x010000 /* Monitor user-level events */ -#define P6CTR_K 0x020000 /* Monitor kernel-level events */ -#define P6CTR_E 0x040000 /* Edge detect */ -#define P6CTR_EN 0x400000 /* Enable counters (counter 0 only) */ -#define P6CTR_I 0x800000 /* Invert counter mask */ +#define P6CTR_U 0x010000 /* Monitor user-level events */ +#define P6CTR_K 0x020000 /* Monitor kernel-level events */ +#define P6CTR_E 0x040000 /* Edge detect */ +#define P6CTR_EN 0x400000 /* Enable counters (counter 0 only) */ +#define P6CTR_I 0x800000 /* Invert counter mask */ /* Unit Mask bits */ -#define P6CTR_UM_M 0x0800 /* Modified cache lines */ -#define P6CTR_UM_E 0x0400 /* Exclusive cache lines */ -#define P6CTR_UM_S 0x0200 /* Shared cache lines */ -#define P6CTR_UM_I 0x0100 /* Invalid cache lines */ +#define P6CTR_UM_M 0x0800 /* Modified cache lines */ +#define P6CTR_UM_E 0x0400 /* Exclusive cache lines */ +#define P6CTR_UM_S 0x0200 /* Shared cache lines */ +#define P6CTR_UM_I 0x0100 /* Invalid cache lines */ #define P6CTR_UM_MESI (P6CTR_UM_M|P6CTR_UM_E|P6CTR_UM_S|P6CTR_UM_I) -#define P6CTR_UM_A 0x2000 /* Any initiator (as opposed to self) */ +#define P6CTR_UM_A 0x2000 /* Any initiator (as opposed to self) */ + +#define P6CTR_CM_SHIFT 24 /* Left shift for counter mask */ /* ioctl to set which counter a device tracks. */ #define PCIOCRD _IOR('c', 1, struct pctrst) /* Read counter value */ @@ -103,17 +105,17 @@ struct pctrst { #ifdef _KERNEL -#define CR4_TSD 0x040 /* Time stamp disable */ -#define CR4_PCE 0x100 /* Performance counter enable */ +#define CR4_TSD 0x040 /* Time stamp disable */ +#define CR4_PCE 0x100 /* Performance counter enable */ -#define MSR_TSC 0x10 /* MSR for TSC */ -#define P5MSR_CTRSEL 0x11 /* MSR for selecting both counters on P5 */ -#define P5MSR_CTR0 0x12 /* Value of Ctr0 on P5 */ -#define P5MSR_CTR1 0x13 /* Value of Ctr1 on P5 */ -#define P6MSR_CTRSEL0 0x186 /* MSR for programming CTR0 on P6 */ -#define P6MSR_CTRSEL1 0x187 /* MSR for programming CTR0 on P6 */ -#define P6MSR_CTR0 0xc1 /* Ctr0 on P6 */ -#define P6MSR_CTR1 0xc2 /* Ctr1 on P6 */ +#define MSR_TSC 0x10 /* MSR for TSC */ +#define P5MSR_CTRSEL 0x11 /* MSR for selecting both counters on P5 */ +#define P5MSR_CTR0 0x12 /* Value of Ctr0 on P5 */ +#define P5MSR_CTR1 0x13 /* Value of Ctr1 on P5 */ +#define P6MSR_CTRSEL0 0x186 /* MSR for programming CTR0 on P6 */ +#define P6MSR_CTRSEL1 0x187 /* MSR for programming CTR0 on P6 */ +#define P6MSR_CTR0 0xc1 /* Ctr0 on P6 */ +#define P6MSR_CTR1 0xc2 /* Ctr1 on P6 */ #define rdmsr(msr) \ ({ \ @@ -126,4 +128,4 @@ struct pctrst { __asm __volatile (".byte 0xf, 0x30" :: "A" ((u_quad_t) (v)), "c" (msr)); #endif /* _KERNEL */ -#endif /* ! _I386_PERFCNT_H_ */ +#endif /* ! _I386_PCTR_H_ */ diff --git a/usr.bin/pctr/pctr.c b/usr.bin/pctr/pctr.c index f34b4f1e8f4..874395c7011 100644 --- a/usr.bin/pctr/pctr.c +++ b/usr.bin/pctr/pctr.c @@ -1,4 +1,4 @@ -/* $OpenBSD: pctr.c,v 1.1 1996/08/14 22:31:48 dm Exp $ */ +/* $OpenBSD: pctr.c,v 1.2 1996/08/16 00:02:35 dm Exp $ */ /* * Pentium performance counter control program for OpenBSD. @@ -82,7 +82,7 @@ struct ctrfn p6fn[] = { "Number of store buffer blocks."}, {0x04, 0, "SB_DRAINS", "Number of store buffer drain cycles."}, - {0x04, 0, "MISALIGN_MEM_REF", + {0x05, 0, "MISALIGN_MEM_REF", "Number of misaligned data memory references."}, {0x06, 0, "SEGMENT_REG_LOADS", "Number of segment register loads."}, @@ -127,7 +127,7 @@ struct ctrfn p6fn[] = { "Number of M state lines allocated in the DCU."}, {0x47, 0, "DCU_M_LINES_OUT", "Number of M state lines evicted from the DCU. " - "This includes evictions via snoop HITM, interfention or replacement"}, + "This includes evictions via snoop HITM, intervention or replacement"}, {0x48, 0, "DCU_MISS_OUTSTANDING", "Weighted number of cycles while a DCU miss is outstanding."}, {0x60, 0, "BUS_REQ_OUTSTANDING", @@ -364,10 +364,6 @@ readst (void) } close (fd); - if (cpufamily == 6) { - st.pctr_hwc[0] = rdpmc (0); - st.pctr_hwc[1] = rdpmc (1); - } for (i = 0; i < PCTR_NUM; i++) printf (" ctr%d = %16qd [%s]\n", i, st.pctr_hwc[i], fn2str (cpufamily, st.pctr_fn[i])); |