diff options
| -rw-r--r-- | sys/arch/sparc/dev/spif.c | 63 | ||||
| -rw-r--r-- | sys/arch/sparc/dev/spifreg.h | 308 | ||||
| -rw-r--r-- | sys/arch/sparc/dev/spifvar.h | 12 |
3 files changed, 231 insertions, 152 deletions
diff --git a/sys/arch/sparc/dev/spif.c b/sys/arch/sparc/dev/spif.c index 627b4920d79..274eab72103 100644 --- a/sys/arch/sparc/dev/spif.c +++ b/sys/arch/sparc/dev/spif.c @@ -1,4 +1,4 @@ -/* $OpenBSD: spif.c,v 1.2 1999/02/01 13:45:22 jason Exp $ */ +/* $OpenBSD: spif.c,v 1.3 1999/02/04 15:43:21 jason Exp $ */ /* * Copyright (c) 1999 Jason L. Wright (jason@thought.net) @@ -91,8 +91,8 @@ int spifsoftintr __P((void *)); int stty_param __P((struct tty *, struct termios *)); struct tty *sttytty __P((dev_t)); int stty_modem_control __P((struct stty_port *, int, int)); -static __inline void spif_write_ccr __P((struct stcregs *, u_int8_t)); -int spif_compute_baud __P((speed_t, int, u_int8_t *, u_int8_t *)); +static __inline void stty_write_ccr __P((struct stcregs *, u_int8_t)); +int stty_compute_baud __P((speed_t, int, u_int8_t *, u_int8_t *)); void stty_start __P((struct tty *)); int sbppmatch __P((struct device *, void *, void *)); @@ -190,7 +190,8 @@ spifattach(parent, self, aux) sc->sc_rev2 = sc->sc_regs->stc.gfrcr; sc->sc_regs->stc.gsvr = 0; - spif_write_ccr(&sc->sc_regs->stc, CD180_CCR_RESET | CD180_CCR_RESETALL); + stty_write_ccr(&sc->sc_regs->stc, + CD180_CCR_CMD_RESET | CD180_CCR_RESETALL); while (sc->sc_regs->stc.gsvr != 0xff); while (sc->sc_regs->stc.gfrcr != sc->sc_rev2); @@ -250,6 +251,9 @@ sttyattach(parent, dev, aux) struct stty_port *sp = &ssc->sc_port[port]; struct tty *tp; + sp->sp_dtr = 0; + sc->sc_regs->dtrlatch[port] = 1; + tp = ttymalloc(); if (tp == NULL) break; @@ -325,8 +329,8 @@ sttyopen(dev, flags, mode, p) s = spltty(); csc->sc_regs->stc.car = sp->sp_channel; - spif_write_ccr(&csc->sc_regs->stc, - CD180_CCR_RESET | CD180_CCR_RESETCHAN); + stty_write_ccr(&csc->sc_regs->stc, + CD180_CCR_CMD_RESET | CD180_CCR_RESETCHAN); stty_param(tp, &tp->t_termios); @@ -386,7 +390,8 @@ sttyclose(dev, flags, mode, p) if (ISSET(tp->t_cflag, HUPCL) || !ISSET(tp->t_state, TS_ISOPEN)) { stty_modem_control(sp, 0, DMSET); csc->sc_regs->stc.car = port; - csc->sc_regs->stc.ccr = CD180_CCR_RESET | CD180_CCR_RESETCHAN; + csc->sc_regs->stc.ccr = + CD180_CCR_CMD_RESET | CD180_CCR_RESETCHAN; } splx(s); @@ -537,11 +542,11 @@ stty_param(tp, t) int s, opt; if (t->c_ospeed && - spif_compute_baud(t->c_ospeed, sc->sc_osc, &tbprl, &tbprh)) + stty_compute_baud(t->c_ospeed, sc->sc_osc, &tbprl, &tbprh)) return (EINVAL); if (t->c_ispeed && - spif_compute_baud(t->c_ispeed, sc->sc_osc, &rbprl, &rbprh)) + stty_compute_baud(t->c_ispeed, sc->sc_osc, &rbprl, &rbprh)) return (EINVAL); s = spltty(); @@ -591,7 +596,7 @@ stty_param(tp, t) sc->sc_regs->stc.cor3 = STTY_RX_FIFO_THRESHOLD; - spif_write_ccr(&sc->sc_regs->stc, CD180_CCR_CORCHG | + stty_write_ccr(&sc->sc_regs->stc, CD180_CCR_CMD_COR | CD180_CCR_CORCHG1 | CD180_CCR_CORCHG2 | CD180_CCR_CORCHG3); sc->sc_regs->stc.schr1 = 0x11; @@ -613,7 +618,7 @@ stty_param(tp, t) sc->sc_regs->stc.rbprl = rbprl; } - spif_write_ccr(&sc->sc_regs->stc, CD180_CCR_CHANCTL | + stty_write_ccr(&sc->sc_regs->stc, CD180_CCR_CMD_CHAN | CD180_CCR_CHAN_TXEN | CD180_CCR_CHAN_RXEN); sp->sp_carrier = sc->sc_regs->stc.msvr & CD180_MSVR_CD; @@ -726,7 +731,7 @@ spifstcintr(vsc) switch (ar) { case CD180_GSVR_RXGOOD: r = 1; - channel = (sc->sc_regs->stc.gscr1 >> 2) & CD180_GSCR_CMASK; + channel = CD180_GSCR_CHANNEL(sc->sc_regs->stc.gscr1); sp = &sc->sc_ttys->sc_port[channel]; ptr = sp->sp_rput; for (i = sc->sc_regs->stc.rdcr; i > 0; i--) { @@ -747,7 +752,7 @@ spifstcintr(vsc) break; case CD180_GSVR_RXEXCEPTION: r = 1; - channel = (sc->sc_regs->stc.gscr1 >> 2) & CD180_GSCR_CMASK; + channel = CD180_GSCR_CHANNEL(sc->sc_regs->stc.gscr1); sp = &sc->sc_ttys->sc_port[channel]; ptr = sp->sp_rput; *ptr++ = sc->sc_regs->stc.rcsr; @@ -775,7 +780,7 @@ spifstcintr(vsc) int cnt = 0; r = 1; - channel = (sc->sc_regs->stc.gscr1 >> 2) & CD180_GSCR_CMASK; + channel = CD180_GSCR_CHANNEL(sc->sc_regs->stc.gscr1); sp = &sc->sc_ttys->sc_port[channel]; if (!ISSET(sp->sp_flags, STTYF_STOP)) { @@ -824,7 +829,7 @@ spifstcintr(vsc) ar = sc->sc_regs->istc.mrar & CD180_GSVR_IMASK; if (ar == CD180_GSVR_STATCHG) { r = 1; - channel = (sc->sc_regs->stc.gscr1 >> 2) & CD180_GSCR_CMASK; + channel = CD180_GSCR_CHANNEL(sc->sc_regs->stc.gscr1); sp = &sc->sc_ttys->sc_port[channel]; ar = sc->sc_regs->stc.mcr; if (ar & CD180_MCR_CD) { @@ -925,8 +930,21 @@ spifsoftintr(vsc) return (r); } +static __inline void +stty_write_ccr(stc, val) + struct stcregs *stc; + u_int8_t val; +{ + int tries = 100000; + + while (stc->ccr && tries--); + if (tries == 0) + printf("CCR: timeout\n"); + stc->ccr = val; +} + int -spif_compute_baud(speed, clock, bprlp, bprhp) +stty_compute_baud(speed, clock, bprlp, bprhp) speed_t speed; int clock; u_int8_t *bprlp, *bprhp; @@ -1051,16 +1069,3 @@ sbppioctl(dev, cmd, data, flags, p) return (error); } - -static __inline void -spif_write_ccr(stc, val) - struct stcregs *stc; - u_int8_t val; -{ - int tries = 100000; - - while (stc->ccr && tries--); - if (tries == 0) - printf("CCR: timeout\n"); - stc->ccr = val; -} diff --git a/sys/arch/sparc/dev/spifreg.h b/sys/arch/sparc/dev/spifreg.h index 2d51275167b..a9b606802f3 100644 --- a/sys/arch/sparc/dev/spifreg.h +++ b/sys/arch/sparc/dev/spifreg.h @@ -1,4 +1,4 @@ -/* $OpenBSD: spifreg.h,v 1.2 1999/02/01 13:45:22 jason Exp $ */ +/* $OpenBSD: spifreg.h,v 1.3 1999/02/04 15:43:22 jason Exp $ */ /* * Copyright (c) 1999 Jason L. Wright (jason@thought.net) @@ -31,9 +31,6 @@ * POSSIBILITY OF SUCH DAMAGE. */ -#define SERIAL_INTR 0 -#define PARALLEL_INTR 1 - struct ppcregs { volatile u_int8_t in_pdata; /* input data reg */ volatile u_int8_t in_pstat; /* input status reg */ @@ -50,6 +47,21 @@ struct ppcregs { volatile u_int8_t iack_pweird; /* intr-ack weird reg */ }; +/* Parallel Status: read only */ +#define PPC_PSTAT_ERROR 0x08 /* error */ +#define PPC_PSTAT_SELECT 0x10 /* select */ +#define PPC_PSTAT_PAPER 0x20 /* paper out */ +#define PPC_PSTAT_ACK 0x40 /* ack */ +#define PPC_PSTAT_BUSY 0x80 /* busy */ + +/* Parallel Control: read/write */ +#define PPC_CTRL_STROBE 0x01 /* strobe, 1=drop strobe */ +#define PPC_CTRL_AFX 0x02 /* auto form-feed */ +#define PPC_CTRL_INIT 0x04 /* init, 1=enable printer */ +#define PPC_CTRL_SLCT 0x08 /* SLC, 1=select printer */ +#define PPC_CTRL_IRQE 0x10 /* IRQ, 1=enable intrs */ +#define PPC_CTRL_OUTPUT 0x20 /* direction: 1=ppc out */ + struct stcregs { volatile u_int8_t _unused0[1]; /* 0x00 unused */ volatile u_int8_t ccr; /* channel command reg */ @@ -121,77 +133,75 @@ struct stcregs { volatile u_int8_t eosrr; /* end of service req reg */ }; -/* - * The register for the SUNW,spif looks something like: - * Offset: Function: - * 0000 - 03ff unused - * 0400 - 0408 dtr latches (one per port) - * 0409 - 07ff unused - * 0800 - 087f CD180 registers (normal mapping) - * 0880 - 0bff unused - * 0c00 - 0c7f CD180 registers (*iack mapping) - * 0c80 - 0dff unused - * 0e00 - 1fff PPC registers - */ -struct spifregs { - volatile u_int8_t _unused1[1024]; /* 0x000-0x3ff unused */ - volatile u_int8_t dtrlatch[8]; /* per port dtr latch */ - volatile u_int8_t _unused2[1016]; /* 0x409-0x7ff unused */ - struct stcregs stc; /* regular cd-180 regs */ - volatile u_int8_t _unused3[896]; /* 0x880-0xbff unused */ - struct stcregs istc; /* *iack cd-180 regs */ - volatile u_int8_t _unused4[384]; /* 0xc80-0xdff unused */ - struct ppcregs ppc; /* parallel port regs */ -}; +/* Service Request Configuration Register */ +#define CD180_SRCR_PKGTYP 0x80 /* chip package type */ +#define CD180_SRCR_REGACKEN 0x40 /* register ack enable */ +#define CD180_SRCR_DAISYEN 0x20 /* daisy chain enable */ +#define CD180_SRCR_GLOBPRI 0x10 /* global priority */ +#define CD180_SRCR_UNFAIR 0x08 /* use unfair interrupts */ +#define CD180_SRCR_AUTOPRI 0x02 /* automatic priority */ +#define CD180_SRCR_PRISEL 0x01 /* select rx/tx as high pri */ -/* The mapping of minor device number -> card and port is done as - * follows by default: - * - * +---+---+---+---+---+---+---+---+ - * | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | - * +---+---+---+---+---+---+---+---+ - * | | | | | | | | - * | | | | | +---+---+---> port number - * | | | | | - * | | | | +---------------> unused - * | | | | - * | | | +-------------------> dialout (on tty ports) - * | | | - * | | +-----------------------> unused - * | | - * +---+---------------------------> card number - * - */ +/* Global Service Vector Register */ +#define CD180_GSVR_IMASK 0x07 /* interrupt type mask */ +#define CD180_GSVR_NOREQUEST 0x00 /* no request pending */ +#define CD180_GSVR_STATCHG 0x01 /* modem signal change */ +#define CD180_GSVR_TXDATA 0x02 /* tx service request */ +#define CD180_GSVR_RXGOOD 0x03 /* rx service request */ +#define CD180_GSVR_reserved1 0x04 /* reserved */ +#define CD180_GSVR_reserved2 0x05 /* reserved */ +#define CD180_GSVR_reserved3 0x06 /* reserved */ +#define CD180_GSVR_RXEXCEPTION 0x07 /* rx exception request */ + +/* Global Service Channel Register (1,2,3) */ +#define CD180_GSCR_CHANNEL(gscr) (((gscr) >> 2) & 7) -#define CD180_SRCR_PKGTYP 0x80 /* chip package type */ -#define CD180_SRCR_REGACKEN 0x40 -#define CD180_SRCR_DAISYEN 0x20 -#define CD180_SRCR_GLOBPRI 0x10 -#define CD180_SRCR_UNFAIR 0x08 -#define CD180_SRCR_AUTOPRI 0x04 -#define CD180_SRCR_reserved 0x02 -#define CD180_SRCR_PRISEL 0x01 - -#define CD180_CCR_RESET 0x80 /* chip/channel reset */ -#define CD180_CCR_RESETALL 0x01 /* global reset */ -#define CD180_CCR_RESETCHAN 0x00 /* current channel reset */ - -#define CD180_CCR_CORCHG 0x40 /* channel option reg has changed */ -#define CD180_CCR_CORCHG1 0x02 /* cor1 has changed */ -#define CD180_CCR_CORCHG2 0x04 /* cor2 has changed */ -#define CD180_CCR_CORCHG3 0x08 /* cor3 has changed */ - -#define CD180_CCR_SENDSPCHG 0x20 -#define CD180_CCR_SSPC0 0x01 -#define CD180_CCR_SSPC1 0x02 -#define CD180_CCR_SSPC2 0x04 - -#define CD180_CCR_CHANCTL 0x10 /* channel control command */ -#define CD180_CCR_CHAN_TXEN 0x08 /* enable channel tx */ -#define CD180_CCR_CHAN_TXDIS 0x04 /* disable channel tx */ -#define CD180_CCR_CHAN_RXEN 0x02 /* enable channel rx */ -#define CD180_CCR_CHAN_RXDIS 0x01 /* disable channel rx */ +/* Receive Data Count Register */ +#define CD180_RDCR_MASK 0x0f /* mask for fifo length */ + +/* Receive Character Status Register */ +#define CD180_RCSR_TO 0x80 /* time out */ +#define CD180_RCSR_SCD2 0x40 /* special char detect 2 */ +#define CD180_RCSR_SCD1 0x20 /* special char detect 1 */ +#define CD180_RCSR_SCD0 0x10 /* special char detect 0 */ +#define CD180_RCSR_BE 0x08 /* break exception */ +#define CD180_RCSR_PE 0x04 /* parity exception */ +#define CD180_RCSR_FE 0x02 /* framing exception */ +#define CD180_RCSR_OE 0x01 /* overrun exception */ + +/* Service Request Enable Register */ +#define CD180_SRER_DSR 0x80 /* DSR service request */ +#define CD180_SRER_CD 0x40 /* CD service request */ +#define CD180_SRER_CTS 0x20 /* CTS service request */ +#define CD180_SRER_RXD 0x10 /* RXD service request */ +#define CD180_SRER_RXSCD 0x08 /* RX special char request */ +#define CD180_SRER_TXD 0x04 /* TX ready service request */ +#define CD180_SRER_TXE 0x02 /* TX empty service request */ +#define CD180_SRER_NNDT 0x01 /* No new data timeout req */ +/* Channel Command Register */ +/* Reset Channel Command */ +#define CD180_CCR_CMD_RESET 0x80 /* chip/channel reset */ +#define CD180_CCR_RESETALL 0x01 /* global reset */ +#define CD180_CCR_RESETCHAN 0x00 /* current channel reset */ +/* Channel Option Register Command */ +#define CD180_CCR_CMD_COR 0x40 /* channel opt reg changed */ +#define CD180_CCR_CORCHG1 0x02 /* cor1 has changed */ +#define CD180_CCR_CORCHG2 0x04 /* cor2 has changed */ +#define CD180_CCR_CORCHG3 0x08 /* cor3 has changed */ +/* Send Special Character Command */ +#define CD180_CCR_CMD_SPC 0x20 /* send special chars changed */ +#define CD180_CCR_SSPC0 0x01 /* send special char 0 change */ +#define CD180_CCR_SSPC1 0x02 /* send special char 1 change */ +#define CD180_CCR_SSPC2 0x04 /* send special char 2 change */ +/* Channel Control Command */ +#define CD180_CCR_CMD_CHAN 0x10 /* channel control command */ +#define CD180_CCR_CHAN_TXEN 0x08 /* enable channel tx */ +#define CD180_CCR_CHAN_TXDIS 0x04 /* disable channel tx */ +#define CD180_CCR_CHAN_RXEN 0x02 /* enable channel rx */ +#define CD180_CCR_CHAN_RXDIS 0x01 /* disable channel rx */ + +/* Channel Option Register 1 */ #define CD180_COR1_EVENPAR 0x00 /* even parity */ #define CD180_COR1_ODDPAR 0x80 /* odd parity */ #define CD180_COR1_PARMODE_NO 0x00 /* no parity */ @@ -208,6 +218,7 @@ struct spifregs { #define CD180_COR1_CS7 0x02 /* 7 bit characters */ #define CD180_COR1_CS8 0x03 /* 8 bit characters */ +/* Channel Option Register 2 */ #define CD180_COR2_IXM 0x80 /* implied xon mode */ #define CD180_COR2_TXIBE 0x40 /* tx in-band flow control */ #define CD180_COR2_ETC 0x20 /* embedded tx command enbl */ @@ -217,83 +228,146 @@ struct spifregs { #define CD180_COR2_CTSAE 0x02 /* CTS automatic enable */ #define CD180_COR2_DSRAE 0x01 /* DSR automatic enable */ +/* Channel Option Register 3 */ +#define CD180_COR3_XON2 0x80 /* XON char in spc1&3 */ +#define CD180_COR3_XON1 0x00 /* XON char in spc1 */ +#define CD180_COR3_XOFF2 0x40 /* XOFF char in spc2&4 */ +#define CD180_COR3_XOFF1 0x00 /* XOFF char in spc2 */ +#define CD180_COR3_FCT 0x20 /* flow control transparency */ +#define CD180_COR3_SCDE 0x10 /* special char recognition */ +#define CD180_COR3_RXFIFO_MASK 0x0f /* rx fifo threshold */ + +/* Channel Control Status Register */ +#define CD180_CCSR_RXEN 0x80 /* rx is enabled */ +#define CD180_CCSR_RXFLOFF 0x40 /* rx flow-off */ +#define CD180_CCSR_RXFLON 0x20 /* rx flow-on */ +#define CD180_CCSR_TXEN 0x08 /* tx is enabled */ +#define CD180_CCSR_TXFLOFF 0x04 /* tx flow-off */ +#define CD180_CCSR_TXFLON 0x02 /* tx flow-on */ + +/* Modem Change Register */ +#define CD180_MCR_DSR 0x80 /* DSR changed */ +#define CD180_MCR_CD 0x40 /* CD changed */ +#define CD180_MCR_CTS 0x20 /* CTS changed */ + +/* Modem Change Option Register 1 */ #define CD180_MCOR1_DSRZD 0x80 /* catch 0->1 DSR changes */ #define CD180_MCOR1_CDZD 0x40 /* catch 0->1 CD changes */ #define CD180_MCOR1_CTSZD 0x40 /* catch 0->1 CTS changes */ #define CD180_MCOR1_DTRTHRESH 0x0f /* DTR threshold mask */ +/* Modem Change Option Register 2 */ #define CD180_MCOR2_DSROD 0x80 /* catch 1->0 DSR changes */ #define CD180_MCOR2_CDOD 0x40 /* catch 1->0 CD changes */ #define CD180_MCOR2_CTSOD 0x20 /* catch 1->0 CTS changes */ -#define CD180_SRER_DSR 0x80 /* DSR service request */ -#define CD180_SRER_CD 0x40 /* CD service request */ -#define CD180_SRER_CTS 0x20 /* CTS service request */ -#define CD180_SRER_RXD 0x10 /* RXD service request */ -#define CD180_SRER_RXSCD 0x08 /* RX special char request */ -#define CD180_SRER_TXD 0x04 /* TX ready service request */ -#define CD180_SRER_TXE 0x02 /* TX empty service request */ -#define CD180_SRER_NNDT 0x01 /* No new data timeout req */ - +/* Modem Signal Value Register */ #define CD180_MSVR_DSR 0x80 /* DSR input state */ #define CD180_MSVR_CD 0x40 /* CD input state */ #define CD180_MSVR_CTS 0x20 /* CTS input state */ #define CD180_MSVR_DTR 0x02 /* DTR output state */ #define CD180_MSVR_RTS 0x01 /* RTS output state */ -#define CD180_GSCR_CMASK 0x07 /* channel mask */ +/* + * The register map for the SUNW,spif looks something like: + * Offset: Function: + * 0000 - 03ff Boot ROM + * 0400 - 0408 dtr latches (one per port) + * 0409 - 07ff unused + * 0800 - 087f CD180 registers (normal mapping) + * 0880 - 0bff unused + * 0c00 - 0c7f CD180 registers (*iack mapping) + * 0c80 - 0dff unused + * 0e00 - 1fff PPC registers + * + * One note about the DTR latches: The values stored there are reversed. + * By writing a 1 to the latch, DTR is lowered, and by writing a 0, DTR + * is raised. The latches cannot be read, and no other value can be written + * there or the system will crash due to "excessive bus loading (see + * SBus loading and capacitance spec)" + * + * The *iack registers are read/written with the IACK bit set. When + * the interrupt routine starts, it reads the MRAR, TRAR, and RRAR registers + * from this mapping. This signals an interrupt acknowlegement cycle. + * (NOTE: these are not really the MRAR, TRAR, and RRAR... They are copies + * of the GSVR, I just mapped them to the same location as the mrar, trar, + * and rrar because it seemed appropriate). + */ +struct spifregs { + volatile u_int8_t _unused1[1024]; /* 0x000-0x3ff unused */ + volatile u_int8_t dtrlatch[8]; /* per port dtr latch */ + volatile u_int8_t _unused2[1016]; /* 0x409-0x7ff unused */ + struct stcregs stc; /* regular cd-180 regs */ + volatile u_int8_t _unused3[896]; /* 0x880-0xbff unused */ + struct stcregs istc; /* *iack cd-180 regs */ + volatile u_int8_t _unused4[384]; /* 0xc80-0xdff unused */ + struct ppcregs ppc; /* parallel port regs */ +}; -#define CD180_GSVR_IMASK 0x07 /* interrupt type mask */ -#define CD180_GSVR_NOREQUEST 0x00 /* no request pending */ -#define CD180_GSVR_STATCHG 0x01 /* modem signal change */ -#define CD180_GSVR_TXDATA 0x02 /* tx service request */ -#define CD180_GSVR_RXGOOD 0x03 /* rx service request */ -#define CD180_GSVR_reserved1 0x04 -#define CD180_GSVR_reserved2 0x05 -#define CD180_GSVR_reserved3 0x06 -#define CD180_GSVR_RXEXCEPTION 0x07 /* rx exception request */ +/* + * The mapping of minor device number -> card and port is done as + * follows by default: + * + * +---+---+---+---+---+---+---+---+ + * | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | + * +---+---+---+---+---+---+---+---+ + * | | | | | | | | + * | | | | | +---+---+---> port number + * | | | | | + * | | | | +---------------> unused + * | | | | + * | | | +-------------------> dialout (on tty ports) + * | | | + * | | +-----------------------> unused + * | | + * +---+---------------------------> card number + * + */ +#define SPIF_MAX_CARDS 4 +#define SPIF_MAX_TTY 8 +#define SPIF_MAX_BPP 1 + +/* + * device selectors + */ +#define SPIF_CARD(x) ((minor(x) >> 6) & 0x03) +#define SPIF_PORT(x) (minor(x) & 0x0f) +#define STTY_DIALOUT(x) (minor(x) & 0x10) #define STTY_RX_FIFO_THRESHOLD 6 #define STTY_RX_DTR_THRESHOLD 7 #define CD180_TX_FIFO_SIZE 8 /* 8 chars of fifo */ -#define CD180_RCSR_TO 0x80 /* time out */ -#define CD180_RCSR_SCD2 0x40 /* special char detect 2 */ -#define CD180_RCSR_SCD1 0x20 /* special char detect 1 */ -#define CD180_RCSR_SCD0 0x10 /* special char detect 0 */ -#define CD180_RCSR_BE 0x08 /* break exception */ -#define CD180_RCSR_PE 0x04 /* parity exception */ -#define CD180_RCSR_FE 0x02 /* framing exception */ -#define CD180_RCSR_OE 0x01 /* overrun exception */ - -#define CD180_MCR_DSR 0x80 /* DSR changed */ -#define CD180_MCR_CD 0x40 /* CD changed */ -#define CD180_MCR_CTS 0x20 /* CTS changed */ - /* - * These are the offsets of the MRAR,TRAR, and RRAR in *IACK space. + * These are the offsets of the MRAR, TRAR, and RRAR in *IACK space. * The high bit must be set as per specs for the MSMR, TSMR, and RSMR. */ #define SPIF_MSMR 0xf5 /* offset of MRAR | 0x80 */ #define SPIF_TSMR 0xf6 /* offset of TRAR | 0x80 */ #define SPIF_RSMR 0xf7 /* offset of RRAR | 0x80 */ -#define SPIF_MAX_CARDS 4 -#define SPIF_MAX_TTY 8 -#define SPIF_MAX_BPP 1 - -#define SPIF_CARD(x) ((minor(x) >> 6) & 0x03) -#define SPIF_PORT(x) (minor(x) & 0x0f) - -#define STTY_DIALOUT(x) (minor(x) & 0x10) - -/* "verosc" node tells which oscillator we have. */ +/* + * "verosc" node tells which oscillator we have. + */ #define SPIF_OSC9 1 /* 9.8304 Mhz */ #define SPIF_OSC10 2 /* 10Mhz */ -#define SPIF_PPRH 0xf0 -#define SPIF_PPRL 0x00 +/* + * There are two interrupts, serial gets interrupt[0], and parallel + * gets interrupt[1] + */ +#define SERIAL_INTR 0 +#define PARALLEL_INTR 1 + +/* + * prescalar values + */ +#define SPIF_PPRH 0xf0 /* high byte */ +#define SPIF_PPRL 0x00 /* low byte */ +/* + * spif tty flags + */ #define STTYF_CDCHG 0x01 /* carrier changed */ #define STTYF_RING_OVERFLOW 0x02 /* ring buffer overflowed */ #define STTYF_DONE 0x04 /* done... flush buffers */ diff --git a/sys/arch/sparc/dev/spifvar.h b/sys/arch/sparc/dev/spifvar.h index 1db8c16cab5..46f973c6281 100644 --- a/sys/arch/sparc/dev/spifvar.h +++ b/sys/arch/sparc/dev/spifvar.h @@ -1,4 +1,4 @@ -/* $OpenBSD: spifvar.h,v 1.1 1999/02/01 00:30:42 jason Exp $ */ +/* $OpenBSD: spifvar.h,v 1.2 1999/02/04 15:43:22 jason Exp $ */ /* * Copyright (c) 1999 Jason L. Wright (jason@thought.net) @@ -45,9 +45,9 @@ struct stty_port { u_char *sp_txp; /* transmit character pointer */ int sp_txc; /* transmit character counter */ - int sp_openflags; - int sp_carrier; - int sp_flags; + int sp_openflags; /* open flags */ + int sp_carrier; /* software carrier status */ + int sp_flags; /* software state */ char sp_dtr; /* software dtr status */ }; @@ -69,11 +69,11 @@ struct spif_softc { struct intrhand sc_ppcih; /* ppc interrupt vectoring */ struct intrhand sc_softih; /* hard interrupt vectoring */ int sc_rev; /* revision level */ - int sc_osc; /* oscillator speed (mhz) */ + int sc_osc; /* oscillator speed (hz) */ int sc_node; /* which sbus node */ int sc_nser; /* number of serial ports */ int sc_npar; /* number of parallel ports */ - unsigned sc_rev2; /* onboard chip revision */ + int sc_rev2; /* cd180 chip revision */ struct spifregs *sc_regs; /* registers */ struct stty_softc *sc_ttys; /* our ttys */ struct sbpp_softc *sc_bpps; /* our ttys */ |