diff options
47 files changed, 135 insertions, 2376 deletions
diff --git a/sys/arch/arm/arm/arm32_machdep.c b/sys/arch/arm/arm/arm32_machdep.c index 4a3c320532d..afcd28cfddf 100644 --- a/sys/arch/arm/arm/arm32_machdep.c +++ b/sys/arch/arm/arm/arm32_machdep.c @@ -1,4 +1,4 @@ -/* $OpenBSD: arm32_machdep.c,v 1.38 2011/06/24 19:47:48 naddy Exp $ */ +/* $OpenBSD: arm32_machdep.c,v 1.39 2011/09/20 22:02:10 miod Exp $ */ /* $NetBSD: arm32_machdep.c,v 1.42 2003/12/30 12:33:15 pk Exp $ */ /* @@ -60,7 +60,6 @@ #include <dev/cons.h> #include <arm/machdep.h> -#include <machine/bootconfig.h> #include <machine/conf.h> #ifdef CONF_HAVE_APM @@ -236,7 +235,7 @@ cpu_startup() proc0.p_addr = proc0paddr; /* Set the cpu control register */ - cpu_setup(boot_args); + cpu_setup(); /* Lock down zero page */ vector_page_setprot(VM_PROT_READ); diff --git a/sys/arch/arm/arm/arm_machdep.c b/sys/arch/arm/arm/arm_machdep.c index 4fdd397f7a7..526c84c6adc 100644 --- a/sys/arch/arm/arm/arm_machdep.c +++ b/sys/arch/arm/arm/arm_machdep.c @@ -1,4 +1,4 @@ -/* $OpenBSD: arm_machdep.c,v 1.2 2010/04/04 12:49:30 miod Exp $ */ +/* $OpenBSD: arm_machdep.c,v 1.3 2011/09/20 22:02:10 miod Exp $ */ /* $NetBSD: arm_machdep.c,v 1.7 2003/10/25 19:44:42 scw Exp $ */ /* @@ -123,150 +123,8 @@ setregs(struct proc *p, struct exec_package *pack, u_long stack, tf->tf_usr_lr = pack->ep_entry; tf->tf_svc_lr = 0x77777777; /* Something we can see */ tf->tf_pc = pack->ep_entry; -#ifdef __PROG32 tf->tf_spsr = PSR_USR32_MODE; -#endif p->p_addr->u_pcb.pcb_flags = 0; retval[1] = 0; } - -#if 0 -/* - * startlwp: - * - * Start a new LWP. - */ -void -startlwp(void *arg) -{ - int err; - ucontext_t *uc = arg; - struct lwp *l = curlwp; - - err = cpu_setmcontext(l, &uc->uc_mcontext, uc->uc_flags); -#ifdef DIAGNOSTIC - if (err) - printf("Error %d from cpu_setmcontext.", err); -#endif - pool_put(&lwp_uc_pool, uc); - - userret(l); -} - -/* - * XXX This is a terrible name. - */ -void -upcallret(struct lwp *l) -{ - - userret(l); -} - -/* - * cpu_upcall: - * - * Send an an upcall to userland. - */ -void -cpu_upcall(struct lwp *l, int type, int nevents, int ninterrupted, void *sas, - void *ap, void *sp, sa_upcall_t upcall) -{ - struct trapframe *tf; - struct saframe *sf, frame; - - tf = process_frame(l); - - /* Finally, copy out the rest of the frame. */ -#if 0 /* First 4 args in regs (see below). */ - frame.sa_type = type; - frame.sa_sas = sas; - frame.sa_events = nevents; - frame.sa_interrupted = ninterrupted; -#endif - frame.sa_arg = ap; - - sf = (struct saframe *)sp - 1; - if (copyout(&frame, sf, sizeof(frame)) != 0) { - /* Copying onto the stack didn't work. Die. */ - sigexit(l, SIGILL); - /* NOTREACHED */ - } - - tf->tf_r0 = type; - tf->tf_r1 = (int) sas; - tf->tf_r2 = nevents; - tf->tf_r3 = ninterrupted; - tf->tf_pc = (int) upcall; - tf->tf_usr_sp = (int) sf; - tf->tf_usr_lr = 0; /* no return */ -} -#endif - - -#if 0 -#define _CONCAT(A,B) A ## B -#define __C(A,B) _CONCAT(A,B) - -#define BUS_SPACE_COPY_N(BYTES,TYPE) \ -void \ -__C(bus_space_copy_,BYTES)(bus_space_tag_t bst, bus_space_handle_t h1, \ - bus_size_t o1, bus_space_handle_t h2, bus_size_t o2, \ - bus_size_t c) \ -{ \ - int i; \ - \ - if (h1 == h2 && o2 > o1) \ - for (i = c-1; i >= 0; i--) \ - __C(bus_space_write_,BYTES)(bst, h2, o2+(BYTES*i), \ - __C(bus_space_read_,BYTES)(bst, h1, o1+(BYTES*i))); \ - else \ - for (i = 0; i < c; i++) \ - __C(bus_space_write_,BYTES)(bst, h2, o2+(BYTES*i), \ - __C(bus_space_read_,BYTES)(bst, h1, o1+(BYTES*i))); \ -} -BUS_SPACE_COPY_N(1,u_int8_t) -BUS_SPACE_COPY_N(2,u_int16_t) -BUS_SPACE_COPY_N(4,u_int32_t) - - - -#define BUS_SPACE_READ_RAW_MULTI_N(BYTES,SHIFT,TYPE) \ -void \ -__C(bus_space_read_raw_multi_,BYTES)(bus_space_tag_t bst, \ - bus_space_handle_t h, bus_addr_t o, u_int8_t *dst, bus_size_t size) \ -{ \ - TYPE *src; \ - TYPE *rdst = (TYPE *)dst; \ - int i; \ - int count = size >> SHIFT; \ - \ - src = (TYPE *)(h+o); \ - for (i = 0; i < count; i++) { \ - rdst[i] = *src; \ - } \ -} -BUS_SPACE_READ_RAW_MULTI_N(2,1,u_int16_t) -BUS_SPACE_READ_RAW_MULTI_N(4,2,u_int32_t) - -#define BUS_SPACE_WRITE_RAW_MULTI_N(BYTES,SHIFT,TYPE) \ -void \ -__C(bus_space_write_raw_multi_,BYTES)( bus_space_tag_t bst, \ - bus_space_handle_t h, bus_addr_t o, const u_int8_t *src, \ - bus_size_t size) \ -{ \ - int i; \ - TYPE *dst; \ - TYPE *rsrc = (TYPE *)src; \ - int count = size >> SHIFT; \ - \ - dst = (TYPE *)(h+o); \ - for (i = 0; i < count; i++) { \ - *dst = rsrc[i]; \ - } \ -} - -BUS_SPACE_WRITE_RAW_MULTI_N(2,1,u_int16_t) -BUS_SPACE_WRITE_RAW_MULTI_N(4,2,u_int32_t) -#endif diff --git a/sys/arch/arm/arm/ast.c b/sys/arch/arm/arm/ast.c index 762c440e125..70b32ac0d5a 100644 --- a/sys/arch/arm/arm/ast.c +++ b/sys/arch/arm/arm/ast.c @@ -1,4 +1,4 @@ -/* $OpenBSD: ast.c,v 1.8 2007/05/14 07:07:09 art Exp $ */ +/* $OpenBSD: ast.c,v 1.9 2011/09/20 22:02:10 miod Exp $ */ /* $NetBSD: ast.c,v 1.6 2003/10/31 16:44:34 cl Exp $ */ /* @@ -59,10 +59,6 @@ #include <uvm/uvm_extern.h> -#ifdef acorn26 -#include <machine/machdep.h> -#endif - /* * Prototypes */ @@ -95,13 +91,7 @@ ast(struct trapframe *tf) { struct proc *p = curproc; -#ifdef acorn26 - /* Enable interrupts if they were enabled before the trap. */ - if ((tf->tf_r15 & R15_IRQ_DISABLE) == 0) - int_on(); -#else /* Interrupts were restored by exception_exit. */ -#endif uvmexp.traps++; uvmexp.softs++; diff --git a/sys/arch/arm/arm/bcopyinout.S b/sys/arch/arm/arm/bcopyinout.S index 684a4d3ac68..7656c111de7 100644 --- a/sys/arch/arm/arm/bcopyinout.S +++ b/sys/arch/arm/arm/bcopyinout.S @@ -1,4 +1,4 @@ -/* $OpenBSD: bcopyinout.S,v 1.1 2004/02/01 05:09:48 drahn Exp $ */ +/* $OpenBSD: bcopyinout.S,v 1.2 2011/09/20 22:02:10 miod Exp $ */ /* $NetBSD: bcopyinout.S,v 1.13 2003/10/31 16:54:05 scw Exp $ */ /* @@ -55,14 +55,8 @@ .word _C_LABEL(curpcb) #endif -#ifdef __PROG32 #define SAVE_REGS stmfd sp!, {r4-r11} #define RESTORE_REGS ldmfd sp!, {r4-r11} -#else -/* Need to save R14_svc because it'll get trampled if we take a page fault. */ -#define SAVE_REGS stmfd sp!, {r4-r11, r14} -#define RESTORE_REGS ldmfd sp!, {r4-r11, r14} -#endif #if defined(__XSCALE__) #define HELLOCPP # @@ -710,7 +704,6 @@ ENTRY(kcopy) mov pc, lr #endif /* !__XSCALE__ */ -#ifdef __PROG32 /* * int badaddr_read_1(const uint8_t *src, uint8_t *dest) * @@ -812,4 +805,3 @@ ENTRY(badaddr_read_4) mov r0, #0 /* No fault */ 1: str ip, [r2, #PCB_ONFAULT] mov pc, lr -#endif /* __PROG32 */ diff --git a/sys/arch/arm/arm/bootconfig.c b/sys/arch/arm/arm/bootconfig.c deleted file mode 100644 index 27ed4736fe6..00000000000 --- a/sys/arch/arm/arm/bootconfig.c +++ /dev/null @@ -1,128 +0,0 @@ -/* $OpenBSD: bootconfig.c,v 1.1 2004/02/01 05:09:48 drahn Exp $ */ -/* $NetBSD: bootconfig.c,v 1.2 2002/03/10 19:56:39 lukem Exp $ */ - -/* - * Copyright (c) 1994-1998 Mark Brinicombe. - * Copyright (c) 1994 Brini. - * All rights reserved. - * - * This code is derived from software written for Brini by Mark Brinicombe - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. All advertising materials mentioning features or use of this software - * must display the following acknowledgement: - * This product includes software developed by Mark Brinicombe - * for the NetBSD Project. - * 4. The name of the company nor the name of the author may be used to - * endorse or promote products derived from this software without specific - * prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#include <sys/param.h> - -#include <sys/systm.h> - -#include <machine/bootconfig.h> - -#include "rd.h" - -/* - * Function to identify and process different types of boot argument - */ - -int -get_bootconf_option(opts, opt, type, result) - char *opts; - char *opt; - int type; - void *result; -{ - char *ptr; - char *optstart; - int not; - - ptr = opts; - - while (*ptr) { - /* Find start of option */ - while (*ptr == ' ' || *ptr == '\t') - ++ptr; - - if (*ptr == 0) - break; - - not = 0; - - /* Is it a negate option */ - if ((type & BOOTOPT_TYPE_MASK) == BOOTOPT_TYPE_BOOLEAN && *ptr == '!') { - not = 1; - ++ptr; - } - - /* Find the end of option */ - optstart = ptr; - while (*ptr != 0 && *ptr != ' ' && *ptr != '\t' && *ptr != '=') - ++ptr; - - if ((*ptr == '=') - || (*ptr != '=' && ((type & BOOTOPT_TYPE_MASK) == BOOTOPT_TYPE_BOOLEAN))) { - /* compare the option */ - if (strncmp(optstart, opt, (ptr - optstart)) == 0) { - /* found */ - - if (*ptr == '=') - ++ptr; - -#if 0 -/* BELCH */ - switch(type & BOOTOPT_TYPE_MASK) { - case BOOTOPT_TYPE_BOOLEAN : - if (*(ptr - 1) == '=') - *((int *)result) = ((u_int)strtoul(ptr, NULL, 10) != 0); - else - *((int *)result) = !not; - break; - case BOOTOPT_TYPE_STRING : - *((char **)result) = ptr; - break; - case BOOTOPT_TYPE_INT : - *((int *)result) = (u_int)strtoul(ptr, NULL, 10); - break; - case BOOTOPT_TYPE_BININT : - *((int *)result) = (u_int)strtoul(ptr, NULL, 2); - break; - case BOOTOPT_TYPE_HEXINT : - *((int *)result) = (u_int)strtoul(ptr, NULL, 16); - break; - default: - return(0); - } -#endif - return(1); - } - } - /* skip to next option */ - while (*ptr != ' ' && *ptr != '\t' && *ptr != 0) - ++ptr; - } - return(0); -} diff --git a/sys/arch/arm/arm/copystr.S b/sys/arch/arm/arm/copystr.S index 2b58c944992..aeb2f3c4db2 100644 --- a/sys/arch/arm/arm/copystr.S +++ b/sys/arch/arm/arm/copystr.S @@ -1,4 +1,4 @@ -/* $OpenBSD: copystr.S,v 1.2 2006/11/15 19:48:29 miod Exp $ */ +/* $OpenBSD: copystr.S,v 1.3 2011/09/20 22:02:10 miod Exp $ */ /* $NetBSD: copystr.S,v 1.8 2002/10/13 14:54:48 bjh21 Exp $ */ /* @@ -85,14 +85,8 @@ ENTRY(copystr) ldmfd sp!, {r4-r5} /* stack is 8 byte aligned */ mov pc, lr -#ifdef __PROG32 #define SAVE_REGS stmfd sp!, {r4-r6} #define RESTORE_REGS ldmfd sp!, {r4-r6} -#else -/* Need to save R14_svc because it'll get trampled if we take a page fault. */ -#define SAVE_REGS stmfd sp!, {r4-r6, r14} -#define RESTORE_REGS ldmfd sp!, {r4-r6, r14} -#endif /* * r0 - user space address diff --git a/sys/arch/arm/arm/cpu.c b/sys/arch/arm/arm/cpu.c index 0a10b619dbc..2adba2dcd64 100644 --- a/sys/arch/arm/arm/cpu.c +++ b/sys/arch/arm/arm/cpu.c @@ -1,4 +1,4 @@ -/* $OpenBSD: cpu.c,v 1.13 2011/03/17 21:49:33 jasper Exp $ */ +/* $OpenBSD: cpu.c,v 1.14 2011/09/20 22:02:10 miod Exp $ */ /* $NetBSD: cpu.c,v 1.56 2004/04/14 04:01:49 bsh Exp $ */ @@ -56,11 +56,6 @@ #include <arm/cpuconf.h> #include <arm/undefined.h> -#ifdef ARMFPE -#include <machine/bootconfig.h> /* For boot args */ -#include <arm/fpe-arm/armfpe.h> -#endif - char cpu_model[256]; /* Prototypes */ @@ -73,12 +68,6 @@ void identify_arm_cpu(struct device *dv, struct cpu_info *); void cpu_attach(struct device *dv) { -#ifdef ARMFPE - int usearmfpe; - - usearmfpe = 1; /* when compiled in, its enabled by default */ -#endif - curcpu()->ci_dev = dv; /* Get the CPU ID from coprocessor 15 */ @@ -90,12 +79,6 @@ cpu_attach(struct device *dv) identify_arm_cpu(dv, curcpu()); - if (curcpu()->ci_arm_cputype == CPU_ID_SA110 && - curcpu()->ci_arm_cpurev < 3) { - printf("%s: SA-110 with bugged STM^ instruction\n", - dv->dv_xname); - } - #ifdef CPU_ARM8 if ((curcpu()->ci_arm_cpuid & CPU_ID_CPU_MASK) == CPU_ID_ARM810) { int clock = arm8_clock_config(0, 0); @@ -120,48 +103,10 @@ cpu_attach(struct device *dv) aprint_normal(" fclk source=%s\n", fclk); } #endif - -#ifdef ARMFPE - /* - * Ok now we test for an FPA - * At this point no floating point emulator has been installed. - * This means any FP instruction will cause undefined exception. - * We install a temporay coproc 1 handler which will modify - * undefined_test if it is called. - * We then try to read the FP status register. If undefined_test - * has been decremented then the instruction was not handled by - * an FPA so we know the FPA is missing. If undefined_test is - * still 1 then we know the instruction was handled by an FPA. - * We then remove our test handler and look at the - * FP status register for identification. - */ - - /* - * Ok if ARMFPE is defined and the boot options request the - * ARM FPE then it will be installed as the FPE. - * This is just while I work on integrating the new FPE. - * It means the new FPE gets installed if compiled int (ARMFPE - * defined) and also gives me a on/off option when I boot in - * case the new FPE is causing panics. - */ - - - if (boot_args) - get_bootconf_option(boot_args, "armfpe", - BOOTOPT_TYPE_BOOLEAN, &usearmfpe); - if (usearmfpe) - initialise_arm_fpe(); -#endif } enum cpu_class { CPU_CLASS_NONE, - CPU_CLASS_ARM2, - CPU_CLASS_ARM2AS, - CPU_CLASS_ARM3, - CPU_CLASS_ARM6, - CPU_CLASS_ARM7, - CPU_CLASS_ARM7TDMI, CPU_CLASS_ARM8, CPU_CLASS_ARM9TDMI, CPU_CLASS_ARM9ES, @@ -272,40 +217,6 @@ struct cpuidtab { }; const struct cpuidtab cpuids[] = { - { CPU_ID_ARM2, CPU_CLASS_ARM2, "ARM2", - generic_steppings }, - { CPU_ID_ARM250, CPU_CLASS_ARM2AS, "ARM250", - generic_steppings }, - - { CPU_ID_ARM3, CPU_CLASS_ARM3, "ARM3", - generic_steppings }, - - { CPU_ID_ARM600, CPU_CLASS_ARM6, "ARM600", - generic_steppings }, - { CPU_ID_ARM610, CPU_CLASS_ARM6, "ARM610", - generic_steppings }, - { CPU_ID_ARM620, CPU_CLASS_ARM6, "ARM620", - generic_steppings }, - - { CPU_ID_ARM700, CPU_CLASS_ARM7, "ARM700", - generic_steppings }, - { CPU_ID_ARM710, CPU_CLASS_ARM7, "ARM710", - generic_steppings }, - { CPU_ID_ARM7500, CPU_CLASS_ARM7, "ARM7500", - generic_steppings }, - { CPU_ID_ARM710A, CPU_CLASS_ARM7, "ARM710a", - generic_steppings }, - { CPU_ID_ARM7500FE, CPU_CLASS_ARM7, "ARM7500FE", - generic_steppings }, - { CPU_ID_ARM710T, CPU_CLASS_ARM7TDMI, "ARM710T", - generic_steppings }, - { CPU_ID_ARM720T, CPU_CLASS_ARM7TDMI, "ARM720T", - generic_steppings }, - { CPU_ID_ARM740T8K, CPU_CLASS_ARM7TDMI, "ARM740T (8 KB cache)", - generic_steppings }, - { CPU_ID_ARM740T4K, CPU_CLASS_ARM7TDMI, "ARM740T (4 KB cache)", - generic_steppings }, - { CPU_ID_ARM810, CPU_CLASS_ARM8, "ARM810", generic_steppings }, @@ -403,18 +314,12 @@ struct cpu_classtab { const struct cpu_classtab cpu_classes[] = { { "unknown", NULL }, /* CPU_CLASS_NONE */ - { "ARM2", "CPU_ARM2" }, /* CPU_CLASS_ARM2 */ - { "ARM2as", "CPU_ARM250" }, /* CPU_CLASS_ARM2AS */ - { "ARM3", "CPU_ARM3" }, /* CPU_CLASS_ARM3 */ - { "ARM6", "CPU_ARM6" }, /* CPU_CLASS_ARM6 */ - { "ARM7", "CPU_ARM7" }, /* CPU_CLASS_ARM7 */ - { "ARM7TDMI", "CPU_ARM7TDMI" }, /* CPU_CLASS_ARM7TDMI */ { "ARM8", "CPU_ARM8" }, /* CPU_CLASS_ARM8 */ { "ARM9TDMI", NULL }, /* CPU_CLASS_ARM9TDMI */ { "ARM9E-S", "CPU_ARM9E" }, /* CPU_CLASS_ARM9ES */ { "ARM9EJ-S", "CPU_ARM9E" }, /* CPU_CLASS_ARM9EJS */ { "ARM10E", "CPU_ARM10" }, /* CPU_CLASS_ARM10E */ - { "SA-1", "CPU_SA110" }, /* CPU_CLASS_SA1 */ + { "SA-1", "CPU_SA1100" }, /* CPU_CLASS_SA1 */ { "XScale", "CPU_XSCALE_..." }, /* CPU_CLASS_XSCALE */ { "ARM11J", "CPU_ARM11" }, /* CPU_CLASS_ARM11J */ { "ARMv7", "CPU_ARMv7" } /* CPU_CLASS_ARMv7 */ @@ -480,9 +385,6 @@ identify_arm_cpu(struct device *dv, struct cpu_info *ci) printf("%s:", dv->dv_xname); switch (cpu_class) { - case CPU_CLASS_ARM6: - case CPU_CLASS_ARM7: - case CPU_CLASS_ARM7TDMI: case CPU_CLASS_ARM8: if ((ci->ci_ctrl & CPU_CONTROL_IDC_ENABLE) == 0) printf(" IDC disabled"); @@ -544,24 +446,6 @@ identify_arm_cpu(struct device *dv, struct cpu_info *ci) skip_pcache: switch (cpu_class) { -#ifdef CPU_ARM2 - case CPU_CLASS_ARM2: -#endif -#ifdef CPU_ARM250 - case CPU_CLASS_ARM2AS: -#endif -#ifdef CPU_ARM3 - case CPU_CLASS_ARM3: -#endif -#ifdef CPU_ARM6 - case CPU_CLASS_ARM6: -#endif -#ifdef CPU_ARM7 - case CPU_CLASS_ARM7: -#endif -#ifdef CPU_ARM7TDMI - case CPU_CLASS_ARM7TDMI: -#endif #ifdef CPU_ARM8 case CPU_CLASS_ARM8: #endif @@ -582,8 +466,7 @@ identify_arm_cpu(struct device *dv, struct cpu_info *ci) case CPU_CLASS_ARMv7: #endif -#if defined(CPU_SA110) || defined(CPU_SA1100) || \ - defined(CPU_SA1110) || defined(CPU_IXP12X0) +#if defined(CPU_SA1100) || defined(CPU_SA1110) || defined(CPU_IXP12X0) case CPU_CLASS_SA1: #endif #if defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \ diff --git a/sys/arch/arm/arm/cpufunc.c b/sys/arch/arm/arm/cpufunc.c index 697f80ea327..ce783495fa5 100644 --- a/sys/arch/arm/arm/cpufunc.c +++ b/sys/arch/arm/arm/cpufunc.c @@ -1,4 +1,4 @@ -/* $OpenBSD: cpufunc.c,v 1.13 2010/07/01 22:40:10 drahn Exp $ */ +/* $OpenBSD: cpufunc.c,v 1.14 2011/09/20 22:02:10 miod Exp $ */ /* $NetBSD: cpufunc.c,v 1.65 2003/11/05 12:53:15 scw Exp $ */ /* @@ -49,10 +49,6 @@ #include <sys/types.h> #include <sys/param.h> #include <sys/systm.h> -#include <uvm/uvm.h> -#include <machine/cpu.h> -#include <machine/pmap.h> -#include <machine/bootconfig.h> #include <uvm/uvm.h> @@ -100,242 +96,6 @@ int arm_dcache_align_mask; /* 1 == use cpu_sleep(), 0 == don't */ int cpu_do_powersave; -#ifdef CPU_ARM3 -struct cpu_functions arm3_cpufuncs = { - /* CPU functions */ - - cpufunc_id, /* id */ - cpufunc_nullop, /* cpwait */ - - /* MMU functions */ - - arm3_control, /* control */ - NULL, /* domain */ - NULL, /* setttb */ - NULL, /* faultstatus */ - NULL, /* faultaddress */ - - /* TLB functions */ - - cpufunc_nullop, /* tlb_flushID */ - (void *)cpufunc_nullop, /* tlb_flushID_SE */ - cpufunc_nullop, /* tlb_flushI */ - (void *)cpufunc_nullop, /* tlb_flushI_SE */ - cpufunc_nullop, /* tlb_flushD */ - (void *)cpufunc_nullop, /* tlb_flushD_SE */ - - /* Cache operations */ - - cpufunc_nullop, /* icache_sync_all */ - (void *) cpufunc_nullop, /* icache_sync_range */ - - arm3_cache_flush, /* dcache_wbinv_all */ - (void *)arm3_cache_flush, /* dcache_wbinv_range */ - (void *)arm3_cache_flush, /* dcache_inv_range */ - (void *)cpufunc_nullop, /* dcache_wb_range */ - - arm3_cache_flush, /* idcache_wbinv_all */ - (void *)arm3_cache_flush, /* idcache_wbinv_range */ - - /* Other functions */ - - cpufunc_nullop, /* flush_prefetchbuf */ - cpufunc_nullop, /* drain_writebuf */ - cpufunc_nullop, /* flush_brnchtgt_C */ - (void *)cpufunc_nullop, /* flush_brnchtgt_E */ - - (void *)cpufunc_nullop, /* sleep */ - - /* Soft functions */ - - early_abort_fixup, /* dataabt_fixup */ - cpufunc_null_fixup, /* prefetchabt_fixup */ - - NULL, /* context_switch */ - - (void *)cpufunc_nullop /* cpu setup */ - -}; -#endif /* CPU_ARM3 */ - -#ifdef CPU_ARM6 -struct cpu_functions arm6_cpufuncs = { - /* CPU functions */ - - cpufunc_id, /* id */ - cpufunc_nullop, /* cpwait */ - - /* MMU functions */ - - cpufunc_control, /* control */ - cpufunc_domains, /* domain */ - arm67_setttb, /* setttb */ - cpufunc_faultstatus, /* faultstatus */ - cpufunc_faultaddress, /* faultaddress */ - - /* TLB functions */ - - arm67_tlb_flush, /* tlb_flushID */ - arm67_tlb_purge, /* tlb_flushID_SE */ - arm67_tlb_flush, /* tlb_flushI */ - arm67_tlb_purge, /* tlb_flushI_SE */ - arm67_tlb_flush, /* tlb_flushD */ - arm67_tlb_purge, /* tlb_flushD_SE */ - - /* Cache operations */ - - cpufunc_nullop, /* icache_sync_all */ - (void *) cpufunc_nullop, /* icache_sync_range */ - - arm67_cache_flush, /* dcache_wbinv_all */ - (void *)arm67_cache_flush, /* dcache_wbinv_range */ - (void *)arm67_cache_flush, /* dcache_inv_range */ - (void *)cpufunc_nullop, /* dcache_wb_range */ - - arm67_cache_flush, /* idcache_wbinv_all */ - (void *)arm67_cache_flush, /* idcache_wbinv_range */ - - /* Other functions */ - - cpufunc_nullop, /* flush_prefetchbuf */ - cpufunc_nullop, /* drain_writebuf */ - cpufunc_nullop, /* flush_brnchtgt_C */ - (void *)cpufunc_nullop, /* flush_brnchtgt_E */ - - (void *)cpufunc_nullop, /* sleep */ - - /* Soft functions */ - -#ifdef ARM6_LATE_ABORT - late_abort_fixup, /* dataabt_fixup */ -#else - early_abort_fixup, /* dataabt_fixup */ -#endif - cpufunc_null_fixup, /* prefetchabt_fixup */ - - arm67_context_switch, /* context_switch */ - - arm6_setup /* cpu setup */ - -}; -#endif /* CPU_ARM6 */ - -#ifdef CPU_ARM7 -struct cpu_functions arm7_cpufuncs = { - /* CPU functions */ - - cpufunc_id, /* id */ - cpufunc_nullop, /* cpwait */ - - /* MMU functions */ - - cpufunc_control, /* control */ - cpufunc_domains, /* domain */ - arm67_setttb, /* setttb */ - cpufunc_faultstatus, /* faultstatus */ - cpufunc_faultaddress, /* faultaddress */ - - /* TLB functions */ - - arm67_tlb_flush, /* tlb_flushID */ - arm67_tlb_purge, /* tlb_flushID_SE */ - arm67_tlb_flush, /* tlb_flushI */ - arm67_tlb_purge, /* tlb_flushI_SE */ - arm67_tlb_flush, /* tlb_flushD */ - arm67_tlb_purge, /* tlb_flushD_SE */ - - /* Cache operations */ - - cpufunc_nullop, /* icache_sync_all */ - (void *)cpufunc_nullop, /* icache_sync_range */ - - arm67_cache_flush, /* dcache_wbinv_all */ - (void *)arm67_cache_flush, /* dcache_wbinv_range */ - (void *)arm67_cache_flush, /* dcache_inv_range */ - (void *)cpufunc_nullop, /* dcache_wb_range */ - - arm67_cache_flush, /* idcache_wbinv_all */ - (void *)arm67_cache_flush, /* idcache_wbinv_range */ - - /* Other functions */ - - cpufunc_nullop, /* flush_prefetchbuf */ - cpufunc_nullop, /* drain_writebuf */ - cpufunc_nullop, /* flush_brnchtgt_C */ - (void *)cpufunc_nullop, /* flush_brnchtgt_E */ - - (void *)cpufunc_nullop, /* sleep */ - - /* Soft functions */ - - late_abort_fixup, /* dataabt_fixup */ - cpufunc_null_fixup, /* prefetchabt_fixup */ - - arm67_context_switch, /* context_switch */ - - arm7_setup /* cpu setup */ - -}; -#endif /* CPU_ARM7 */ - -#ifdef CPU_ARM7TDMI -struct cpu_functions arm7tdmi_cpufuncs = { - /* CPU functions */ - - cpufunc_id, /* id */ - cpufunc_nullop, /* cpwait */ - - /* MMU functions */ - - cpufunc_control, /* control */ - cpufunc_domains, /* domain */ - arm7tdmi_setttb, /* setttb */ - cpufunc_faultstatus, /* faultstatus */ - cpufunc_faultaddress, /* faultaddress */ - - /* TLB functions */ - - arm7tdmi_tlb_flushID, /* tlb_flushID */ - arm7tdmi_tlb_flushID_SE, /* tlb_flushID_SE */ - arm7tdmi_tlb_flushID, /* tlb_flushI */ - arm7tdmi_tlb_flushID_SE, /* tlb_flushI_SE */ - arm7tdmi_tlb_flushID, /* tlb_flushD */ - arm7tdmi_tlb_flushID_SE, /* tlb_flushD_SE */ - - /* Cache operations */ - - cpufunc_nullop, /* icache_sync_all */ - (void *)cpufunc_nullop, /* icache_sync_range */ - - arm7tdmi_cache_flushID, /* dcache_wbinv_all */ - (void *)arm7tdmi_cache_flushID, /* dcache_wbinv_range */ - (void *)arm7tdmi_cache_flushID, /* dcache_inv_range */ - (void *)cpufunc_nullop, /* dcache_wb_range */ - - arm7tdmi_cache_flushID, /* idcache_wbinv_all */ - (void *)arm7tdmi_cache_flushID, /* idcache_wbinv_range */ - - /* Other functions */ - - cpufunc_nullop, /* flush_prefetchbuf */ - cpufunc_nullop, /* drain_writebuf */ - cpufunc_nullop, /* flush_brnchtgt_C */ - (void *)cpufunc_nullop, /* flush_brnchtgt_E */ - - (void *)cpufunc_nullop, /* sleep */ - - /* Soft functions */ - - late_abort_fixup, /* dataabt_fixup */ - cpufunc_null_fixup, /* prefetchabt_fixup */ - - arm7tdmi_context_switch, /* context_switch */ - - arm7tdmi_setup /* cpu setup */ - -}; -#endif /* CPU_ARM7TDMI */ - #ifdef CPU_ARM8 struct cpu_functions arm8_cpufuncs = { /* CPU functions */ @@ -377,18 +137,11 @@ struct cpu_functions arm8_cpufuncs = { cpufunc_nullop, /* flush_prefetchbuf */ cpufunc_nullop, /* drain_writebuf */ - cpufunc_nullop, /* flush_brnchtgt_C */ - (void *)cpufunc_nullop, /* flush_brnchtgt_E */ (void *)cpufunc_nullop, /* sleep */ /* Soft functions */ - - cpufunc_null_fixup, /* dataabt_fixup */ - cpufunc_null_fixup, /* prefetchabt_fixup */ - arm8_context_switch, /* context_switch */ - arm8_setup /* cpu setup */ }; #endif /* CPU_ARM8 */ @@ -435,20 +188,12 @@ struct cpu_functions arm9_cpufuncs = { cpufunc_nullop, /* flush_prefetchbuf */ armv4_drain_writebuf, /* drain_writebuf */ - cpufunc_nullop, /* flush_brnchtgt_C */ - (void *)cpufunc_nullop, /* flush_brnchtgt_E */ (void *)cpufunc_nullop, /* sleep */ /* Soft functions */ - - cpufunc_null_fixup, /* dataabt_fixup */ - cpufunc_null_fixup, /* prefetchabt_fixup */ - arm9_context_switch, /* context_switch */ - arm9_setup /* cpu setup */ - }; #endif /* CPU_ARM9 */ @@ -494,20 +239,12 @@ struct cpu_functions armv5_ec_cpufuncs = { cpufunc_nullop, /* flush_prefetchbuf */ armv4_drain_writebuf, /* drain_writebuf */ - cpufunc_nullop, /* flush_brnchtgt_C */ - (void *)cpufunc_nullop, /* flush_brnchtgt_E */ (void *)cpufunc_nullop, /* sleep */ /* Soft functions */ - - cpufunc_null_fixup, /* dataabt_fixup */ - cpufunc_null_fixup, /* prefetchabt_fixup */ - arm10_context_switch, /* context_switch */ - arm10_setup /* cpu setup */ - }; #endif /* CPU_ARM9E || CPU_ARM10 */ @@ -553,20 +290,12 @@ struct cpu_functions arm10_cpufuncs = { cpufunc_nullop, /* flush_prefetchbuf */ armv4_drain_writebuf, /* drain_writebuf */ - cpufunc_nullop, /* flush_brnchtgt_C */ - (void *)cpufunc_nullop, /* flush_brnchtgt_E */ (void *)cpufunc_nullop, /* sleep */ /* Soft functions */ - - cpufunc_null_fixup, /* dataabt_fixup */ - cpufunc_null_fixup, /* prefetchabt_fixup */ - arm10_context_switch, /* context_switch */ - arm10_setup /* cpu setup */ - }; #endif /* CPU_ARM10 */ @@ -611,18 +340,11 @@ struct cpu_functions arm11_cpufuncs = { cpufunc_nullop, /* flush_prefetchbuf */ arm11_drain_writebuf, /* drain_writebuf */ - cpufunc_nullop, /* flush_brnchtgt_C */ - (void *)cpufunc_nullop, /* flush_brnchtgt_E */ arm11_cpu_sleep, /* sleep (wait for interrupt) */ /* Soft functions */ - - cpufunc_null_fixup, /* dataabt_fixup */ - cpufunc_null_fixup, /* prefetchabt_fixup */ - arm11_context_switch, /* context_switch */ - arm11_setup /* cpu setup */ }; #endif /* CPU_ARM11 */ @@ -668,80 +390,16 @@ struct cpu_functions armv7_cpufuncs = { cpufunc_nullop, /* flush_prefetchbuf */ armv7_drain_writebuf, /* drain_writebuf */ - cpufunc_nullop, /* flush_brnchtgt_C */ - (void *)cpufunc_nullop, /* flush_brnchtgt_E */ armv7_cpu_sleep, /* sleep (wait for interrupt) */ /* Soft functions */ - - cpufunc_null_fixup, /* dataabt_fixup */ - cpufunc_null_fixup, /* prefetchabt_fixup */ - armv7_context_switch, /* context_switch */ - armv7_setup /* cpu setup */ }; #endif /* CPU_ARMv7 */ -#ifdef CPU_SA110 -struct cpu_functions sa110_cpufuncs = { - /* CPU functions */ - - cpufunc_id, /* id */ - cpufunc_nullop, /* cpwait */ - - /* MMU functions */ - - cpufunc_control, /* control */ - cpufunc_domains, /* domain */ - sa1_setttb, /* setttb */ - cpufunc_faultstatus, /* faultstatus */ - cpufunc_faultaddress, /* faultaddress */ - - /* TLB functions */ - - armv4_tlb_flushID, /* tlb_flushID */ - sa1_tlb_flushID_SE, /* tlb_flushID_SE */ - armv4_tlb_flushI, /* tlb_flushI */ - (void *)armv4_tlb_flushI, /* tlb_flushI_SE */ - armv4_tlb_flushD, /* tlb_flushD */ - armv4_tlb_flushD_SE, /* tlb_flushD_SE */ - - /* Cache operations */ - - sa1_cache_syncI, /* icache_sync_all */ - sa1_cache_syncI_rng, /* icache_sync_range */ - - sa1_cache_purgeD, /* dcache_wbinv_all */ - sa1_cache_purgeD_rng, /* dcache_wbinv_range */ -/*XXX*/ sa1_cache_purgeD_rng, /* dcache_inv_range */ - sa1_cache_cleanD_rng, /* dcache_wb_range */ - - sa1_cache_purgeID, /* idcache_wbinv_all */ - sa1_cache_purgeID_rng, /* idcache_wbinv_range */ - - /* Other functions */ - - cpufunc_nullop, /* flush_prefetchbuf */ - armv4_drain_writebuf, /* drain_writebuf */ - cpufunc_nullop, /* flush_brnchtgt_C */ - (void *)cpufunc_nullop, /* flush_brnchtgt_E */ - - (void *)cpufunc_nullop, /* sleep */ - - /* Soft functions */ - - cpufunc_null_fixup, /* dataabt_fixup */ - cpufunc_null_fixup, /* prefetchabt_fixup */ - - sa110_context_switch, /* context_switch */ - - sa110_setup /* cpu setup */ -}; -#endif /* CPU_SA110 */ - #if defined(CPU_SA1100) || defined(CPU_SA1110) struct cpu_functions sa11x0_cpufuncs = { /* CPU functions */ @@ -783,18 +441,11 @@ struct cpu_functions sa11x0_cpufuncs = { sa11x0_drain_readbuf, /* flush_prefetchbuf */ armv4_drain_writebuf, /* drain_writebuf */ - cpufunc_nullop, /* flush_brnchtgt_C */ - (void *)cpufunc_nullop, /* flush_brnchtgt_E */ sa11x0_cpu_sleep, /* sleep */ /* Soft functions */ - - cpufunc_null_fixup, /* dataabt_fixup */ - cpufunc_null_fixup, /* prefetchabt_fixup */ - sa11x0_context_switch, /* context_switch */ - sa11x0_setup /* cpu setup */ }; #endif /* CPU_SA1100 || CPU_SA1110 */ @@ -838,20 +489,13 @@ struct cpu_functions ixp12x0_cpufuncs = { /* Other functions */ - ixp12x0_drain_readbuf, /* flush_prefetchbuf */ + ixp12x0_drain_readbuf, /* flush_prefetchbuf */ armv4_drain_writebuf, /* drain_writebuf */ - cpufunc_nullop, /* flush_brnchtgt_C */ - (void *)cpufunc_nullop, /* flush_brnchtgt_E */ (void *)cpufunc_nullop, /* sleep */ /* Soft functions */ - - cpufunc_null_fixup, /* dataabt_fixup */ - cpufunc_null_fixup, /* prefetchabt_fixup */ - ixp12x0_context_switch, /* context_switch */ - ixp12x0_setup /* cpu setup */ }; #endif /* CPU_IXP12X0 */ @@ -898,18 +542,11 @@ struct cpu_functions xscale_cpufuncs = { cpufunc_nullop, /* flush_prefetchbuf */ armv4_drain_writebuf, /* drain_writebuf */ - cpufunc_nullop, /* flush_brnchtgt_C */ - (void *)cpufunc_nullop, /* flush_brnchtgt_E */ xscale_cpu_sleep, /* sleep */ /* Soft functions */ - - cpufunc_null_fixup, /* dataabt_fixup */ - cpufunc_null_fixup, /* prefetchabt_fixup */ - xscale_context_switch, /* context_switch */ - xscale_setup /* cpu setup */ }; #endif @@ -923,7 +560,7 @@ struct cpu_functions cpufuncs; u_int cputype; u_int cpu_reset_needs_v4_MMU_disable; /* flag used in locore.s */ -#if defined(CPU_ARM7TDMI) || defined(CPU_ARM8) || defined(CPU_ARM9) || \ +#if defined(CPU_ARM8) || defined(CPU_ARM9) || \ defined(CPU_ARM9E) || defined(CPU_ARM10) || defined(CPU_ARM11) || \ defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \ defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) @@ -1005,9 +642,7 @@ get_cachetype_cp15() } #endif /* ARM7TDMI || ARM8 || ARM9 || XSCALE */ -#if defined(CPU_ARM2) || defined(CPU_ARM250) || defined(CPU_ARM3) || \ - defined(CPU_ARM6) || defined(CPU_ARM7) || defined(CPU_SA110) || \ - defined(CPU_SA1100) || defined(CPU_SA1110) || defined(CPU_IXP12X0) +#if defined(CPU_SA1100) || defined(CPU_SA1110) || defined(CPU_IXP12X0) /* Cache information for CPUs without cache type registers. */ struct cachetab { u_int32_t ct_cpuid; @@ -1023,16 +658,7 @@ struct cachetab { struct cachetab cachetab[] = { /* cpuid, cache type, u, dsiz, ls, wy, isiz, ls, wy */ - { CPU_ID_ARM2, 0, 1, 0, 0, 0, 0, 0, 0 }, - { CPU_ID_ARM250, 0, 1, 0, 0, 0, 0, 0, 0 }, - { CPU_ID_ARM3, CPU_CT_CTYPE_WT, 1, 4096, 16, 64, 0, 0, 0 }, - { CPU_ID_ARM610, CPU_CT_CTYPE_WT, 1, 4096, 16, 64, 0, 0, 0 }, - { CPU_ID_ARM710, CPU_CT_CTYPE_WT, 1, 8192, 32, 4, 0, 0, 0 }, - { CPU_ID_ARM7500, CPU_CT_CTYPE_WT, 1, 4096, 16, 4, 0, 0, 0 }, - { CPU_ID_ARM710A, CPU_CT_CTYPE_WT, 1, 8192, 16, 4, 0, 0, 0 }, - { CPU_ID_ARM7500FE, CPU_CT_CTYPE_WT, 1, 4096, 16, 4, 0, 0, 0 }, /* XXX is this type right for SA-1? */ - { CPU_ID_SA110, CPU_CT_CTYPE_WB1, 0, 16384, 32, 32, 16384, 32, 32 }, { CPU_ID_SA1100, CPU_CT_CTYPE_WB1, 0, 8192, 32, 32, 16384, 32, 32 }, { CPU_ID_SA1110, CPU_CT_CTYPE_WB1, 0, 8192, 32, 32, 16384, 32, 32 }, { CPU_ID_IXP1200, CPU_CT_CTYPE_WB1, 0, 16384, 32, 32, 16384, 32, 32 }, /* XXX */ @@ -1066,7 +692,7 @@ get_cachetype_table() arm_dcache_align_mask = arm_dcache_align - 1; } -#endif /* ARM2 || ARM250 || ARM3 || ARM6 || ARM7 || SA110 || SA1100 || SA1111 || IXP12X0 */ +#endif /* SA110 || SA1100 || SA1111 || IXP12X0 */ #ifdef CPU_ARMv7 void arm_get_cachetype_cp15v7 (void); @@ -1272,47 +898,6 @@ set_cpufuncs() * CPU type where we want to use it by default, then we set it. */ -#ifdef CPU_ARM3 - if ((cputype & CPU_ID_IMPLEMENTOR_MASK) == CPU_ID_ARM_LTD && - (cputype & 0x00000f00) == 0x00000300) { - cpufuncs = arm3_cpufuncs; - cpu_reset_needs_v4_MMU_disable = 0; - get_cachetype_table(); - return 0; - } -#endif /* CPU_ARM3 */ -#ifdef CPU_ARM6 - if ((cputype & CPU_ID_IMPLEMENTOR_MASK) == CPU_ID_ARM_LTD && - (cputype & 0x00000f00) == 0x00000600) { - cpufuncs = arm6_cpufuncs; - cpu_reset_needs_v4_MMU_disable = 0; - get_cachetype_table(); - pmap_pte_init_generic(); - return 0; - } -#endif /* CPU_ARM6 */ -#ifdef CPU_ARM7 - if ((cputype & CPU_ID_IMPLEMENTOR_MASK) == CPU_ID_ARM_LTD && - CPU_ID_IS7(cputype) && - (cputype & CPU_ID_7ARCH_MASK) == CPU_ID_7ARCH_V3) { - cpufuncs = arm7_cpufuncs; - cpu_reset_needs_v4_MMU_disable = 0; - get_cachetype_table(); - pmap_pte_init_generic(); - return 0; - } -#endif /* CPU_ARM7 */ -#ifdef CPU_ARM7TDMI - if ((cputype & CPU_ID_IMPLEMENTOR_MASK) == CPU_ID_ARM_LTD && - CPU_ID_IS7(cputype) && - (cputype & CPU_ID_7ARCH_MASK) == CPU_ID_7ARCH_V4T) { - cpufuncs = arm7tdmi_cpufuncs; - cpu_reset_needs_v4_MMU_disable = 0; - get_cachetype_cp15(); - pmap_pte_init_generic(); - return 0; - } -#endif #ifdef CPU_ARM8 if ((cputype & CPU_ID_IMPLEMENTOR_MASK) == CPU_ID_ARM_LTD && (cputype & 0x0000f000) == 0x00008000) { @@ -1406,15 +991,6 @@ set_cpufuncs() return 0; } #endif /* CPU_ARMv7 */ -#ifdef CPU_SA110 - if (cputype == CPU_ID_SA110) { - cpufuncs = sa110_cpufuncs; - cpu_reset_needs_v4_MMU_disable = 1; /* SA needs it */ - get_cachetype_table(); - pmap_pte_init_sa1(); - return 0; - } -#endif /* CPU_SA110 */ #ifdef CPU_SA1100 if (cputype == CPU_ID_SA1100) { cpufuncs = sa11x0_cpufuncs; @@ -1586,574 +1162,12 @@ set_cpufuncs() } /* - * Fixup routines for data and prefetch aborts. - * - * Several compile time symbols are used - * - * DEBUG_FAULT_CORRECTION - Print debugging information during the - * correction of registers after a fault. - * ARM6_LATE_ABORT - ARM6 supports both early and late aborts - * when defined should use late aborts - */ - - -/* - * Null abort fixup routine. - * For use when no fixup is required. - */ -int -cpufunc_null_fixup(arg) - void *arg; -{ - return(ABORT_FIXUP_OK); -} - - -#if defined(CPU_ARM2) || defined(CPU_ARM250) || defined(CPU_ARM3) || \ - defined(CPU_ARM6) || defined(CPU_ARM7) || defined(CPU_ARM7TDMI) - -#ifdef DEBUG_FAULT_CORRECTION -#define DFC_PRINTF(x) printf x -#define DFC_DISASSEMBLE(x) disassemble(x) -#else -#define DFC_PRINTF(x) /* nothing */ -#define DFC_DISASSEMBLE(x) /* nothing */ -#endif - -/* - * "Early" data abort fixup. - * - * For ARM2, ARM2as, ARM3 and ARM6 (in early-abort mode). Also used - * indirectly by ARM6 (in late-abort mode) and ARM7[TDMI]. - * - * In early aborts, we may have to fix up LDM, STM, LDC and STC. - */ -int -early_abort_fixup(arg) - void *arg; -{ - trapframe_t *frame = arg; - u_int fault_pc; - u_int fault_instruction; - int saved_lr = 0; - - if ((frame->tf_spsr & PSR_MODE) == PSR_SVC32_MODE) { - - /* Ok an abort in SVC mode */ - - /* - * Copy the SVC r14 into the usr r14 - The usr r14 is garbage - * as the fault happened in svc mode but we need it in the - * usr slot so we can treat the registers as an array of ints - * during fixing. - * NOTE: This PC is in the position but writeback is not - * allowed on r15. - * Doing it like this is more efficient than trapping this - * case in all possible locations in the following fixup code. - */ - - saved_lr = frame->tf_usr_lr; - frame->tf_usr_lr = frame->tf_svc_lr; - - /* - * Note the trapframe does not have the SVC r13 so a fault - * from an instruction with writeback to r13 in SVC mode is - * not allowed. This should not happen as the kstack is - * always valid. - */ - } - - /* Get fault address and status from the CPU */ - - fault_pc = frame->tf_pc; - fault_instruction = *((volatile unsigned int *)fault_pc); - - /* Decode the fault instruction and fix the registers as needed */ - - if ((fault_instruction & 0x0e000000) == 0x08000000) { - int base; - int loop; - int count; - int *registers = &frame->tf_r0; - - DFC_PRINTF(("LDM/STM\n")); - DFC_DISASSEMBLE(fault_pc); - if (fault_instruction & (1 << 21)) { - DFC_PRINTF(("This instruction must be corrected\n")); - base = (fault_instruction >> 16) & 0x0f; - if (base == 15) - return ABORT_FIXUP_FAILED; - /* Count registers transferred */ - count = 0; - for (loop = 0; loop < 16; ++loop) { - if (fault_instruction & (1<<loop)) - ++count; - } - DFC_PRINTF(("%d registers used\n", count)); - DFC_PRINTF(("Corrected r%d by %d bytes ", - base, count * 4)); - if (fault_instruction & (1 << 23)) { - DFC_PRINTF(("down\n")); - registers[base] -= count * 4; - } else { - DFC_PRINTF(("up\n")); - registers[base] += count * 4; - } - } - } else if ((fault_instruction & 0x0e000000) == 0x0c000000) { - int base; - int offset; - int *registers = &frame->tf_r0; - - /* REGISTER CORRECTION IS REQUIRED FOR THESE INSTRUCTIONS */ - - DFC_DISASSEMBLE(fault_pc); - - /* Only need to fix registers if write back is turned on */ - - if ((fault_instruction & (1 << 21)) != 0) { - base = (fault_instruction >> 16) & 0x0f; - if (base == 13 && - (frame->tf_spsr & PSR_MODE) == PSR_SVC32_MODE) - return ABORT_FIXUP_FAILED; - if (base == 15) - return ABORT_FIXUP_FAILED; - - offset = (fault_instruction & 0xff) << 2; - DFC_PRINTF(("r%d=%08x\n", base, registers[base])); - if ((fault_instruction & (1 << 23)) != 0) - offset = -offset; - registers[base] += offset; - DFC_PRINTF(("r%d=%08x\n", base, registers[base])); - } - } else if ((fault_instruction & 0x0e000000) == 0x0c000000) - return ABORT_FIXUP_FAILED; - - if ((frame->tf_spsr & PSR_MODE) == PSR_SVC32_MODE) { - - /* Ok an abort in SVC mode */ - - /* - * Copy the SVC r14 into the usr r14 - The usr r14 is garbage - * as the fault happened in svc mode but we need it in the - * usr slot so we can treat the registers as an array of ints - * during fixing. - * NOTE: This PC is in the position but writeback is not - * allowed on r15. - * Doing it like this is more efficient than trapping this - * case in all possible locations in the prior fixup code. - */ - - frame->tf_svc_lr = frame->tf_usr_lr; - frame->tf_usr_lr = saved_lr; - - /* - * Note the trapframe does not have the SVC r13 so a fault - * from an instruction with writeback to r13 in SVC mode is - * not allowed. This should not happen as the kstack is - * always valid. - */ - } - - return(ABORT_FIXUP_OK); -} -#endif /* CPU_ARM2/250/3/6/7 */ - - -#if (defined(CPU_ARM6) && defined(ARM6_LATE_ABORT)) || defined(CPU_ARM7) || \ - defined(CPU_ARM7TDMI) -/* - * "Late" (base updated) data abort fixup - * - * For ARM6 (in late-abort mode) and ARM7. - * - * In this model, all data-transfer instructions need fixing up. We defer - * LDM, STM, LDC and STC fixup to the early-abort handler. - */ -int -late_abort_fixup(arg) - void *arg; -{ - trapframe_t *frame = arg; - u_int fault_pc; - u_int fault_instruction; - int saved_lr = 0; - - if ((frame->tf_spsr & PSR_MODE) == PSR_SVC32_MODE) { - - /* Ok an abort in SVC mode */ - - /* - * Copy the SVC r14 into the usr r14 - The usr r14 is garbage - * as the fault happened in svc mode but we need it in the - * usr slot so we can treat the registers as an array of ints - * during fixing. - * NOTE: This PC is in the position but writeback is not - * allowed on r15. - * Doing it like this is more efficient than trapping this - * case in all possible locations in the following fixup code. - */ - - saved_lr = frame->tf_usr_lr; - frame->tf_usr_lr = frame->tf_svc_lr; - - /* - * Note the trapframe does not have the SVC r13 so a fault - * from an instruction with writeback to r13 in SVC mode is - * not allowed. This should not happen as the kstack is - * always valid. - */ - } - - /* Get fault address and status from the CPU */ - - fault_pc = frame->tf_pc; - fault_instruction = *((volatile unsigned int *)fault_pc); - - /* Decode the fault instruction and fix the registers as needed */ - - /* Was is a swap instruction ? */ - - if ((fault_instruction & 0x0fb00ff0) == 0x01000090) { - DFC_DISASSEMBLE(fault_pc); - } else if ((fault_instruction & 0x0c000000) == 0x04000000) { - - /* Was is a ldr/str instruction */ - /* This is for late abort only */ - - int base; - int offset; - int *registers = &frame->tf_r0; - - DFC_DISASSEMBLE(fault_pc); - - /* This is for late abort only */ - - if ((fault_instruction & (1 << 24)) == 0 - || (fault_instruction & (1 << 21)) != 0) { - /* postindexed ldr/str with no writeback */ - - base = (fault_instruction >> 16) & 0x0f; - if (base == 13 && - (frame->tf_spsr & PSR_MODE) == PSR_SVC32_MODE) - return ABORT_FIXUP_FAILED; - if (base == 15) - return ABORT_FIXUP_FAILED; - DFC_PRINTF(("late abt fix: r%d=%08x : ", - base, registers[base])); - if ((fault_instruction & (1 << 25)) == 0) { - /* Immediate offset - easy */ - - offset = fault_instruction & 0xfff; - if ((fault_instruction & (1 << 23))) - offset = -offset; - registers[base] += offset; - DFC_PRINTF(("imm=%08x ", offset)); - } else { - /* offset is a shifted register */ - int shift; - - offset = fault_instruction & 0x0f; - if (offset == base) - return ABORT_FIXUP_FAILED; - - /* - * Register offset - hard we have to - * cope with shifts ! - */ - offset = registers[offset]; - - if ((fault_instruction & (1 << 4)) == 0) - /* shift with amount */ - shift = (fault_instruction >> 7) & 0x1f; - else { - /* shift with register */ - if ((fault_instruction & (1 << 7)) != 0) - /* undefined for now so bail out */ - return ABORT_FIXUP_FAILED; - shift = ((fault_instruction >> 8) & 0xf); - if (base == shift) - return ABORT_FIXUP_FAILED; - DFC_PRINTF(("shift reg=%d ", shift)); - shift = registers[shift]; - } - DFC_PRINTF(("shift=%08x ", shift)); - switch (((fault_instruction >> 5) & 0x3)) { - case 0 : /* Logical left */ - offset = (int)(((u_int)offset) << shift); - break; - case 1 : /* Logical Right */ - if (shift == 0) shift = 32; - offset = (int)(((u_int)offset) >> shift); - break; - case 2 : /* Arithmetic Right */ - if (shift == 0) shift = 32; - offset = (int)(((int)offset) >> shift); - break; - case 3 : /* Rotate right (rol or rxx) */ - return ABORT_FIXUP_FAILED; - break; - } - - DFC_PRINTF(("abt: fixed LDR/STR with " - "register offset\n")); - if ((fault_instruction & (1 << 23))) - offset = -offset; - DFC_PRINTF(("offset=%08x ", offset)); - registers[base] += offset; - } - DFC_PRINTF(("r%d=%08x\n", base, registers[base])); - } - } - - if ((frame->tf_spsr & PSR_MODE) == PSR_SVC32_MODE) { - - /* Ok an abort in SVC mode */ - - /* - * Copy the SVC r14 into the usr r14 - The usr r14 is garbage - * as the fault happened in svc mode but we need it in the - * usr slot so we can treat the registers as an array of ints - * during fixing. - * NOTE: This PC is in the position but writeback is not - * allowed on r15. - * Doing it like this is more efficient than trapping this - * case in all possible locations in the prior fixup code. - */ - - frame->tf_svc_lr = frame->tf_usr_lr; - frame->tf_usr_lr = saved_lr; - - /* - * Note the trapframe does not have the SVC r13 so a fault - * from an instruction with writeback to r13 in SVC mode is - * not allowed. This should not happen as the kstack is - * always valid. - */ - } - - /* - * Now let the early-abort fixup routine have a go, in case it - * was an LDM, STM, LDC or STC that faulted. - */ - - return early_abort_fixup(arg); -} -#endif /* CPU_ARM6(LATE)/7/7TDMI */ - -/* * CPU Setup code */ -#if defined(CPU_ARM6) || defined(CPU_ARM7) || defined(CPU_ARM7TDMI) || \ - defined(CPU_ARM8) || defined (CPU_ARM9) || defined (CPU_ARM9E) || \ - defined(CPU_SA110) || defined(CPU_SA1100) || defined(CPU_SA1110) || \ - defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \ - defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \ - defined(CPU_ARM10) || defined(CPU_ARM11) || defined(CPU_ARMv7) - -#define IGN 0 -#define OR 1 -#define BIC 2 - -struct cpu_option { - char *co_name; - int co_falseop; - int co_trueop; - int co_value; -}; - -static u_int parse_cpu_options (char *, struct cpu_option *, u_int); - -static u_int -parse_cpu_options(args, optlist, cpuctrl) - char *args; - struct cpu_option *optlist; - u_int cpuctrl; -{ - int integer; - - if (args == NULL) - return(cpuctrl); - - while (optlist->co_name) { - if (get_bootconf_option(args, optlist->co_name, - BOOTOPT_TYPE_BOOLEAN, &integer)) { - if (integer) { - if (optlist->co_trueop == OR) - cpuctrl |= optlist->co_value; - else if (optlist->co_trueop == BIC) - cpuctrl &= ~optlist->co_value; - } else { - if (optlist->co_falseop == OR) - cpuctrl |= optlist->co_value; - else if (optlist->co_falseop == BIC) - cpuctrl &= ~optlist->co_value; - } - } - ++optlist; - } - return(cpuctrl); -} -#endif /* CPU_ARM6 || CPU_ARM7 || CPU_ARM7TDMI || CPU_ARM8 || CPU_SA110 */ - -#if defined (CPU_ARM6) || defined(CPU_ARM7) || defined(CPU_ARM7TDMI) \ - || defined(CPU_ARM8) -struct cpu_option arm678_options[] = { - { "cpu.cache", BIC, OR, CPU_CONTROL_IDC_ENABLE }, - { "cpu.nocache", OR, BIC, CPU_CONTROL_IDC_ENABLE }, - { "cpu.writebuf", BIC, OR, CPU_CONTROL_WBUF_ENABLE }, - { "cpu.nowritebuf", OR, BIC, CPU_CONTROL_WBUF_ENABLE }, - { NULL, IGN, IGN, 0 } -}; - -#endif /* CPU_ARM6 || CPU_ARM7 || CPU_ARM7TDMI || CPU_ARM8 */ - -#ifdef CPU_ARM6 -struct cpu_option arm6_options[] = { - { "arm6.cache", BIC, OR, CPU_CONTROL_IDC_ENABLE }, - { "arm6.nocache", OR, BIC, CPU_CONTROL_IDC_ENABLE }, - { "arm6.writebuf", BIC, OR, CPU_CONTROL_WBUF_ENABLE }, - { "arm6.nowritebuf", OR, BIC, CPU_CONTROL_WBUF_ENABLE }, - { NULL, IGN, IGN, 0 } -}; - -void -arm6_setup(args) - char *args; -{ - int cpuctrl, cpuctrlmask; - - /* Set up default control registers bits */ - cpuctrl = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_32BP_ENABLE - | CPU_CONTROL_32BD_ENABLE | CPU_CONTROL_SYST_ENABLE - | CPU_CONTROL_IDC_ENABLE | CPU_CONTROL_WBUF_ENABLE; - cpuctrlmask = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_32BP_ENABLE - | CPU_CONTROL_32BD_ENABLE | CPU_CONTROL_SYST_ENABLE - | CPU_CONTROL_IDC_ENABLE | CPU_CONTROL_WBUF_ENABLE - | CPU_CONTROL_ROM_ENABLE | CPU_CONTROL_BEND_ENABLE - | CPU_CONTROL_AFLT_ENABLE; - -#ifdef ARM6_LATE_ABORT - cpuctrl |= CPU_CONTROL_LABT_ENABLE; -#endif /* ARM6_LATE_ABORT */ - -#ifndef ARM32_DISABLE_ALIGNMENT_FAULTS - cpuctrl |= CPU_CONTROL_AFLT_ENABLE; -#endif - - cpuctrl = parse_cpu_options(args, arm678_options, cpuctrl); - cpuctrl = parse_cpu_options(args, arm6_options, cpuctrl); - -#ifdef __ARMEB__ - cpuctrl |= CPU_CONTROL_BEND_ENABLE; -#endif - - /* Clear out the cache */ - cpu_idcache_wbinv_all(); - - /* Set the control register */ - curcpu()->ci_ctrl = cpuctrl; - cpu_control(0xffffffff, cpuctrl); -} -#endif /* CPU_ARM6 */ - -#ifdef CPU_ARM7 -struct cpu_option arm7_options[] = { - { "arm7.cache", BIC, OR, CPU_CONTROL_IDC_ENABLE }, - { "arm7.nocache", OR, BIC, CPU_CONTROL_IDC_ENABLE }, - { "arm7.writebuf", BIC, OR, CPU_CONTROL_WBUF_ENABLE }, - { "arm7.nowritebuf", OR, BIC, CPU_CONTROL_WBUF_ENABLE }, - { "arm700.fpaclk", BIC, OR, CPU_CONTROL_CPCLK }, - { NULL, IGN, IGN, 0 } -}; - -void -arm7_setup(args) - char *args; -{ - int cpuctrl, cpuctrlmask; - - cpuctrl = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_32BP_ENABLE - | CPU_CONTROL_32BD_ENABLE | CPU_CONTROL_SYST_ENABLE - | CPU_CONTROL_IDC_ENABLE | CPU_CONTROL_WBUF_ENABLE; - cpuctrlmask = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_32BP_ENABLE - | CPU_CONTROL_32BD_ENABLE | CPU_CONTROL_SYST_ENABLE - | CPU_CONTROL_IDC_ENABLE | CPU_CONTROL_WBUF_ENABLE - | CPU_CONTROL_CPCLK | CPU_CONTROL_LABT_ENABLE - | CPU_CONTROL_ROM_ENABLE | CPU_CONTROL_BEND_ENABLE - | CPU_CONTROL_AFLT_ENABLE; - -#ifndef ARM32_DISABLE_ALIGNMENT_FAULTS - cpuctrl |= CPU_CONTROL_AFLT_ENABLE; -#endif - - cpuctrl = parse_cpu_options(args, arm678_options, cpuctrl); - cpuctrl = parse_cpu_options(args, arm7_options, cpuctrl); - -#ifdef __ARMEB__ - cpuctrl |= CPU_CONTROL_BEND_ENABLE; -#endif - - /* Clear out the cache */ - cpu_idcache_wbinv_all(); - - /* Set the control register */ - curcpu()->ci_ctrl = cpuctrl; - cpu_control(0xffffffff, cpuctrl); -} -#endif /* CPU_ARM7 */ - -#ifdef CPU_ARM7TDMI -struct cpu_option arm7tdmi_options[] = { - { "arm7.cache", BIC, OR, CPU_CONTROL_IDC_ENABLE }, - { "arm7.nocache", OR, BIC, CPU_CONTROL_IDC_ENABLE }, - { "arm7.writebuf", BIC, OR, CPU_CONTROL_WBUF_ENABLE }, - { "arm7.nowritebuf", OR, BIC, CPU_CONTROL_WBUF_ENABLE }, - { "arm700.fpaclk", BIC, OR, CPU_CONTROL_CPCLK }, - { NULL, IGN, IGN, 0 } -}; - -void -arm7tdmi_setup(args) - char *args; -{ - int cpuctrl; - - cpuctrl = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_32BP_ENABLE - | CPU_CONTROL_32BD_ENABLE | CPU_CONTROL_SYST_ENABLE - | CPU_CONTROL_IDC_ENABLE | CPU_CONTROL_WBUF_ENABLE; - - cpuctrl = parse_cpu_options(args, arm678_options, cpuctrl); - cpuctrl = parse_cpu_options(args, arm7tdmi_options, cpuctrl); - -#ifdef __ARMEB__ - cpuctrl |= CPU_CONTROL_BEND_ENABLE; -#endif - - /* Clear out the cache */ - cpu_idcache_wbinv_all(); - - /* Set the control register */ - curcpu()->ci_ctrl = cpuctrl; - cpu_control(0xffffffff, cpuctrl); -} -#endif /* CPU_ARM7TDMI */ - #ifdef CPU_ARM8 -struct cpu_option arm8_options[] = { - { "arm8.cache", BIC, OR, CPU_CONTROL_IDC_ENABLE }, - { "arm8.nocache", OR, BIC, CPU_CONTROL_IDC_ENABLE }, - { "arm8.writebuf", BIC, OR, CPU_CONTROL_WBUF_ENABLE }, - { "arm8.nowritebuf", OR, BIC, CPU_CONTROL_WBUF_ENABLE }, - { "cpu.branchpredict", BIC, OR, CPU_CONTROL_BPRD_ENABLE }, - { "arm8.branchpredict", BIC, OR, CPU_CONTROL_BPRD_ENABLE }, - { NULL, IGN, IGN, 0 } -}; - void -arm8_setup(args) - char *args; +arm8_setup() { int integer; int cpuctrl, cpuctrlmask; @@ -2162,20 +1176,14 @@ arm8_setup(args) cpuctrl = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_32BP_ENABLE | CPU_CONTROL_32BD_ENABLE | CPU_CONTROL_SYST_ENABLE - | CPU_CONTROL_IDC_ENABLE | CPU_CONTROL_WBUF_ENABLE; + | CPU_CONTROL_IDC_ENABLE | CPU_CONTROL_WBUF_ENABLE + | CPU_CONTROL_AFLT_ENABLE; cpuctrlmask = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_32BP_ENABLE | CPU_CONTROL_32BD_ENABLE | CPU_CONTROL_SYST_ENABLE | CPU_CONTROL_IDC_ENABLE | CPU_CONTROL_WBUF_ENABLE | CPU_CONTROL_BPRD_ENABLE | CPU_CONTROL_ROM_ENABLE | CPU_CONTROL_BEND_ENABLE | CPU_CONTROL_AFLT_ENABLE; -#ifndef ARM32_DISABLE_ALIGNMENT_FAULTS - cpuctrl |= CPU_CONTROL_AFLT_ENABLE; -#endif - - cpuctrl = parse_cpu_options(args, arm678_options, cpuctrl); - cpuctrl = parse_cpu_options(args, arm8_options, cpuctrl); - #ifdef __ARMEB__ cpuctrl |= CPU_CONTROL_BEND_ENABLE; #endif @@ -2183,34 +1191,6 @@ arm8_setup(args) /* Get clock configuration */ clocktest = arm8_clock_config(0, 0) & 0x0f; - /* Special ARM8 clock and test configuration */ - if (get_bootconf_option(args, "arm8.clock.reset", BOOTOPT_TYPE_BOOLEAN, &integer)) { - clocktest = 0; - setclock = 1; - } - if (get_bootconf_option(args, "arm8.clock.dynamic", BOOTOPT_TYPE_BOOLEAN, &integer)) { - if (integer) - clocktest |= 0x01; - else - clocktest &= ~(0x01); - setclock = 1; - } - if (get_bootconf_option(args, "arm8.clock.sync", BOOTOPT_TYPE_BOOLEAN, &integer)) { - if (integer) - clocktest |= 0x02; - else - clocktest &= ~(0x02); - setclock = 1; - } - if (get_bootconf_option(args, "arm8.clock.fast", BOOTOPT_TYPE_BININT, &integer)) { - clocktest = (clocktest & ~0xc0) | (integer & 3) << 2; - setclock = 1; - } - if (get_bootconf_option(args, "arm8.test", BOOTOPT_TYPE_BININT, &integer)) { - clocktest |= (integer & 7) << 5; - setclock = 1; - } - /* Clear out the cache */ cpu_idcache_wbinv_all(); @@ -2225,28 +1205,15 @@ arm8_setup(args) #endif /* CPU_ARM8 */ #ifdef CPU_ARM9 -struct cpu_option arm9_options[] = { - { "cpu.cache", BIC, OR, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) }, - { "cpu.nocache", OR, BIC, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) }, - { "arm9.cache", BIC, OR, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) }, - { "arm9.icache", BIC, OR, CPU_CONTROL_IC_ENABLE }, - { "arm9.dcache", BIC, OR, CPU_CONTROL_DC_ENABLE }, - { "cpu.writebuf", BIC, OR, CPU_CONTROL_WBUF_ENABLE }, - { "cpu.nowritebuf", OR, BIC, CPU_CONTROL_WBUF_ENABLE }, - { "arm9.writebuf", BIC, OR, CPU_CONTROL_WBUF_ENABLE }, - { NULL, IGN, IGN, 0 } -}; - void -arm9_setup(args) - char *args; +arm9_setup() { int cpuctrl, cpuctrlmask; cpuctrl = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_32BP_ENABLE | CPU_CONTROL_32BD_ENABLE | CPU_CONTROL_SYST_ENABLE | CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE - | CPU_CONTROL_WBUF_ENABLE; + | CPU_CONTROL_WBUF_ENABLE | CPU_CONTROL_AFLT_ENABLE; cpuctrlmask = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_32BP_ENABLE | CPU_CONTROL_32BD_ENABLE | CPU_CONTROL_SYST_ENABLE | CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE @@ -2255,12 +1222,6 @@ arm9_setup(args) | CPU_CONTROL_LABT_ENABLE | CPU_CONTROL_VECRELOC | CPU_CONTROL_ROUNDROBIN; -#ifndef ARM32_DISABLE_ALIGNMENT_FAULTS - cpuctrl |= CPU_CONTROL_AFLT_ENABLE; -#endif - - cpuctrl = parse_cpu_options(args, arm9_options, cpuctrl); - #ifdef __ARMEB__ cpuctrl |= CPU_CONTROL_BEND_ENABLE; #endif @@ -2279,27 +1240,15 @@ arm9_setup(args) #endif /* CPU_ARM9 */ #if defined(CPU_ARM9E) || defined(CPU_ARM10) -struct cpu_option arm10_options[] = { - { "cpu.cache", BIC, OR, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) }, - { "cpu.nocache", OR, BIC, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) }, - { "arm10.cache", BIC, OR, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) }, - { "arm10.icache", BIC, OR, CPU_CONTROL_IC_ENABLE }, - { "arm10.dcache", BIC, OR, CPU_CONTROL_DC_ENABLE }, - { "cpu.writebuf", BIC, OR, CPU_CONTROL_WBUF_ENABLE }, - { "cpu.nowritebuf", OR, BIC, CPU_CONTROL_WBUF_ENABLE }, - { "arm10.writebuf", BIC, OR, CPU_CONTROL_WBUF_ENABLE }, - { NULL, IGN, IGN, 0 } -}; - void -arm10_setup(args) - char *args; +arm10_setup() { int cpuctrl, cpuctrlmask; cpuctrl = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_SYST_ENABLE | CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE - | CPU_CONTROL_WBUF_ENABLE | CPU_CONTROL_BPRD_ENABLE; + | CPU_CONTROL_WBUF_ENABLE | CPU_CONTROL_BPRD_ENABLE + | CPU_CONTROL_AFLT_ENABLE; cpuctrlmask = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_SYST_ENABLE | CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE | CPU_CONTROL_WBUF_ENABLE | CPU_CONTROL_ROM_ENABLE @@ -2307,12 +1256,6 @@ arm10_setup(args) | CPU_CONTROL_BPRD_ENABLE | CPU_CONTROL_ROUNDROBIN | CPU_CONTROL_CPCLK; -#ifndef ARM32_DISABLE_ALIGNMENT_FAULTS - cpuctrl |= CPU_CONTROL_AFLT_ENABLE; -#endif - - cpuctrl = parse_cpu_options(args, arm10_options, cpuctrl); - #ifdef __ARMEB__ cpuctrl |= CPU_CONTROL_BEND_ENABLE; #endif @@ -2339,36 +1282,20 @@ arm10_setup(args) #endif /* CPU_ARM9E || CPU_ARM10 */ #ifdef CPU_ARM11 -struct cpu_option arm11_options[] = { - { "cpu.cache", BIC, OR, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) }, - { "cpu.nocache", OR, BIC, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) }, - { "arm11.cache", BIC, OR, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) }, - { "arm11.icache", BIC, OR, CPU_CONTROL_IC_ENABLE }, - { "arm11.dcache", BIC, OR, CPU_CONTROL_DC_ENABLE }, - { NULL, IGN, IGN, 0 } -}; - void -arm11_setup(args) - char *args; +arm11_setup() { int cpuctrl, cpuctrlmask; cpuctrl = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_SYST_ENABLE | CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE - /* | CPU_CONTROL_BPRD_ENABLE */; + | CPU_CONTROL_AFLT_ENABLE /* | CPU_CONTROL_BPRD_ENABLE */; cpuctrlmask = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_SYST_ENABLE | CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE | CPU_CONTROL_ROM_ENABLE | CPU_CONTROL_BPRD_ENABLE | CPU_CONTROL_BEND_ENABLE | CPU_CONTROL_AFLT_ENABLE | CPU_CONTROL_ROUNDROBIN | CPU_CONTROL_CPCLK; -#ifndef ARM32_DISABLE_ALIGNMENT_FAULTS - cpuctrl |= CPU_CONTROL_AFLT_ENABLE; -#endif - - cpuctrl = parse_cpu_options(args, arm11_options, cpuctrl); - #ifdef __ARMEB__ cpuctrl |= CPU_CONTROL_BEND_ENABLE; #endif @@ -2389,18 +1316,14 @@ arm11_setup(args) #endif /* CPU_ARM11 */ #ifdef CPU_ARMv7 -struct cpu_option armv7_options[] = { -}; - void -armv7_setup(args) - char *args; +armv7_setup() { int cpuctrl, cpuctrlmask; cpuctrl = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_SYST_ENABLE | CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE - | CPU_CONTROL_BPRD_ENABLE ; + | CPU_CONTROL_BPRD_ENABLE | CPU_CONTROL_AFLT_ENABLE; cpuctrlmask = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_SYST_ENABLE | CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE | CPU_CONTROL_ROM_ENABLE | CPU_CONTROL_BPRD_ENABLE @@ -2408,15 +1331,9 @@ armv7_setup(args) | CPU_CONTROL_ROUNDROBIN | CPU_CONTROL_CPCLK | CPU_CONTROL_VECRELOC | CPU_CONTROL_FI | CPU_CONTROL_VE; -#ifndef ARM32_DISABLE_ALIGNMENT_FAULTS - cpuctrl |= CPU_CONTROL_AFLT_ENABLE; -#endif - if (vector_page == ARM_VECTORS_HIGH) cpuctrl |= CPU_CONTROL_VECRELOC; - cpuctrl = parse_cpu_options(args, armv7_options, cpuctrl); - /* Clear out the cache */ cpu_idcache_wbinv_all(); @@ -2435,86 +1352,17 @@ armv7_setup(args) } #endif /* CPU_ARMv7 */ -#ifdef CPU_SA110 -struct cpu_option sa110_options[] = { - { "cpu.cache", BIC, OR, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) }, - { "cpu.nocache", OR, BIC, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) }, - { "sa110.cache", BIC, OR, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) }, - { "sa110.icache", BIC, OR, CPU_CONTROL_IC_ENABLE }, - { "sa110.dcache", BIC, OR, CPU_CONTROL_DC_ENABLE }, - { "cpu.writebuf", BIC, OR, CPU_CONTROL_WBUF_ENABLE }, - { "cpu.nowritebuf", OR, BIC, CPU_CONTROL_WBUF_ENABLE }, - { "sa110.writebuf", BIC, OR, CPU_CONTROL_WBUF_ENABLE }, - { NULL, IGN, IGN, 0 } -}; - -void -sa110_setup(args) - char *args; -{ - int cpuctrl, cpuctrlmask; - - cpuctrl = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_32BP_ENABLE - | CPU_CONTROL_32BD_ENABLE | CPU_CONTROL_SYST_ENABLE - | CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE - | CPU_CONTROL_WBUF_ENABLE; - cpuctrlmask = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_32BP_ENABLE - | CPU_CONTROL_32BD_ENABLE | CPU_CONTROL_SYST_ENABLE - | CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE - | CPU_CONTROL_WBUF_ENABLE | CPU_CONTROL_ROM_ENABLE - | CPU_CONTROL_BEND_ENABLE | CPU_CONTROL_AFLT_ENABLE - | CPU_CONTROL_LABT_ENABLE | CPU_CONTROL_BPRD_ENABLE - | CPU_CONTROL_CPCLK; - -#ifndef ARM32_DISABLE_ALIGNMENT_FAULTS - cpuctrl |= CPU_CONTROL_AFLT_ENABLE; -#endif - - cpuctrl = parse_cpu_options(args, sa110_options, cpuctrl); - -#ifdef __ARMEB__ - cpuctrl |= CPU_CONTROL_BEND_ENABLE; -#endif - - /* Clear out the cache */ - cpu_idcache_wbinv_all(); - - /* Set the control register */ - curcpu()->ci_ctrl = cpuctrl; -/* cpu_control(cpuctrlmask, cpuctrl);*/ - cpu_control(0xffffffff, cpuctrl); - - /* - * enable clockswitching, note that this doesn't read or write to r0, - * r0 is just to make it valid asm - */ - __asm ("mcr 15, 0, r0, c15, c1, 2"); -} -#endif /* CPU_SA110 */ - #if defined(CPU_SA1100) || defined(CPU_SA1110) -struct cpu_option sa11x0_options[] = { - { "cpu.cache", BIC, OR, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) }, - { "cpu.nocache", OR, BIC, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) }, - { "sa11x0.cache", BIC, OR, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) }, - { "sa11x0.icache", BIC, OR, CPU_CONTROL_IC_ENABLE }, - { "sa11x0.dcache", BIC, OR, CPU_CONTROL_DC_ENABLE }, - { "cpu.writebuf", BIC, OR, CPU_CONTROL_WBUF_ENABLE }, - { "cpu.nowritebuf", OR, BIC, CPU_CONTROL_WBUF_ENABLE }, - { "sa11x0.writebuf", BIC, OR, CPU_CONTROL_WBUF_ENABLE }, - { NULL, IGN, IGN, 0 } -}; - void -sa11x0_setup(args) - char *args; +sa11x0_setup() { int cpuctrl, cpuctrlmask; cpuctrl = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_32BP_ENABLE | CPU_CONTROL_32BD_ENABLE | CPU_CONTROL_SYST_ENABLE | CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE - | CPU_CONTROL_WBUF_ENABLE | CPU_CONTROL_LABT_ENABLE; + | CPU_CONTROL_WBUF_ENABLE | CPU_CONTROL_LABT_ENABLE + | CPU_CONTROL_AFLT_ENABLE; cpuctrlmask = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_32BP_ENABLE | CPU_CONTROL_32BD_ENABLE | CPU_CONTROL_SYST_ENABLE | CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE @@ -2523,12 +1371,6 @@ sa11x0_setup(args) | CPU_CONTROL_LABT_ENABLE | CPU_CONTROL_BPRD_ENABLE | CPU_CONTROL_CPCLK | CPU_CONTROL_VECRELOC; -#ifndef ARM32_DISABLE_ALIGNMENT_FAULTS - cpuctrl |= CPU_CONTROL_AFLT_ENABLE; -#endif - - cpuctrl = parse_cpu_options(args, sa11x0_options, cpuctrl); - #ifdef __ARMEB__ cpuctrl |= CPU_CONTROL_BEND_ENABLE; #endif @@ -2545,41 +1387,21 @@ sa11x0_setup(args) #endif /* CPU_SA1100 || CPU_SA1110 */ #if defined(CPU_IXP12X0) -struct cpu_option ixp12x0_options[] = { - { "cpu.cache", BIC, OR, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) }, - { "cpu.nocache", OR, BIC, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) }, - { "ixp12x0.cache", BIC, OR, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) }, - { "ixp12x0.icache", BIC, OR, CPU_CONTROL_IC_ENABLE }, - { "ixp12x0.dcache", BIC, OR, CPU_CONTROL_DC_ENABLE }, - { "cpu.writebuf", BIC, OR, CPU_CONTROL_WBUF_ENABLE }, - { "cpu.nowritebuf", OR, BIC, CPU_CONTROL_WBUF_ENABLE }, - { "ixp12x0.writebuf", BIC, OR, CPU_CONTROL_WBUF_ENABLE }, - { NULL, IGN, IGN, 0 } -}; - void -ixp12x0_setup(args) - char *args; +ixp12x0_setup() { int cpuctrl, cpuctrlmask; cpuctrl = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_DC_ENABLE | CPU_CONTROL_WBUF_ENABLE | CPU_CONTROL_SYST_ENABLE - | CPU_CONTROL_IC_ENABLE; - + | CPU_CONTROL_IC_ENABLE | CPU_CONTROL_AFLT_ENABLE; cpuctrlmask = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_AFLT_ENABLE | CPU_CONTROL_DC_ENABLE | CPU_CONTROL_WBUF_ENABLE | CPU_CONTROL_BEND_ENABLE | CPU_CONTROL_SYST_ENABLE | CPU_CONTROL_ROM_ENABLE | CPU_CONTROL_IC_ENABLE | CPU_CONTROL_VECRELOC; -#ifndef ARM32_DISABLE_ALIGNMENT_FAULTS - cpuctrl |= CPU_CONTROL_AFLT_ENABLE; -#endif - - cpuctrl = parse_cpu_options(args, ixp12x0_options, cpuctrl); - #ifdef __ARMEB__ cpuctrl |= CPU_CONTROL_BEND_ENABLE; #endif @@ -2599,20 +1421,8 @@ ixp12x0_setup(args) #if defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \ defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) -struct cpu_option xscale_options[] = { - { "cpu.branchpredict", BIC, OR, CPU_CONTROL_BPRD_ENABLE }, - { "cpu.cache", BIC, OR, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) }, - { "cpu.nocache", OR, BIC, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) }, - { "xscale.branchpredict", BIC, OR, CPU_CONTROL_BPRD_ENABLE }, - { "xscale.cache", BIC, OR, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) }, - { "xscale.icache", BIC, OR, CPU_CONTROL_IC_ENABLE }, - { "xscale.dcache", BIC, OR, CPU_CONTROL_DC_ENABLE }, - { NULL, IGN, IGN, 0 } -}; - void -xscale_setup(args) - char *args; +xscale_setup() { uint32_t auxctl; int cpuctrl, cpuctrlmask; @@ -2627,7 +1437,7 @@ xscale_setup(args) | CPU_CONTROL_32BD_ENABLE | CPU_CONTROL_SYST_ENABLE | CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE | CPU_CONTROL_WBUF_ENABLE | CPU_CONTROL_LABT_ENABLE - | CPU_CONTROL_BPRD_ENABLE; + | CPU_CONTROL_BPRD_ENABLE | CPU_CONTROL_AFLT_ENABLE; cpuctrlmask = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_32BP_ENABLE | CPU_CONTROL_32BD_ENABLE | CPU_CONTROL_SYST_ENABLE | CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE @@ -2636,12 +1446,6 @@ xscale_setup(args) | CPU_CONTROL_LABT_ENABLE | CPU_CONTROL_BPRD_ENABLE | CPU_CONTROL_CPCLK | CPU_CONTROL_VECRELOC; -#ifndef ARM32_DISABLE_ALIGNMENT_FAULTS - cpuctrl |= CPU_CONTROL_AFLT_ENABLE; -#endif - - cpuctrl = parse_cpu_options(args, xscale_options, cpuctrl); - #ifdef __ARMEB__ cpuctrl |= CPU_CONTROL_BEND_ENABLE; #endif diff --git a/sys/arch/arm/arm/cpuswitch.S b/sys/arch/arm/arm/cpuswitch.S index 09d1b5e76c3..0e95603c9fc 100644 --- a/sys/arch/arm/arm/cpuswitch.S +++ b/sys/arch/arm/arm/cpuswitch.S @@ -1,4 +1,4 @@ -/* $OpenBSD: cpuswitch.S,v 1.11 2010/11/28 20:45:46 miod Exp $ */ +/* $OpenBSD: cpuswitch.S,v 1.12 2011/09/20 22:02:10 miod Exp $ */ /* $NetBSD: cpuswitch.S,v 1.41 2003/11/15 08:44:18 scw Exp $ */ /* @@ -451,12 +451,6 @@ ENTRY(cpu_switchto) /* rem: r6 = new proc */ /* rem: r7 = new pcb */ -#ifdef ARMFPE - add r0, r7, #(USER_SIZE) & 0x00ff - add r0, r0, #(USER_SIZE) & 0xff00 - bl _C_LABEL(arm_fpe_core_changecontext) -#endif - /* We can enable interrupts again */ IRQenableALL diff --git a/sys/arch/arm/arm/db_trace.c b/sys/arch/arm/arm/db_trace.c index d1a29b95824..72e58241989 100644 --- a/sys/arch/arm/arm/db_trace.c +++ b/sys/arch/arm/arm/db_trace.c @@ -1,4 +1,4 @@ -/* $OpenBSD: db_trace.c,v 1.4 2010/11/27 20:46:39 miod Exp $ */ +/* $OpenBSD: db_trace.c,v 1.5 2011/09/20 22:02:10 miod Exp $ */ /* $NetBSD: db_trace.c,v 1.8 2003/01/17 22:28:48 thorpej Exp $ */ /* @@ -114,11 +114,7 @@ db_stack_trace_print(addr, have_addr, count, modif, pr) return; } u = p->p_addr; -#ifdef acorn26 - frame = (u_int32_t *)(u->u_pcb.pcb_sf->sf_r11); -#else frame = (u_int32_t *)(u->u_pcb.pcb_un.un_32.pcb32_r11); -#endif (*pr)("at %p\n", frame); } else frame = (u_int32_t *)(addr); @@ -137,24 +133,13 @@ db_stack_trace_print(addr, have_addr, count, modif, pr) * In theory, the SCP isn't guaranteed to be in the function * that generated the stack frame. We hope for the best. */ -#ifdef __PROG26 - scp = frame[FR_SCP] & R15_PC; -#else scp = frame[FR_SCP]; -#endif db_printsym(scp, DB_STGY_PROC, pr); - (*pr)("\n\t"); -#ifdef __PROG26 - (*pr)("scp=0x%08x rlv=0x%08x (", scp, frame[FR_RLV] & R15_PC); - db_printsym(frame[FR_RLV] & R15_PC, DB_STGY_PROC, pr); - (*pr)(")\n"); -#else - (*pr)("scp=0x%08x rlv=0x%08x (", scp, frame[FR_RLV]); + (*pr)("\n\tscp=0x%08x rlv=0x%08x (", scp, frame[FR_RLV]); db_printsym(frame[FR_RLV], DB_STGY_PROC, pr); - (*pr)(")\n"); -#endif - (*pr)("\trsp=0x%08x rfp=0x%08x", frame[FR_RSP], frame[FR_RFP]); + (*pr)(")\n\trsp=0x%08x rfp=0x%08x", + frame[FR_RSP], frame[FR_RFP]); savecode = ((u_int32_t *)scp)[scp_offset]; if ((savecode & 0x0e100000) == 0x08000000) { diff --git a/sys/arch/arm/arm/exception.S b/sys/arch/arm/arm/exception.S index 6dd0316f797..6329bc4bfbc 100644 --- a/sys/arch/arm/arm/exception.S +++ b/sys/arch/arm/arm/exception.S @@ -1,4 +1,4 @@ -/* $OpenBSD: exception.S,v 1.2 2004/02/01 06:10:33 drahn Exp $ */ +/* $OpenBSD: exception.S,v 1.3 2011/09/20 22:02:10 miod Exp $ */ /* $NetBSD: exception.S,v 1.13 2003/10/31 16:30:15 scw Exp $ */ /* @@ -54,7 +54,7 @@ .text .align 0 -AST_ALIGNMENT_FAULT_LOCALS +AST_LOCALS /* * reset_entry: @@ -77,12 +77,11 @@ Lreset_panicmsg: */ ASENTRY_NP(swi_entry) PUSHFRAME - ENABLE_ALIGNMENT_FAULTS mov r0, sp /* Pass the frame to any function */ bl _C_LABEL(swi_handler) /* It's a SWI ! */ - DO_AST_AND_RESTORE_ALIGNMENT_FAULTS + DO_AST PULLFRAME movs pc, lr /* Exit */ @@ -99,7 +98,6 @@ ASENTRY_NP(prefetch_abort_entry) sub lr, lr, #0x00000004 /* Adjust the lr */ PUSHFRAMEINSVC - ENABLE_ALIGNMENT_FAULTS ldr r1, Lprefetch_abort_handler_address adr lr, exception_exit @@ -138,7 +136,6 @@ ASENTRY_NP(data_abort_entry) PUSHFRAMEINSVC /* Push trap frame and switch */ /* to SVC32 mode */ - ENABLE_ALIGNMENT_FAULTS ldr r1, Ldata_abort_handler_address adr lr, exception_exit @@ -191,14 +188,12 @@ Laddress_exception_msg: * Interrupts are disabled at suitable points to avoid ASTs * being posted between testing and exit to user mode. * - * This function uses PULLFRAMEFROMSVCANDEXIT and - * DO_AST_AND_RESTORE_ALIGNMENT_FAULTS thus should - * only be called if the exception handler used PUSHFRAMEINSVC - * followed by ENABLE_ALIGNMENT_FAULTS. + * This function uses PULLFRAMEFROMSVCANDEXIT and DO_AST thus should + * only be called if the exception handler used PUSHFRAMEINSVC. */ exception_exit: - DO_AST_AND_RESTORE_ALIGNMENT_FAULTS + DO_AST PULLFRAMEFROMSVCANDEXIT /* @@ -351,7 +346,6 @@ Lundefined_handler_indirection: ENTRY_NP(undefinedinstruction_bounce) PUSHFRAMEINSVC - ENABLE_ALIGNMENT_FAULTS mov r0, sp adr lr, exception_exit diff --git a/sys/arch/arm/arm/fault.c b/sys/arch/arm/arm/fault.c index 0eb1279e5b3..af7cd6e0f92 100644 --- a/sys/arch/arm/arm/fault.c +++ b/sys/arch/arm/arm/fault.c @@ -1,4 +1,4 @@ -/* $OpenBSD: fault.c,v 1.10 2007/05/15 16:02:18 drahn Exp $ */ +/* $OpenBSD: fault.c,v 1.11 2011/09/20 22:02:11 miod Exp $ */ /* $NetBSD: fault.c,v 1.46 2004/01/21 15:39:21 skrll Exp $ */ /* @@ -112,12 +112,6 @@ int last_fault_code; /* For the benefit of pmap_fault_fixup() */ #endif -#if defined(CPU_ARM3) || defined(CPU_ARM6) || \ - defined(CPU_ARM7) || defined(CPU_ARM7TDMI) -/* These CPUs may need data/prefetch abort fixups */ -#define CPU_ABORT_FIXUP_REQUIRED -#endif - struct sigdata { int signo; int code; @@ -165,36 +159,6 @@ static const struct data_abort data_aborts[] = { (((1 << ((x) & FAULT_TYPE_MASK)) & \ ((1 << FAULT_PERM_P) | (1 << FAULT_PERM_S))) != 0) -static __inline int -data_abort_fixup(trapframe_t *tf, u_int fsr, u_int far, struct proc *l) -{ -#ifdef CPU_ABORT_FIXUP_REQUIRED - int error; - - /* Call the cpu specific data abort fixup routine */ - error = cpu_dataabt_fixup(tf); - if (__predict_true(error != ABORT_FIXUP_FAILED)) - return (error); - - /* - * Oops, couldn't fix up the instruction - */ - printf("data_abort_fixup: fixup for %s mode data abort failed.\n", - TRAP_USERMODE(tf) ? "user" : "kernel"); - printf("pc = 0x%08x, opcode 0x%08x, insn = ", tf->tf_pc, - *((u_int *)tf->tf_pc)); - disassemble(tf->tf_pc); - - /* Die now if this happened in kernel mode */ - if (!TRAP_USERMODE(tf)) - dab_fatal(tf, fsr, far, l, NULL); - - return (error); -#else - return (ABORT_FIXUP_OK); -#endif /* CPU_ABORT_FIXUP_REQUIRED */ -} - void data_abort_handler(trapframe_t *tf) { @@ -283,21 +247,6 @@ data_abort_handler(trapframe_t *tf) dab_fatal(tf, fsr, far, p, NULL); } - /* See if the cpu state needs to be fixed up */ - switch (data_abort_fixup(tf, fsr, far, p)) { - case ABORT_FIXUP_RETURN: - return; - case ABORT_FIXUP_FAILED: - /* Deliver a SIGILL to the process */ - sd.signo = SIGILL; - sd.code = ILL_ILLOPC; - sd.addr = far; - sd.trap = fsr; - goto do_trapsignal; - default: - break; - } - va = trunc_page((vaddr_t)far); /* @@ -522,9 +471,6 @@ dab_align(trapframe_t *tf, u_int fsr, u_int far, struct proc *p, /* pcb_onfault *must* be NULL at this point */ KDASSERT(p->p_addr->u_pcb.pcb_onfault == NULL); - /* See if the cpu state needs to be fixed up */ - (void) data_abort_fixup(tf, fsr, far, p); - /* Deliver a bus error signal to the process */ sd->signo = SIGBUS; sd->code = BUS_ADRALN; @@ -617,9 +563,6 @@ dab_buserr(trapframe_t *tf, u_int fsr, u_int far, struct proc *p, return (0); } - /* See if the cpu state needs to be fixed up */ - (void) data_abort_fixup(tf, fsr, far, p); - /* * At this point, if the fault happened in kernel mode or user mode, * we're toast @@ -629,37 +572,6 @@ dab_buserr(trapframe_t *tf, u_int fsr, u_int far, struct proc *p, return (1); } -static __inline int -prefetch_abort_fixup(trapframe_t *tf) -{ -#ifdef CPU_ABORT_FIXUP_REQUIRED - int error; - - /* Call the cpu specific prefetch abort fixup routine */ - error = cpu_prefetchabt_fixup(tf); - if (__predict_true(error != ABORT_FIXUP_FAILED)) - return (error); - - /* - * Oops, couldn't fix up the instruction - */ - printf( - "prefetch_abort_fixup: fixup for %s mode prefetch abort failed.\n", - TRAP_USERMODE(tf) ? "user" : "kernel"); - printf("pc = 0x%08x, opcode 0x%08x, insn = ", tf->tf_pc, - *((u_int *)tf->tf_pc)); - disassemble(tf->tf_pc); - - /* Die now if this happened in kernel mode */ - if (!TRAP_USERMODE(tf)) - dab_fatal(tf, 0, tf->tf_pc, NULL, NULL); - - return (error); -#else - return (ABORT_FIXUP_OK); -#endif /* CPU_ABORT_FIXUP_REQUIRED */ -} - /* * void prefetch_abort_handler(trapframe_t *tf) * @@ -691,23 +603,6 @@ prefetch_abort_handler(trapframe_t *tf) if (__predict_true((tf->tf_spsr & I32_bit) == 0)) enable_interrupts(I32_bit); - /* See if the cpu state needs to be fixed up */ - switch (prefetch_abort_fixup(tf)) { - case ABORT_FIXUP_RETURN: - return; - case ABORT_FIXUP_FAILED: - /* Deliver a SIGILL to the process */ - sv.sival_ptr = (u_int32_t *) tf->tf_pc; - trapsignal(p, SIGILL, BUS_ADRERR, ILL_ILLOPC, sv); - - p = curproc; - p->p_addr->u_pcb.pcb_tf = tf; - - goto out; - default: - break; - } - /* Prefetch aborts cannot happen in kernel mode */ if (__predict_false(!TRAP_USERMODE(tf))) dab_fatal(tf, 0, tf->tf_pc, NULL, NULL); diff --git a/sys/arch/arm/arm/fiq.c b/sys/arch/arm/arm/fiq.c index 076675aa641..6bf734c501f 100644 --- a/sys/arch/arm/arm/fiq.c +++ b/sys/arch/arm/arm/fiq.c @@ -1,4 +1,4 @@ -/* $OpenBSD: fiq.c,v 1.1 2004/02/01 05:09:48 drahn Exp $ */ +/* $OpenBSD: fiq.c,v 1.2 2011/09/20 22:02:11 miod Exp $ */ /* $NetBSD: fiq.c,v 1.5 2002/04/03 23:33:27 thorpej Exp $ */ /* @@ -44,9 +44,7 @@ #include <arm/cpufunc.h> #include <arm/fiq.h> -#ifdef __PROG32 #include <uvm/uvm.h> -#endif TAILQ_HEAD(, fiqhandler) fiqhandler_stack = TAILQ_HEAD_INITIALIZER(fiqhandler_stack); @@ -54,13 +52,8 @@ TAILQ_HEAD(, fiqhandler) fiqhandler_stack = extern char fiqvector[]; extern char fiq_nullhandler[], fiq_nullhandler_end[]; -#ifdef __PROG32 #define IRQ_BIT I32_bit #define FIQ_BIT F32_bit -#else -#define IRQ_BIT R15_IRQ_DISABLE -#define FIQ_BIT R15_FIQ_DISABLE -#endif /* __PROG32 */ /* * fiq_installhandler: @@ -75,18 +68,16 @@ extern char fiq_nullhandler[], fiq_nullhandler_end[]; static void fiq_installhandler(void *func, size_t size) { -#if defined(__PROG32) && !defined(__ARM_FIQ_INDIRECT) +#if !defined(__ARM_FIQ_INDIRECT) vector_page_setprot(VM_PROT_READ|VM_PROT_WRITE); #endif memcpy(fiqvector, func, size); -#ifdef __PROG32 #if !defined(__ARM_FIQ_INDIRECT) vector_page_setprot(VM_PROT_READ); #endif cpu_icache_sync_range((vaddr_t) fiqvector, size); -#endif } /* diff --git a/sys/arch/arm/arm/fiq_subr.S b/sys/arch/arm/arm/fiq_subr.S index dfdc543c5ff..860a79fad3e 100644 --- a/sys/arch/arm/arm/fiq_subr.S +++ b/sys/arch/arm/arm/fiq_subr.S @@ -1,4 +1,4 @@ -/* $OpenBSD: fiq_subr.S,v 1.1 2004/02/01 05:09:48 drahn Exp $ */ +/* $OpenBSD: fiq_subr.S,v 1.2 2011/09/20 22:02:11 miod Exp $ */ /* $NetBSD: fiq_subr.S,v 1.3 2002/04/12 18:50:31 thorpej Exp $ */ /* @@ -42,39 +42,15 @@ #include <arm/asm.h> #include <arm/cpuconf.h> -/* - * MODE_CHANGE_NOP should be inserted between a mode change and a - * banked register (R8--R15) access. - */ -#if defined(CPU_ARM2) || defined(CPU_ARM250) -#define MODE_CHANGE_NOP mov r0, r0 -#else -#define MODE_CHANGE_NOP /* Data sheet says ARM3 doesn't need it */ -#endif - -#ifdef __PROG32 #define SWITCH_TO_FIQ_MODE \ mrs r2, cpsr_all ; \ mov r3, r2 ; \ bic r2, r2, #(PSR_MODE) ; \ orr r2, r2, #(PSR_FIQ32_MODE) ; \ msr cpsr_all, r2 -#else -#define SWITCH_TO_FIQ_MODE ; \ - mov r1, r15 ; \ - bic r2, r1, #(R15_MODE) ; \ - teqp r2, #(R15_MODE_FIQ) ; \ - MODE_CHANGE_NOP -#endif /* __PROG32 */ -#ifdef __PROG32 #define BACK_TO_SVC_MODE \ msr cpsr_all, r3 -#else -#define BACK_TO_SVC_MODE ; \ - teqp r1, #0 ; \ - MODE_CHANGE_NOP -#endif /* __PROG32 */ /* * fiq_getregs: diff --git a/sys/arch/arm/arm/genassym.cf b/sys/arch/arm/arm/genassym.cf index 3ffdb707531..94138a00c6e 100644 --- a/sys/arch/arm/arm/genassym.cf +++ b/sys/arch/arm/arm/genassym.cf @@ -1,4 +1,4 @@ -# $OpenBSD: genassym.cf,v 1.8 2007/10/10 15:53:51 art Exp $ +# $OpenBSD: genassym.cf,v 1.9 2011/09/20 22:02:11 miod Exp $ # $NetBSD: genassym.cf,v 1.27 2003/11/04 10:33:16 dsl Exp$ # Copyright (c) 1982, 1990 The Regents of the University of California. @@ -56,14 +56,13 @@ include <machine/pmap.h> include <machine/frame.h> include <machine/vmparam.h> -define __PROG32 1 +export VM_MIN_ADDRESS +export VM_MAXUSER_ADDRESS + ifdef __ARM_FIQ_INDIRECT define __ARM_FIQ_INDIRECT 1 endif -export VM_MIN_ADDRESS -export VM_MAXUSER_ADDRESS - export DOMAIN_CLIENT export PMAP_DOMAIN_KERNEL diff --git a/sys/arch/arm/arm/irq_dispatch.S b/sys/arch/arm/arm/irq_dispatch.S index 38a2a43713a..da07574381b 100644 --- a/sys/arch/arm/arm/irq_dispatch.S +++ b/sys/arch/arm/arm/irq_dispatch.S @@ -1,4 +1,4 @@ -/* $OpenBSD: irq_dispatch.S,v 1.6 2005/12/27 20:05:34 drahn Exp $ */ +/* $OpenBSD: irq_dispatch.S,v 1.7 2011/09/20 22:02:11 miod Exp $ */ /* $NetBSD: irq_dispatch.S,v 1.5 2003/10/30 08:57:24 scw Exp $ */ /* @@ -89,13 +89,12 @@ .Lcurrent_intr_depth: .word _C_LABEL(current_intr_depth) -AST_ALIGNMENT_FAULT_LOCALS +AST_LOCALS ASENTRY_NP(irq_entry) sub lr, lr, #0x00000004 /* Adjust the lr */ PUSHFRAMEINSVC /* Push an interrupt frame */ - ENABLE_ALIGNMENT_FAULTS /* * Increment the interrupt nesting depth and call the interrupt @@ -120,7 +119,7 @@ ASENTRY_NP(irq_entry) */ str r6, [r5] - DO_AST_AND_RESTORE_ALIGNMENT_FAULTS + DO_AST PULLFRAMEFROMSVCANDEXIT movs pc, lr /* Exit */ diff --git a/sys/arch/arm/arm/pmap.c b/sys/arch/arm/arm/pmap.c index 9bf926ab3fb..29757271a64 100644 --- a/sys/arch/arm/arm/pmap.c +++ b/sys/arch/arm/arm/pmap.c @@ -1,4 +1,4 @@ -/* $OpenBSD: pmap.c,v 1.31 2011/05/14 19:19:32 matthew Exp $ */ +/* $OpenBSD: pmap.c,v 1.32 2011/09/20 22:02:11 miod Exp $ */ /* $NetBSD: pmap.c,v 1.147 2004/01/18 13:03:50 scw Exp $ */ /* @@ -2892,20 +2892,6 @@ pmap_fault_fixup(pmap_t pm, vaddr_t va, vm_prot_t ftype, int user) rv = 1; } -#ifdef CPU_SA110 - /* - * There are bugs in the rev K SA110. This is a check for one - * of them. - */ - if (rv == 0 && curcpu()->ci_arm_cputype == CPU_ID_SA110 && - curcpu()->ci_arm_cpurev < 3) { - /* Always current pmap */ - if (l2pte_valid(pte)) { - rv = 1; - } - } -#endif /* CPU_SA110 */ - #ifdef DEBUG /* * If 'rv == 0' at this point, it generally indicates that there is a diff --git a/sys/arch/arm/arm/process_machdep.c b/sys/arch/arm/arm/process_machdep.c index 067c25a2a77..90de0e298a0 100644 --- a/sys/arch/arm/arm/process_machdep.c +++ b/sys/arch/arm/arm/process_machdep.c @@ -1,4 +1,4 @@ -/* $OpenBSD: process_machdep.c,v 1.3 2005/12/16 21:36:31 miod Exp $ */ +/* $OpenBSD: process_machdep.c,v 1.4 2011/09/20 22:02:11 miod Exp $ */ /* $NetBSD: process_machdep.c,v 1.11 2003/08/07 16:26:52 agc Exp $ */ /* @@ -114,10 +114,6 @@ #include <arm/armreg.h> -#ifdef ARMFPE -#include <arm/fpe-arm/armfpe.h> -#endif - static __inline struct trapframe * process_frame(struct proc *p) { @@ -149,14 +145,9 @@ process_read_regs(struct proc *p, struct reg *regs) int process_read_fpregs(struct proc *p, struct fpreg *regs) { -#ifdef ARMFPE - arm_fpe_getcontext(p, regs); - return(0); -#else /* ARMFPE */ /* No hardware FP support */ memset(regs, 0, sizeof(struct fpreg)); return(0); -#endif /* ARMFPE */ } #ifdef PTRACE @@ -170,7 +161,6 @@ process_write_regs(struct proc *p, struct reg *regs) bcopy((caddr_t)regs->r, (caddr_t)&tf->tf_r0, sizeof(regs->r)); tf->tf_usr_sp = regs->r_sp; tf->tf_usr_lr = regs->r_lr; -#ifdef __PROG32 tf->tf_pc = regs->r_pc; tf->tf_spsr &= ~PSR_FLAGS; tf->tf_spsr |= regs->r_cpsr & PSR_FLAGS; @@ -179,12 +169,6 @@ process_write_regs(struct proc *p, struct reg *regs) && tf->tf_spsr & I32_bit) panic("process_write_regs: Interrupts blocked in user process"); #endif -#else /* __PROG26 */ - if ((regs->r_pc & (R15_MODE | R15_IRQ_DISABLE | R15_FIQ_DISABLE)) != 0) - return EPERM; - - tf->tf_r15 = regs->r_pc; -#endif return(0); } @@ -192,13 +176,8 @@ process_write_regs(struct proc *p, struct reg *regs) int process_write_fpregs(struct proc *p, struct fpreg *regs) { -#ifdef ARMFPE - arm_fpe_setcontext(p, regs); - return(0); -#else /* ARMFPE */ /* No hardware FP support */ return(0); -#endif /* ARMFPE */ } int @@ -215,14 +194,7 @@ process_set_pc(struct proc *p, caddr_t addr) struct trapframe *tf = process_frame(p); KASSERT(tf != NULL); -#ifdef __PROG32 tf->tf_pc = (int)addr; -#else /* __PROG26 */ - /* Only set the PC, not the PSR */ - if (((register_t)addr & R15_PC) != (register_t)addr) - return EINVAL; - tf->tf_r15 = (tf->tf_r15 & ~R15_PC) | (register_t)addr; -#endif return (0); } diff --git a/sys/arch/arm/arm/sig_machdep.c b/sys/arch/arm/arm/sig_machdep.c index 7516bd7a965..13b9bfc113f 100644 --- a/sys/arch/arm/arm/sig_machdep.c +++ b/sys/arch/arm/arm/sig_machdep.c @@ -1,4 +1,4 @@ -/* $OpenBSD: sig_machdep.c,v 1.6 2011/07/05 04:48:01 guenther Exp $ */ +/* $OpenBSD: sig_machdep.c,v 1.7 2011/09/20 22:02:11 miod Exp $ */ /* $NetBSD: sig_machdep.c,v 1.22 2003/10/08 00:28:41 thorpej Exp $ */ /* @@ -56,9 +56,7 @@ #include <machine/cpu.h> #include <machine/frame.h> #include <machine/pcb.h> -#ifndef acorn26 #include <arm/cpufunc.h> -#endif static __inline struct trapframe * process_frame(struct proc *p) @@ -236,15 +234,9 @@ sys_sigreturn(struct proc *p, void *v, register_t *retval) * Make sure the processor mode has not been tampered with and * interrupts have not been disabled. */ -#ifdef __PROG32 if ((context.sc_spsr & PSR_MODE) != PSR_USR32_MODE || (context.sc_spsr & (I32_bit | F32_bit)) != 0) return (EINVAL); -#else /* __PROG26 */ - if ((context.sc_pc & R15_MODE) != R15_MODE_USR || - (context.sc_pc & (R15_IRQ_DISABLE | R15_FIQ_DISABLE)) != 0) - return EINVAL; -#endif /* Restore register context. */ tf = process_frame(p); @@ -274,110 +266,7 @@ sys_sigreturn(struct proc *p, void *v, register_t *retval) p->p_sigstk.ss_flags &= ~SS_ONSTACK; /* Restore signal mask. */ -#if 0 - (void) sigprocmask1(p, SIG_SETMASK, &context.sc_mask, 0); -#else p->p_sigmask = context.sc_mask & ~sigcantmask; -#endif return (EJUSTRETURN); } - -#if 0 -void -cpu_getmcontext(p, mcp, flags) - struct proc *p; - mcontext_t *mcp; - unsigned int *flags; -{ - struct trapframe *tf = process_frame(p); - __greg_t *gr = mcp->__gregs; - __greg_t ras_pc; - - /* Save General Register context. */ - gr[_REG_R0] = tf->tf_r0; - gr[_REG_R1] = tf->tf_r1; - gr[_REG_R2] = tf->tf_r2; - gr[_REG_R3] = tf->tf_r3; - gr[_REG_R4] = tf->tf_r4; - gr[_REG_R5] = tf->tf_r5; - gr[_REG_R6] = tf->tf_r6; - gr[_REG_R7] = tf->tf_r7; - gr[_REG_R8] = tf->tf_r8; - gr[_REG_R9] = tf->tf_r9; - gr[_REG_R10] = tf->tf_r10; - gr[_REG_R11] = tf->tf_r11; - gr[_REG_R12] = tf->tf_r12; - gr[_REG_SP] = tf->tf_usr_sp; - gr[_REG_LR] = tf->tf_usr_lr; - gr[_REG_PC] = tf->tf_pc; - gr[_REG_CPSR] = tf->tf_spsr; - - if ((ras_pc = (__greg_t)ras_lookup(l->l_proc, - (caddr_t) gr[_REG_PC])) != -1) - gr[_REG_PC] = ras_pc; - - *flags |= _UC_CPU; - -#ifdef ARMFPE - /* Save Floating Point Register context. */ - arm_fpe_getcontext(p, (struct fpreg *)(void *)&mcp->fpregs); - *flags |= _UC_FPU; -#endif -} - -int -cpu_setmcontext(p, mcp, flags) - struct proc *p; - const mcontext_t *mcp; - unsigned int flags; -{ - struct trapframe *tf = process_frame(l); - __greg_t *gr = mcp->__gregs; - - if ((flags & _UC_CPU) != 0) { - /* Restore General Register context. */ - /* Make sure the processor mode has not been tampered with. */ -#ifdef PROG32 - if ((gr[_REG_CPSR] & PSR_MODE) != PSR_USR32_MODE || - (gr[_REG_CPSR] & (I32_bit | F32_bit)) != 0) - return (EINVAL); -#else /* PROG26 */ - if ((gr[_REG_PC] & R15_MODE) != R15_MODE_USR || - (gr[_REG_PC] & (R15_IRQ_DISABLE | R15_FIQ_DISABLE)) != 0) - return (EINVAL); -#endif - - tf->tf_r0 = gr[_REG_R0]; - tf->tf_r1 = gr[_REG_R1]; - tf->tf_r2 = gr[_REG_R2]; - tf->tf_r3 = gr[_REG_R3]; - tf->tf_r4 = gr[_REG_R4]; - tf->tf_r5 = gr[_REG_R5]; - tf->tf_r6 = gr[_REG_R6]; - tf->tf_r7 = gr[_REG_R7]; - tf->tf_r8 = gr[_REG_R8]; - tf->tf_r9 = gr[_REG_R9]; - tf->tf_r10 = gr[_REG_R10]; - tf->tf_r11 = gr[_REG_R11]; - tf->tf_r12 = gr[_REG_R12]; - tf->tf_usr_sp = gr[_REG_SP]; - tf->tf_usr_lr = gr[_REG_LR]; - tf->tf_pc = gr[_REG_PC]; - tf->tf_spsr = gr[_REG_CPSR]; - } - -#ifdef ARMFPE - if ((flags & _UC_FPU) != 0) { - /* Restore Floating Point Register context. */ - arm_fpe_setcontext(p, (struct fpreg *)(void *)&mcp->__fpregs); - } -#endif - if (flags & _UC_SETSTACK) - l->l_proc->p_sigctx.ps_sigstk.ss_flags |= SS_ONSTACK; - if (flags & _UC_CLRSTACK) - l->l_proc->p_sigctx.ps_sigstk.ss_flags &= ~SS_ONSTACK; - - return (0); -} -#endif diff --git a/sys/arch/arm/arm/syscall.c b/sys/arch/arm/arm/syscall.c index f3a02906c92..3b242d13dec 100644 --- a/sys/arch/arm/arm/syscall.c +++ b/sys/arch/arm/arm/syscall.c @@ -1,4 +1,4 @@ -/* $OpenBSD: syscall.c,v 1.12 2011/04/03 14:56:28 guenther Exp $ */ +/* $OpenBSD: syscall.c,v 1.13 2011/09/20 22:02:11 miod Exp $ */ /* $NetBSD: syscall.c,v 1.24 2003/11/14 19:03:17 scw Exp $ */ /*- @@ -95,10 +95,6 @@ #include <machine/pcb.h> #include <arm/swi.h> -#ifdef acorn26 -#include <machine/machdep.h> -#endif - #define MAXARGS 8 void diff --git a/sys/arch/arm/arm/undefined.c b/sys/arch/arm/arm/undefined.c index 636011b3a67..66fb3266a76 100644 --- a/sys/arch/arm/arm/undefined.c +++ b/sys/arch/arm/arm/undefined.c @@ -1,4 +1,4 @@ -/* $OpenBSD: undefined.c,v 1.4 2008/05/19 18:42:11 miod Exp $ */ +/* $OpenBSD: undefined.c,v 1.5 2011/09/20 22:02:11 miod Exp $ */ /* $NetBSD: undefined.c,v 1.22 2003/11/29 22:21:29 bjh21 Exp $ */ /* @@ -65,10 +65,6 @@ #include <machine/trap.h> -#ifdef acorn26 -#include <machine/machdep.h> -#endif - static int gdb_trapper(u_int, u_int, struct trapframe *, int); LIST_HEAD(, undefined_handler) undefined_handlers[MAX_COPROCS]; @@ -158,23 +154,11 @@ undefinedinstruction(trapframe_t *frame) union sigval sv; /* Enable interrupts if they were enabled before the exception. */ -#ifdef acorn26 - if ((frame->tf_r15 & R15_IRQ_DISABLE) == 0) - int_on(); -#else if (!(frame->tf_spsr & I32_bit)) enable_interrupts(I32_bit); -#endif -#ifndef acorn26 frame->tf_pc -= INSN_SIZE; -#endif - -#ifdef __PROG26 - fault_pc = frame->tf_r15 & R15_PC; -#else fault_pc = frame->tf_pc; -#endif /* Get the current proc structure or proc0 if there is none. */ p = (curproc == NULL) ? &proc0 : curproc; @@ -192,11 +176,11 @@ undefinedinstruction(trapframe_t *frame) } /* - * Should use fuword() here .. but in the interests of squeezing every - * bit of speed we will just use ReadWord(). We know the instruction + * Should use copyin() here .. but in the interests of squeezing every + * bit of speed we will just read it directly. We know the instruction * can be read as was just executed so this will never fail unless the * kernel is screwed up in which case it does not really matter does - * it ? + * it? */ fault_instruction = *(u_int32_t *)fault_pc; @@ -218,12 +202,7 @@ undefinedinstruction(trapframe_t *frame) else coprocessor = 0; -#ifdef __PROG26 - if ((frame->tf_r15 & R15_MODE) == R15_MODE_USR) -#else - if ((frame->tf_spsr & PSR_MODE) == PSR_USR32_MODE) -#endif - { + if ((frame->tf_spsr & PSR_MODE) == PSR_USR32_MODE) { /* * Modify the fault_code to reflect the USR/SVC state at * time of fault. diff --git a/sys/arch/arm/arm/vm_machdep.c b/sys/arch/arm/arm/vm_machdep.c index 7d48ccf0da4..2cc24b14c9a 100644 --- a/sys/arch/arm/arm/vm_machdep.c +++ b/sys/arch/arm/arm/vm_machdep.c @@ -1,4 +1,4 @@ -/* $OpenBSD: vm_machdep.c,v 1.9 2009/01/28 08:02:02 grange Exp $ */ +/* $OpenBSD: vm_machdep.c,v 1.10 2011/09/20 22:02:11 miod Exp $ */ /* $NetBSD: vm_machdep.c,v 1.31 2004/01/04 11:33:29 jdolecek Exp $ */ /* @@ -64,10 +64,6 @@ #include <machine/reg.h> #include <machine/vmparam.h> -#ifdef ARMFPE -#include <arm/fpe-arm/armfpe.h> -#endif - extern pv_addr_t systempage; int process_read_regs (struct proc *p, struct reg *regs); @@ -159,12 +155,6 @@ cpu_fork(p1, p2, stack, stacksize, func, arg) pmap_activate(p2); -#ifdef ARMFPE - /* Initialise a new FP context for p2 and copy the context from p1 */ - arm_fpe_core_initcontext(FP_CONTEXT(p2)); - arm_fpe_copycontext(FP_CONTEXT(p1), FP_CONTEXT(p2)); -#endif /* ARMFPE */ - p2->p_addr->u_pcb.pcb_tf = tf = (struct trapframe *)pcb->pcb_un.un_32.pcb32_sp - 1; *tf = *p1->p_addr->u_pcb.pcb_tf; diff --git a/sys/arch/arm/conf/files.arm b/sys/arch/arm/conf/files.arm index db781655620..38e4dc3d0d4 100644 --- a/sys/arch/arm/conf/files.arm +++ b/sys/arch/arm/conf/files.arm @@ -1,11 +1,6 @@ -# $OpenBSD: files.arm,v 1.16 2010/12/06 18:05:29 jasper Exp $ +# $OpenBSD: files.arm,v 1.17 2011/09/20 22:02:12 miod Exp $ # $NetBSD: files.arm,v 1.76 2003/11/05 12:53:15 scw Exp $ -# Floating point emulator -#file arch/arm/fpe-arm/armfpe_glue.S armfpe -#file arch/arm/fpe-arm/armfpe_init.c armfpe -#file arch/arm/fpe-arm/armfpe.S armfpe - # generic networking files file arch/arm/arm/in_cksum_arm.S inet @@ -17,8 +12,8 @@ file arch/arm/arm/db_machdep.c ddb file arch/arm/arm/kgdb_machdep.c kgdb # FIQ support -file arch/arm/arm/fiq.c -file arch/arm/arm/fiq_subr.S +file arch/arm/arm/fiq.c fiq +file arch/arm/arm/fiq_subr.S fiq # mainbus files device mainbus {[base = -1], [dack = -1], [irq = -1]} @@ -43,14 +38,10 @@ file arch/arm/arm/arm_machdep.c file arch/arm/arm/ast.c file arch/arm/arm/bcopyinout.S file arch/arm/arm/blockio.S -file arch/arm/arm/bootconfig.c file arch/arm/arm/compat_13_machdep.c compat_13 file arch/arm/arm/copystr.S file arch/arm/arm/cpufunc.c file arch/arm/arm/cpufunc_asm.S -file arch/arm/arm/cpufunc_asm_arm3.S cpu_arm3 -file arch/arm/arm/cpufunc_asm_arm67.S cpu_arm6 | cpu_arm7 -file arch/arm/arm/cpufunc_asm_arm7tdmi.S cpu_arm7tdmi file arch/arm/arm/cpufunc_asm_arm8.S cpu_arm8 file arch/arm/arm/cpufunc_asm_arm9.S cpu_arm9 file arch/arm/arm/cpufunc_asm_arm10.S cpu_arm9e | cpu_arm10 @@ -82,9 +73,7 @@ file arch/arm/arm/sig_machdep.c file arch/arm/arm/sigcode.S file arch/arm/arm/syscall.c file arch/arm/arm/undefined.c -# vectors.S gets included manually by Makefile.acorn26, since it needs -# to be at the start of the text segment on those machines. -file arch/arm/arm/vectors.S +file arch/arm/arm/vectors.S file arch/arm/arm/vm_machdep_arm.c # files common to arm implementations @@ -102,7 +91,7 @@ file arch/arm/arm/sys_machdep.c file arch/arm/arm/vm_machdep.c # arm library functions -file arch/arm/arm/bcopy_page.S +file arch/arm/arm/bcopy_page.S # machine-dependent libkern components file lib/libkern/arch/arm/divsi3.S diff --git a/sys/arch/arm/include/_types.h b/sys/arch/arm/include/_types.h index 731ea0f04a3..6f3d95f214c 100644 --- a/sys/arch/arm/include/_types.h +++ b/sys/arch/arm/include/_types.h @@ -1,4 +1,4 @@ -/* $OpenBSD: _types.h,v 1.8 2011/09/08 03:40:32 guenther Exp $ */ +/* $OpenBSD: _types.h,v 1.9 2011/09/20 22:02:13 miod Exp $ */ /*- * Copyright (c) 1990, 1993 @@ -142,9 +142,4 @@ typedef int __rune_t; typedef void * __wctrans_t; typedef void * __wctype_t; -/* OpenBSD only supports arm32 */ -#ifdef _KERNEL -#define __PROG32 /* indicate 32-bit mode */ -#endif - #endif /* _ARM__TYPES_H_ */ diff --git a/sys/arch/arm/include/armreg.h b/sys/arch/arm/include/armreg.h index 9dbc467e881..50bccc49766 100644 --- a/sys/arch/arm/include/armreg.h +++ b/sys/arch/arm/include/armreg.h @@ -1,4 +1,4 @@ -/* $OpenBSD: armreg.h,v 1.9 2011/03/17 21:49:33 jasper Exp $ */ +/* $OpenBSD: armreg.h,v 1.10 2011/09/20 22:02:13 miod Exp $ */ /* $NetBSD: armreg.h,v 1.27 2003/09/06 08:43:02 rearnsha Exp $ */ /* @@ -81,26 +81,6 @@ #define PSR_32_MODE 0x00000010 #define PSR_IN_USR_MODE(psr) (!((psr) & 3)) /* XXX */ -#define PSR_IN_32_MODE(psr) ((psr) & PSR_32_MODE) - -/* In 26-bit modes, the PSR is stuffed into R15 along with the PC. */ - -#define R15_MODE 0x00000003 -#define R15_MODE_USR 0x00000000 -#define R15_MODE_FIQ 0x00000001 -#define R15_MODE_IRQ 0x00000002 -#define R15_MODE_SVC 0x00000003 - -#define R15_PC 0x03fffffc - -#define R15_FIQ_DISABLE 0x04000000 -#define R15_IRQ_DISABLE 0x08000000 - -#define R15_FLAGS 0xf0000000 -#define R15_FLAG_N 0x80000000 -#define R15_FLAG_Z 0x40000000 -#define R15_FLAG_C 0x20000000 -#define R15_FLAG_V 0x10000000 /* * Co-processor 15: The system control co-processor. diff --git a/sys/arch/arm/include/cpu.h b/sys/arch/arm/include/cpu.h index d44de5e13d3..0f197bedd67 100644 --- a/sys/arch/arm/include/cpu.h +++ b/sys/arch/arm/include/cpu.h @@ -1,4 +1,4 @@ -/* $OpenBSD: cpu.h,v 1.27 2011/06/24 19:47:48 naddy Exp $ */ +/* $OpenBSD: cpu.h,v 1.28 2011/09/20 22:02:13 miod Exp $ */ /* $NetBSD: cpu.h,v 1.34 2003/06/23 11:01:08 martin Exp $ */ /* @@ -108,7 +108,6 @@ extern int cpu_do_powersave; #endif -#ifdef __PROG32 #ifdef _LOCORE #define IRQdisable \ stmfd sp!, {r0} ; \ @@ -128,7 +127,6 @@ extern int cpu_do_powersave; #define IRQdisable __set_cpsr_c(I32_bit, I32_bit); #define IRQenable __set_cpsr_c(I32_bit, 0); #endif /* _LOCORE */ -#endif #ifndef _LOCORE @@ -138,47 +136,27 @@ extern int cpu_do_powersave; * CLKF_USERMODE: Return TRUE/FALSE (1/0) depending on whether the * frame came from USR mode or not. */ -#ifdef __PROG32 #define CLKF_USERMODE(frame) ((frame->if_spsr & PSR_MODE) == PSR_USR32_MODE) -#else -#define CLKF_USERMODE(frame) ((frame->if_r15 & R15_MODE) == R15_MODE_USR) -#endif /* * CLKF_INTR: True if we took the interrupt from inside another * interrupt handler. */ extern int current_intr_depth; -#ifdef __PROG32 -/* Hack to treat FPE time as interrupt time so we can measure it */ -#define CLKF_INTR(frame) \ - ((current_intr_depth > 1) || \ - (frame->if_spsr & PSR_MODE) == PSR_UND32_MODE) -#else #define CLKF_INTR(frame) (current_intr_depth > 1) -#endif /* * CLKF_PC: Extract the program counter from a clockframe */ -#ifdef __PROG32 #define CLKF_PC(frame) (frame->if_pc) -#else -#define CLKF_PC(frame) (frame->if_r15 & R15_PC) -#endif /* * PROC_PC: Find out the program counter for the given process. */ -#ifdef __PROG32 #define PROC_PC(p) ((p)->p_addr->u_pcb.pcb_tf->tf_pc) -#else -#define PROC_PC(p) ((p)->p_addr->u_pcb.pcb_tf->tf_r15 & R15_PC) -#endif /* The address of the vector page. */ extern vaddr_t vector_page; -#ifdef __PROG32 void arm32_vector_init(vaddr_t, int); #define ARM_VEC_RESET (1 << 0) @@ -192,7 +170,6 @@ void arm32_vector_init(vaddr_t, int); #define ARM_NVEC 8 #define ARM_VEC_ALL 0xffffffff -#endif /* * Per-CPU information. For now we assume one CPU. @@ -216,9 +193,6 @@ struct cpu_info { u_int32_t ci_arm_cputype; /* CPU type */ u_int32_t ci_arm_cpurev; /* CPU revision */ u_int32_t ci_ctrl; /* The CPU control register */ -#ifdef MULTIPROCESSOR - MP_CPU_INFO_MEMBERS -#endif u_int32_t ci_randseed; }; @@ -235,12 +209,6 @@ extern struct cpu_info cpu_info_store; #define cpu_unidle(ci) #endif -#ifdef __PROG32 -void cpu_proc_fork(struct proc *, struct proc *); -#else -#define cpu_proc_fork(p1, p2) -#endif - /* * Scheduling glue */ @@ -270,7 +238,6 @@ extern int want_resched; /* resched() was called */ */ #define need_proftick(p) setsoftast() -#ifndef acorn26 /* * cpu device glue (belongs in cpuvar.h) */ @@ -278,17 +245,11 @@ extern int want_resched; /* resched() was called */ struct device; void cpu_attach (struct device *); int cpu_alloc_idlepcb (struct cpu_info *); -#endif - /* * Random cruft */ -/* locore.S */ -void atomic_set_bit (u_int *address, u_int setmask); -void atomic_clear_bit (u_int *address, u_int clearmask); - /* cpuswitch.S */ struct pcb; void savectx (struct pcb *pcb); diff --git a/sys/arch/arm/include/cpuconf.h b/sys/arch/arm/include/cpuconf.h index a02c98e0b6a..4a64e12cdb9 100644 --- a/sys/arch/arm/include/cpuconf.h +++ b/sys/arch/arm/include/cpuconf.h @@ -1,4 +1,4 @@ -/* $OpenBSD: cpuconf.h,v 1.6 2009/05/24 04:56:19 drahn Exp $ */ +/* $OpenBSD: cpuconf.h,v 1.7 2011/09/20 22:02:13 miod Exp $ */ /* $NetBSD: cpuconf.h,v 1.7 2003/05/23 00:57:24 ichiro Exp $ */ /* @@ -48,20 +48,8 @@ /* * Determine which ARM architecture versions are configured. */ -#if (defined(CPU_ARM2) || defined(CPU_ARM250) || defined(CPU_ARM3)) -#define ARM_ARCH_2 1 -#else -#define ARM_ARCH_2 0 -#endif - -#if (defined(CPU_ARM6) || defined(CPU_ARM7)) -#define ARM_ARCH_3 1 -#else -#define ARM_ARCH_3 0 -#endif - -#if (defined(CPU_ARM7TDMI) || defined(CPU_ARM8) || defined(CPU_ARM9) || \ - defined(CPU_SA110) || defined(CPU_SA1100) || defined(CPU_SA1110) || \ +#if (defined(CPU_ARM8) || defined(CPU_ARM9) || \ + defined(CPU_SA1100) || defined(CPU_SA1110) || \ defined(CPU_IXP12X0) || defined(CPU_XSCALE_IXP425)) #define ARM_ARCH_4 1 #else @@ -91,9 +79,6 @@ /* * Define which MMU classes are configured: * - * ARM_MMU_MEMC Prehistoric, external memory controller - * and MMU for ARMv2 CPUs. - * * ARM_MMU_GENERIC Generic ARM MMU, compatible with ARM6. * * ARM_MMU_SA1 StrongARM SA-1 MMU. Compatible with generic @@ -105,21 +90,15 @@ * ARM_MMU_V7 v6/v7 MMU with XP bit enabled subpage * protection is not used, TEX/AP is used instead. */ -#if (defined(CPU_ARM2) || defined(CPU_ARM250) || defined(CPU_ARM3)) -#define ARM_MMU_MEMC 1 -#else -#define ARM_MMU_MEMC 0 -#endif -#if (defined(CPU_ARM6) || defined(CPU_ARM7) || defined(CPU_ARM7TDMI) || \ - defined(CPU_ARM8) || defined(CPU_ARM9) || defined(CPU_ARM9E) || \ +#if (defined(CPU_ARM8) || defined(CPU_ARM9) || defined(CPU_ARM9E) || \ defined(CPU_ARM10) || defined(CPU_ARM11) || defined(CPU_ARMv7) ) #define ARM_MMU_GENERIC 1 #else #define ARM_MMU_GENERIC 0 #endif -#if (defined(CPU_SA110) || defined(CPU_SA1100) || defined(CPU_SA1110) ||\ +#if (defined(CPU_SA1100) || defined(CPU_SA1110) ||\ defined(CPU_IXP12X0)) #define ARM_MMU_SA1 1 #else @@ -139,7 +118,7 @@ #define ARM_MMU_V7 0 #endif -#define ARM_NMMUS (ARM_MMU_MEMC + ARM_MMU_GENERIC + \ +#define ARM_NMMUS (ARM_MMU_GENERIC + \ ARM_MMU_SA1 + ARM_MMU_XSCALE + ARM_MMU_V7) /* diff --git a/sys/arch/arm/include/cpufunc.h b/sys/arch/arm/include/cpufunc.h index e3dd2d860b0..dbfa8e32661 100644 --- a/sys/arch/arm/include/cpufunc.h +++ b/sys/arch/arm/include/cpufunc.h @@ -1,4 +1,4 @@ -/* $OpenBSD: cpufunc.h,v 1.8 2011/03/23 16:54:34 pirofti Exp $ */ +/* $OpenBSD: cpufunc.h,v 1.9 2011/09/20 22:02:13 miod Exp $ */ /* $NetBSD: cpufunc.h,v 1.29 2003/09/06 09:08:35 rearnsha Exp $ */ /* @@ -137,19 +137,12 @@ struct cpu_functions { void (*cf_flush_prefetchbuf) (void); void (*cf_drain_writebuf) (void); - void (*cf_flush_brnchtgt_C) (void); - void (*cf_flush_brnchtgt_E) (u_int va); void (*cf_sleep) (int mode); /* Soft functions */ - - int (*cf_dataabt_fixup) (void *arg); - int (*cf_prefetchabt_fixup) (void *arg); - void (*cf_context_switch) (u_int); - - void (*cf_setup) (char *string); + void (*cf_setup) (void); }; extern struct cpu_functions cpufuncs; @@ -184,17 +177,9 @@ extern u_int cputype; #define cpu_flush_prefetchbuf() cpufuncs.cf_flush_prefetchbuf() #define cpu_drain_writebuf() cpufuncs.cf_drain_writebuf() -#define cpu_flush_brnchtgt_C() cpufuncs.cf_flush_brnchtgt_C() -#define cpu_flush_brnchtgt_E(e) cpufuncs.cf_flush_brnchtgt_E(e) #define cpu_sleep(m) cpufuncs.cf_sleep(m) -#define cpu_dataabt_fixup(a) cpufuncs.cf_dataabt_fixup(a) -#define cpu_prefetchabt_fixup(a) cpufuncs.cf_prefetchabt_fixup(a) -#define ABORT_FIXUP_OK 0 /* fixup succeeded */ -#define ABORT_FIXUP_FAILED 1 /* fixup failed */ -#define ABORT_FIXUP_RETURN 2 /* abort handler should return */ - #define cpu_context_switch(a) cpufuncs.cf_context_switch(a) #define cpu_setup(a) cpufuncs.cf_setup(a) @@ -203,7 +188,6 @@ int set_cpufuncs (void); #define ARCHITECTURE_NOT_SUPPORTED 2 /* not known */ void cpufunc_nullop (void); -int cpufunc_null_fixup (void *); int early_abort_fixup (void *); int late_abort_fixup (void *); u_int cpufunc_id (void); @@ -212,37 +196,6 @@ void cpufunc_domains (u_int domains); u_int cpufunc_faultstatus (void); u_int cpufunc_faultaddress (void); -#ifdef CPU_ARM3 -u_int arm3_control (u_int clear, u_int bic); -void arm3_cache_flush (void); -#endif /* CPU_ARM3 */ - -#if defined(CPU_ARM6) || defined(CPU_ARM7) -void arm67_setttb (u_int ttb); -void arm67_tlb_flush (void); -void arm67_tlb_purge (u_int va); -void arm67_cache_flush (void); -void arm67_context_switch (u_int); -#endif /* CPU_ARM6 || CPU_ARM7 */ - -#ifdef CPU_ARM6 -void arm6_setup (char *string); -#endif /* CPU_ARM6 */ - -#ifdef CPU_ARM7 -void arm7_setup (char *string); -#endif /* CPU_ARM7 */ - -#ifdef CPU_ARM7TDMI -int arm7_dataabt_fixup (void *arg); -void arm7tdmi_setup (char *string); -void arm7tdmi_setttb (u_int ttb); -void arm7tdmi_tlb_flushID (void); -void arm7tdmi_tlb_flushID_SE (u_int va); -void arm7tdmi_cache_flushID (void); -void arm7tdmi_context_switch (u_int); -#endif /* CPU_ARM7TDMI */ - #ifdef CPU_ARM8 void arm8_setttb (u_int ttb); void arm8_tlb_flushID (void); @@ -263,26 +216,21 @@ void arm8_cache_syncI_rng (vaddr_t start, vsize_t end); void arm8_context_switch (u_int); -void arm8_setup (char *string); +void arm8_setup (void); u_int arm8_clock_config (u_int, u_int); #endif -#ifdef CPU_SA110 -void sa110_setup (char *string); -void sa110_context_switch (u_int); -#endif /* CPU_SA110 */ - #if defined(CPU_SA1100) || defined(CPU_SA1110) void sa11x0_drain_readbuf (void); void sa11x0_context_switch (u_int); void sa11x0_cpu_sleep (int mode); -void sa11x0_setup (char *string); +void sa11x0_setup (void); #endif -#if defined(CPU_SA110) || defined(CPU_SA1100) || defined(CPU_SA1110) +#if defined(CPU_SA1100) || defined(CPU_SA1110) void sa1_setttb (u_int ttb); void sa1_tlb_flushID_SE (u_int va); @@ -328,7 +276,7 @@ void arm9_idcache_wbinv_range (vaddr_t, vsize_t); void arm9_context_switch (u_int); -void arm9_setup (char *string); +void arm9_setup (void); extern unsigned arm9_dcache_sets_max; extern unsigned arm9_dcache_sets_inc; @@ -342,7 +290,7 @@ void arm10_tlb_flushI_SE (u_int); void arm10_context_switch (u_int); -void arm10_setup (char *string); +void arm10_setup (void); #endif #if defined(CPU_ARM9E) || defined (CPU_ARM10) @@ -368,7 +316,7 @@ void arm11_tlb_flushI_SE (u_int); void arm11_context_switch (u_int); -void arm11_setup (char *string); +void arm11_setup (void); void arm11_tlb_flushID (void); void arm11_tlb_flushI (void); void arm11_tlb_flushD (void); @@ -408,7 +356,7 @@ void armv7_tlb_flushI_SE (u_int); void armv7_context_switch (u_int); void armv7_context_switch (u_int); -void armv7_setup (char *string); +void armv7_setup (void); void armv7_tlb_flushID (void); void armv7_tlb_flushI (void); void armv7_tlb_flushD (void); @@ -438,7 +386,7 @@ extern unsigned armv7_dcache_index_inc; #if defined(CPU_ARM9) || defined(CPU_ARM9E) || defined(CPU_ARM10) || \ - defined(CPU_SA110) || defined(CPU_SA1100) || defined(CPU_SA1110) || \ + defined(CPU_SA1100) || defined(CPU_SA1110) || \ defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \ defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) @@ -453,7 +401,7 @@ void armv4_drain_writebuf (void); #if defined(CPU_IXP12X0) void ixp12x0_drain_readbuf (void); void ixp12x0_context_switch (u_int); -void ixp12x0_setup (char *string); +void ixp12x0_setup (void); #endif #if defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \ @@ -495,7 +443,7 @@ void xscale_cache_flushD_rng (vaddr_t start, vsize_t end); void xscale_context_switch (u_int); -void xscale_setup (char *string); +void xscale_setup (void); #endif /* CPU_XSCALE_80200 || CPU_XSCALE_80321 || CPU_XSCALE_PXA2X0 || CPU_XSCALE_IXP425 */ #define tlb_flush cpu_tlb_flushID @@ -505,7 +453,6 @@ void xscale_setup (char *string); /* * Macros for manipulating CPU interrupts */ -#ifdef __PROG32 /* Functions to manipulate the CPSR. */ static __inline u_int32_t __set_cpsr_c(u_int bic, u_int eor); static __inline u_int32_t __get_cpsr(void); @@ -545,22 +492,6 @@ __get_cpsr() #define restore_interrupts(old_cpsr) \ (__set_cpsr_c((I32_bit | F32_bit), (old_cpsr) & (I32_bit | F32_bit))) -#else /* ! __PROG32 */ -#define disable_interrupts(mask) \ - (set_r15((mask) & (R15_IRQ_DISABLE | R15_FIQ_DISABLE), \ - (mask) & (R15_IRQ_DISABLE | R15_FIQ_DISABLE))) - -#define enable_interrupts(mask) \ - (set_r15((mask) & (R15_IRQ_DISABLE | R15_FIQ_DISABLE), 0)) - -#define restore_interrupts(old_r15) \ - (set_r15((R15_IRQ_DISABLE | R15_FIQ_DISABLE), \ - (old_r15) & (R15_IRQ_DISABLE | R15_FIQ_DISABLE))) - -/* Functions to manipulate the processor control bits in r15. */ -u_int set_r15(u_int bic, u_int eor); -u_int get_r15(void); -#endif /* __PROG32 */ /* * Functions to manipulate cpu r13 diff --git a/sys/arch/arm/include/db_machdep.h b/sys/arch/arm/include/db_machdep.h index e85fdac6484..5346870b469 100644 --- a/sys/arch/arm/include/db_machdep.h +++ b/sys/arch/arm/include/db_machdep.h @@ -1,4 +1,4 @@ -/* $OpenBSD: db_machdep.h,v 1.6 2010/11/27 19:57:23 miod Exp $ */ +/* $OpenBSD: db_machdep.h,v 1.7 2011/09/20 22:02:13 miod Exp $ */ /* $NetBSD: db_machdep.h,v 1.5 2001/11/22 18:00:00 thorpej Exp $ */ /* @@ -51,13 +51,8 @@ typedef trapframe_t db_regs_t; extern db_regs_t ddb_regs; /* register state */ #define DDB_REGS (&ddb_regs) -#ifdef __PROG26 -#define PC_REGS(regs) ((db_addr_t)(regs)->tf_r15 & R15_PC) -#define PC_ADVANCE(regs) ((regs)->tf_r15 += 4) -#else #define PC_REGS(regs) ((db_addr_t)(regs)->tf_pc) #define SET_PC_REGS(regs, value) (regs)->tf_pc = (register_t)(value) -#endif #define BKPT_INST (KERNEL_BREAKPOINT) /* breakpoint instruction */ #define BKPT_SIZE (INSN_SIZE) /* size of breakpoint inst */ diff --git a/sys/arch/arm/include/frame.h b/sys/arch/arm/include/frame.h index afc98ddf7b9..2fab91ef9ea 100644 --- a/sys/arch/arm/include/frame.h +++ b/sys/arch/arm/include/frame.h @@ -1,4 +1,4 @@ -/* $OpenBSD: frame.h,v 1.3 2006/03/07 20:20:30 miod Exp $ */ +/* $OpenBSD: frame.h,v 1.4 2011/09/20 22:02:13 miod Exp $ */ /* $NetBSD: frame.h,v 1.9 2003/12/01 08:48:33 scw Exp $ */ /* @@ -56,7 +56,7 @@ */ typedef struct trapframe { - register_t tf_spsr; /* Zero on arm26 */ + register_t tf_spsr; register_t tf_r0; register_t tf_r1; register_t tf_r2; @@ -72,8 +72,8 @@ typedef struct trapframe { register_t tf_r12; register_t tf_usr_sp; register_t tf_usr_lr; - register_t tf_svc_sp; /* Not used on arm26 */ - register_t tf_svc_lr; /* Not used on arm26 */ + register_t tf_svc_sp; + register_t tf_svc_lr; register_t tf_pc; } trapframe_t; @@ -95,7 +95,7 @@ struct sigframe { siginfo_t sf_si; }; -/* the pointers are use in the trampoline code to locate the ucontext */ +/* the pointers are used in the trampoline code to locate the ucontext */ #if 0 struct sigframe_siginfo { siginfo_t sf_si; /* actual saved siginfo */ @@ -163,26 +163,13 @@ struct frame { u_int fr_pc; }; -#ifdef _KERNEL -void validate_trapframe (trapframe_t *, int); -#endif /* _KERNEL */ - #else /* _LOCORE */ -/* - * AST_ALIGNMENT_FAULT_LOCALS and ENABLE_ALIGNMENT_FAULTS - * These are used in order to support dynamic enabling/disabling of - * alignment faults when executing old a.out ARM binaries (which we do - * not support). - */ - -#define AST_ALIGNMENT_FAULT_LOCALS ;\ +#define AST_LOCALS \ .Laflt_astpending: ;\ .word _C_LABEL(astpending) -#define ENABLE_ALIGNMENT_FAULTS /* nothing */ - -#define DO_AST_AND_RESTORE_ALIGNMENT_FAULTS \ +#define DO_AST \ ldr r0, [sp] /* Get the SPSR from stack */ ;\ mrs r4, cpsr /* save CPSR */ ;\ and r0, r0, #(PSR_MODE) /* Returning to USR mode? */ ;\ @@ -213,17 +200,12 @@ void validate_trapframe (trapframe_t *, int); /* * PUSHFRAME - macro to push a trap frame on the stack in the current mode * Since the current mode is used, the SVC lr field is not defined. - * - * NOTE: r13 and r14 are stored separately as a work around for the - * SA110 rev 2 STM^ bug */ #define PUSHFRAME \ str lr, [sp, #-4]!; /* Push the return address */ \ sub sp, sp, #(4*17); /* Adjust the stack pointer */ \ - stmia sp, {r0-r12}; /* Push the user mode registers */ \ - add r0, sp, #(4*13); /* Adjust the stack pointer */ \ - stmia r0, {r13-r14}^; /* Push the user mode registers */ \ + stmia sp, {r0-r14}^; /* Push the user mode registers */ \ mov r0, r0; /* NOP for previous instruction */ \ mrs r0, spsr_all; /* Put the SPSR on the stack */ \ str r0, [sp, #-4]! @@ -247,9 +229,6 @@ void validate_trapframe (trapframe_t *, int); * mode. The processor mode is switched to SVC mode and the trap frame is * stored. The SVC lr field is used to store the previous value of * lr in SVC mode. - * - * NOTE: r13 and r14 are stored separately as a work around for the - * SA110 rev 2 STM^ bug */ #define PUSHFRAMEINSVC \ @@ -268,9 +247,7 @@ void validate_trapframe (trapframe_t *, int); msr spsr_all, r3; /* Restore correct spsr */ \ ldmdb r1, {r0-r3}; /* Restore 4 regs from xxx mode */ \ sub sp, sp, #(4*15); /* Adjust the stack pointer */ \ - stmia sp, {r0-r12}; /* Push the user mode registers */ \ - add r0, sp, #(4*13); /* Adjust the stack pointer */ \ - stmia r0, {r13-r14}^; /* Push the user mode registers */ \ + stmia sp, {r0-r14}^; /* Push the user mode registers */ \ mov r0, r0; /* NOP for previous instruction */ \ mrs r0, spsr_all; /* Put the SPSR on the stack */ \ str r0, [sp, #-4]! diff --git a/sys/arch/arm/include/param.h b/sys/arch/arm/include/param.h index 25a67007b87..164b1a0dc67 100644 --- a/sys/arch/arm/include/param.h +++ b/sys/arch/arm/include/param.h @@ -1,4 +1,4 @@ -/* $OpenBSD: param.h,v 1.16 2011/09/08 03:40:32 guenther Exp $ */ +/* $OpenBSD: param.h,v 1.17 2011/09/20 22:02:13 miod Exp $ */ /* $NetBSD: param.h,v 1.9 2002/03/24 03:37:23 thorpej Exp $ */ /* @@ -86,12 +86,12 @@ * in use and whether there is hardware FP support. However we can put * an upper limit on it. * The undefined stack needs to be at least 512 bytes. This is a requirement - * if the FP emulators - * The kernel stack should be at least 4K is size. + * of the FP emulators + * The kernel stack should be at least 4K in size. * * The stack top addresses are used to set the stack pointers. The stack bottom - * addresses at the addresses monitored by the diagnostic code for stack overflows - * + * addresses are the addresses monitored by the diagnostic code for stack + * overflows. */ #define FPCONTEXTSIZE (0x100) diff --git a/sys/arch/arm/include/pcb.h b/sys/arch/arm/include/pcb.h index b50827f5627..daf8b58d4eb 100644 --- a/sys/arch/arm/include/pcb.h +++ b/sys/arch/arm/include/pcb.h @@ -1,4 +1,4 @@ -/* $OpenBSD: pcb.h,v 1.3 2006/05/27 20:36:05 miod Exp $ */ +/* $OpenBSD: pcb.h,v 1.4 2011/09/20 22:02:13 miod Exp $ */ /* $NetBSD: pcb.h,v 1.10 2003/10/13 21:46:39 scw Exp $ */ /* @@ -71,11 +71,6 @@ struct pcb_arm32 { #define pcb_dacr pcb_un.un_32.pcb32_dacr #define pcb_cstate pcb_un.un_32.pcb32_cstate -struct pcb_arm26 { - struct switchframe *pcb26_sf; -}; -#define pcb_sf pcb_un.un_26.pcb26_sf - /* * WARNING! * See warning for struct pcb_arm32, above, before changing struct pcb! @@ -87,11 +82,9 @@ struct pcb { caddr_t pcb_onfault; /* On fault handler */ union { struct pcb_arm32 un_32; - struct pcb_arm26 un_26; } pcb_un; struct fpe_sp_state pcb_fpstate; /* Floating Point state */ }; -#define pcb_ff pcb_fpstate /* for arm26 */ /* * No additional data for core dumps. diff --git a/sys/arch/arm/include/pmap.h b/sys/arch/arm/include/pmap.h index b3c372b0959..8a1db4759dc 100644 --- a/sys/arch/arm/include/pmap.h +++ b/sys/arch/arm/include/pmap.h @@ -1,4 +1,4 @@ -/* $OpenBSD: pmap.h,v 1.18 2011/04/28 20:50:58 ariane Exp $ */ +/* $OpenBSD: pmap.h,v 1.19 2011/09/20 22:02:13 miod Exp $ */ /* $NetBSD: pmap.h,v 1.76 2003/09/06 09:10:46 rearnsha Exp $ */ /* @@ -461,11 +461,6 @@ extern void (*pmap_zero_page_func)(struct vm_page *); /*****************************************************************************/ /* - * tell MI code that the cache is virtually-indexed *and* virtually-tagged. - */ -#define PMAP_CACHE_VIVT - -/* * Definitions for MMU domains */ #define PMAP_DOMAINS 15 /* 15 'user' domains (0-14) */ diff --git a/sys/arch/arm/include/profile.h b/sys/arch/arm/include/profile.h index a15f022bff5..75df4f5e310 100644 --- a/sys/arch/arm/include/profile.h +++ b/sys/arch/arm/include/profile.h @@ -1,4 +1,4 @@ -/* $OpenBSD: profile.h,v 1.1 2004/02/01 05:09:49 drahn Exp $ */ +/* $OpenBSD: profile.h,v 1.2 2011/09/20 22:02:13 miod Exp $ */ /* $NetBSD: profile.h,v 1.5 2002/03/24 15:49:40 bjh21 Exp $ */ /* @@ -62,22 +62,17 @@ * Preserve registers that are trashed during mcount \ */ \ __asm__("stmfd sp!, {r0-r3, ip, lr}"); \ - /* Check what mode we're in. EQ => 32, NE => 26 */ \ - __asm__("teq r0, r0"); \ - __asm__("teq pc, r15"); \ /* \ * find the return address for mcount, \ * and the return address for mcount's caller. \ * \ * frompcindex = pc pushed by call into self. \ */ \ - __asm__("moveq r0, ip"); \ - __asm__("bicne r0, ip, #0xfc000003"); \ + __asm__("mov r0, ip"); \ /* \ * selfpc = pc pushed by mcount call \ */ \ - __asm__("moveq r1, lr"); \ - __asm__("bicne r1, lr, #0xfc000003"); \ + __asm__("mov r1, lr"); \ /* \ * Call the real mcount code \ */ \ @@ -88,12 +83,6 @@ __asm__("ldmfd sp!, {r0-r3, lr, pc}"); #ifdef _KERNEL -#ifdef __PROG26 -extern int int_off_save(void); -extern void int_restore(int); -#define MCOUNT_ENTER (s = int_off_save()) -#define MCOUNT_EXIT int_restore(s) -#else #include <arm/cpufunc.h> /* * splhigh() and splx() are heavyweight, and call mcount(). Therefore @@ -103,5 +92,4 @@ extern void int_restore(int); */ #define MCOUNT_ENTER s = __set_cpsr_c(0x0080, 0x0080); /* kill IRQ */ #define MCOUNT_EXIT __set_cpsr_c(0xffffffff, s); /* restore old value */ -#endif /* !acorn26 */ #endif /* _KERNEL */ diff --git a/sys/arch/arm/include/setjmp.h b/sys/arch/arm/include/setjmp.h index f20cab2e929..13017aa7242 100644 --- a/sys/arch/arm/include/setjmp.h +++ b/sys/arch/arm/include/setjmp.h @@ -1,15 +1,11 @@ -/* $OpenBSD: setjmp.h,v 1.1 2004/02/01 05:09:49 drahn Exp $ */ +/* $OpenBSD: setjmp.h,v 1.2 2011/09/20 22:02:13 miod Exp $ */ /* $NetBSD: setjmp.h,v 1.2 2001/08/25 14:45:59 bjh21 Exp $ */ /* * machine/setjmp.h: machine dependent setjmp-related information. */ -#ifdef __ELF__ #define _JBLEN 64 /* size, in longs, of a jmp_buf */ -#else -#define _JBLEN 29 /* size, in longs, of a jmp_buf */ -#endif /* * NOTE: The internal structure of a jmp_buf is *PRIVATE* diff --git a/sys/arch/arm/include/signal.h b/sys/arch/arm/include/signal.h index 5db3568611b..5af8396e380 100644 --- a/sys/arch/arm/include/signal.h +++ b/sys/arch/arm/include/signal.h @@ -1,4 +1,4 @@ -/* $OpenBSD: signal.h,v 1.6 2011/03/23 16:54:34 pirofti Exp $ */ +/* $OpenBSD: signal.h,v 1.7 2011/09/20 22:02:13 miod Exp $ */ /* $NetBSD: signal.h,v 1.5 2003/10/18 17:57:21 briggs Exp $ */ /* @@ -82,10 +82,6 @@ struct sigcontext { unsigned int sc_usr_lr; unsigned int sc_svc_lr; unsigned int sc_pc; - -#if 0 - sigset_t sc_mask; /* signal mask to restore (new style) */ -#endif }; #endif /* __BSD_VISIBLE || __XPG_VISIBLE >= 420 */ #endif /* !_LOCORE */ diff --git a/sys/arch/arm/xscale/pxa2x0_intr.c b/sys/arch/arm/xscale/pxa2x0_intr.c index 20b4d446835..70d3d436d2b 100644 --- a/sys/arch/arm/xscale/pxa2x0_intr.c +++ b/sys/arch/arm/xscale/pxa2x0_intr.c @@ -1,4 +1,4 @@ -/* $OpenBSD: pxa2x0_intr.c,v 1.21 2010/09/20 06:33:47 matthew Exp $ */ +/* $OpenBSD: pxa2x0_intr.c,v 1.22 2011/09/20 22:02:13 miod Exp $ */ /* $NetBSD: pxa2x0_intr.c,v 1.5 2003/07/15 00:24:55 lukem Exp $ */ /* @@ -688,11 +688,7 @@ pxa2x0_spllower(int ipl) void pxa2x0_setsoftintr(int si) { -#if 0 - atomic_set_bit( (u_int *)&softint_pending, SI_TO_IRQBIT(si) ); -#else softint_pending |= SI_TO_IRQBIT(si); -#endif /* Process unmasked pending soft interrupts. */ if ( softint_pending & pxa2x0_imask[current_spl_level] ) diff --git a/sys/arch/armish/armish/autoconf.c b/sys/arch/armish/armish/autoconf.c index 5072d36f41a..280c42bc52d 100644 --- a/sys/arch/armish/armish/autoconf.c +++ b/sys/arch/armish/armish/autoconf.c @@ -1,4 +1,4 @@ -/* $OpenBSD: autoconf.c,v 1.11 2010/11/28 20:44:20 miod Exp $ */ +/* $OpenBSD: autoconf.c,v 1.12 2011/09/20 22:02:13 miod Exp $ */ /* $NetBSD: autoconf.c,v 1.2 2001/09/05 16:17:36 matt Exp $ */ /* @@ -57,7 +57,6 @@ #include <dev/cons.h> struct device *bootdv = NULL; -extern char *boot_file; void dumpconf(void); diff --git a/sys/arch/armish/include/bootconfig.h b/sys/arch/armish/include/bootconfig.h index 5903977c2e9..0afef558e5c 100644 --- a/sys/arch/armish/include/bootconfig.h +++ b/sys/arch/armish/include/bootconfig.h @@ -1,4 +1,4 @@ -/* $OpenBSD: bootconfig.h,v 1.2 2006/07/30 21:38:12 drahn Exp $ */ +/* $OpenBSD: bootconfig.h,v 1.3 2011/09/20 22:02:13 miod Exp $ */ /* $NetBSD: bootconfig.h,v 1.2 2001/06/21 22:08:28 chris Exp $ */ /* @@ -43,13 +43,13 @@ * Based on kate/boot/bootconfig.h */ +#if defined(_KERNEL) || defined(_STANDALONE) + typedef struct _PhysMem { u_int address; u_int pages; } PhysMem; -#if defined(_KERNEL) || defined(_STANDALONE) - #define DRAM_BLOCKS 1 typedef struct _BootConfig { @@ -60,17 +60,8 @@ typedef struct _BootConfig { extern BootConfig bootconfig; #define MAX_BOOT_STRING 255 -#define BOOTOPT_TYPE_BOOLEAN 0 -#define BOOTOPT_TYPE_STRING 1 -#define BOOTOPT_TYPE_INT 2 -#define BOOTOPT_TYPE_BININT 3 -#define BOOTOPT_TYPE_HEXINT 4 -#define BOOTOPT_TYPE_MASK 7 - #endif /* _KERNEL || _STANDALONE */ #if defined(_KERNEL) -int get_bootconf_option (char *string, char *option, int type, void *result); - extern char *boot_args; extern char *boot_file; #endif /* _KERNEL */ diff --git a/sys/arch/beagle/beagle/autoconf.c b/sys/arch/beagle/beagle/autoconf.c index bd82d8af3d5..3ab3a815231 100644 --- a/sys/arch/beagle/beagle/autoconf.c +++ b/sys/arch/beagle/beagle/autoconf.c @@ -1,4 +1,4 @@ -/* $OpenBSD: autoconf.c,v 1.2 2010/11/28 20:44:20 miod Exp $ */ +/* $OpenBSD: autoconf.c,v 1.3 2011/09/20 22:02:13 miod Exp $ */ /* $NetBSD: autoconf.c,v 1.2 2001/09/05 16:17:36 matt Exp $ */ /* @@ -49,11 +49,11 @@ #include <sys/conf.h> #include <sys/kernel.h> #include <sys/malloc.h> + #include <machine/bootconfig.h> #include <machine/intr.h> struct device *bootdv = NULL; -extern char *boot_file; void dumpconf(void); diff --git a/sys/arch/beagle/include/bootconfig.h b/sys/arch/beagle/include/bootconfig.h index 6786d5207d1..bb612488a51 100644 --- a/sys/arch/beagle/include/bootconfig.h +++ b/sys/arch/beagle/include/bootconfig.h @@ -1,4 +1,4 @@ -/* $OpenBSD: bootconfig.h,v 1.2 2010/02/07 18:47:45 drahn Exp $ */ +/* $OpenBSD: bootconfig.h,v 1.3 2011/09/20 22:02:13 miod Exp $ */ /* $NetBSD: bootconfig.h,v 1.2 2001/06/21 22:08:28 chris Exp $ */ /* @@ -43,13 +43,13 @@ * Based on kate/boot/bootconfig.h */ +#if defined(_KERNEL) || defined(_STANDALONE) + typedef struct _PhysMem { u_int address; u_int pages; } PhysMem; -#if defined(_KERNEL) || defined(_STANDALONE) - #define DRAM_BLOCKS 2 typedef struct _BootConfig { @@ -60,17 +60,8 @@ typedef struct _BootConfig { extern BootConfig bootconfig; #define MAX_BOOT_STRING 255 -#define BOOTOPT_TYPE_BOOLEAN 0 -#define BOOTOPT_TYPE_STRING 1 -#define BOOTOPT_TYPE_INT 2 -#define BOOTOPT_TYPE_BININT 3 -#define BOOTOPT_TYPE_HEXINT 4 -#define BOOTOPT_TYPE_MASK 7 - #endif /* _KERNEL || _STANDALONE */ #if defined(_KERNEL) -int get_bootconf_option (char *string, char *option, int type, void *result); - extern char *boot_args; extern char *boot_file; #endif /* _KERNEL */ diff --git a/sys/arch/gumstix/gumstix/autoconf.c b/sys/arch/gumstix/gumstix/autoconf.c index 9025518dfd6..133f45e0dc5 100644 --- a/sys/arch/gumstix/gumstix/autoconf.c +++ b/sys/arch/gumstix/gumstix/autoconf.c @@ -1,4 +1,4 @@ -/* $OpenBSD: autoconf.c,v 1.2 2010/11/28 20:44:20 miod Exp $ */ +/* $OpenBSD: autoconf.c,v 1.3 2011/09/20 22:02:13 miod Exp $ */ /* $NetBSD: autoconf.c,v 1.2 2001/09/05 16:17:36 matt Exp $ */ /* @@ -58,7 +58,6 @@ #include <dev/cons.h> struct device *bootdv = NULL; -extern char *boot_file; void dumpconf(void); diff --git a/sys/arch/gumstix/include/bootconfig.h b/sys/arch/gumstix/include/bootconfig.h index bb061e30be2..6e9e95dd59b 100644 --- a/sys/arch/gumstix/include/bootconfig.h +++ b/sys/arch/gumstix/include/bootconfig.h @@ -1,4 +1,4 @@ -/* $OpenBSD: bootconfig.h,v 1.1 2008/11/26 14:18:11 drahn Exp $ */ +/* $OpenBSD: bootconfig.h,v 1.2 2011/09/20 22:02:13 miod Exp $ */ /* $NetBSD: bootconfig.h,v 1.2 2001/06/21 22:08:28 chris Exp $ */ /* @@ -43,13 +43,13 @@ * Based on kate/boot/bootconfig.h */ +#if defined(_KERNEL) + typedef struct _PhysMem { u_int address; u_int pages; } PhysMem; -#if defined(_KERNEL) - #define DRAM_BLOCKS 1 typedef struct _BootConfig { @@ -60,15 +60,6 @@ typedef struct _BootConfig { extern BootConfig bootconfig; #define MAX_BOOT_STRING 255 -#define BOOTOPT_TYPE_BOOLEAN 0 -#define BOOTOPT_TYPE_STRING 1 -#define BOOTOPT_TYPE_INT 2 -#define BOOTOPT_TYPE_BININT 3 -#define BOOTOPT_TYPE_HEXINT 4 -#define BOOTOPT_TYPE_MASK 7 - -int get_bootconf_option (char *string, char *option, int type, void *result); - extern char *boot_args; extern char *boot_file; #endif /* _KERNEL */ diff --git a/sys/arch/palm/include/bootconfig.h b/sys/arch/palm/include/bootconfig.h index 1250503f3d2..6e9e95dd59b 100644 --- a/sys/arch/palm/include/bootconfig.h +++ b/sys/arch/palm/include/bootconfig.h @@ -1,4 +1,4 @@ -/* $OpenBSD: bootconfig.h,v 1.1 2009/09/05 01:22:11 marex Exp $ */ +/* $OpenBSD: bootconfig.h,v 1.2 2011/09/20 22:02:13 miod Exp $ */ /* $NetBSD: bootconfig.h,v 1.2 2001/06/21 22:08:28 chris Exp $ */ /* @@ -43,13 +43,13 @@ * Based on kate/boot/bootconfig.h */ +#if defined(_KERNEL) + typedef struct _PhysMem { u_int address; u_int pages; } PhysMem; -#if defined(_KERNEL) - #define DRAM_BLOCKS 1 typedef struct _BootConfig { @@ -60,15 +60,6 @@ typedef struct _BootConfig { extern BootConfig bootconfig; #define MAX_BOOT_STRING 255 -#define BOOTOPT_TYPE_BOOLEAN 0 -#define BOOTOPT_TYPE_STRING 1 -#define BOOTOPT_TYPE_INT 2 -#define BOOTOPT_TYPE_BININT 3 -#define BOOTOPT_TYPE_HEXINT 4 -#define BOOTOPT_TYPE_MASK 7 - -int get_bootconf_option (char *string, char *option, int type, void *result); - extern char *boot_args; extern char *boot_file; #endif /* _KERNEL */ diff --git a/sys/arch/palm/palm/autoconf.c b/sys/arch/palm/palm/autoconf.c index a47cc627c39..480a4e72b56 100644 --- a/sys/arch/palm/palm/autoconf.c +++ b/sys/arch/palm/palm/autoconf.c @@ -1,4 +1,4 @@ -/* $OpenBSD: autoconf.c,v 1.2 2010/11/28 20:44:20 miod Exp $ */ +/* $OpenBSD: autoconf.c,v 1.3 2011/09/20 22:02:13 miod Exp $ */ /* $NetBSD: autoconf.c,v 1.2 2001/09/05 16:17:36 matt Exp $ */ /* @@ -58,7 +58,6 @@ #include <dev/cons.h> struct device *bootdv = NULL; -extern char *boot_file; void dumpconf(void); diff --git a/sys/arch/zaurus/include/bootconfig.h b/sys/arch/zaurus/include/bootconfig.h index 559ab2d491d..6e9e95dd59b 100644 --- a/sys/arch/zaurus/include/bootconfig.h +++ b/sys/arch/zaurus/include/bootconfig.h @@ -1,4 +1,4 @@ -/* $OpenBSD: bootconfig.h,v 1.1 2004/12/31 00:04:35 drahn Exp $ */ +/* $OpenBSD: bootconfig.h,v 1.2 2011/09/20 22:02:13 miod Exp $ */ /* $NetBSD: bootconfig.h,v 1.2 2001/06/21 22:08:28 chris Exp $ */ /* @@ -43,13 +43,13 @@ * Based on kate/boot/bootconfig.h */ +#if defined(_KERNEL) + typedef struct _PhysMem { u_int address; u_int pages; } PhysMem; -#if defined(_KERNEL) - #define DRAM_BLOCKS 1 typedef struct _BootConfig { @@ -60,15 +60,6 @@ typedef struct _BootConfig { extern BootConfig bootconfig; #define MAX_BOOT_STRING 255 -#define BOOTOPT_TYPE_BOOLEAN 0 -#define BOOTOPT_TYPE_STRING 1 -#define BOOTOPT_TYPE_INT 2 -#define BOOTOPT_TYPE_BININT 3 -#define BOOTOPT_TYPE_HEXINT 4 -#define BOOTOPT_TYPE_MASK 7 - -int get_bootconf_option (char *string, char *option, int type, void *result); - extern char *boot_args; extern char *boot_file; #endif /* _KERNEL */ diff --git a/sys/arch/zaurus/zaurus/autoconf.c b/sys/arch/zaurus/zaurus/autoconf.c index 9c96ef1e4f4..0bbcf5a3c6e 100644 --- a/sys/arch/zaurus/zaurus/autoconf.c +++ b/sys/arch/zaurus/zaurus/autoconf.c @@ -1,4 +1,4 @@ -/* $OpenBSD: autoconf.c,v 1.14 2010/11/28 20:44:20 miod Exp $ */ +/* $OpenBSD: autoconf.c,v 1.15 2011/09/20 22:02:13 miod Exp $ */ /* $NetBSD: autoconf.c,v 1.2 2001/09/05 16:17:36 matt Exp $ */ /* @@ -58,7 +58,6 @@ #include <dev/cons.h> struct device *bootdv = NULL; -extern char *boot_file; void dumpconf(void); |