diff options
| -rw-r--r-- | sys/arch/i386/conf/files.i386 | 3 | ||||
| -rw-r--r-- | sys/arch/i386/pci/pci_intr_fixup.c | 7 | ||||
| -rw-r--r-- | sys/arch/i386/pci/pcibiosvar.h | 4 | ||||
| -rw-r--r-- | sys/arch/i386/pci/rccosb4.c | 137 | ||||
| -rw-r--r-- | sys/arch/i386/pci/rccosb4reg.h | 52 |
5 files changed, 200 insertions, 3 deletions
diff --git a/sys/arch/i386/conf/files.i386 b/sys/arch/i386/conf/files.i386 index 5a48c7b3763..cfc875f878f 100644 --- a/sys/arch/i386/conf/files.i386 +++ b/sys/arch/i386/conf/files.i386 @@ -1,4 +1,4 @@ -# $OpenBSD: files.i386,v 1.124 2004/06/16 18:22:19 grange Exp $ +# $OpenBSD: files.i386,v 1.125 2004/06/22 09:47:01 mickey Exp $ # # new style config file for i386 architecture # @@ -307,6 +307,7 @@ file arch/i386/pci/pci_addr_fixup.c pcibios file arch/i386/pci/opti82c558.c pcibios file arch/i386/pci/opti82c700.c pcibios file arch/i386/pci/piix.c pcibios +file arch/i386/pci/rccosb4.c pcibios file arch/i386/pci/sis85c503.c pcibios file arch/i386/pci/via82c586.c pcibios file arch/i386/pci/via8231.c pcibios diff --git a/sys/arch/i386/pci/pci_intr_fixup.c b/sys/arch/i386/pci/pci_intr_fixup.c index ea0cfd009f1..f150af46373 100644 --- a/sys/arch/i386/pci/pci_intr_fixup.c +++ b/sys/arch/i386/pci/pci_intr_fixup.c @@ -1,4 +1,4 @@ -/* $OpenBSD: pci_intr_fixup.c,v 1.33 2004/06/13 21:49:16 niklas Exp $ */ +/* $OpenBSD: pci_intr_fixup.c,v 1.34 2004/06/22 09:47:01 mickey Exp $ */ /* $NetBSD: pci_intr_fixup.c,v 1.10 2000/08/10 21:18:27 soda Exp $ */ /* @@ -160,6 +160,11 @@ const struct pciintr_icu_table { { PCI_VENDOR_OPTI, PCI_PRODUCT_OPTI_82C700, opti82c700_init }, + { PCI_VENDOR_RCC, PCI_PRODUCT_RCC_ROSB4, + osb4_init }, + { PCI_VENDOR_RCC, PCI_PRODUCT_RCC_CSB5, + osb4_init }, + { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT82C596A, via82c586_init, }, { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT82C586_ISA, diff --git a/sys/arch/i386/pci/pcibiosvar.h b/sys/arch/i386/pci/pcibiosvar.h index e00e38a8910..f74255ca488 100644 --- a/sys/arch/i386/pci/pcibiosvar.h +++ b/sys/arch/i386/pci/pcibiosvar.h @@ -1,4 +1,4 @@ -/* $OpenBSD: pcibiosvar.h,v 1.12 2003/11/16 20:30:06 avsm Exp $ */ +/* $OpenBSD: pcibiosvar.h,v 1.13 2004/06/22 09:47:01 mickey Exp $ */ /* $NetBSD: pcibios.h,v 1.2 2000/04/28 17:15:16 uch Exp $ */ /* @@ -173,4 +173,6 @@ int amd756_init(pci_chipset_tag_t, bus_space_tag_t, pcitag_t, pciintr_icu_tag_t *, pciintr_icu_handle_t *); int ali1543_init(pci_chipset_tag_t, bus_space_tag_t, pcitag_t, pciintr_icu_tag_t *, pciintr_icu_handle_t *); +int osb4_init(pci_chipset_tag_t, bus_space_tag_t, pcitag_t, + pciintr_icu_tag_t *, pciintr_icu_handle_t *); diff --git a/sys/arch/i386/pci/rccosb4.c b/sys/arch/i386/pci/rccosb4.c new file mode 100644 index 00000000000..7361e7b7bf0 --- /dev/null +++ b/sys/arch/i386/pci/rccosb4.c @@ -0,0 +1,137 @@ +/* $OpenBSD: rccosb4.c,v 1.1 2004/06/22 09:47:01 mickey Exp $ */ + +/* + * Copyright (c) 2004 Michael Shalayeff + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * Support for RCC South Bridge interrupt controller + */ + +#include <sys/param.h> +#include <sys/systm.h> +#include <sys/device.h> +#include <sys/malloc.h> + +#include <machine/intr.h> +#include <machine/bus.h> + +#include <dev/pci/pcivar.h> +#include <dev/pci/pcireg.h> + +#include <i386/pci/pcibiosvar.h> +#include <i386/pci/piixvar.h> +#include <i386/pci/rccosb4reg.h> + +struct osb4_handle { + struct piix_handle piix; + +#define osb4_iot piix.ph_iot + bus_space_handle_t osb4_ioh; +}; + +int osb4_getclink(pciintr_icu_handle_t, int, int *); +int osb4_get_intr(pciintr_icu_handle_t, int, int *); +int osb4_set_intr(pciintr_icu_handle_t, int, int); + +const struct pciintr_icu osb4_pci_icu = { + osb4_getclink, + osb4_get_intr, + osb4_set_intr, + piix_get_trigger, + piix_set_trigger, +}; + +int +osb4_init(pci_chipset_tag_t pc, bus_space_tag_t iot, pcitag_t tag, + pciintr_icu_tag_t *ptagp, pciintr_icu_handle_t *phandp) +{ + struct osb4_handle *ph; + + ph = malloc(sizeof(*ph), M_DEVBUF, M_NOWAIT); + if (ph == NULL) + return (1); + + ph->piix.ph_iot = iot; + ph->piix.ph_pc = pc; + ph->piix.ph_tag = tag; + + if (bus_space_map(iot, OSB4_PIAIR, 2, 0, &ph->osb4_ioh)) { + free(ph, M_DEVBUF); + return (1); + } + + if (bus_space_map(iot, OSB4_REG_ELCR, 2, 0, &ph->piix.ph_elcr_ioh)) { + free(ph, M_DEVBUF); + return (1); + } + + *ptagp = &osb4_pci_icu; + *phandp = ph; + return (0); +} + +int +osb4_getclink(pciintr_icu_handle_t v, int link, int *clinkp) +{ + if (OSB4_LEGAL_LINK(link - 1)) { + *clinkp = link - 1; + return (0); + } + + return (1); +} + +int +osb4_get_intr(pciintr_icu_handle_t v, int clink, int *irqp) +{ + struct osb4_handle *ph = v; + + if (!OSB4_LEGAL_LINK(clink)) + return (1); + + bus_space_write_1(ph->osb4_iot, ph->osb4_ioh, 0, + clink | OSB4_PIAIR_PMASK); + *irqp = bus_space_read_1(ph->osb4_iot, ph->osb4_ioh, 1); + if (*irqp == 0) + *irqp = I386_PCI_INTERRUPT_LINE_NO_CONNECTION; + + return (0); +} + +int +osb4_set_intr(pciintr_icu_handle_t v, int clink, int irq) +{ + struct osb4_handle *ph = v; + + if (!OSB4_LEGAL_LINK(clink) || !OSB4_LEGAL_IRQ(irq)) + return (1); + + bus_space_write_1(ph->osb4_iot, ph->osb4_ioh, 0, + clink | OSB4_PIAIR_PMASK); + bus_space_write_1(ph->osb4_iot, ph->osb4_ioh, 1, irq); + + return (0); +} diff --git a/sys/arch/i386/pci/rccosb4reg.h b/sys/arch/i386/pci/rccosb4reg.h new file mode 100644 index 00000000000..9a2d9c466d8 --- /dev/null +++ b/sys/arch/i386/pci/rccosb4reg.h @@ -0,0 +1,52 @@ +/* $OpenBSD: rccosb4reg.h,v 1.1 2004/06/22 09:47:01 mickey Exp $ */ + +/* + * Copyright (c) 2004, Michael Shalayeff + * Copyright (c) 1999, by UCHIYAMA Yasushi + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. The name of the developer may NOT be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +/* + * Register definitions for the RCC South Bridge interrupt controller. + */ + +#define OSB4_LEGAL_LINK(link) ((link) >= 0 && (link) <= 15) + +#define OSB4_PIRQ_MASK 0xdef8 +#define OSB4_LEGAL_IRQ(irq) ((irq) > 0 && (irq) <= 15 && \ + ((1 << (irq)) & OSB4_PIRQ_MASK) != 0) + +/* + * PCI Interrupts Address Index Register + */ +#define OSB4_PIAIR 0xc00 +#define OSB4_PIAIR_PMASK 0x10 +#define OSB4_PIRR 0xc01 + +/* + * ELCR - EDGE/LEVEL CONTROL REGISTER + * + * PCI I/O registers 0x4d0, 0x4d1 + */ +#define OSB4_REG_ELCR 0x4d0 +#define OSB4_REG_ELCR_SIZE 2 |