diff options
| -rw-r--r-- | sys/arch/sgi/include/autoconf.h | 13 | ||||
| -rw-r--r-- | sys/arch/sgi/include/intr.h | 8 | ||||
| -rw-r--r-- | sys/arch/sgi/localbus/macebus.c | 5 | ||||
| -rw-r--r-- | sys/arch/sgi/pci/macepcibridge.c | 4 | ||||
| -rw-r--r-- | sys/arch/sgi/sgi/machdep.c | 39 |
5 files changed, 60 insertions, 9 deletions
diff --git a/sys/arch/sgi/include/autoconf.h b/sys/arch/sgi/include/autoconf.h index de6943333c7..cfeca154e64 100644 --- a/sys/arch/sgi/include/autoconf.h +++ b/sys/arch/sgi/include/autoconf.h @@ -1,4 +1,4 @@ -/* $OpenBSD: autoconf.h,v 1.7 2004/08/10 21:11:42 pefo Exp $ */ +/* $OpenBSD: autoconf.h,v 1.8 2004/09/20 10:31:16 pefo Exp $ */ /* * Copyright (c) 2001-2003 Opsycon AB (www.opsycon.se / www.opsycon.com) @@ -56,12 +56,21 @@ struct sys_rec { u_int32_t cfg_reg; u_int32_t stat_reg; } cpu[MAX_CPUS]; + /* Published Cache OPS */ + void (*_SyncCache)(void); + void (*_InvalidateICache)(vaddr_t, int); + void (*_InvalidateICachePage)(vaddr_t); + void (*_SyncDCachePage)(vaddr_t); + void (*_HitSyncDCache)(vaddr_t, int); + void (*_IOSyncDCache)(vaddr_t, int, int); + void (*_HitInvalidateDCache)(vaddr_t, int); + /* BUS mappings */ struct mips_bus_space local; struct mips_bus_space isa_io; struct mips_bus_space isa_mem; struct mips_bus_space pci_io[2]; struct mips_bus_space pci_mem[2]; - + /* Console/Serial configuration */ int cons_baudclk; struct mips_bus_space console_io; /* for stupid map designs */ struct mips_bus_space *cons_iot; diff --git a/sys/arch/sgi/include/intr.h b/sys/arch/sgi/include/intr.h index 94a93eee758..319eea78308 100644 --- a/sys/arch/sgi/include/intr.h +++ b/sys/arch/sgi/include/intr.h @@ -1,4 +1,4 @@ -/* $OpenBSD: intr.h,v 1.3 2004/08/10 19:16:18 deraadt Exp $ */ +/* $OpenBSD: intr.h,v 1.4 2004/09/20 10:31:16 pefo Exp $ */ /* * Copyright (c) 2001-2004 Opsycon AB (www.opsycon.se / www.opsycon.com) @@ -148,7 +148,6 @@ intrmask_t imask[NIPLS]; /* Inlines */ static __inline void register_pending_int_handler(void (*)(void)); -static __inline int splraise(int newcpl); static __inline void splx(int newcpl); static __inline int spllower(int newcpl); @@ -163,6 +162,8 @@ register_pending_int_handler(void(*pending)(void)) /* */ +#ifdef INLINE_SPLRAISE +static __inline int splraise(int newcpl); static __inline int splraise(int newcpl) { @@ -174,6 +175,9 @@ splraise(int newcpl) __asm__ (" sync\n .set reorder\n"); return (oldcpl); } +#else +int splraise(int newcpl); +#endif static __inline void splx(int newcpl) diff --git a/sys/arch/sgi/localbus/macebus.c b/sys/arch/sgi/localbus/macebus.c index aff96b984d3..b65e5bbf8a8 100644 --- a/sys/arch/sgi/localbus/macebus.c +++ b/sys/arch/sgi/localbus/macebus.c @@ -1,4 +1,4 @@ -/* $OpenBSD: macebus.c,v 1.6 2004/09/09 22:11:39 pefo Exp $ */ +/* $OpenBSD: macebus.c,v 1.7 2004/09/20 10:31:16 pefo Exp $ */ /* * Copyright (c) 2000-2004 Opsycon AB (www.opsycon.se) @@ -73,6 +73,8 @@ long crime_ext_storage[EXTENT_FIXED_STORAGE_SIZE(8) / sizeof (long)]; int maceticks; /* Time tracker for special events */ +u_int64_t crimestat; + struct cfattach macebus_ca = { sizeof(struct device), macebusmatch, macebusattach }; @@ -671,6 +673,7 @@ macebus_iointr(intrmask_t hwpend, struct trap_frame *cf) u_int64_t intstat, isastat, mask; intstat = bus_space_read_8(&crimebus_tag, crime_h, CRIME_INT_STAT); +crimestat=intstat; intstat &= 0x0000ffff; isastat = bus_space_read_8(&macebus_tag, mace_h, MACE_ISA_INT_STAT); catched = 0; diff --git a/sys/arch/sgi/pci/macepcibridge.c b/sys/arch/sgi/pci/macepcibridge.c index 24e114952ea..6a478c843a2 100644 --- a/sys/arch/sgi/pci/macepcibridge.c +++ b/sys/arch/sgi/pci/macepcibridge.c @@ -1,4 +1,4 @@ -/* $OpenBSD: macepcibridge.c,v 1.3 2004/08/11 15:13:35 deraadt Exp $ */ +/* $OpenBSD: macepcibridge.c,v 1.4 2004/09/20 10:31:16 pefo Exp $ */ /* * Copyright (c) 2001-2004 Opsycon AB (www.opsycon.se) @@ -184,7 +184,7 @@ pcibrattach(struct device *parent, struct device *self, void *aux) sc->sc_pc.pc_attach_hook = pcibr_attach_hook; sc->sc_pc.pc_make_tag = pcibr_make_tag; sc->sc_pc.pc_decompose_tag = pcibr_decompose_tag; - sc->sc_pc.pc_sync_cache = Mips_IOSyncDCache; + sc->sc_pc.pc_sync_cache = sys_config._IOSyncDCache; /* Create extents for PCI mappings */ pcibbus_io_tag.bus_extent = extent_create("pci_io", diff --git a/sys/arch/sgi/sgi/machdep.c b/sys/arch/sgi/sgi/machdep.c index 47006e5b0dd..aabb33d0e2f 100644 --- a/sys/arch/sgi/sgi/machdep.c +++ b/sys/arch/sgi/sgi/machdep.c @@ -1,4 +1,4 @@ -/* $OpenBSD: machdep.c,v 1.11 2004/09/16 19:38:30 miod Exp $ */ +/* $OpenBSD: machdep.c,v 1.12 2004/09/20 10:31:16 pefo Exp $ */ /* * Copyright (c) 2003-2004 Opsycon AB (www.opsycon.se / www.opsycon.com) @@ -305,7 +305,6 @@ mips_init(int argc, int32_t *argv) CpuTertiaryCacheSize = 0; } - sys_config.cpu[0].cfg_reg = Mips_ConfigCache(); sys_config.cpu[0].type = (cp0_get_prid() >> 8) & 0xff; sys_config.cpu[0].vers_maj = (cp0_get_prid() >> 4) & 0x0f; sys_config.cpu[0].vers_min = cp0_get_prid() & 0x0f; @@ -318,6 +317,7 @@ mips_init(int argc, int32_t *argv) */ switch(sys_config.cpu[0].type) { case MIPS_RM7000: + /* Rev A (version >= 2) CPU's have 64 TLB entries. */ if (sys_config.cpu[0].vers_maj < 2) { sys_config.cpu[0].tlbsize = 48; } else { @@ -325,11 +325,46 @@ mips_init(int argc, int32_t *argv) } break; + case MIPS_R10000: + case MIPS_R12000: + case MIPS_R14000: + sys_config.cpu[0].tlbsize = 64; + break; + default: sys_config.cpu[0].tlbsize = 48; break; } + /* + * Configure Cache. + */ + switch(sys_config.cpu[0].type) { + case MIPS_R10000: + case MIPS_R12000: + case MIPS_R14000: + sys_config.cpu[0].cfg_reg = Mips10k_ConfigCache(); + sys_config._SyncCache = Mips10k_SyncCache; + sys_config._InvalidateICache = Mips10k_InvalidateICache; + sys_config._InvalidateICachePage = Mips10k_InvalidateICachePage; + sys_config._SyncDCachePage = Mips10k_SyncDCachePage; + sys_config._HitSyncDCache = Mips10k_HitSyncDCache; + sys_config._IOSyncDCache = Mips10k_IOSyncDCache; + sys_config._HitInvalidateDCache = Mips10k_HitInvalidateDCache; + break; + + default: + sys_config.cpu[0].cfg_reg = Mips5k_ConfigCache(); + sys_config._SyncCache = Mips5k_SyncCache; + sys_config._InvalidateICache = Mips5k_InvalidateICache; + sys_config._InvalidateICachePage = Mips5k_InvalidateICachePage; + sys_config._SyncDCachePage = Mips5k_SyncDCachePage; + sys_config._HitSyncDCache = Mips5k_HitSyncDCache; + sys_config._IOSyncDCache = Mips5k_IOSyncDCache; + sys_config._HitInvalidateDCache = Mips5k_HitInvalidateDCache; + break; + } + tlb_set_wired(0); tlb_flush(sys_config.cpu[0].tlbsize); tlb_set_wired(sys_config.cpu[0].tlbwired); |