diff options
| -rw-r--r-- | sys/dev/pci/files.pci | 9 | ||||
| -rw-r--r-- | sys/dev/pci/noct.c | 469 | ||||
| -rw-r--r-- | sys/dev/pci/noctreg.h | 150 | ||||
| -rw-r--r-- | sys/dev/pci/noctvar.h | 62 |
4 files changed, 688 insertions, 2 deletions
diff --git a/sys/dev/pci/files.pci b/sys/dev/pci/files.pci index 9b0478f93d0..308fe5b8494 100644 --- a/sys/dev/pci/files.pci +++ b/sys/dev/pci/files.pci @@ -1,4 +1,4 @@ -# $OpenBSD: files.pci,v 1.134 2002/05/15 21:33:22 jason Exp $ +# $OpenBSD: files.pci,v 1.135 2002/06/02 18:15:03 jason Exp $ # $NetBSD: files.pci,v 1.20 1996/09/24 17:47:15 christos Exp $ # # Config file and device description for machine-independent PCI code. @@ -301,7 +301,7 @@ device lofn: crypto attach lofn at pci file dev/pci/lofn.c lofn -# Hi/fn 7751 +# Hi/fn 7751/7811/7951 device hifn: crypto attach hifn at pci file dev/pci/hifn7751.c hifn @@ -316,6 +316,11 @@ device ubsec: crypto attach ubsec at pci file dev/pci/ubsec.c ubsec +# Netoctave NSP2000 +device noct: crypto +attach noct at pci +file dev/pci/noct.c noct + # Pijnenburg PCC-ISES device ises: crypto attach ises at pci diff --git a/sys/dev/pci/noct.c b/sys/dev/pci/noct.c new file mode 100644 index 00000000000..2217c08997d --- /dev/null +++ b/sys/dev/pci/noct.c @@ -0,0 +1,469 @@ +/* $OpenBSD: noct.c,v 1.1 2002/06/02 18:15:03 jason Exp $ */ + +/* + * Copyright (c) 2002 Jason L. Wright (jason@thought.net) + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by Jason L. Wright + * 4. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * Effort sponsored in part by the Defense Advanced Research Projects + * Agency (DARPA) and Air Force Research Laboratory, Air Force + * Materiel Command, USAF, under agreement number F30602-01-2-0537. + * + */ + +/* + * Driver for the Netoctave NSP2000 security processor. + */ + +#include <sys/param.h> +#include <sys/systm.h> +#include <sys/proc.h> +#include <sys/errno.h> +#include <sys/malloc.h> +#include <sys/kernel.h> +#include <sys/mbuf.h> +#include <sys/device.h> + +#include <uvm/uvm_extern.h> + +#include <crypto/cryptodev.h> +#include <dev/rndvar.h> + +#include <dev/pci/pcireg.h> +#include <dev/pci/pcivar.h> +#include <dev/pci/pcidevs.h> + +#include <dev/pci/noctreg.h> +#include <dev/pci/noctvar.h> + +int noct_probe(struct device *, void *, void *); +void noct_attach(struct device *, struct device *, void *); + +int noct_ram_size(struct noct_softc *); +void noct_ram_write(struct noct_softc *, u_int32_t, u_int64_t); +u_int64_t noct_ram_read(struct noct_softc *, u_int32_t); + +void noct_rng_enable(struct noct_softc *); +void noct_rng_disable(struct noct_softc *); +void noct_rng_init(struct noct_softc *); +void noct_rng_intr(struct noct_softc *); +void noct_rng_tick(void *); + +u_int64_t noct_read_8(struct noct_softc *, u_int32_t); +void noct_write_8(struct noct_softc *, u_int32_t, u_int64_t); + +struct cfattach noct_ca = { + sizeof(struct noct_softc), noct_probe, noct_attach, +}; + +struct cfdriver noct_cd = { + 0, "noct", DV_DULL +}; + +int noct_intr(void *); + +int +noct_probe(parent, match, aux) + struct device *parent; + void *match; + void *aux; +{ + struct pci_attach_args *pa = (struct pci_attach_args *) aux; + + if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_NETOCTAVE && + PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_NETOCTAVE_NSP2K) + return (1); + return (0); +} + +void +noct_attach(parent, self, aux) + struct device *parent, *self; + void *aux; +{ + struct noct_softc *sc = (struct noct_softc *)self; + struct pci_attach_args *pa = aux; + pci_chipset_tag_t pc = pa->pa_pc; + pci_intr_handle_t ih; + const char *intrstr = NULL; + bus_size_t iosize = 0; + u_int32_t cmd; + + cmd = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); + cmd |= PCI_COMMAND_MEM_ENABLE; + pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, cmd); + cmd = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); + + if (!(cmd & PCI_COMMAND_MEM_ENABLE)) { + printf(": failed to enable memory mapping\n"); + goto fail; + } + + if (pci_mapreg_map(pa, NOCT_BAR0, PCI_MAPREG_MEM_TYPE_64BIT, 0, + &sc->sc_st, &sc->sc_sh, NULL, &iosize, 0)) { + printf(": can't map mem space\n"); + goto fail; + } + + /* Before we do anything else, put the chip in little endian mode */ + NOCT_WRITE_4(sc, NOCT_BRDG_ENDIAN, 0); + + sc->sc_dmat = pa->pa_dmat; + + if (pci_intr_map(pa, &ih)) { + printf(": couldn't map interrupt\n"); + goto fail; + } + intrstr = pci_intr_string(pc, ih); + sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, noct_intr, sc, + self->dv_xname); + if (sc->sc_ih == NULL) { + printf(": couldn't establish interrupt"); + if (intrstr != NULL) + printf(" at %s", intrstr); + printf("\n"); + goto fail; + } + + if (noct_ram_size(sc)) + goto fail; + + printf(": %s, %uMB\n", intrstr, sc->sc_ramsize); + + noct_rng_init(sc); + + return; + +fail: + if (iosize != 0) + bus_space_unmap(sc->sc_st, sc->sc_sh, iosize); +} + +int +noct_intr(vsc) + void *vsc; +{ + struct noct_softc *sc = vsc; + u_int32_t reg; + int r = 0; + + reg = NOCT_READ_4(sc, NOCT_BRDG_STAT); + + if (reg & BRDGSTS_RNG_INT) { + r = 1; + noct_rng_intr(sc); + } + + return (r); +} + +int +noct_ram_size(sc) + struct noct_softc *sc; +{ + u_int64_t t; + + noct_ram_write(sc, 0x000000, 64); + noct_ram_write(sc, 0x400000, 32); + t = noct_ram_read(sc, 0x000000); + noct_ram_write(sc, 0x000000, 128); + noct_ram_write(sc, 0x800000, t); + t = noct_ram_read(sc, 0x000000); + + if (t != 32 && t != 64 && t != 128) { + printf(": invalid ram size %llx\n", (unsigned long long)t); + return (1); + } + + sc->sc_ramsize = t; + return (0); +} + +void +noct_ram_write(sc, adr, dat) + struct noct_softc *sc; + u_int32_t adr; + u_int64_t dat; +{ + u_int32_t reg; + + /* wait for pending writes to finish */ + for (;;) { + reg = NOCT_READ_4(sc, NOCT_EA_CTX_ADDR); + if ((reg & CTXADDR_WRITEPEND) == 0) + break; + } + + NOCT_WRITE_4(sc, NOCT_EA_CTX_ADDR, adr); + NOCT_WRITE_4(sc, NOCT_EA_CTX_DAT_1, (dat >> 32) & 0xffffffff); + NOCT_WRITE_4(sc, NOCT_EA_CTX_DAT_0, (dat >> 0) & 0xffffffff); + + for (;;) { + reg = NOCT_READ_4(sc, NOCT_EA_CTX_ADDR); + if ((reg & CTXADDR_WRITEPEND) == 0) + break; + } +} + +u_int64_t +noct_ram_read(sc, adr) + struct noct_softc *sc; + u_int32_t adr; +{ + u_int64_t dat; + u_int32_t reg; + + /* wait for pending reads to finish */ + for (;;) { + reg = NOCT_READ_4(sc, NOCT_EA_CTX_ADDR); + if ((reg & CTXADDR_READPEND) == 0) + break; + } + + NOCT_WRITE_4(sc, NOCT_EA_CTX_ADDR, adr | CTXADDR_READPEND); + + for (;;) { + reg = NOCT_READ_4(sc, NOCT_EA_CTX_ADDR); + if ((reg & CTXADDR_READPEND) == 0) + break; + } + + dat = NOCT_READ_4(sc, NOCT_EA_CTX_DAT_1); + dat <<= 32; + dat |= NOCT_READ_4(sc, NOCT_EA_CTX_DAT_0); + return (dat); +} + +void +noct_rng_disable(sc) + struct noct_softc *sc; +{ + u_int64_t csr; + u_int32_t r; + + /* Turn off RN irq */ + NOCT_WRITE_4(sc, NOCT_BRDG_CTL, + NOCT_READ_4(sc, NOCT_BRDG_CTL) & ~(BRDGCTL_RNIRQ_ENA)); + + /* Turn off RNH interrupts */ + r = NOCT_READ_4(sc, NOCT_RNG_CSR); + r &= ~(RNGCSR_INT_KEY | RNGCSR_INT_DUP | + RNGCSR_INT_BUS | RNGCSR_INT_ACCESS); + NOCT_WRITE_4(sc, NOCT_RNG_CSR, r); + + /* Turn off RN queue */ + r = NOCT_READ_4(sc, NOCT_RNG_CSR); + r &= ~(RNGCSR_XFER_ENABLE | RNGCSR_INT_KEY | RNGCSR_INT_BUS | + RNGCSR_INT_DUP | RNGCSR_INT_ACCESS); + NOCT_WRITE_4(sc, NOCT_RNG_CSR, r); + + for (;;) { + r = NOCT_READ_4(sc, NOCT_RNG_CSR); + if ((r & RNGCSR_XFER_BUSY) == 0) + break; + } + + /* Turn off RN generator */ + csr = NOCT_READ_8(sc, NOCT_RNG_CTL); + csr &= ~RNGCTL_RNG_ENA; + NOCT_WRITE_8(sc, NOCT_RNG_CTL, csr); +} + +void +noct_rng_enable(sc) + struct noct_softc *sc; +{ + u_int64_t adr; + u_int32_t r; + + adr = sc->sc_rngmap->dm_segs[0].ds_addr; + NOCT_WRITE_4(sc, NOCT_RNG_BAR1, (adr >> 32) & 0xffffffff); + NOCT_WRITE_4(sc, NOCT_RNG_Q_LEN, NOCT_RNG_QLEN); + NOCT_WRITE_4(sc, NOCT_RNG_BAR0, (adr >> 0 ) & 0xffffffff); + + NOCT_WRITE_8(sc, NOCT_RNG_CTL, + RNGCTL_RNG_ENA | + RNGCTL_TOD_ENA | + RNGCTL_BUFSRC_SEED | + RNGCTL_SEEDSRC_INT | + RNGCTL_EXTCLK_ENA | + RNGCTL_DIAG | + (100 & RNGCTL_ITERCNT)); + + /* Turn on interrupts and enable xfer */ + r = RNGCSR_XFER_ENABLE | RNGCSR_INT_ACCESS | + RNGCSR_INT_KEY | RNGCSR_INT_BUS | RNGCSR_INT_DUP; + NOCT_WRITE_4(sc, NOCT_RNG_CSR, r); + + /* Turn on bridge/rng interrupts */ + r = NOCT_READ_4(sc, NOCT_BRDG_CTL); + r |= BRDGCTL_RNIRQ_ENA; + NOCT_WRITE_4(sc, NOCT_BRDG_CTL, r); +} + +void +noct_rng_init(sc) + struct noct_softc *sc; +{ + bus_dma_segment_t seg; + int rseg; + + if (bus_dmamem_alloc(sc->sc_dmat, NOCT_RNG_BUFSIZE, + PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { + printf("%s: failed rng buf alloc\n", sc->sc_dv.dv_xname); + goto fail; + } + if (bus_dmamem_map(sc->sc_dmat, &seg, rseg, NOCT_RNG_BUFSIZE, + (caddr_t *)&sc->sc_rngbuf, BUS_DMA_NOWAIT)) { + printf("%s: failed rng buf map\n", sc->sc_dv.dv_xname); + goto fail_1; + } + if (bus_dmamap_create(sc->sc_dmat, NOCT_RNG_BUFSIZE, rseg, + NOCT_RNG_BUFSIZE, 0, BUS_DMA_NOWAIT, &sc->sc_rngmap)) { + printf("%s: failed rng map create\n", sc->sc_dv.dv_xname); + goto fail_2; + } + if (bus_dmamap_load_raw(sc->sc_dmat, sc->sc_rngmap, + &seg, rseg, NOCT_RNG_BUFSIZE, BUS_DMA_NOWAIT)) { + printf("%s: failed rng buf load\n", sc->sc_dv.dv_xname); + goto fail_3; + } + + noct_rng_disable(sc); + noct_rng_enable(sc); + + if (hz > 100) + sc->sc_rngtick = hz/100; + else + sc->sc_rngtick = 1; + timeout_set(&sc->sc_rngto, noct_rng_tick, sc); + timeout_add(&sc->sc_rngto, sc->sc_rngtick); + + return; + +fail_3: + bus_dmamap_destroy(sc->sc_dmat, sc->sc_rngmap); +fail_2: + bus_dmamem_unmap(sc->sc_dmat, + (caddr_t)sc->sc_rngbuf, NOCT_RNG_BUFSIZE); +fail_1: + bus_dmamem_free(sc->sc_dmat, &seg, rseg); +fail: + sc->sc_rngbuf = NULL; + sc->sc_rngmap = NULL; + return; +} + +void +noct_rng_intr(sc) + struct noct_softc *sc; +{ + u_int32_t csr; + int enable = 1; + + csr = NOCT_READ_4(sc, NOCT_RNG_CSR); + NOCT_WRITE_4(sc, NOCT_RNG_CSR, csr); + + if (csr & RNGCSR_ERR_KEY) { + u_int32_t ctl; + + enable = 0; + ctl = NOCT_READ_4(sc, NOCT_RNG_CTL); + printf("%s: rng bad key(s)", sc->sc_dv.dv_xname); + if (ctl & RNGCTL_KEY1PAR_ERR) + printf(", key1 parity"); + if (ctl & RNGCTL_KEY2PAR_ERR) + printf(", key2 parity"); + printf("\n"); + } + if (csr & RNGCSR_ERR_BUS) { + enable = 0; + printf("%s: rng bus error\n", sc->sc_dv.dv_xname); + } + if (csr & RNGCSR_ERR_DUP) { + enable = 0; + printf("%s: rng duplicate block\n", sc->sc_dv.dv_xname); + } + if (csr & RNGCSR_ERR_ACCESS) { + enable = 0; + printf("%s: rng invalid access\n", sc->sc_dv.dv_xname); + } + + if (!enable) + noct_rng_disable(sc); +} + +void +noct_rng_tick(vsc) + void *vsc; +{ + struct noct_softc *sc = vsc; + u_int64_t val; + u_int32_t reg, rd, wr; + int cons = 0; + + reg = NOCT_READ_4(sc, NOCT_RNG_Q_PTR); + rd = (reg & RNGQPTR_READ_M) >> RNGQPTR_READ_S; + wr = (reg & RNGQPTR_WRITE_M) >> RNGQPTR_WRITE_S; + + while (rd != wr) { + val = sc->sc_rngbuf[rd]; + add_true_randomness((val >> 32) & 0xffffffff); + add_true_randomness((val >> 0) & 0xffffffff); + if (++rd == NOCT_RNG_ENTRIES) + rd = 0; + cons++; + } + + if (cons != 0) + NOCT_WRITE_4(sc, NOCT_RNG_Q_PTR, rd); + timeout_add(&sc->sc_rngto, sc->sc_rngtick); +} + +void +noct_write_8(sc, reg, val) + struct noct_softc *sc; + u_int32_t reg; + u_int64_t val; +{ + NOCT_WRITE_4(sc, reg, (val >> 32) & 0xffffffff); + NOCT_WRITE_4(sc, reg + 4, (val >> 0) & 0xffffffff); +} + +u_int64_t +noct_read_8(sc, reg) + struct noct_softc *sc; + u_int32_t reg; +{ + u_int64_t ret; + + ret = NOCT_READ_4(sc, reg); + ret <<= 32; + ret |= NOCT_READ_4(sc, reg + 4); + return (ret); +} diff --git a/sys/dev/pci/noctreg.h b/sys/dev/pci/noctreg.h new file mode 100644 index 00000000000..e0fc20fb69f --- /dev/null +++ b/sys/dev/pci/noctreg.h @@ -0,0 +1,150 @@ +/* $OpenBSD: noctreg.h,v 1.1 2002/06/02 18:15:03 jason Exp $ */ + +/* + * Copyright (c) 2002 Jason L. Wright (jason@thought.net) + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by Jason L. Wright + * 4. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#define NOCT_BAR0 0x10 /* PCI base address */ + +#define NOCT_BRDG_ENDIAN 0x0000 /* bridge endian mode */ +#define NOCT_BRDG_TIMER_PRESET 0x0004 /* bridge timer preset */ +#define NOCT_BRDG_STAT 0x0008 /* bridge status */ +#define NOCT_BRDG_CTL 0x000c /* bridge control */ +#define NOCT_BRDG_TIMR 0x0010 /* bridge timer */ +#define NOCT_BRDG_TEST 0x0014 /* bridge test */ +#define NOCT_BRDG_RPMR 0x0018 /* bridge read ptr mirror */ +#define NOCT_EA_TEST_1 0x8000 /* e/a test 1 */ +#define NOCT_EA_TEST_0 0x8004 /* e/a test 0 */ +#define NOCT_EA_CMDQ_LEN 0x8008 /* e/a cmd queue len */ +#define NOCT_EA_CMDQ_PTR 0x800c /* e/a cmd queue ptr */ +#define NOCT_EA_CMDQ_BAR1 0x8010 /* e/a cmd queue bar 1 */ +#define NOCT_EA_CMDQ_BAR0 0x8014 /* e/a cmd queue bar 0 */ +#define NOCT_EA_IER 0x8018 /* e/a intr enable */ +#define NOCT_EA_CSR 0x801c /* e/a control/status */ +#define NOCT_EA_CTX_DAT_1 0x8020 /* e/a context data 1 */ +#define NOCT_EA_CTX_DAT_0 0x8024 /* e/a context data 0 */ +#define NOCT_EA_CTX_ADDR 0x8028 /* e/a context address */ +#define NOCT_EA_SDRAM_CFG 0x802c /* e/a sdram config */ +#define NOCT_RNG_TOD 0xc000 /* rng time of day */ +#define NOCT_RNG_TOD_SCALE 0xc008 /* rng pre-scale */ +#define NOCT_RNG_TOD_READ 0xc010 /* rng time of day (read) */ +#define NOCT_RNG_X917_KEY1 0xc018 /* rng x9.17 key 1 */ +#define NOCT_RNG_X917_KEY2 0xc020 /* rng x9.17 key 2 */ +#define NOCT_RNG_HOSTSEED 0xc028 /* rng host seed */ +#define NOCT_RNG_SAMPBIAS 0xc030 /* rng intrl seed gen/bias */ +#define NOCT_RNG_EXTCLK_SCALE 0xc038 /* rng extrn clock scale */ +#define NOCT_RNG_WRITE 0xc040 /* rng write pointer */ +#define NOCT_RNG_SEEDSAMP 0xc048 /* rng seed sample */ +#define NOCT_RNG_LFSRDIAG 0xc050 /* rng lfsr diagnostics */ +#define NOCT_RNG_LFSRHIST_1 0xc058 /* rng lfsr history 1 */ +#define NOCT_RNG_LFSRHIST_2 0xc060 /* rng lfsr history 2 */ +#define NOCT_RNG_LFSRHIST_3 0xc068 /* rng lfsr history 3 */ +#define NOCT_RNG_LFSRHIST_4 0xc070 /* rng lfsr history 4 */ +#define NOCT_RNG_CTL 0xc078 /* rng control */ +#define NOCT_RNG_TEST_1 0xd000 /* rng test 1 */ +#define NOCT_RNG_TEST_0 0xd004 /* rng test 0 */ +#define NOCT_RNG_Q_LEN 0xd008 /* rng queue length */ +#define NOCT_RNG_Q_PTR 0xd00c /* rng queue pointer */ +#define NOCT_RNG_BAR1 0xd010 /* rng bar1 */ +#define NOCT_RNG_BAR0 0xd014 /* rng bar0 */ +#define NOCT_RNG_CSR 0xd018 /* rng control/status */ + +#define CTXADDR_READPEND 0x80000000 /* read pending/start */ +#define CTXADDR_WRITEPEND 0x40000000 /* write pending/start */ +#define CTXADDR_MASK 0x00ffffff /* address mask */ + +/* NOCT_BRDG_STAT */ +#define BRDGSTS_PKP_INT 0x80000000 /* pkp interrupt */ +#define BRDGSTS_CCH_INT 0x40000000 /* cch interrupt */ +#define BRDGSTS_RNG_INT 0x20000000 /* rng interrupt */ +#define BRDGSTS_BRG_INT 0x10000000 /* bridge interrupt */ +#define BRDGSTS_TMR_INT 0x08000000 /* timer interrupt */ +#define BRDGSTS_CCH_ENA 0x01000000 /* mirror from e/a */ +#define BRDGSTS_CCH_BSY 0x00800000 /* mirror from e/a */ +#define BRDGSTS_CCH_ERR 0x00400000 /* mirror from e/a */ +#define BRDGSTS_CCH_RD_PEND 0x00200000 /* mirror from e/a */ +#define BRDGSTS_CCH_WR_PEND 0x00100000 /* mirror from e/a */ +#define BRDGSTS_PKH_ENA 0x00080000 /* mirror from pkh */ +#define BRDGSTS_PKH_BSY 0x00040000 /* mirror from pkh */ +#define BRDGSTS_PKH_ERR 0x00020000 /* mirror from pkh */ +#define BRDGSTS_PKH_SKS 0x00010000 /* mirror from pkh */ +#define BRDGSTS_HRESP_ERR 0x00002000 /* AHB slave HRESP error */ +#define BRDGSTS_HBURST_ERR 0x00001000 /* ccm, illegal burst */ +#define BRDGSTS_HSIZE_ERR 0x00000800 /* ccm, illegal size */ +#define BRDGSTS_PCIACC_ERR 0x00000400 /* pci access error */ +#define BRDGSTS_RSVMEM_ERR 0x00000200 /* reserved access */ +#define BRDGSTS_TRCVFIFO_PERR 0x00000100 /* CS6464AF parity error */ +#define BRDGSTS_PCIPERR 0x00000080 /* host parity error */ + +/* NOCT_BRDG_CTL */ +#define BRDGCTL_PKIRQ_ENA 0x80000000 /* pkh interrupt enable */ +#define BRDGCTL_EAIRQ_ENA 0x40000000 /* ea interrupt enable */ +#define BRDGCTL_RNIRQ_ENA 0x20000000 /* rng interrupt enable */ +#define BRDGCTL_BIRQ_ENA 0x10000000 /* bridge interrupt enable */ +#define BRDGCTL_TIRQ_ENA 0x08000000 /* timer interrupt enable */ +#define BRDGCTL_TIMER_ENA 0x00000001 /* enable timer */ + +/* NOCT_RNG_CTL */ +#define RNGCTL_RNG_ENA 0x80000000 /* rng enable */ +#define RNGCTL_TOD_ENA 0x40000000 /* enable tod counter */ +#define RNGCTL_EXTCLK_ENA 0x20000000 /* external clock enable */ +#define RNGCTL_DIAG 0x10000000 /* diagnostic mode */ +#define RNGCTL_BUFSRC_M 0x0c000000 /* buffer source: */ +#define RNGCTL_BUFSRC_X917 0x00000000 /* X9.17 expander */ +#define RNGCTL_BUFSRC_SEED 0x04000000 /* seed generator */ +#define RNGCTL_BUFSRC_HOST 0x08000000 /* host data */ +#define RNGCTL_SEEDSRC_M 0x03000000 /* seed source: */ +#define RNGCTL_SEEDSRC_INT 0x00000000 /* internal seed generator */ +#define RNGCTL_SEEDSRC_EXT 0x01000000 /* external seed generator */ +#define RNGCTL_SEEDSRC_HOST 0x02000000 /* host seed */ +#define RNGCTL_SEED_ERR 0x00008000 /* seed error */ +#define RNGCTL_X917_ERR 0x00004000 /* X9.17 error */ +#define RNGCTL_KEY1PAR_ERR 0x00002000 /* key 1 parity error */ +#define RNGCTL_KEY2PAR_ERR 0x00001000 /* key 2 parity error */ +#define RNGCTL_HOSTSEEDVALID 0x00000400 /* host seed not consumed */ +#define RNGCTL_BUF_RDY 0x00000200 /* buffer ready for write */ +#define RNGCTL_ITERCNT 0x000000ff /* iteration count */ + +/* NOCT_RNG_CSR */ +#define RNGCSR_XFER_ENABLE 0x80000000 /* enable xfer queue */ +#define RNGCSR_XFER_BUSY 0x40000000 /* xfer in progress */ +#define RNGCSR_ERR_KEY 0x00800000 /* key error */ +#define RNGCSR_ERR_BUS 0x00400000 /* pci bus error */ +#define RNGCSR_ERR_DUP 0x00200000 /* duplicate block generated */ +#define RNGCSR_ERR_ACCESS 0x00100000 /* access error */ +#define RNGCSR_INT_KEY 0x00080000 /* intr ena: key error */ +#define RNGCSR_INT_BUS 0x00040000 /* intr ena: pci error */ +#define RNGCSR_INT_DUP 0x00020000 /* intr ena: dup error */ +#define RNGCSR_INT_ACCESS 0x00010000 /* intr ena: access error */ + +#define RNGQPTR_READ_M 0x00007fff /* read mask */ +#define RNGQPTR_READ_S 0 /* read shift */ +#define RNGQPTR_WRITE_M 0x7fff0000 /* write mask */ +#define RNGQPTR_WRITE_S 16 /* write shift */ diff --git a/sys/dev/pci/noctvar.h b/sys/dev/pci/noctvar.h new file mode 100644 index 00000000000..4e4af25607e --- /dev/null +++ b/sys/dev/pci/noctvar.h @@ -0,0 +1,62 @@ +/* $OpenBSD: noctvar.h,v 1.1 2002/06/02 18:15:03 jason Exp $ */ + +/* + * Copyright (c) 2002 Jason L. Wright (jason@thought.net) + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by Jason L. Wright + * 4. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * Effort sponsored in part by the Defense Advanced Research Projects + * Agency (DARPA) and Air Force Research Laboratory, Air Force + * Materiel Command, USAF, under agreement number F30602-01-2-0537. + * + */ + +struct noct_softc { + struct device sc_dv; + bus_space_tag_t sc_st; + bus_space_handle_t sc_sh; + bus_dma_tag_t sc_dmat; + void *sc_ih; + u_int sc_ramsize; + u_int64_t *sc_rngbuf; + bus_dmamap_t sc_rngmap; + struct timeout sc_rngto; + int sc_rngtick; +}; + +#define NOCT_READ_4(sc,r) \ + bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (r)) +#define NOCT_WRITE_4(sc,r,v) \ + bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (r), (v)) + +#define NOCT_READ_8(sc,r) noct_read_8(sc, r) +#define NOCT_WRITE_8(sc,r,v) noct_write_8(sc, r, v) + +#define NOCT_RNG_QLEN 15 +#define NOCT_RNG_ENTRIES (1 << NOCT_RNG_QLEN) +#define NOCT_RNG_BUFSIZE (NOCT_RNG_ENTRIES * sizeof(u_int64_t)) |